52nd week of 2010 patent applcation highlights part 17 |
Patent application number | Title | Published |
20100327368 | ENHANCING SELECTIVITY DURING FORMATION OF A CHANNEL SEMICONDUCTOR ALLOY BY A WET OXIDATION PROCESS - High-k metal gate electrode structures are formed on the basis of a threshold adjusting semiconductor alloy formed in the channel region of one type of transistor, which may be accomplished on the basis of selective epitaxial growth techniques using an oxide hard mask growth mask. The hard mask may be provided with superior thickness uniformity on the basis of a wet oxidation process. Consequently, this may allow re-working substrates prior to the selective epitaxial growth process, for instance in view of queue time violations, while also providing superior transistor characteristics in the transistors that do not require the threshold adjusting semiconductor alloy. | 2010-12-30 |
20100327369 | Semiconductor Constructions - Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C | 2010-12-30 |
20100327370 | Non-planar embedded polysilicon resistor - The present invention discloses a method comprising: forming a sacrificial polysilicon gate (of a transistor) and a polysilicon resistor; and replacing said sacrificial polysilicon gate (of said transistor) with a metal gate while covering said polysilicon resistor. | 2010-12-30 |
20100327371 | Memory device and method of fabricating the same - A nonvolatile memory including a plurality of memory transistors in series, wherein source/drain and channel regions therebetween are of a first type and a select transistor, at each end of the plurality of memory transistors in series, wherein channels regions of each of the select transistors is of the first type. The first type may be n-type or p-type. The nonvolatile memory may further include a first dummy select transistor at one end of the plurality of memory transistors in series between one of the select transistors and the plurality of memory transistors in series and a second dummy select transistor at the other end of the plurality of memory transistors in series between the other select transistor and the plurality of memory transistors in series. | 2010-12-30 |
20100327372 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor substrate according to one embodiment includes: a first transistor having a first gate insulating film formed on a semiconductor substrate, a first gate electrode formed on the first gate insulating film and a first sidewall formed on a side face of the first gate electrode, the first gate insulating film comprising a high-dielectric constant material as a base material, a part of the first sidewall contacting with the first gate insulating film and containing Si and N; and a second transistor having a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film and a second sidewall formed on a side face of the second gate electrode so as to contact with the second gate insulating film, the second gate insulating film comprising a high-dielectric constant material as a base material, a part of the second sidewall contacting with the second gate insulating film and containing Si and N, wherein at least one of an abundance ratio of Si—H bond to N—H bond per unit volume, an amount of Cl per unit volume and an amount of H per unit volume of the second sidewall is larger than that of the first sidewall; and a threshold voltage of the second transistor is higher than that of the first transistor. | 2010-12-30 |
20100327373 | UNIFORM HIGH-K METAL GATE STACKS BY ADJUSTING THRESHOLD VOLTAGE FOR SOPHISTICATED TRANSISTORS BY DIFFUSING A METAL SPECIES PRIOR TO GATE PATTERNING - Sophisticated gate electrode structures for N-channel transistors and P-channel transistors are patterned on the basis of substantially the same configuration while, nevertheless, the work function adjustment may be accomplished in an early manufacturing stage. For this purpose, diffusion layer and cap layer materials are removed after incorporating the desired work function metal species into the high-k dielectric material and subsequently a common gate layer stack is deposited and subsequently patterned. | 2010-12-30 |
20100327374 | LOW COST TRANSISTORS USING GATE ORIENTATION AND OPTIMIZED IMPLANTS - An integrated circuit is disclosed having symmetric and asymmetric MOS transistors of the same polarity, oriented perpendicularly to each other, formed by concurrent halo ion, LDD ion and/or S/D ion implant processes using angled, rotated sub-implants which vary the tilt angle, dose and/or energy between rotations. Implanted halo, LDD and/or S/D source and drain regions formed by angled subimplants may have different extents of overlap with, or lateral separation from, gates of the two types of transistors, producing transistors with two different sets of electrical properties. A process for concurrently fabricating the two types of transistors is also disclosed. Specific embodiments of processes for concurrently forming symmetric and asymmetric transistors are disclosed. | 2010-12-30 |
20100327375 | SHALLOW EXTENSION REGIONS HAVING ABRUPT EXTENSION JUNCTIONS - A method of forming a semiconductor device is provided that includes forming a gate structure atop a substrate and implanting dopants into the substrate to a depth of 10 nm or less from an upper surface of the substrate. In a following step, an anneal is performed with a peak temperature ranging from 1200° C. to 1400° C., and a hold time period ranging from 1 millisecond to 5 milliseconds. | 2010-12-30 |
20100327376 | Metal High-K Transistor Having Silicon Sidewall For Reduced Parasitic Capacitance, And Process To Fabricate Same - A method forms a metal high dielectric constant (MHK) transistor and includes: providing a MHK stack disposed on a substrate, the MHK stack including a first layer of high dielectric constant material, a second overlying layer, and a third overlying layer; selectively removing only the second and third layers, without removing the first layer, to form an upstanding portion of a MHK gate structure; forming a first sidewall layer on sidewalls of the upstanding portion of the MHK gate structure; forming a second sidewall layer on sidewalls of the first sidewall layer; removing a portion of the first layer to form exposed surfaces; forming an offset spacer layer over the second sidewall layer and over the first layer, and forming in the substrate extensions that underlie the first and second sidewall layers and that extend under a portion but not all of the upstanding portion of the MHK gate structure. | 2010-12-30 |
20100327377 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same - An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer. | 2010-12-30 |
20100327378 | SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area. | 2010-12-30 |
20100327379 | CAPPED INTEGRATED DEVICE WITH PROTECTIVE CAP, COMPOSITE WAFER INCORPORATING INTEGRATED DEVICES AND PROCESS FOR BONDING INTEGRATED DEVICES WITH RESPECTIVE PROTECTIVE CAPS - A capped integrated device includes a semiconductor chip, incorporating an integrated device and a protective cap, bonded to the semiconductor chip for protection of the integrated device by means of a bonding layer made of a bonding material. The bonding material forms anchorage elements within recesses, formed in at least one between the semiconductor chip and the protective cap. | 2010-12-30 |
20100327380 | METHOD OF MANUFACTURING CAPACITIVE ELECTROMECHANICAL TRANSDUCER AND CAPACITIVE ELECTROMECHANICAL TRANSDUCER - In a method of manufacturing a capacitive electromechanical transducer, a first electrode ( | 2010-12-30 |
20100327381 | SIDEWALL PHOTODETECTOR - Sidewall photodetectors for integrated photonic devices and their method of manufacture. An embodiment includes a p-i-n film stack formed on a sidewall of a substrate semiconductor feature having sufficiently large area to accommodate the spot size of a multi-mode fiber. An embodiment includes a first sidewall photodetector coupled to a second sidewall photodetector by a waveguide, the first sidewall photodetector having an i-layer tuned to absorb a first wavelength of light incident to the first sidewall and pass a second wavelength of light to the second sidewall photodetector having an i-layer tuned to absorb the second wavelength. | 2010-12-30 |
20100327382 | High Bandwidth, Monolithic Traveling Wave Photodiode Array - The monolithic application of a high speed TWPDA with impedance matching. Use of the high speed monolithic TWPDA will allow for more efficient transfer of optical signals within analog circuits and over distances. | 2010-12-30 |
20100327383 | SEMICONDUCTOR DEVICE INCLUDING THROUGH-ELECTRODE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes the following structure. The first insulating film is formed on a first major surface of a semiconductor substrate. The electrode pad is formed in the first insulating film. The electrode pad includes a conductive film. At least a part of the conductive film includes a free region in which the conductive film is not present. The external connection terminal is formed on a second major surface facing the first major surface. The through-electrode is formed in a through-hole formed from the second major surface side of the semiconductor substrate and reaching the electrode pad. The first insulating film is present in the free region, and a step, on a through-electrode side, between the first insulating film being present in the free region and the electrode pad is not greater than a thickness of the electrode pad. | 2010-12-30 |
20100327384 | SOLID-STATE IMAGE DEVICE - Stacked filters are primary color filters and complementary color filters. Thus it is possible to suppress an increase in spectral characteristics and improve the color reproducibility of the primary color filters. | 2010-12-30 |
20100327385 | SEMICONDUCTOR LIGHT-RECEIVING ELEMENT - The Si waveguide | 2010-12-30 |
20100327386 | PHOTODIODE ARRAY, IMAGE PICKUP DEVICE, AND MANUFACTURING METHOD - A photodiode array includes a substrate of a common read-out control circuit; and a plurality of photodiodes arrayed on the substrate and each including an absorption layer, and a pair of a first conductive-side electrode and a second conductive-side electrode. In this photodiode array, each of the photodiodes is isolated from adjacent photodiodes, the first conductive-side electrodes are provided on first conductivity-type regions and electrically connected in common across all the photodiodes, and the second conductive-side electrodes are provided on second conductivity-type regions and individually electrically connected to read-out electrodes of the read-out control circuit. | 2010-12-30 |
20100327387 | Avalanche Photodiode - A photodiode may include a first region comprising substantially intrinsic semiconductor material, the region having a first side and a second side opposite to the first side. The photodiode may also include a second region comprising highly-doped p-type semiconductor material formed proximate to the first side of the first region. The photodiode may additionally include a third region comprising highly-doped n-type semiconductor material formed proximate to the second side of the first region. The photodiode may further include a fourth region comprising one of: (i) highly-doped p-type semiconductor formed between the first region and the third region, or (ii) highly-doped n-type semiconductor formed between the first region and the second region. | 2010-12-30 |
20100327388 | Back-illuminated image sensors having both frontside and a backside photodetectors - A back-illuminated image sensor includes a sensor layer of a first conductivity type having a frontside and a backside opposite the frontside. One or more frontside regions of a second conductivity type are formed in at least a portion of the frontside of the sensor layer. A backside region of the second conductivity type is formed in the backside of the sensor layer. A plurality of frontside photodetectors of the first conductivity type is disposed in the sensor layer. A distinct plurality of backside photodetectors of the first conductivity type separate from the plurality of frontside photodetectors are formed in the sensor layer contiguous to portions of the region of the second conductivity type. A voltage terminal is disposed on the frontside of the sensor layer. One or more connecting regions of the second conductivity type are disposed in respective portions of the sensor layer between the voltage terminal and the backside region for electrically connecting the voltage terminal to the backside region. | 2010-12-30 |
20100327389 | Back-illuminated image sensors having both frontside and backside photodetectors - A back-illuminated image sensor includes a sensor layer of a first conductivity type having a frontside and a backside opposite the frontside. One or more frontside regions of the first conductivity type are formed in at least a portion of the frontside of the sensor layer. A backside region of the first conductivity type is formed in the backside of the sensor layer. A plurality of frontside photodetectors of a second conductivity type is disposed in the sensor layer adjacent to the frontside of the sensor layer. A distinct plurality of backside photodetectors of the second conductivity type separate from the plurality of frontside photodetectors are formed in the sensor layer contiguous to the backside region. One or more or more channel regions of the second conductivity type are disposed in respective portions of the sensor layer between the frontside photodetector and the backside photodetector in each photodetector pair. | 2010-12-30 |
20100327390 | BACK-ILLUMINATED IMAGE SENSOR WITH ELECTRICALLY BIASED CONDUCTIVE MATERIAL AND BACKSIDE WELL - Back-illuminated image sensors include one or more contact implant regions disposed adjacent to a backside of a sensor layer. An electrically conductive material, including, but not limited to, a conductive lightshield, is disposed over the backside of the sensor layer. A backside well is formed in the sensor layer adjacent to the backside, and an insulating layer is disposed over the surface of the backside. Contacts formed in the insulating layer electrically connect the electrically conducting material to respective contact implant regions. At least a portion of the contact implant regions are arranged in a shape that corresponds to one or more pixel edges. | 2010-12-30 |
20100327391 | BACK-ILLUMINATED IMAGE SENSOR WITH ELECTRICALLY BIASED FRONTSIDE AND BACKSIDE - A back-illuminated image sensor includes a sensor layer of a first conductivity type having a frontside and a backside opposite the frontside. One or more regions of a second conductivity type are formed in at least a portion of the sensor layer adjacent to the frontside. The one or more regions are connected to a voltage terminal for biasing these regions to a predetermined voltage. A backside well of the second conductivity type is formed in the sensor layer adjacent to the backside. The backside well is electrically connected to another voltage terminal for biasing the backside well at a second predetermined voltage that is different from the first predetermined voltage. | 2010-12-30 |
20100327392 | BACK-ILLUMINATED IMAGE SENSORS HAVING BOTH FRONTSIDE AND BACKSIDE PHOTODETECTORS - A back-illuminated image sensor includes a sensor layer of a first conductivity type having a frontside and a backside opposite the frontside. An insulating layer is disposed over the backside. A circuit layer is formed adjacent to the frontside such that the sensor layer is positioned between the circuit layer and the insulating layer. One or more frontside regions of a second conductivity type are formed in at least a portion of the frontside of the sensor layer. A backside region of the second conductivity type is formed in the backside of the sensor layer. A plurality of frontside photodetectors of the first conductivity type is disposed in the sensor layer. A distinct plurality of backside photodetectors of the first conductivity type separate from the plurality of frontside photodetectors is formed in the sensor layer contiguous to portions of the backside region of the second conductivity type. | 2010-12-30 |
20100327393 | Method and structures for etching cavity in silicon under dielectric membrane - A semiconductor device includes a semiconductor layer ( | 2010-12-30 |
20100327394 | EM RECTIFYING ANTENNA SUITABLE FOR USE IN CONJUCTION WITH A NATURAL BREAKDOWN DEVICE - A rectenna capable of power conversion from electromagnetic (EM) waves of high frequencies is provided. In one embodiment, a rectenna element generates currents from two sources—based upon the power of the incident EM wave and from an n-type semiconductor, or another electron source attached to a maximum voltage point of an antenna element. The combined current from both sources increases the power output of the antenna, thereby increasing the detection sensitivity of the antenna of a low power signal. Full wave rectification is achieved using a novel diode connected to a gap in the antenna element of an rectenna element. The diode is conductive at a zero bias voltage, and rectifies the antenna signal generated by the desired EM wave received by antenna. Further, the diode may provide a fixed output voltage regardless of the input signal level. The rectenna element of the present invention may be used as a building block to create large rectenna arrays. | 2010-12-30 |
20100327395 | SEMICONDUCTOR DEVICE ON DIRECT SILICON BONDED SUBSTRATE WITH DIFFERENT LAYER THICKNESS - A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices. | 2010-12-30 |
20100327396 | PATTERN STRUCTURE AND METHOD OF FORMING THE SAME - A pattern structure for a semiconductor device includes a plurality of first patterns, each of the first patterns extending in a first direction in the shape of a line, neighboring first patterns being spaced apart from each other by a gap distance, the plurality of first patterns including a plurality of trenches in parallel with the line shapes, respective trenches being between neighboring first patterns, the plurality of trenches including long trenches and short trenches alternately arranged in a second direction substantially perpendicular to the first direction, and at least a second pattern, the second pattern being coplanar with the first pattern, end portions of the first patterns being connected to the second pattern. | 2010-12-30 |
20100327397 | METHOD FOR MANUFACTURING SIMOX WAFER AND SIMOX WAFER - This method for manufacturing a SIMOX wafer includes: forming a mask layer on one surface side of a silicon single crystal wafer, which has an opening on a region where a BOX layer is to be formed; implanting oxygen ions through the opening of the mask layer into the silicon single crystal wafer to a predetermined depth, and locally forming an oxygen implantation region; annealing the silicon single crystal wafer with the mask layer, and oxidizing the oxygen implantation region so as to form the BOX layer; and removing a coated oxide film that covers the whole silicon single crystal wafer which is formed in the annealing of the silicon single crystal wafer, wherein the mask layer has a lamination comprising an oxide film and either one or both of a polysilicon film and an amorphous silicon film. | 2010-12-30 |
20100327398 | DESIGN STRUCTURE AND METHOD FOR BURIED INDUCTORS FOR ULTRA-HIGH RESISTIVITY WAFERS FOR SOI/RF SIGE APPLICATIONS - A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a high resistivity substrate and a buried inductor formed directly in the high resistivity substrate and devoid of an insulating layer therebetween. | 2010-12-30 |
20100327399 | ELECTRICALLY PROGRAMMABLE FUSE USING ANISOMETRIC CONTACTS AND FABRICATION METHOD - An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively. | 2010-12-30 |
20100327400 | FUSE STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor device includes a fuse box including a plurality of fuses and a plurality of common nodes, wherein paired fuses among the plurality of fuses are aligned in a first direction and the plurality of common nodes between fuses of each of the pairs at a different height is aligned in a second direction perpendicular to the first direction. | 2010-12-30 |
20100327401 | FUSE OF SEMICONDUCTOR DEVICE - The present invention relates to a fuse for a semiconductor device, and discloses the technique capable of preventing fuse damage, which might occur during a fuse blowing step, with reducing area of the fuse occupying the semiconductor device. The present invention includes a common source region, wherein a plurality of fuses are radially arranged about the common source region, and a fuse box wall is formed outside the fuses. | 2010-12-30 |
20100327402 | FUSE STRUCTURE FOR HIGH INTEGRATED SEMICONDUCTOR DEVICE - The present invention provides a technology capable of improving an operation reliability of a semiconductor device. Particularly, a fuse material which constitutes the copper can be prevented from migrating being locked in the recesses or the grooves after a blowing process. A semiconductor device includes an insulating layer including a concave-convex-shaped upper part; and a fuse formed on the insulating layer. | 2010-12-30 |
20100327403 | Semiconductor chip, semiconductor wafer, method of manufacturing semiconductor chip - One exemplary embodiment includes a semiconductor chip that has a rectangle principal surface including a first and a second side that oppose each other. A first and a second semiconductor element, and a first and a second wire are formed on the principal surface. The first wire is formed from the first side to reach the second side, and coupled to the first semiconductor element. The second wire is formed to contact at least the first wire, and coupled to the second semiconductor element. Further, an edge part of the first wire on the second side and an edge part of the second wire on the first side are placed to substantially position on a common straight line which is vertical to the first and the second sides. | 2010-12-30 |
20100327404 | INDUCTOR STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - An IC device ( | 2010-12-30 |
20100327405 | ELECTRICAL PROPERTY ALTERING, PLANAR MEMBER WITH SOLDER ELEMENT IN IC CHIP PACKAGE - A structure includes a solder element for electrically coupling a substrate of an integrated circuit (IC) chip package and a printed circuit board (PCB); and a first electrical property altering, substantially planar member positioned between the solder element and at least one of a landing pad of the substrate and a landing pad of the PCB. In another embodiment, the electrical property altering, planar member can be applied to the solder element(s) between the IC chip and the package substrate. | 2010-12-30 |
20100327406 | Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench In Substrate - A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is conformally applied over the substrate and into the trench. An insulating material, such as polymer, is deposited over the first insulating layer in the trench. A first conductive layer is formed over the insulating material. A second insulating layer is formed over the first insulating layer and first conductive layer. A second conductive layer is formed over the second insulating layer and electrically contacts the first conductive layer. The first and second conductive layers are isolated from the substrate by the insulating material in the trench. A third insulating layer is formed over the second insulating layer and second conductive layer. The first and second conductive layers are coiled over the substrate to exhibit inductive properties. | 2010-12-30 |
20100327407 | INTERCONNECTION WIRING STRUCTURE OF A SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A method for manufacturing an interconnection wiring structure of a semiconductor device includes forming an isolation region, which arranges active regions in a diagonal direction, in a semiconductor substrate; forming first damascene trenches, which open upper portions of a bit line contacts, by selectively etching a second interlayer insulation layer; forming bit lines which fill the first damascene trenches; forming second damascene trenches, which expose portions of the active region, by selectively etching the portion of a second interlayer insulation layer between the bit lines and the portion of the first interlayer insulation layer thereunder; attaching trench spacer on side walls of the second damascene trench; forming storage node contact lines which fill the second damascene trenches. | 2010-12-30 |
20100327408 | CARBON/EPOXY RESIN COMPOSITION, AND CARBON-EPOXY DIELECTRIC FILM PRODUCED BY USING THE SAME - A carbon/epoxy composition includes a bisphenol-based epoxy, an amine-based curing agent, an imidazole-based curing catalyst, and carbon black. A carbon-epoxy dielectric layer is fabricated using a reaction product of the carbon/epoxy composition. | 2010-12-30 |
20100327409 | SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENT - A capacitive element formed within a semiconductor device comprises an upper electrode, a capacitive insulating film containing an oxide and/or silicate of a transition metal element, and a lower electrode having a polycrystalline conductive film composed of a material having higher oxidation resistance than the transition metal element and an amorphous or microcrystalline conductive film formed below the polycrystalline conductive film. | 2010-12-30 |
20100327410 | SEMICONDUCTOR DEVICE HAVING A HIGH ASPECT CYLINDRICAL CAPACITOR AND METHOD FOR FABRICATING THE SAME - A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer. | 2010-12-30 |
20100327411 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes a semiconductor substrate, a semiconductor region, a first and second electrodes. The semiconductor region is provided on the semiconductor substrate via an insulating film. The semiconductor region includes a protection diode. An overvoltage causes breakdown of the protection diode. A PN junction of the protection diode is exposed at an end face of the semiconductor region. A first and second electrodes are provided distally to the exposed end face of the PN junction. The first and second electrodes are connected to the semiconductor region to provide a current to the protection diode. | 2010-12-30 |
20100327412 | METHOD OF SEMICONDUCTOR MANUFACTURING FOR SMALL FEATURES - Small feature patterning is accomplished using a multilayer hard mask (HM). Embodiments include sequentially forming a first HM layer and a multilayer HM layer over a substrate, the multilayer HM layer comprising sublayers, etching the multilayer HM layer to form a first opening having an upper first opening with sides converging to a lower second opening and a second opening with substantially parallel sides and an opening substantially corresponding to the lower second opening of the first opening, etching through the second opening to form a corresponding opening in the first HM layer, and etching the substrate through the corresponding opening in the first HM layer. | 2010-12-30 |
20100327413 | HARDMASK OPEN AND ETCH PROFILE CONTROL WITH HARDMASK OPEN - A method for opening a carbon-based hardmask layer formed on an etch layer over a substrate is provided. The hardmask layer is disposed below a patterned mask. The substrate is placed in a plasma processing chamber. The hardmask layer is opened by flowing a hardmask opening gas including a COS component into the plasma chamber, forming a plasma from the hardmask opening gas, and stopping the flow of the hardmask opening gas. The hardmask layer may be made of amorphous carbon, or made of spun-on carbon, and the hardmask opening gas may further include O | 2010-12-30 |
20100327414 | Method For Producing A Semiconductor Wafer - Semiconductor wafers are produced by a process of:
| 2010-12-30 |
20100327415 | SILICON EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF - Provided is a method for manufacturing a silicon epitaxial wafer by growing an epitaxial layer by placing a silicon substrate on a susceptor. The method includes at least a step of forming a silicon oxide film entirely on the rear surface of the silicon substrate; a step of removing the silicon oxide film formed at least on an edge section of the silicon substrate; and a step of placing the silicon substrate on the susceptor with the silicon oxide film in between. An epitaxial layer is grown on the silicon substrate, while holding the silicon substrate by the susceptor with the silicon oxide film in between. Thus, the silicon epitaxial wafer by which generation of particles can be reduced in a device manufacturing process and a method for manufacturing such silicon epitaxial wafer are provided. | 2010-12-30 |
20100327416 | Laser beam machining method, laser beam machining apparatus, and laser beam machining product - It is an object to provide a laser beam machining method which can easily cut a machining target. The laser beam machining method irradiates laser light while positioning a focus point at the inside of a machining target to thereby form a treated area based on multiphoton absorption along a planned cutting line of the machining target inside the machining target and also form a minute cavity at a predetermined position corresponding to the treated area in the machining target. | 2010-12-30 |
20100327417 | ELECTRONIC DEVICE HAVING A MOLDING COMPOUND INCLUDING A COMPOSITE MATERIAL - An electronic device includes a packaged integrated circuit having an integrated circuit die having an active surface, and a molding compound overlaying the active surface of the integrated circuit die. In a particular embodiment, the packaged integrated circuit includes at least approximately five weight percent (5 wt %) zinc relative to the molding compound. In another embodiment, the packaged integrated circuit includes approximately 0.3 μmol/cm | 2010-12-30 |
20100327418 | INTEGRATED CIRCUIT PACKAGE SYSTEM USING HEAT SLUG - An integrated circuit package system includes a substrate having an integrated circuit die thereon; a heat slug having a tie bar, the tie bar having characteristics of singulation from an adjacent heat slug; and an encapsulant molded on the substrate, the heat slug, and the integrated circuit die includes the encapsulant which fills all of the space between the integrated circuit die and the heat slug. | 2010-12-30 |
20100327419 | Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same - A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer. | 2010-12-30 |
20100327420 | SEMICONDUCTOR DEVICE WITH EMBEDDED INTERCONNECT PAD - A semiconductor device comprising: a lower semiconductor package that comprises a first set of one or more semiconductor dies, an upper semiconductor package that is stacked on the lower semiconductor package, the upper semiconductor package comprises a second set of one or more semiconductor dies, and a first interconnect pad that is embedded in a top side of the lower semiconductor package to couple the upper semiconductor package to the lower semiconductor package. | 2010-12-30 |
20100327421 | IC PACKAGE DESIGN WITH STRESS RELIEF FEATURE - A protective structure is provided on a substrate to which a semiconductor die is attached. The protective structure surrounds the die and reduces the thermo-mechanical stresses to which the die is subject. The die is protected against cracking, warping, and delamination. | 2010-12-30 |
20100327422 | SEMICONDUCTOR CHIP, METHOD OF FABRICATING THE SAME, AND STACK MODULE AND MEMORY CARD INCLUDING THE SAME - A semiconductor chip, a method of fabricating the same, and a stack module and a memory card including the semiconductor chip include a first surface and a second surface facing the first surface is provided. At least one via hole including a first portion extending in a direction from the first surface of the substrate to the second surface of the substrate and a second portion that is connected to the first portion and has a tapered shape. At least one via electrode filling the at least one via hole is provided. | 2010-12-30 |
20100327423 | SEMICONDUCTOR PACKAGING STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a method and semiconductor packaging structure comprising a conductive substrate having a first surface, a first lateral surface and a second lateral surface adjacent to the first surface. A first electrode line with two ends are provided on the first surface and the first lateral surface, and a second electrode line with two ends are provided on the first surface and a second lateral surface respectively. A semiconductor device is provided on the first surface of the conductive substrate which electrically connected to the first electrode line and the second electrode line, a protective plate with through holes covers the first surface, and a sheathing overlays the semiconductor device. | 2010-12-30 |
20100327424 | Multi-chip package and method of providing die-to-die interconnects in same - A multi-chip package includes a substrate ( | 2010-12-30 |
20100327425 | FLAT CHIP PACKAGE AND FABRICATION METHOD THEREOF - A flat chip package comprises an encapsulation body, a plurality of connecting fingers, a plurality of conductive lines, a chip, a plurality of bond wires and an insulation layer. The conductive lines, the chip, and the bond wires are encapsulated in the encapsulation body. The connecting fingers comprise a ground finger, a power finger and at least one signal finger. One side of the connecting fingers adheres to a surface of the encapsulation body, the other side of the connecting fingers is left exposed. The conductive lines comprise a ground line connected to the ground finger, and a power line connected to the power finger. The chip comprises a ground pin, a power pin and at least one signal pin. The bond wires connect the connecting fingers, the conductive lines and the chip. The insulation layer is printed on the surface of the encapsulation body except for the connecting fingers. | 2010-12-30 |
20100327426 | Semiconductor chip package and method of manufacturing the same - Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip including a first face having a chip pad, a second face facing the first face, and a side face connecting the first and second faces, a first lamination layer covering the second face and a portion of the side face, a second lamination layer disposed on a top surface of the first lamination layer and forming a gap having a predetermined distance from the side face, and a redistribution pattern disposed on the first face and electrically connected to the chip pad. The semiconductor package and the method of manufacturing the same achieve a high process yield and reliability. | 2010-12-30 |
20100327427 | Semiconductor device and method for manufacturing the same - A semiconductor device includes a wiring layer, a semiconductor chip which is arranged on the wiring layer with a gap there between, the semiconductor chip being electrically connected to the wiring layer through a connecting portion, a first sealing member which is filled in a space between the wiring layer and the semiconductor chip, and a second sealing member which coats the semiconductor chip. The first sealing member and the second sealing member include same organic resin, the organic resin including inorganic filler. The second sealing member has larger content of inorganic filler than the first sealing member. | 2010-12-30 |
20100327428 | PACKAGE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method for manufacturing a package comprises a first step of forming a metal pattern including a frame and a plurality of leads extending inward from the frame, a second step of molding a resin pattern including a first resin portion which holds the plurality of leads from an inner side thereof, and second resin portions which cover bottom surfaces of peripheral portions, adjacent to portions to be removed, in the plurality of leads while exposing bottom surfaces of the portions to be removed in the plurality of leads, so as to hold the plurality of leads from a lower side thereof, and a third step of cutting the plurality of leads into a plurality of first leads and a plurality of second leads by removing the portions to be removed in the plurality of leads while the resin pattern keeps holding the peripheral portions in the plurality of leads. | 2010-12-30 |
20100327429 | SEMICONDUCTOR PACKAGE STRUCTURE AND PACKAGE METHOD THEREOF - A semiconductor package structure and a package method thereof are provided. The semiconductor package structure includes a substrate, a sensing chip, a first patterned conductive layer and a electrical connection portion. The substrate has an accommodating portion, a first surface and a second surface opposite to the first surface. The accommodating portion are extended to the second surface from the first surface. | 2010-12-30 |
20100327430 | SEMICONDUCTOR DEVICE ASSEMBLY HAVING A STRESS-RELIEVING BUFFER LAYER - Disclosed is a multilayer thermal interface material which includes a first layer of metallic thermal interface material, a buffer layer and preferably a second layer of thermal interface material which may be metallic or nonmetallic. The multilayer thermal interface material is used in conjunction with a semiconductor device assembly of a chip carrier substrate, a heat spreader for attaching to the substrate, a semiconductor device mounted on the substrate and underneath the heat spreader and the multilayer thermal interface material interposed between the heat spreader and the semiconductor device. The heat spreader has a first coefficient of thermal expansion (CTE), CTE | 2010-12-30 |
20100327431 | Semiconductor Chip Thermal Interface Structures - Various thermal interface structures and methods are disclosed. In one aspect, a method of manufacturing is provided. The method includes providing plural carbon nanotubes in a thermal interface structure. The thermal interface structure is soldered to a side of a semiconductor chip. In another aspect, an apparatus is provided. The apparatus includes a thermal interface structure that has plural carbon nanotubes. A semiconductor chip is soldered to the thermal interface structure. | 2010-12-30 |
20100327432 | PACKAGE WITH HEAT TRANSFER - A semiconductor package includes an encapsulant, a semiconductor device within the encapsulant, and one or more terminals for electrically coupling the semiconductor device to a node exterior to the package. The package further includes bonding means coupling the semiconductor device to the one or more terminals. The semiconductor package is configured to dissipate heat through a top surface of the package. To directly dissipate heat via the top surface of the package, a thermally conductive layer is coupled to the semiconductor device, and the layer is exposed at a surface of the package. | 2010-12-30 |
20100327433 | High Density MIM Capacitor Embedded in a Substrate - An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor. | 2010-12-30 |
20100327434 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: a first semiconductor chip having a first active surface and a bonding surface forming an opposite side of the first active surface, the bonding surface being bonded to a mounting surface of a substrate; a second semiconductor chip having a second active surface facing the first active surface, and stacked on the first semiconductor chip; a slope section having a sloping surface with a shape of smoothing a step between the first active surface and the mounting surface, and adapted to bury the step in at least a part of a periphery of the first semiconductor chip; and a first wiring wire laid down between the mounting surface and the first active surface via the sloping surface of the slope section, and connected to a first bump provided to the second active surface on the first active surface. | 2010-12-30 |
20100327435 | ELECTRONIC COMPONENT AND MANUFACTURE METHOD THEREOF - An electronic component includes a package substrate, a plurality of conductive pads, an insulating material and a semiconductor device. The plurality of conductive pads is disposed on the package substrate. The insulating material is disposed between the plurality of conductive pads. The insulating material includes a top surface located on an identical plane to an upper surface of the plurality of conductive pads. The semiconductor device includes a conductive bump aligned on a corresponding conductive pad of the plurality of conductive pads. | 2010-12-30 |
20100327436 | APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUITS - A multi-chip stack module provides increased circuit density for a given surface chip footprint. Support structures are alternated with standard surface mount type chips to form a stack wherein the support structures electrically interconnect the chips. One aspect is a structure and method for interconnecting a plurality of generally planar chips in a vertical stack such that signals, which are common to the chips, are connected in the stack and signals, which are accessed individually, are separated within the stack. | 2010-12-30 |
20100327437 | WIRING BOARD AND SEMICONDUCTOR DEVICE USING THE WIRING BOARD - Provided is a wiring board wherein a circuit is not short-circuited when a IC chip is mounted on the wiring board. A wiring board ( | 2010-12-30 |
20100327438 | NEAR CHIP SCALE SEMICONDUCTOR PACKAGES - Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die. | 2010-12-30 |
20100327439 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME - A semiconductor package includes a first package substrate, a first semiconductor chip disposed on the first package substrate, the semiconductor chip including first through hole vias, and a chip package disposed on the first semiconductor chip, the chip package including a second package substrate and a second semiconductor chip disposed on the second package substrate, wherein a first conductive terminal is disposed on a first surface of the semiconductor chip and a second conductive terminal is disposed on a first surface of the second package substrate, the first conductive terminal disposed on the second conductive terminal. | 2010-12-30 |
20100327440 | 3-D SEMICONDUCTOR DIE STRUCTURE WITH CONTAINING FEATURE AND METHOD - A die-on-die assembly has a first die ( | 2010-12-30 |
20100327441 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND WIRING STRUCTURE - A semiconductor device includes a semiconductor package, a circuit board, an interconnection electrically connecting the semiconductor package and the circuit board, and a wiring structure. The wiring structure includes a through hole, a contact disposed at the through hole and a lead pattern extending from the contact. The wiring structure is disposed between the semiconductor package and the circuit board. The interconnection passes through the through hole and connects with the contact. | 2010-12-30 |
20100327442 | Package and the Method for Making the Same, and a Stacked Package - The present invention relates to a package and the method for making the same, and a stacked package. The method for making the package includes the following steps: (a) providing a carrier having a plurality of platforms; (b) providing a plurality of dice, and disposing the dice on the platforms; (c) performing a reflow process so that the dice are self-aligned on the platforms; (d) forming a molding compound in the gaps between the dice, and (e) performing a cutting process so as to form a plurality of packages. Since the dice are self-aligned on the platforms during the reflow process, a die attach machine with low accuracy can achieve highly accurate placement. | 2010-12-30 |
20100327443 | JOINING STRUCTURE AND A SUBSTRATE-JOINING METHOD USING THE SAME - The present invention concerns a joining structure and a substrate-joining method using the same. The joining structure comprises a substrate, and comprises a plurality of joining patterns which are located on the said substrate and which are spaced apart from each other. The substrate-joining method using the joining structure can comprise: a stage involving the formation of a plurality of joining patterns which are spaced apart from each other on a first substrate; and a stage of joining a second substrate on the plurality of joining patterns. When the said joining structure is employed, it is possible to reduce or prevent damage due to spreading of the joining substance during joining of the two substrates. | 2010-12-30 |
20100327444 | SHEET STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD OF GROWING CARBON STRUCTURE - The sheet structure includes a plurality of linear structure bundles including a plurality of linear structures of carbon atoms arranged at a first gap, and arranged at a second gap larger than the first gap, a graphite layer formed in a region between the plurality of linear structure bundles and connected to the plurality of linear structure bundles, and a filling layer filled in the first gap and the second gap and retaining the plurality of linear structure bundles and the graphite layer. | 2010-12-30 |
20100327445 | STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME - An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided. | 2010-12-30 |
20100327446 | VIA GOUGED INTERCONNECT STRUCTURE AND METHOD OF FABRICATING SAME - An interconnect structure including a gouging feature at the bottom of a via opening and a method of forming the same are provided. The method of the present invention does not disrupt the coverage of the deposited trench diffusion barrier in a line opening that is located atop the via opening, and/or does not introduce damages caused by creating a gouging feature at the bottom of the via opening by sputtering into the interconnect dielectric material that includes the via and line openings. Such an interconnect structure is achieved by providing a gouging feature in the bottom of the via opening by first forming the line opening within the interconnect dielectric, followed by forming the via opening and then the gouging feature. | 2010-12-30 |
20100327447 | Method of manufacturing semiconductor device and semiconductor device - A method of manufacturing a semiconductor device includes forming a barrier metal film including a high melting point metal in a concave portion formed in an insulating film formed over a substrate; forming a seed alloy film including copper and an impurity metal different from the copper over the barrier metal film so as to fill a portion of the concave portion; forming a plated metal film containing copper as a major ingredient over the seed alloy film so as to fill the concave portion; first heat-treating the seed alloy film and the plated metal film at 200° C. or higher and for ten minutes or less; removing the plated metal film, the seed alloy film, and the barrier metal film which are exposed to the outside of the concave portion, after the first heat-treating; and second heat-treating the seed alloy film and the plated metal film. | 2010-12-30 |
20100327448 | Semiconductor with Bottom-Side Wrap-Around Flange Contact - A packaging technique for electronic devices includes wafer fabrication of flexible contacts on the bottom surface of the substrate underneath the active circuit. Inherently reliable contacts suitable for a variety of devices can be formed via a simple fabrication process with good wafer packing density. For one embodiment, a trench is formed from the back of the substrate, exposing an upper conductive layer on the top surface. A standoff is formed on the bottom surface of the substrate. A lower conductive layer is formed that runs from and electrically connects with the exposed portion of the upper conductive layer onto the substrate standoff. The standoff is removed, releasing the formed conductors, resulting in a flexible contact. | 2010-12-30 |
20100327449 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %. | 2010-12-30 |
20100327450 | SEMICONDUCTOR DEVICE BONDING WIRE AND WIRE BONDING METHOD - It is an object of the present invention to provide a copper-based bonding wire whose material cost is low, having excellent ball bondability, reliability in a heat cycle test or reflow test, and storage life, enabling an application to thinning of a wire used for fine pitch connection. The bonding wire includes a core material having copper as a main component and an outer layer which is provided on the core material and contains a metal M and copper, in which the metal M differs from the core material in one or both of components and composition. The outer layer is 0.021 to 0.12 μm in thickness. | 2010-12-30 |
20100327451 | ALIGNMENT MARK - An alignment mark for defect inspection is disclosed. The alignment mark includes: a semiconductor substrate; a first type well disposed in the semiconductor substrate; a second type doping region disposed in the first type well; a dielectric layer disposed on the semiconductor substrate to cover the first type well and the second type doping region; and a plurality of conductive plugs formed in the dielectric layer for connecting to the second type doping region. | 2010-12-30 |
20100327452 | MOUNTING STRUCTURE AND METHOD OF MANUFACTURING THE SAME - To provide a mounting structure having a substrate and a semiconductor package mounted thereon which enables suppression of unnecessary electromagnetic radiation and improvement of drop impact resistance, and a method of manufacturing the same. A substrate | 2010-12-30 |
20100327453 | Semiconductor Device and Method of Manufacturing the Same - A semiconductor device comprises a first substrate in which a first memory cell array is formed, a second substrate in which a second memory cell array, a page buffer, and decoders are formed, and a coupling structure formed on the first and second substrates and configured to have the page buffer and the decoders operated in conjunction with the first and second memory cell arrays. The second substrate is adhered over the first substrate. | 2010-12-30 |
20100327454 | SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE - There is provided a semiconductor device including: an insulating layer provided on a substrate and formed with plural cavities; wiring lines provided on the insulating layer; plural branched wiring lines that branch from the wiring lines so as to respectively overlap with the plural cavities when seen in plan view; a conductive portion formed on the wiring lines; an external terminal formed on the conductive portion; and a sealing resin layer that seals the wiring lines and the conductive portion. | 2010-12-30 |
20100327455 | Semiconductor device including two heat sinks and method of manufacturing the same - A semiconductor device includes a semiconductor element, a first heat sink, a second heat sink, and a resin member. The semiconductor element has first and second surfaces. The first heat sink has a first heat radiation surface and a first end surface. The first end surface is coupled with the first surface. The second heat sink has a second heat radiation surface, the second end surface being opposite the second heat radiation surface, and a depressed section depressed toward the second heat radiation surface. The second surface of the semiconductor element is coupled with a bottom surface of the depressed section. The resin member is disposed in the depressed section and seals the semiconductor element, the first heat sink, and the second heat sink in such a manner that the first heat radiation surface is exposed outside the resin member. | 2010-12-30 |
20100327456 | Process for Improving the Reliability of Interconnect Structures and Resulting Structure - An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate. | 2010-12-30 |
20100327457 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - To provide a semiconductor chip whose number of electrodes are minimized while the horizontal position between the semiconductor chip and the mounted substrate is maintained in implementation to avoid any connection problem, as well as to prevent the damage to the semiconductor circuit of such chip. | 2010-12-30 |
20100327458 | Semiconductor device - There is provided a semiconductor device including: a metal wiring line formed on a semiconductor substrate; an inside chamfer provided only at the inside of a bend in the metal wiring line, widening the wiring line width at the inside of the bend; and a protection film covering the metal wiring line. | 2010-12-30 |
20100327459 | SEMICONDUCTOR DEVICE HAVING PLURALITY OF WIRING LAYERS AND DESIGNING METHOD THEREOF - A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. According to the present invention, because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. Therefore, the flexibility of the layout of the second wiring layer is enhanced and the restriction on the wiring density can be relaxed. | 2010-12-30 |
20100327460 | CAPACTIVE CONNECTORS WITH ENHANCED CAPACITIVE COUPLING - A single-chip module (SCM) and a multi-chip module (MCM) that includes at least two instances of the SCM are described. The SCM includes a pad disposed on a substrate. This pad has a top surface that includes a pattern of features. A given feature in the pattern of features has a height that extends above a minimum thickness of the pad, thereby increasing a capacitance associated with the pad relative to a configuration in which the top surface is planar. Furthermore, pads disposed on the two instances of the SCM in the MCM may each have a corresponding pattern of features that increases the capacitive coupling between the pads relative to a configuration in which the top surfaces of either or both of the pads are planar. Note that the pads may be aligned such that features in the patterns of features on these pads are interdigited with each other. | 2010-12-30 |
20100327461 | Electrical interconnect for die stacked in zig-zag configuration - A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support. Die in the first tier are electrically interconnected die-to-die, and the tier is electrically connected to a support, by traces of an electrically conductive material contacting interconnect pads on the die and a first set of bond pads on the support. Pillars of a electrically conductive material are formed on a second set of bond pads, and die in the second tier are electrically interconnected die-to-die, and the tier is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the substrate. | 2010-12-30 |
20100327462 | METHODS FOR WAFER-LEVEL PACKAGING OF MICROFEATURE DEVICES AND MICROFEATURE DEVICES FORMED USING SUCH METHODS - Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other. | 2010-12-30 |
20100327463 | STACKED STRUCTURES AND METHODS OF FABRICATING STACKED STRUCTURES - A stacked structure includes a first substrate bonded to a second substrate such that a first pad structure of the first substrate contacts a second pad structure of the second substrate. A transistor gate is formed over the second substrate, and a first conductive structure extends through the second substrate and has a top surface that is substantially planar with a top surface of the second substrate. An interlayer dielectric (ILD) layer is disposed over the transistor gate, and a passivation layer is disposed over the ILD layer and includes a second pad structure that makes electrical contact with the second conductive structure. The ILD layer includes at least one contact structure that extends through the ILD layer and makes electrical contact with the transistor gate. A second conductive structure is disposed in the ILD layer and is at least partially disposed over a surface of the first conductive structure. | 2010-12-30 |
20100327464 | Layered chip package - A layered chip package includes a main body including a plurality of layer portions, and wiring disposed on a side surface of the main body. Each layer portion includes a semiconductor chip, an insulating portion covering at least one side surface of the semiconductor chip, and a plurality of electrodes connected to the semiconductor chip. The insulating portion has an end face located at the side surface of the main body on which the wiring is disposed. Each electrode has an end face surrounded by the insulating portion and located at the side surface of the main body on which the wiring is disposed. | 2010-12-30 |
20100327465 | PACKAGE PROCESS AND PACKAGE STRUCTURE - A package process is provided. First, a semiconductor substrate is disposed on a carrier, in which a surface of the carrier has an adhesive layer and the semiconductor substrate is bonded to the carrier by the adhesive layer. Next, a chip is bonded on the semiconductor substrate by flip chip technique and a first underfill is formed between the chip and the semiconductor substrate to encapsulate a plurality of first conductive bumps at the bottom of the chip. Then, a first molding compound is formed on the semiconductor substrate. The first molding compound at least encapsulates the side surface of the chip and the first underfill. Finally, the semiconductor substrate together with the chip and the first molding compound located thereon are separated from the adhesive layer of the carrier to form an array package structure. | 2010-12-30 |
20100327466 | TECHNIQUE FOR FABRICATING MICROSPRINGS ON NON-PLANAR SURFACES - A processing technique facilitating the fabrication of the integrated circuit with microsprings at different vertical positions relative to a surface of a substrate is described. During the fabrication technique, microsprings are lithographically defined on surfaces of a first substrate and a second substrate. Then, a hole is created through a first substrate. Moreover, the integrated circuit may be created by rigidly mechanically coupling the two substrates to each other such that the microsprings on the surface of the second substrate are within a region defined at least in part by an edge around the hole. Subsequently, photoresist that constrains the microsprings on the surfaces of the two substrates may be removed. In this way, microsprings at the different vertical positions can be fabricated. | 2010-12-30 |
20100327467 | Method of processing dummy pattern based on boundary length and density of wiring pattern, semiconductor design apparatus and semiconductor device - A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. | 2010-12-30 |