52nd week of 2011 patent applcation highlights part 63 |
Patent application number | Title | Published |
20110320785 | Binary Rewriting in Software Instruction Cache - Mechanisms are provided for dynamically rewriting branch instructions in a portion of code. The mechanisms execute a branch instruction in the portion of code. The mechanisms determine if a target instruction of the branch instruction, to which the branch instruction branches, is present in an instruction cache associated with the processor. Moreover, the mechanisms directly branch execution of the portion of code to the target instruction in the instruction cache, without intervention from an instruction cache runtime system, in response to a determination that the target instruction is present in the instruction cache. In addition, the mechanisms redirect execution of the portion of code to the instruction cache runtime system in response to a determination that the target instruction cannot be determined to be present in the instruction cache. | 2011-12-29 |
20110320786 | Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction - Mechanisms are provided for evicting cache lines from an instruction cache of the data processing system. The mechanisms store, for a portion of code in a current cache line, a linked list of call sites that directly or indirectly target the portion of code in the current cache line. A determination is made as to whether the current cache line is to be evicted from the instruction cache. The linked list of call sites is processed to identify one or more rewritten branch instructions having associated branch stubs, that either directly or indirectly target the portion of code in the current cache line. In addition, the one or more rewritten branch instructions are rewritten to restore the one or more rewritten branch instructions to an original state based on information in the associated branch stubs. | 2011-12-29 |
20110320787 | Indirect Branch Hint - A processor implements an apparatus and a method for predicting an indirect branch address. A target address generated by an instruction is automatically identified. A predicted next program address is prepared based on the target address before an indirect branch instruction utilizing the target address is speculatively executed. The apparatus suitably employs a register for holding an instruction memory address that is specified by a program as a predicted indirect address of an indirect branch instruction. The apparatus also employs a next program address selector that selects the predicted indirect address from the register as the next program address for use in speculatively executing the indirect branch instruction. | 2011-12-29 |
20110320788 | METHOD AND APPARATUS FOR BRANCH REDUCTION IN A MULTITHREADED PACKET PROCESSOR - A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a configuration bit vector wherein each bit in the configuration bit vector corresponds to a respective feature. When said branch flag returns a first result processing is continues at an instruction located at a first location relative to a Program Counter (PC) and when the branch flag returns a second result processing is continued at a second location relative to said PC. | 2011-12-29 |
20110320789 | Method and Apparatus for High Performance Cache Translation Look-Aside Buffer TLB Lookups Using Multiple Page Size Prediction - A computer processing system method and apparatus having a processor employing an operating system (O/S) multi-task control between multiple user programs and which ensures that the programs do not interfere with each other, said computing processing system having a branch multiple page size prediction mechanism which predicts a page size along with a branch direction and a branch target of a branch for instructions of a processing pipeline, having a branch target buffer (BTB) predicting the branch target, said branch prediction mechanism storing recently used instructions close to the processor in a local cache, and having a translation look-aside buffer TLB mechanism which tracks the translation of the most recent pages and supports multiple page sizes. | 2011-12-29 |
20110320790 | Link Stack Repair of Erroneous Speculative Update - Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer. | 2011-12-29 |
20110320791 | Method and Apparatus to Limit Millicode Routine End Branch Prediction - A computing system method, program and hardware for correlation of millicode predictions with specific millicode routines receives architected millicode and stores the millicode in internal memory. The computer systems processors' pipeline is employed to predict and select a branch target buffer's (BTB) target address. A computer millicode control enabling an operating system (O/S) multi-task control between multiple user programs able to use millicode routines and ensuring that the programs do not interfere with each other, by use of a branch target buffer (BTB) prediction of a branch target to ensure that a millicode routine does not fetch outside of said millicode routine while performing operations as required by said millicode routing, said branch target buffer prediction employing a correlation mechanism for predicting millicoded branch millicode entry and millicode end instructions and for correlating millicode end predictions with specific millicode routines. | 2011-12-29 |
20110320792 | STATE MACHINE-BASED FILTERING OF PATTERN HISTORY TABLES BASED ON DISTINGUISHABLE PATTERN DETECTION - Machine-based filtering of a pattern history table includes identifying a matching previous occurrence of a current branch instruction in an address history vector (AHV), the AHV storing addresses, or partial addresses, of most recently occurring branch instructions. In response to determining a direction history of the previous occurrence matches a direction history of the current branch, the machine-based filtering includes comparing the outcome of the previous occurrence with the outcome of the current branch instruction, and preventing the pattern history table from being updated with the outcome of the current branch instruction when the outcome of the previous occurrence does not match the outcome of the current branch instruction. | 2011-12-29 |
20110320793 | OPERATING SYSTEM AWARE BRANCH PREDICTOR USING A DYNAMICALLY RECONFIGURABLE BRANCH HISTORY TABLE - A processor resource manager assigns a branch history resource to a first execution mode. The branch history resource is utilized for predicting a branch direction of a branch instruction. Next, the resource manager logs a number of branch mispredictions that occur while the processor executes a second execution mode. The resource manager, in turn, reassigns the branch history resource to the second execution mode based upon the number of branch mispredictions. | 2011-12-29 |
20110320794 | Flash System And Method For Updating The Flash System - A FLASH system includes two system image partitions each storing an updating program, a first boot variable partition storing a first boot variable, a second boot variable partition storing a second boot variable, and a bootloader partition storing a bootloader program. The updating program checks whether the first boot variable is valid or not, and selects which system image partition to be updated according to the first boot variable. The updating program further checks whether the FLASH system is successfully updated or not so as to report back a failure or modify the value of the first boot variable and then copy all data of the first boot variable partition to replace those of the second boot variable partition. The bootloader program checks whether the first boot variable is valid or not, and selects which system image partition to be booted according to the first boot variable. | 2011-12-29 |
20110320795 | POWER MANAGEMENT USING CONSTRAINTS IN MULTI-DIMENSIONAL PARAMETER SPACE - An embodiment of a method and system are provided for managing both system resources and power consumption of a computer system, involving different layers of the system: an application layer, a middle layer where the operating system is running and where a power manager is provided, and a hardware layer used for communicating with the hardware devices. Hardware devices have different operating modes which provide distinct trade-offs between performances and power consumption. Performance requirements defined at the level of the application layer, as well as the device power status of the system, set constraints on the system resources. The middle layer power manager may be in charge of retrieving performance requirements in form of constraints set on system parameters, aggregating these constraints opportunely and communicating corresponding information to the device drivers which may then select a best operating mode. | 2011-12-29 |
20110320796 | REDUNDANT POWER SUPPLY CONFIGURATION FOR A DATA CENTER - A redundant power supply configuration for a data center is provided. A method includes receiving instructions to operate power supplies at a high current mode. An individual current for each of the power supplies is calculated to total a high current at the high current mode. The power supplies are operated at the high current mode to provide the high current at the high current mode. In response to operation at the high current mode being complete, the power supplies are operated at a normal mode to provide a normal current at the normal current mode. | 2011-12-29 |
20110320797 | METHOD AND SYSTEM FOR REDUCING AN IMPACT OF MALWARE DURING A BOOTING SEQUENCE - Methods for reducing the impact of malware during a booting sequence for an interrupt driven computing device are disclosed. One or more parameters associated with an interrupt vector table (IVT) are manipulated to force the computing device into a clean state following a system level portion of the booting sequence. In another embodiment, occurring prior to the loading of an operating system or a call to a non-returnable main( ) function, one or more unused interrupt vectors in an IVT are replaced. A function filter is implemented for one or more interrupt vectors in the IVT to disallow unnecessary interrupt functions from being executed. One or more required interrupt vector functions are replaced with one or more corresponding custom vector functions. One or more memory locations are wiped if the one or more memory locations do not hold at least a portion of the IVT and/or the interrupt vector functions. | 2011-12-29 |
20110320798 | Providing Silicon Integrated Code For A System - In one embodiment, a semiconductor integrated code (SIC) may be provided in a binary format by a processor manufacturer. This SIC may include platform independent code of the processor manufacturer. Such code may include embedded processor logic to initialize the processor and at least one link that couples the processor to a memory, and embedded memory logic to initialize the memory. Other embodiments are described and claimed. | 2011-12-29 |
20110320799 | APPARATUS AND METHOD FOR NETWORK DRIVER INJECTION INTO TARGET IMAGE - A method provides network driver injection into a target image to transform the target image to be compatible with one or more source machines, for facilitating operating system streaming over a network. The method may include: facilitating access to a source system registry file of a source machine; facilitating access to a target system registry file of the target image, without copying the target image; determining whether source network interface cards of the source machine are compatible with the target image; and if the source network interface cards are not compatible with the target image, performing network interface driver injection into the target image. The target image may include an operating system. A machine-readable storage medium and apparatus are provided. A method is described for building a program for providing network driver injection into a target image to transform the target image to be compatible with computing machines. | 2011-12-29 |
20110320800 | System And Method For Booting A Computer System Using Preboot Data - Exemplary embodiments of the present invention disclosed herein relate to a method of booting a computer system using preboot data. A method in accordance with an exemplary embodiment of the present invention comprises transmitting a boot request and receiving, in response to the boot request, a boot loader that is adapted to read preboot data. The exemplary method may additionally comprise transmitting a request for boot data corresponding to the preboot data, receiving boot data corresponding to the preboot data, and booting the computer system using the boot data. | 2011-12-29 |
20110320801 | INFORMATION PROCESSING APPARATUS AND START-UP METHOD - An information processing apparatus includes, a processer, a non-volatile memory to store a plurality of programs, a volatile memory to store at least one program executed by the processor and data accessed by the program, an acceptance unit to accept context information when power supplied to the processor is resumed from a state in which power supplied to the processor is interrupted while a power supplied to the volatile memory is maintained, a selection unit to select one program from the plurality of programs stored in the non-volatile memory based on context information accepted by the acceptance unit, and a program determination unit to determine whether the one program selected by the selection unit is stored in the volatile memory. When the processor determines the one program selected by the program determination unit is stored in the volatile memory, the processor starts the one program stored in the volatile memory. | 2011-12-29 |
20110320802 | AUTHENTICATION METHOD, KEY DISTRIBUTION METHOD AND AUTHENTICATION AND KEY DISTRIBUTION METHOD - An authentication method, and a key distribution method, and an authentication and key distribution method are provided. The authentication method is adapted for a machine type communication involved with a wireless communication system, and includes the following steps. At least a user equipment (UE) transmits an application request including at least a first security material to a network application function (NAF), where the at least a first security material is not a key directly obtained through a bootstrapping procedure of a generic bootstrapping architecture. The NAF generates a second security material, which is not the key, either. The NAF replies the UE an application answer with the at least a second security material. In addition, the NAF authenticates the UE by the second security material, or the UE authenticates the NAF by the second security material. | 2011-12-29 |
20110320803 | Light-weight security solution for host-based mobility & multihoming protocols - A transport connection system is set forth. The system includes a first device adapted to send and receive messages. A second device, adapted to send and receive message, is also provided. A message i generated by the first device includes a secret Ri- | 2011-12-29 |
20110320804 | DATA ACCESS MANAGEMENT IN A HYBRID MEMORY SERVER - A method, accelerator system, and computer program access data in an out-of-core processing environment. A data access configuration is received from a server system managing a plurality of data sets. A determination is made that data sets retrieved from the server system are to be stored locally based on the data access configuration. A request to interact with a given data set is received from a user client. At least a portion of the given data set is retrieved from the server system. The at least a portion of the given data set is stored locally a memory based on the data access configuration that has been received. | 2011-12-29 |
20110320805 | SECURE SHARING OF DATA ALONG SUPPLY CHAINS - Implementations of methods of sharing data in a supply chain, the data corresponding to an item having a tag associated therewith, include generating data corresponding to the item, generating a data reference, encrypting the data using an encryption key to provide encrypted data, transmitting the encrypted data over a network for storage in a database based on the data reference, writing the data reference and the encryption key to the tag, and transferring the item to a successor in the supply chain. Implementations include retrieving information electronically stored on the tag, the information comprising a data reference and an encryption key, transmitting a data request over a network for retrieving encrypted data from a database, the data request comprising the data reference, receiving the encrypted data from the database, and decrypting the encrypted data using the encryption key to provide decrypted data. | 2011-12-29 |
20110320806 | SYSTEM AND METHOD FOR MODULUS OBFUSCATION - Disclosed herein are methods for obfuscating data via a modulus operation. A client device receives input data, stores an operation value, performs a modulus obfuscation on the operation value, performs a modulus operation on the operation value and the input data, performs a modulus transformation on the operation value and the input data to obtain client output data, and checks if the client output data matches corresponding server output data. A corresponding server device receives input data, performs a modulus transformation on the input data to obtain a result, performs a plain operation on the result and an operation value to obtain server output data, and checks if the server output data matches corresponding client output data from the client device. The client and/or server can optionally authenticate the client input data and the server input data if the server output data matches the client output data. | 2011-12-29 |
20110320807 | SYSTEM AND METHOD FOR PROCESSING ENCODED MESSAGES - Systems and methods for processing encoded messages at a message receiver. A received encoded message is decoded and stored in a memory. The stored decoded message can subsequently be displayed or otherwise processed without repeating the decoding operations. Decoding operations may include signature verification, decryption, other types of decoding, or some combination thereof. | 2011-12-29 |
20110320808 | SYSTEM AND METHOD FOR INCORPORATING AN ORIGINATING SITE INTO A SECURITY PROTOCOL FOR A DOWNLOADED PROGRAM OBJECT - Disclosed herein are systems, methods, and non-transitory computer-readable storage media for verifying a digital object obtained from a remote host. A system configured to practice the method downloads a first object from a first remote source and presents the user with a first request to allow access to the first object. Upon user approval, a multitude of characteristics associated with the object are stored to facilitate future uses of the object. When a second object is downloaded from a second remote source, the system checks the database for a stored user approval. Access to the second object is allowed if the multitude of characteristics associated with the first and second objects match. If the system does not find a match, the user is presented with a second request to allow access to the object. | 2011-12-29 |
20110320809 | METHOD AND APPARATUS FOR KEY REVOCATION IN AN ATTRIBUTE-BASED ENCRYPTION SCHEME - A method and apparatus for key revocation in an attribute-based encryption scheme is provided herein. Prior to operation, a key management service performs a randomized setup algorithm resulting in the generation of public parameters and the key management service's master secret, MK. During operation, the key management service is provided with verified user attribute information. The key management service creates keys for users based on their list of attributes. The keys can then be used to decode appropriate ciphertext. During the key creation, each attribute is associated with a particular text string. As attributes are revoked, the text string is updated. | 2011-12-29 |
20110320810 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing device includes: a data processing unit that executes a process of reproducing content recorded in a medium; and a memory storing a content revocation list in which an identifier (ID) of revoked content is recorded, wherein the data processing unit compares a minimum allowable version of a content revocation list recorded in a token which is management data corresponding to content recorded in the medium with a version of a content revocation list acquired from the memory, and when the version of the content revocation list acquired from the memory is an old version lower than the minimum allowable version of the content revocation list recorded in the token, the data processing unit halts determination on revocation of content based on the content revocation list acquired from the memory and reproduction of content. | 2011-12-29 |
20110320811 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing device includes: a data processing unit that executes a process of reproducing content recorded in a medium, wherein the data processing unit acquires a token from the medium, the token being management data corresponding to content recorded in the medium, compares a server ID recorded in the acquired token with a server ID recorded in a server certificate acquired from a server from which the management data is acquired, and halts reproduction of content when the two server IDs are not identical. | 2011-12-29 |
20110320812 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing device includes: a memory having a protected area which is a data recording area in which access restriction is set; and a data processing unit that determines accessibility in response to a request for accessing the protected area from an access requesting device, wherein the data processing unit verifies a device certificate received from the access requesting device and determines accessibility to the protected area based on access control information recorded in the device certificate. | 2011-12-29 |
20110320813 | Network system and authentication method thereof - A management server includes an encryption processor for individually scrambling a control program and authentication information in response to a transmission request from a terminal, a merging unit for merging the control program and the authentication information subsequent to scrambling, a communication control unit for transmitting the merge information to the terminal, and a permission signal generator for checking decrypted authentication information from the terminal against the original authentication information, and generating a permission signal that permits the control program to be installed if the decrypted authentication signal matches the original authentication signal. The terminal includes a communication control unit for transmitting the transmission request to the management server, a decryption processor unit for separating the control program and the authentication information from the merge signal from the management server, and individually decrypting the control program and the authentication information, the communication control unit for returning the decrypted authentication information to the management server, and an installation processor unit for starting installing the control program in response to a reception of the permission signal from the management server. | 2011-12-29 |
20110320814 | SYSTEM AND METHOD OF AUTHENTICATION - Disclosed herein are systems, methods and computer readable media for performing authentication. The proposed scheme utilizes new algorithms that introduce randomness using a physical value for authentication. An exemplary method includes sharing an initial state value S(0) with a sender and a receiver, generating a sender S(t, v) based on a parameter t and an identifier v and based at least in part on the value S(0). The method includes generating a receiver S(t, v) from S(0) based on the parameter t and the identifier v wherein the parameter t is related to a physical value in authenticating the identifier v based on a comparison of the sender S(t, v) and the receiver S(t, v). The process of generating the sender S(t, v) and the receiver S(t, v) includes a random variable generated by a process such as by a random number generator, the Brownian Motion or Wiener Process. Other embodiments do not use the physical value for authentication. | 2011-12-29 |
20110320815 | Key Sharing System, Communication Terminal, Management Device, Key Sharing Method, and Computer Program - In a case where another user's communication terminal (nTE | 2011-12-29 |
20110320816 | SYSTEMS AND METHOD FOR MALWARE DETECTION - A system and method for distinguishing human input events from malware-generated events includes one or more central processing units (CPUs), one or more input devices and memory. The memory includes program code that when executed by the CPU causes the CPU to obtain a first set of input events from a user utilizing the input device. The first input events are used to obtain or derive a feature indicative of the user, such as a multi-dimensional feature vector as provided by a support vector machine. Second input events are then obtained, and the second input events are classified against the feature to determine if either the user or malware initiated the second input events. | 2011-12-29 |
20110320817 | ELECTRONIC CERTIFICATE ISSUANCE SYSTEM, ELECTRONIC CERTIFICATE ISSUING DEVICE, COMMUNICATION DEVICE, AND PROGRAM THEREFOR - An electronic certificate issuance system comprising at least one communication device, and an electronic certificate issuing device for issuing a set of an electronic certificate and a private key corresponding to the electronic certificate as a certification set for each of the at least one communication device, is provided. The electronic certificate issuing device includes a first connecting interface, an obtaining system, which is adapted to obtain a node ID assigned to each of the at least one communication device, a generating system, and a writing system. The at least one communication device includes a second connecting interface, a judging system, and an installing system. | 2011-12-29 |
20110320818 | SYSTEM AND METHOD FOR PROVIDING SECURITY IN BROWSER-BASED ACCESS TO SMART CARDS - A method of operating a host computer having a web-browser with the capability of executing at least one web-browser add-on to provide a web application access to a smart card to protect the smart card from security threats associated with being connected to the Internet. Prior to establishing a connection between a web application executing in the web browser, verifying that the web application has been authorized to connect to a smart care using the web-browser add-on to provide a web application access to a smart card. | 2011-12-29 |
20110320819 | ACCESSING RESTRICTED CONTENT BASED ON PROXIMITY - A license to use content (e.g., a movie, song, application, etc.) is provided to a consumer. The license allows for use of the content by the device the consumer is using (e.g., logged into) and devices near the device the consumer is using. For example, a first computing device obtains a license to restricted content. A second computing device obtains a copy of the restricted content; however, the second computing device is not licensed to use the content and may not be able to access the content because the content is encrypted or otherwise restricted. The first computing device is brought into proximity with the second computing device. In response to detecting that the first computing device is in proximity with the second computing device, the second computing device is provided with legal access to the restricted content. The second computing device can then decrypt (or otherwise access) and play the content. | 2011-12-29 |
20110320820 | Restoring Secure Sessions - The different illustrative embodiments provide a method, a computer program product, and an apparatus for restoring secure sessions. A determination is made whether cached information for a session for the requestor is stored at the data processing system using a session cookie responsive to receiving a request at a data processing system from a requestor to access a resource. Access to the resource is controlled using the cached information and a number of privileges for the requestor associated with the cached information responsive to a determination that the cached information for the session is stored at the data processing system. A migration cookie is requested from the requestor responsive to an absence of a determination that the cached information for the session is stored at the data processing system. The cached information is generated for the session using the migration cookie. | 2011-12-29 |
20110320821 | FEDERATION AMONG SERVICES FOR SUPPORTING VIRTUAL-NETWORK OVERLAYS - Computerized methods, systems, and computer-readable media for promoting cooperation between a first and second virtual network overlay (“overlay”) are provided. The first overlay is governed by a first authority domain and includes members assigned virtual IP addresses from a first address range. The second overlay is governed by a second authority domain, which is associated with a second federation mechanism, for negotiating on behalf of the second overlay. The second federation mechanism is capable of negotiating with, or soliciting delegation of authority from, a first federation mechanism that is associated with the first authority domain. When negotiations are successful or authority is delegated, the second federation mechanism establishes a communication link between the second overlay and the first overlay or joins a member of the second overlay to the first overlay. Joining involves allocating a guest IP address from the first address range to the member. | 2011-12-29 |
20110320822 | KEYED HUMAN INTERACTIVE PROOF PLAYERS - A human interactive puzzle (HIP) authorization architecture where keyed and animated puzzles are executed by HIP players which are distinct and obfuscated to the point where breaking a single player is a relatively costly operation. A key is created in response to a request for a service, a HIP player is created based on the key, and a small installation executable is created that expands during installation to produce a computationally expensive data structure on the client relative to verification of the solution at the server. Thus, copying of the player or relay of the puzzle to a third system requires more time than allowed to receive the solution at the server. | 2011-12-29 |
20110320823 | TRUSTED SENSORS - Architecture that provides trusted sensors and trusted sensor readings on computing devices such as mobile devices. The architecture utilizes a trustworthy computing technology (e.g., trusted platform module (TPM). In the context of TPM, one implementation requires no additional hardware beyond the TPM and a virtualized environment to provide trusted sensor readings. A second implementation incorporates trusted computing primitives directly into sensors and enhances security using signed sensor readings. Privacy issues arising from the deployment of trusted sensors are also addressed by utilizing protocols. | 2011-12-29 |
20110320824 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing method has a request determining part determining a request type for streaming contents from a communicating apparatus, a copy number managing part managing the number of copies permissible for the communicating apparatus when permission of one or more of copies of streaming contents is requested, a stream number managing part managing the number of streams now in communication when the request determining part determines that the communicating apparatus has requested transfer of streaming contents without asking permission of one or more of copies, and to make stop transfer of streaming contents if the number of streams now in communication exceeds a predetermined threshold value, a key-selection processing part selecting a first key corresponding to transfer of streaming contents permissible for one or more of copies or a second key corresponding to transfer of streaming contents for copies with generation management restriction or not permissible for copies, an encryption processing part generating encrypted streaming contents using the first or the second key, and a packet processing part generating a packet that includes the encrypted streaming contents and key information selected by the key-selection processing part and to include information on the number of copies to the packet when the first key is selected. | 2011-12-29 |
20110320825 | FUNCTION VIRTUALIZATION FACILITY FOR FUNCTION QUERY OF A PROCESSOR - Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed. | 2011-12-29 |
20110320826 | Sharing Power Between Two Or More Power Sharing Servers - Methods, systems, and power sharing servers that include a computer processor; a computer memory operatively coupled to the computer processor; a power supply unit coupled to a power domain unit via a power supply unit port; an intravoltage port configured to receive a shared power cable coupled to an intravoltage port of a different power sharing server; and a transfused power card coupled to the power supply unit via a primary input power line, the transfused power card further coupled to the intravoltage port via a shared power line, the transfused power card configured to export electrical current via an intravoltage port when the transfused power card is receiving electrical current, above a threshold, from the power supply unit, and import electrical current via the intravoltage port when the transfused power card is not receiving electrical current, above the threshold, from the power supply unit. | 2011-12-29 |
20110320827 | System and Method for Identifying Power Connections in Computer Systems Having Redundant Power Supplies - A Power Distribution Unit (PDU) control system controls a PDU and communicates with a server management controller of a server. Through its connections, the PDU control system can track and manage the power supplies and locations of servers connected to those power supplies. A PDU receives commands at its communications port from a PDU control system to shut down a power strip or power outlet to which the PDU is connected via one of plural power interfaces. In turn, a server's management controller detects when a power supply shuts down due to the shut down of the power strip or power outlet. The server's management controller can be either queried by the PDU control system or the controller can send a notification to the PDU control system indicating which power supply lost power, thereby correlating the power strip to the server. | 2011-12-29 |
20110320828 | POWER MANAGEMENT AND PRIORITY CHARGING ASSIGNMENTS - Systems and methods are provided for managing power to devices in a network, using a centralized power allocation controller. The method of managing power consumption of a plurality of devices includes receiving scheduled upcoming calendar events and/or activities from one or more of a plurality of devices connected in a network. The method further includes centrally managing power consumption of a device of the plurality of devices in the network based on the scheduled upcoming calendar events and/or activities. | 2011-12-29 |
20110320829 | Power Supply Device Having USB Port with Large Current - A power supply device is mounted in a computer system. The power supply device includes a shield defining an opening, a USB port received in the opening to be exposed to an exterior, and a power supply module residing in the shield to provide power for both the computer system and the USB port. The USB port is coupled to the power supply module and provides charging current up to 2000 mA to meet the demand of external electronic devices. | 2011-12-29 |
20110320830 | SYSTEM FOR CONTROLLING APPARATUS DRIVEN BY BATTERY - In one embodiment, a system for controlling an apparatus driven by a battery, the system operating by the battery, includes a computer to control the apparatus, a control signal circuit to send a signal from the computer to the apparatus so as to control the apparatus, and a nonvolatile memory circuit to store an operating state of the computer. The operating state includes a first operating state and a second operating state, the computer sets the apparatus to a low load state in accordance with the operating state and controls the apparatus when the computer is reset for shutdown due to a decrease of the residual quantity of the battery and is restarted for power-on. | 2011-12-29 |
20110320831 | INFORMATION PROCESSING APPARATUS, POWER SOURCE CONTROL METHOD OF INFORMATION PROCESSING APPARATUS, PROGRAM OF POWER SOURCE CONTROL METHOD, AND STORAGE OF PROGRAM - An information processing apparatus includes an information storage to store information indicating a state of the information processing apparatus; an information writing processor to write the information to the information storage; a main power source and an auxiliary power source to supply power to the information writing processor; and a discharge controller to control a discharge speed of the auxiliary power source. When a voltage output of the main power source becomes a reference voltage, the discharge controller switches a power source for the information writing processor from the main power source to the auxiliary power source, and then after completing information writing to the information storage by using the information writing processor and the auxiliary power source, the discharge controller controls the discharge speed of the auxiliary power source to decrease a voltage output of the auxiliary power source to a given voltage within a given time period. | 2011-12-29 |
20110320832 | MANAGING ELECTRICAL POWER IN A VIRTUAL POWER DELIVERY NETWORK - Systems and methods are provided for managing power to devices in a virtual power delivery network, using a centralized power allocation controller. The method of managing power consumption of a plurality of devices includes receiving device information from one or more devices connected in a virtual power delivery network. The method further includes managing power consumption of the one or more devices in the virtual power delivery network based on the received device information. | 2011-12-29 |
20110320833 | SYSTEM AND METHOD FOR PROVIDING INTELLIGENT POWER MANAGEMENT IN A NETWORK ENVIRONMENT - An example method is provided and includes communicating a first packet to a network element in order to indicate whether an endpoint can have its power managed by network communications. The first packet includes an Internet protocol (IP) address associated with the endpoint. The method also includes receiving a second packet from the network element to identify whether the endpoint can have its power managed. The endpoint is configured to have its power managed via a port associated with the endpoint. In more specific embodiments, a state associated with the endpoint is used to determine whether to power on, or to power off the endpoint. In other implementations, the endpoint is powered on, or powered off at a specific time based on a policy associated with the endpoint. | 2011-12-29 |
20110320834 | DATA CENTER MANAGEMENT UNIT WITH IMPROVED DISASTER PREVENTION AND RECOVERY - A data center management unit for managing and controlling power distribution to computers in a data center includes a power inlet, a plurality of power outlets for providing power to respective ones of the computers, and a processor. In addition thereto, the data center management unit includes a memory for storing logged parameters or events. The processor in the data center management unit takes measures for disaster prevention and/or disaster recovery based on the logged parameters or events. The measures for disaster prevention or disaster recovery comprise generating alert messages, de-activating one or more power outlets, activating one or more power outlets and/or re-activating a power outlet that has been de-activated earlier. | 2011-12-29 |
20110320835 | SYSTEM AND METHOD FOR DYNAMICALLY MANAGING POWER IN AN ELECTRONIC DEVICE - A power controller receives a status signal, generates a control signal from the status signal, and reduces an output voltage of a voltage regulator based on the power control signal. The status signal is indicative of an operating tolerance or condition of a circuit or function of an electronic device during a low power state, and the output voltage of the voltage regulator is reduced to a value that corresponds to the operating tolerance or condition of the circuit or function of the electronic device. | 2011-12-29 |
20110320836 | Apparatus and Method of Managing Consumption in the Apparatus - An apparatus ( | 2011-12-29 |
20110320837 | POWER SUPPLY CIRCUIT, POWER SUPPLY METHOD, AND SIGNAL PROCESSING APPARATUS - A power supply circuit connected to an information processor including first and second controllers via a first cable having a first signal line and a first power line and a second cable having a second signal line and a second power line includes a controller that operates using a current of a first level supplied via the second power line and that performs setup by communicating with the second controller via the second signal line and a switch circuit that supplies, to an external device controller, currents supplied via the first and second power lines. When setup of the external device controller is completed through communication between the external device controller and the first controller via the first signal line, the switch circuit supplies, to the external device controller, a current of a second level higher than the first level supplied via each of the first and second power lines. | 2011-12-29 |
20110320838 | DYNAMIC CPU VOLTAGE REGULATOR PHASE SHEDDING - A voltage regulator phase shedding system includes one or more subsystems to receive a system management interrupt (SMI), gather processor utilization information, determine whether to adjust a performance state, lookup voltage regulator information for new performance state, adjust active voltage regulator phase, and adjust performance state. The voltage regulator phase shedding system can also include one or more subsystems to read a power measurement, calculate throttling requirements, determine whether to adjust a throttling, lookup voltage regulator information for new performance state capacity, adjust active voltage regulator phase, and adjust throttling. | 2011-12-29 |
20110320839 | MEMORY POWER MANAGEMENT VIA DYNAMIC MEMORY OPERATION STATES - Described herein are techniques for dynamic memory frequency/voltage scaling to augment existing memory power management techniques and further improve memory power efficiency. Each operating point is defined as an operational state for the memory. | 2011-12-29 |
20110320840 | Transparently Increasing Power Savings in a Power Management Environment - A mechanism is provided for transparently consolidating resources of logical partitions. Responsive to the existence of the non-folded resource on an originating resource chip, the virtualization mechanism determines whether there is a destination resource chip to either exchange operations of the non-folded resource with a folded resource on the destination chip or migrate operations of the non-folded resource to a non-folded resource on the destination chip. Responsive to the existence of the folded resource on the destination resource chip, the virtualization mechanism transparently exchanges the operations of the non-folded resource from the originating resource chip to the folded resource on the destination resource chip, where the folded resource remains folded on the originating resource chip after the exchange. Responsive to the absence of another non-folded resource on the originating resource chip, the vitalization mechanism places the originating resource chip into a deeper power saving mode. | 2011-12-29 |
20110320841 | Method for power management of data buses in electronic devices - Provided are systems and methods for execution by a core of a peripheral component to provide power management for a data bus in a electronic device, suhc as a mobile electronic device. One method comprises determining whether a device in the peripheral component is inactive, transmitting a request for deactivation of at least one data channel to the device, receiving a command to deactivate the at least one data channel, determining whether any remaining devices in the peripheral component are active, and placing the peripheral component in a first low power mode wherein the core remains active in order to monitor a data bus clock. | 2011-12-29 |
20110320842 | POWER SUPPLY CONTROL DEVICE, IMAGE PROCESSING DEVICE, POWER SUPPLY CONTROL METHOD, AND COMPUTER READABLE MEDIUM - A power supply control device including a mode switching controller, a first power supply section, a second power supply section, a third power supply section, a wiring system opening and closing unit and a controller. During the sleep mode, the first power supply section continues to supply power to a specific control system, the second power supply section shuts off its supply of power, and the third power supply section supplies power to the specific control system by a separate system to the specific control system. The wiring system opening/closing unit sets a power supply wiring system of the commercial power source to an open state or a closed state. When the third power supply section is supplying power during the sleep mode, the controller controls the wiring system opening and closing unit and sets the power supply wiring system of the commercial power supply to the open state. | 2011-12-29 |
20110320843 | SEMICONDUCTOR DEVICES AND SYSTEMS-ON-CHIP HAVING THE SAME - A semiconductor device includes a power gating unit, a combinational logic unit and a clamping unit. The power gating unit is turned on to output an internal signal at an output electrode based on an input signal or turned off according to operation modes. The combinational logic unit includes an input electrode directly connected to the output electrode of the power gating unit through a data line, and generates an output signal based on the internal signal received through the data line. The clamping unit is turned on to clamp the internal signal at a logic high level or at a logic low level or turned off according to the operation modes. The semiconductor device clamps the output electrode of the power gating unit without degrading an operation speed of the semiconductor device. | 2011-12-29 |
20110320844 | DYNAMIC CONTROL OF REDUCED VOLTAGE STATE OF GRAPHICS CONTROLLER COMPONENT OF MEMORY CONTROLLER - A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller component of a memory controller. The reduction in voltage may cause the voltage to be reduced below a voltage level required to maintain context information in the graphics controller component. | 2011-12-29 |
20110320845 | POWER SUPPLY CONTROL APPARATUS, IMAGE PROCESSING APPARATUS, STORAGE MEDIUM STORING POWER SUPPLY CONTROL PROGRAM - A power supply control apparatus that includes an instruction component, an execution component and a power supply control component is provided. The power supply control component is equipped with at least two measurement functions that have different measurement durations for cases in which the duration until interrupting the power supply to device(s) is measured, wherein measurement is activated with a first measurement function of relatively long measurement duration at a completion time of prior image processing, and measurement is activated with a second measurement function of relatively short measurement duration for device(s) to which power is being supplied at the time of completion of the prior image processing but which are not required in later image processing. | 2011-12-29 |
20110320846 | ADAPTIVE MEMORY FREQUENCY SCALING - Methods and apparatuses for adaptive memory operational state management. A memory performance parameter is determined for at least a portion of a memory system. The memory performance parameter is compared to one or more threshold values. An operating frequency of the memory system can be modified based on results of the comparison of the memory performance parameter and the one or more threshold values. | 2011-12-29 |
20110320847 | METHOD AND APPARATUS FOR REDUCING POWER CONSUMPTION FOR MEMORIES - Described herein are a method and an apparatus for reducing power consumption of memories by monitoring the power states of the memories via an operating system. The method comprises reading counter values corresponding to power states of each memory of a plurality memories; computing a power state usage corresponding to the power states of each memory of the plurality, the computing based on the counter values; determining whether the power state usage exceeds a predetermined threshold usage; and adjusting current and future usage of each memory of the plurality in response to determining that the power state usage exceeds the predetermined threshold usage. | 2011-12-29 |
20110320848 | FIELD-PROGRAMMABLE GATE ARRAY POWER SUPPLY SYSTEM DESIGNER - A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of a plurality of loads of a multiple-load device; determine a plurality of power supply architectures that may be used to provide power supply solutions satisfying the plurality of loads, each power supply architecture including at least one position requiring a component configured to satisfy a load requirement; for each one of at least a subset of the plurality of power supply architectures, determine, based on the characteristics of the plurality of components, at least one component configured to satisfy the corresponding load requirement for each position of the one of the power supply architectures; and generate at least one power supply design in accordance with the power supply architectures and the determined components. | 2011-12-29 |
20110320849 | DETERMINING POWER TOPOLOGY OF A PLURALITY OF COMPUTER SYSTEMS - Determining power topology of a computer system. At least some of the illustrative embodiments are methods including communicating with a first computer system of a plurality of computer systems mounted in a rack (the communicating through dedicated communication conductors integral with a first cord carrying operational power to first computer system), communicating with a second computer system of the plurality of computer systems (the communicating through dedicated communication conductors integral with a second cord carrying operational power to first computer system), determining a power topology regarding the plurality of computer systems based on the communicating, and displaying an indication of the power topology. | 2011-12-29 |
20110320850 | OFFLINE AT START UP OF A POWERED ON DEVICE - A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence. | 2011-12-29 |
20110320851 | PORT ENABLE SIGNAL GENERATION FOR GATING A MEMORY ARRAY DEVICE OUTPUT - A method of generating a dynamic port enable signal for gating memory array data to an output node includes generating a programmable leading edge clock signal derivation of an input dynamic clock signal; generating a programmable trailing edge clock signal derivation of the input dynamic clock signal, wherein the leading edge clock signal derivation and the trailing edge clock signal derivation are independently programmable with respect to one another; and gating the generated programmable leading and trailing edge clock signal derivations with a static input enable signal so as to generate the port enable signal such that, when inactive, the port enable signal prevents early memory array data from being coupled to the output node. | 2011-12-29 |
20110320852 | CLOCK CIRCUIT AND RESET CIRCUIT AND METHOD THEREOF - A clock circuit is suitable for use in a timing circuit which provides time information according to a reference clock. The clock circuit includes a clock detector to detect whether or not an interruption of the reference clock occurs. When the interruption of the reference clock occurs, a clock interruption signal is issued as a reference whether or not to reset the timing circuit. | 2011-12-29 |
20110320853 | COMMUNICATION INTERFACE DEVICE AND COMMUNICATION METHOD - A communication interface device includes: a first interface circuit including a chip select terminal connected to a first terminal, a clock terminal connected to a second terminal, and a data terminal connected to a third terminal; and a second interface circuit including a second clock terminal connected to the first terminal and a data terminal connected to the third terminal In a case of performing communication by the first interface circuit, a fixed signal fixed at a predetermined level is input into the first terminal, a clock signal is input into the second terminal, and a data signal is input into the third terminal, and in a case of performing communication by the second interface circuit, the clock signal is input into the first terminal and the data signal is input into the third terminal | 2011-12-29 |
20110320854 | Inter-clock domain data transfer FIFO circuit - The inter-clock domain data transfer FIFO circuit provides a circuit that transfers data between two clock domains of unrelated frequencies. The gate count is kept relatively low, thereby allowing data transfer between the two clock domains at one data item per cycle of the lower of the two frequencies. Depending on the frequency difference between the data producer and consumer, the initial latency could be as low as a fraction of a cycle and no more than two cycles of the consumer's clock. The operation of the data transfer FIFO circuit has been verified using gate-level simulations for several ratios of clock frequencies. | 2011-12-29 |
20110320855 | ERROR DETECTION AND RECOVERY IN A SHARED PIPELINE - A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic. | 2011-12-29 |
20110320856 | METHOD AND APPARATUS FOR SELECTIVE READING OF SYSTEM INFORMATION IN A MOBILE WIRELESS DEVICE - A method to read selectively system information messages in a mobile wireless communication device. The mobile wireless device receives a first transmission of a multiple segment message through a radio frequency receiver. The mobile wireless device detects decoding errors in at least one of the received segments of the first transmission. In response to detecting decoding errors, the mobile wireless device selectively receives a first subset of segments in a second transmission of the multiple segment message. The mobile wireless device powers down at least a portion of the radio frequency receiver during receive time intervals for a second subset of segments in the second transmission. The first subset of segments in the second transmission corresponds to segments in the first transmission received with decoding errors. The second subset of segments in the second transmission corresponds to segments in the first transmission received without decoding errors. | 2011-12-29 |
20110320857 | BOTTOM-UP MULTILAYER NETWORK RECOVERY METHOD BASED ON ROOT-CAUSE ANALYSIS - A bottom-up (or upward) multilayer network recovery method and apparatus based on a root-cause analysis are disclosed to quickly and accurately perform a recovery operation. The bottom-up multilayer network recovery method based on a root-cause analysis includes: simultaneously counting, by a fault detection layer, a root-cause analysis (RA) time and a hold-off (HO) time, upon detecting an occurrence of a fault; performing, by the fault detection layer, a root-cause analysis during the RA time to recognize a layer in which a root-cause has occurred; when the root-cause has occurred in the fault detection layer, immediately recovering the fault by the fault detection layer, and when a root-cause has occurrence in a lower layer, waiting for the HO time until such time as the lower layer can recover the fault; and when the fault has not been recovered even after the HO time has lapsed, recovering the fault by the fault detection layer. | 2011-12-29 |
20110320858 | MONITORING SOFTWARE THREAD EXECUTION - The invention is directed to monitoring execution of software threads, particularly by detecting a lockup or stall in execution of a software thread and initiating a remedial action in response. Advantageously, some embodiments of the invention automatically detect a lockup or stall in execution of a software thread by periodically sampling information corresponding to the thread, and, in accordance with a determination made using the information, initiate an attempt to recover from such a condition in execution without the need for manual intervention. | 2011-12-29 |
20110320859 | METHOD AND SYSTEM FOR INTERFERENCE DETECTION AND MITIGATION - In a method for adjusting modulation on a network, a modulation profile of a network node on the network is set a specified density. A plurality of messages that are received at the network node are monitored on an ongoing basis. The modulation profile of the network node is updated continually based on the monitored messages. A determination is made that a predetermined class of messages is received incorrectly at the network node. The network node is disconnected from the network based on the incorrectly received predetermined class of messages and is reconnected to the network to initiate the network node on the network. | 2011-12-29 |
20110320860 | MANAGING PROCESSING ASSOCIATED WITH HARDWARE EVENTS - Detection, notification and/or processing of events, such as errors associated with adapters, are facilitated. Hardware detects an event, places one or more adapters in an error state to prevent access to/from the adapters, and notifies the operating system of the event. | 2011-12-29 |
20110320861 | SWITCH FAILOVER CONTROL IN A MULTIPROCESSOR COMPUTER SYSTEM - A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node. | 2011-12-29 |
20110320862 | Edram Macro Disablement in Cache Memory - Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining. | 2011-12-29 |
20110320863 | DYNAMIC RE-ALLOCATION OF CACHE BUFFER SLOTS - Dynamic re-allocation of cache buffer slots includes moving data out of a reserved buffer slot upon detecting an error in the reserved buffer slot, creating a new buffer slot, and storing the data moved out of the reserved buffer slot in the new buffer slot. | 2011-12-29 |
20110320864 | HETEROGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM - Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete. | 2011-12-29 |
20110320865 | DEDUPLICATION IN A HYBRID STORAGE ENVIRONMENT - Deduplication in a hybrid storage environment includes determining characteristics of a first data set. The first data set is identified as redundant to a second data set and the second data set is stored in a first storage system. The deduplication also includes mapping the characteristics of the first data set to storage preferences, the storage preferences specifying storage system selections for storing data sets based upon attributes of the respective storage systems. The deduplication further includes storing, as a persistent data set, one of the first data set and the second data set in one of the storage systems identified from the mapping. | 2011-12-29 |
20110320866 | DYNAMIC PIPELINE CACHE ERROR CORRECTION - Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data. | 2011-12-29 |
20110320867 | METHOD AND APPARATUS FOR TRAINING A MEMORY SIGNAL VIA AN ERROR SIGNAL OF A MEMORY - Described herein is a method and an apparatus for training a memory signal via an error signal of a memory. The method comprises transmitting from a memory controller a command-address (C/A) signal to a memory module; determining by the memory controller an error in the memory module via an error signal from an error pin of the memory module, the error associated with the C/A signal transmitted to the memory module; and modifying by the memory controller the C/A signal in response to determining an error in the memory module, wherein the error pin is a parity error pin of the memory module, and wherein the memory module comprises a Double Data Rate 4 (DDR4) interface. | 2011-12-29 |
20110320868 | DATA STORAGE APPARATUS AND METHOD FOR WRITING DATA - According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory. | 2011-12-29 |
20110320869 | HOMOGENEOUS RECOVERY IN A REDUNDANT MEMORY SYSTEM - Providing homogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for blocking off new operations from starting on the memory channels, for completing any pending operations on the memory channels, for performing a recovery operation on the memory channels and for starting the new operations on at least a first subset of the memory channels. The memory system is capable of operating with the first subset of the memory channels. | 2011-12-29 |
20110320870 | COLLECTING NETWORK-LEVEL PACKETS INTO A DATA STRUCTURE IN RESPONSE TO AN ABNORMAL CONDITION - A sniffer device determines whether an abnormal condition is present in a network communication. In response to determining that the abnormal condition is present, the sniffer device collects network-level packets into a data structure. The data structure containing the collected network-level packets can be analyzed for determining whether the abnormal condition caused an issue with a communicating entity. | 2011-12-29 |
20110320871 | RS-485 PORT TEST APPARATUS - An RS-485 port test apparatus includes an RS-485 connector, a micro control unit (MCU), a multiprotocol transceiver, and a display. The RS-485 connector receives a first test code signal from a test RS-485 port of an electronic device. The multiprotocol transceiver receives the first test code signal from the RS-485 connector, converts the first test code signal to a second test code signal which can be identified by the MCU, and transmits the second signal to the MCU. The MCU receives the second test code signal and displays the second test code signal by the display. The MCU sends back the second test code signal to the multiprotocol transceiver. The multiprotocol transceiver converts the second test code signal to the first test code and transmits the first test code to the test RS-485 port of the electronic device through the RS-485 connector. | 2011-12-29 |
20110320872 | HIERARCHICAL ERROR INJECTION FOR COMPLEX RAIM/ECC DESIGN - A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined. | 2011-12-29 |
20110320873 | ERROR IDENTIFICATION - A method of identifying errors in a computing system operation is provided and includes identifying that a certain record of interest in system trace information has a number of entries that exceeds a predefined number and inferring from the excessive number of entries that a work unit associated with the certain record of interest is affected by an error. | 2011-12-29 |
20110320874 | METHOD AND APPARATUS FOR ESTIMATING CANDIDATE CAUSE - A method for estimating a candidate cause in a failure occurred in an information processing apparatus by a computer, the method includes retrieving, by the computer, a first set of incident information from a data storage region on the basis of failure symptom data which is set on the computer, the data storage region storing incident information, each piece of the incident information including failure symptom data, first cause data of a positive judgment result of a cause in the failure, and second cause data of a negative judgment result of the cause in the failure, each of the first set including the failure symptom data identical to the set failure symptom data. | 2011-12-29 |
20110320875 | INFORMATION TERMINAL AND INFORMATION PROCESSING METHOD - An information terminal includes a start processing unit of a central processing unit which executes restart processing and a notification unit which outputs reason information indicating a reason for executing the restart processing. | 2011-12-29 |
20110320876 | Systems and methods for processing source code during debugging operations - Systems and methods consistent with the invention may include displaying, during debugging of source code having corresponding executable code, a screen including a first section, wherein a variable name included in the source code is displayed in a first format in the first section, receiving a user selection of the variable name, converting, by using a processor, the first format of the variable name to a second format in response to the received selection, wherein the variable name includes a plurality of characters and converting the first format of the variable name to the second format includes converting the characters to uppercase, searching for a corresponding variable name in the executable code, and displaying, on the display device, a second section including the corresponding variable name, wherein the variable name is displayed in a third format in the second section. | 2011-12-29 |
20110320877 | REPLAYING ARCHITECTURAL EXECUTION WITH A PROBELESS TRACE CAPTURE - A system and method provide for capturing architecture data for software executing on a system, wherein the architecture data can include state data and event data. The captured architecture data may be replayed in a simulator, wherein failure information corresponding to the software is obtained from the simulator. | 2011-12-29 |
20110320878 | Parametric Trace Slicing - A program trace is obtained and events of the program trace are traversed. For each event identified in traversing the program trace, a trace slice of which the identified event is a part is identified based on the parameter instance of the identified event. For each trace slice of which the identified event is a part, the identified event is added to an end of a record of the trace slice. These parametric trace slices can be used in a variety of different manners, such as for monitoring, mining, and predicting. | 2011-12-29 |
20110320879 | Methods and systems for a mobile device testing framework - A mobile device test framework is used in combination with client controllers and device controllers so that a single mobile device API test can be used with mobile devices having different operating system platforms. The client controllers can provide information specific to the client and the device controllers can provide information needed to apply the test to each of the mobile device platforms. The test framework can navigate through the controls of the mobile device GUIs and input information. The test framework can then check that the text and images displayed by the mobile devices match the expected information. | 2011-12-29 |
20110320880 | SYSTEM IDENTIFYING AND INFERRING WEB SESSION EVENTS - A test system uses an instrumented browser to identify events that were not successfully captured during a client web session. The identified events can be used to modify a capture system that captures the client web session. Alternatively, the test system may generate replay rules that are used by a replay system to infer the missed events while replaying of the previously captured client web session. The events can include changes to Document Object Models (DOMs) for web pages used during the web sessions. The DOMs can be used to identify significant web session events and force replay sessions into the correct states. | 2011-12-29 |
20110320881 | ISOLATION OF FAULTY LINKS IN A TRANSMISSION MEDIUM - Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link. | 2011-12-29 |
20110320882 | ACCELERATED VIRTUAL ENVIRONMENTS DEPLOYMENT TROUBLESHOOTING BASED ON TWO LEVEL FILE SYSTEM SIGNATURE - Troubleshooting virtual environment deployment based on two level file system signatures, in one aspect, may include creating a first level file system signature including a set of file names of files in an image of a virtual machine taken at a point in time and associated status of the files as compared with an image of the virtual machine taken at a preceding point in time. A second level file system signature may be created using file content differences of the files having modified status in the set of file names. The first level file system signature may be compared with a first level file system signature pattern associated with one or more previous deployment of the same software and related to the same point in time. Optionally, the second level file system signature may be compared with a second level file system signature pattern. | 2011-12-29 |
20110320883 | MEMORY-HAZARD DETECTION AND AVOIDANCE INSTRUCTIONS FOR VECTOR PROCESSING - A processor that is configured to perform parallel operations in a computer system where one or more memory hazards may be present is described. An instruction fetch unit within the processor is configured to fetch instructions for detecting one or more critical memory hazards between memory addresses if memory operations are performed in parallel on multiple addresses corresponding to at least a partial vector of addresses. Note that critical memory hazards include memory hazards that lead to different results when the memory addresses are processed in parallel than when the memory addresses are processed sequentially. Furthermore, an execution unit within the processor is configured to execute the instructions for detecting the one or more critical memory hazards. | 2011-12-29 |
20110320884 | REQUEST BASED LOGGING - Systems, methods, and other embodiments associated with event logging are described. One example method includes collecting request-based event log data associated with processing a request and temporarily storing the event log data in a memory. In the event of an error, the event log data is transferred to a storage device. | 2011-12-29 |