52nd week of 2011 patent applcation highlights part 15 |
Patent application number | Title | Published |
20110315981 | Microbolometer for infrared detector or Terahertz detector and method for manufacturing the same - A microbolometer includes a micro-bridge structure for uncooling infrared or terahertz detectors. The thermistor and light absorbing materials of the micro-bridge structure are the vanadium oxide-carbon nanotube composite film formed by one-dimensional carbon nanotubes and two-dimensional vanadium oxide film. The micro-bridge is a three-layer sandwich structure consisting of a layer of amorphous silicon nitride base film as the supporting and insulating layer of the micro-bridge, a layer or multi-layer of vanadium oxide-carbon nanotube composite film in the middle of the micro-bridge as the heat sensitive and light absorbing layer of the microbolometer, and a layer of amorphous silicon nitride top film as the stress control layer and passivation of the heat sensitive film. The microbolometer and method for manufacturing the same can overcome the shortcomings of the prior art, improve the performance of the device, reduce the cost of raw materials and is suitable for large-scale industrial production. | 2011-12-29 |
20110315982 | METHOD FOR PRODUCING SEMICONDUCTING INDIUM OXIDE LAYERS, INDIUM OXIDE LAYERS PRODUCED ACCORDING TO SAID METHOD AND THEIR USE - The present invention relates to a process for producing semiconductive indium oxide layers, in which a substrate is coated with a liquid, anhydrous composition comprising a) at least one indium alkoxide and b) at least one solvent, optionally dried and thermally treated at temperatures greater than | 2011-12-29 |
20110315983 | THIN FILM TRANSISTOR HAVING SEMICONDUCTOR ACTIVE LAYER - A method of manufacturing an IGZO active layer includes depositing ions including In, Ga, and Zn from a first target, and depositing ions including In from a second target having a different atomic composition from the first target. The deposition of ions from the second target may be controlled to adjust an atomic % of In in the IGZO layer to be about | 2011-12-29 |
20110315984 | SEMICONDUCTOR MEMORY CARD AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory card that includes a printed substrate in which an electronic component is mounted on one surface, and an external terminal is installed on the other surface, and that is molded in a card form. The printed substrate is a laminated body in which a metallic interconnection for connecting the electronic component to the terminal and a solder resist are sequentially laminated on both surfaces of a core material. The semiconductor memory card includes an ink layer on the solder resist of the other surface, and a mark is engraved by a laser on the ink layer. | 2011-12-29 |
20110315985 | SENSOR-FITTED SUBSTRATE AND METHOD FOR PRODUCING SENSOR-FITTED SUBSTRATE - A sensor-fitted substrate allowing a sensor-fitted wafer for measuring the temperature or strain to be produced inexpensively, moreover, allowing measurements of the temperature or strain to be carried out with satisfactory accuracy, and a method for producing such a sensor-fitted substrate. An undercoat film is formed on the surface of a substrate, the film being configured, compared to when no undercoat film is formed, to allow the strength of close contact of a dispersed nano-particle ink with the substrate to be increased, the diffusion of the dispersed nano-particle ink into the substrate to be suppressed, and the growth of metal crystal particles contained in the dispersed nano-particle ink to be suppressed. A wiring pattern of the sensor is traced on the surface of the undercoat film of the substrate surface by using the dispersed nano-particle ink, and the dispersed nano-particle ink is baked and metalized. | 2011-12-29 |
20110315986 | SEMICONDUCTOR INTEGRATED CIRCUIT - Whether there is a defect such as chipping of a die or separation of a resin in a wafer level package is electrically detected. A peripheral wiring is disposed along four peripheries of a semiconductor substrate outside a circuit region and pad electrodes P | 2011-12-29 |
20110315987 | PORTABLE MEMORY DEVICES - Improved techniques to produce integrated circuit products are disclosed. The improved techniques permit smaller and less costly production of integrated circuit products. One aspect of the invention concerns covering test contacts (e.g., test pins) provided with the integrated circuit products using printed ink. Once covered with the ink, the test contacts are no longer electrically exposed. Hence, the integrated circuit products are not susceptible to accidental access or electrostatic discharge. Moreover, the integrated circuit products can be efficiently produced in a small form factor without any need for additional packaging or labels to electrically isolate the test contacts. | 2011-12-29 |
20110315988 | PASSIVATED UPSTANDING NANOSTRUCTURES AND METHODS OF MAKING THE SAME - Described herein is a device comprising: a substrate; one or more of a nanostructure extending essentially perpendicularly from the substrate; wherein the nanostructure comprises a core of a doped semiconductor, an first layer disposed on the core, and a second layer of an opposite type from the core and disposed on the first layer. | 2011-12-29 |
20110315989 | DISPLAY DEVICE, LASER TRANSFER PRINTING METHOD AND LASER TRANSFER COLOR DONOR SHEET - A display device includes a thin film transistor substrate, a display layer, a patterned color resist layer, a patterned UV block layer and a transparent protective layer. The thin film transistor substrate has a substrate and a plurality of thin film transistors. The display layer is disposed on the thin film transistor substrate. The patterned color resist layer is disposed on the display layer. The patterned UV block layer is disposed on the patterned color resist layer. The transparent protective layer is disposed on the patterned UV block layer. The present invention also provides a laser transfer printing method for fabricating the color resist layer and the patterned UV block layer. | 2011-12-29 |
20110315990 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND ELECTRONIC APPLIANCE - To provide a semiconductor device in which a channel formation region can be thinned without adversely affecting a source region and a drain region through a simple process and a method for manufacturing the semiconductor device. In the method for manufacturing a semiconductor device, a semiconductor film, having a thickness smaller than a height of a projection of a substrate, is formed over a surface of the substrate having the projections; the semiconductor film is etched to have an island shape with a resist used as a mask; the resist is etched to expose a portion of the semiconductor film which covers a top surface of the projection; and the exposed portion of the semiconductor film is etched to be thin, while the adjacent portions of the semiconductor film on both sides of the projection remain covered with the resist. | 2011-12-29 |
20110315991 | ARRAY SUBSTRATE, LIQUID CRYSTAL PANEL, LIQUID CRYSTAL DISPLAY DEVICE, AND TELEVISION RECEIVER - An array substrate disclosed herein includes: scanning signal lines ( | 2011-12-29 |
20110315992 | PLASMA-ENHANCED CHEMICAL VAPOR DEPOSITION OF CRYSTALLINE GERMANIUM - In a method of depositing a crystalline germanium layer on a substrate, a substrate is placed in the process zone comprising a pair of process electrodes. In a deposition stage, a crystalline germanium layer is deposited on the substrate by introducing a deposition gas comprising a germanium-containing gas into the process zone, and forming a capacitively coupled plasma of the deposition gas by coupling energy to the process electrodes. In a subsequent treatment stage, the deposited crystalline germanium layer is treated by exposing the crystalline germanium layer to an energized treatment gas or by annealing the layer. | 2011-12-29 |
20110315993 | Light Emitting Device and Method of Manufacturing the Same - There is provided a light emitting device in which low power consumption can be realized even in the case of a large screen. The surface of a source signal line or a power supply line in a pixel portion is plated to reduce a resistance of a wiring. The source signal line in the pixel portion is manufactured by a step different from a source signal line in a driver circuit portion. The power supply line in the pixel portion is manufactured by a step different from a power supply line led on a substrate. A terminal is similarly plated to made the resistance reduction. It is desirable that a wiring before plating is made of the same material as a gate electrode and the surface of the wiring is plated to form the source signal line or the power supply line. | 2011-12-29 |
20110315994 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a display device includes forming a gate electrode on a substrate, a gate insulating layer on the gate electrode, and an active layer on the gate insulating layer, the gate electrode made of extrinsic polycrystalline silicon, the active layer made of intrinsic polycrystalline silicon; forming an etch stopper on the active layer; forming source and drain electrodes spaced apart from each other on the etch stopper; forming an ohmic contact layer each between a side of the active layer and the source electrode and between an opposing side of the active layer and the drain electrode; forming a gate line connected to the gate electrode; and forming a data line crossing the gate line. | 2011-12-29 |
20110315995 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Disclosed is a semiconductor device which includes a substrate | 2011-12-29 |
20110315996 | SEMICONDUCTOR DEVICE, LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME - Disclosed are a semiconductor device, a light emitting device, and a method of manufacturing the same. The semiconductor device includes a substrate, a plurality of rods aligned on the substrate, a metal layer disposed on the substrate between the rods, and a semiconductor layer disposed on and between the rods. Electrical and optical characteristics of the semiconductor device are improved due to the metal layer. | 2011-12-29 |
20110315997 | GaN Substrate and Method of Its Manufacture, Method of Manufacturing GaN Layer-Bonded Substrate, and Method of Manufacturing Semiconductor Device - The present invention makes available a GaN substrate, and a method of its manufacture, that, with minimal machining allowances, facilitates consistent machining, and makes available a method of manufacturing a GaN layer-bonded substrate, and a semiconductor device, utilizing the GaN substrate. A GaN substrate ( | 2011-12-29 |
20110315998 | EPITAXIAL WAFER, METHOD FOR MANUFACTURING GALLIUM NITRIDE SEMICONDUCTOR DEVICE, GALLIUM NITRIDE SEMICONDUCTOR DEVICE AND GALLIUM OXIDE WAFER - A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base | 2011-12-29 |
20110315999 | Gallium and Nitrogen Containing Triangular or Diamond-shaped Configuration for Optical Devices - A gallium and nitrogen containing optical device has a base region and no more than three major planar side regions configured in a triangular arrangement provided from the base region. | 2011-12-29 |
20110316000 | MANUFACTURING OF LOW DEFECT DENSITY FREE-STANDING GALLIUM NITRIDE SUBSTRATES AND DEVICES FABRICATED THEREOF - The invention relates to a method for manufacturing a single crystal of nitride by epitaxial growth on a support ( | 2011-12-29 |
20110316001 | METHOD FOR GROWING GROUP III-V NITRIDE FILM AND STRUCTURE THEREOF - A method for growing a Group III-V nitride film and a structure thereof are presented. The method is carried out by hydride vapor phase epitaxy (HVPE). The method includes the steps of, inter alia, slowly epitaxially growing a temperature ramping nitride layer on a substrate by rising a first growth temperature of 900-950° C. to a second growth temperature of 1000-1050° C. at a temperature-rising rate of 0.5-10° C./min. The lattice quality of the temperature ramping nitride layer is slowly transformed with the layer height, so that a stress induced by lattice mismatch between a sapphire substrate and a gallium nitride (GaN) layer is relieved. | 2011-12-29 |
20110316002 | CMOS IMAGE SENSOR - A complementary metal-oxide-semiconductor (CMOS) image sensor, including a wiring layer, a photodiode stacked with the wiring layer, a micro-lens stacked on the photodiode, an anti-reflection layer stacked on the photodiode. An anti-absorption layer may be provided between the photodiode and the anti-reflection layer. The photodiode may include a first portion and a second portion. Light may be focused on the first portion by the micro-lens and the second portion may at least partially surround the first portion. A material of the first portion may have a refractive index higher than a refractive index of a material of the second portion. The anti-absorption layer may include a compound semiconductor having an energy band gap greater than an energy band gap of a semiconductor included in the photodiode. | 2011-12-29 |
20110316003 | Multilayered Semiconductor Wafer and Process For Manufacturing The Same - Silicon carbide substrate wafers are prepared by transferring a monocrystalline silicon layer from a donor wafer onto a handle wafer, the silicon layer being implanted with carbon and annealed to form a monocrystalline SiC layer prior to or after transfer of the silicon layer. | 2011-12-29 |
20110316004 | LIGHT EMITTING DEVICE - The embodiment relates to a light emitting device and a method for manufacturing the same. The light emitting device includes a substrate, a plurality of convex portions protruding from a flat top surface of the substrate, a first semiconductor layer on the substrate, an active layer on the first semiconductor layer, and a second conductive semiconductor layer on the active layer. A circumferential surface of each convex portion includes a continuous spherical surface, and a height of the convex portion is about 1.5 μm or less. | 2011-12-29 |
20110316005 | DISPLAY APPARATUS - In a liquid crystal display apparatus ( | 2011-12-29 |
20110316006 | Surface-Textured Encapsulations for use with Light Emitting Diodes - Surface-textured encapsulations for use with light emitting diodes. In an aspect, a light emitting diode (LED) array apparatus includes a plurality of LEDs mounted to a substrate and an encapsulation covering the LEDs and having a surface texturing configured to extract light, wherein the surface texturing is includes at least one light extracting feature having a diameter larger than two or more of the LEDs. | 2011-12-29 |
20110316007 | DISPLAY DEVICE - A display device includes, on a substrate, light emitting elements each formed by sequentially stacking a first electrode layer, an organic layer including a light emission layer, and a second electrode layer and arranged in first and second directions which cross each other, a drive circuit including drive elements that drive light emitting elements, and a wiring extending in the first direction, and an insulating layer disposed in a gap region sandwiched by the light emitting elements neighboring in the second direction and having a recess or a projection. The wiring is disposed in an overlap region overlapping with the recess or the projection in the insulating layer in a thickness direction, in the gap region, and the second electrode layers in the light emitting elements neighboring in the second direction are separated from each other by the recess or the projection in the insulating layer. | 2011-12-29 |
20110316008 | FLAT PANEL DISPLAY - According to one embodiment, a flat panel display includes a first mounting portion including a first input pad and a first output pad, a second mounting portion including a second input pad and a second output pad, a first common terminal and a second common terminal, which have a common potential, and a guard ring wiring which is formed in a manner to extend from the first common terminal, to pass between the first input pad and the first output pad of the first mounting portion, to pass between the second input pad and the second output pad of the second mounting portion, and to reach the second common terminal, the guard ring wiring including a first resistor element of a first resistance value and a second resistor element of a second resistance value which is higher than the first resistance value. | 2011-12-29 |
20110316009 | LIGHT-EMITTING DEVICE - A light-emitting device includes a substrate, and a plurality of light-emitting arrays or light-emitting groups arranged on the substrate. The light-emitting arrays or light-emitting groups include a plurality of LED elements connected in parallel with a pair of adjacent electrodes. The number of the LED elements constituting each of the light-emitting arrays or the light-emitting groups differs in each of the light-emitting arrays or the light-emitting groups. Of the plurality of light-emitting arrays arranged in parallel with each other or the light-emitting groups arranged in a line, the number of the LED elements of the light-emitting arrays or the light-emitting groups positioned inside the substrate is more than the number of the LED elements of the light-emitting arrays or the light-emitting groups positioned outside the substrate. | 2011-12-29 |
20110316010 | LIQUID CRYSTAL DISPLAY DEVICE AND TELEVISION SET - Provided is a liquid crystal display device, including: a liquid crystal display panel; and a backlight unit, in which: the backlight unit includes: a plurality of light emitting diodes each having an anode and a cathode; a first substrate; and a second substrate, the plurality of light emitting diodes being mounted on the first substrate and the second substrate; the first substrate and the second substrate are disposed adjacent to each other; light emitting diodes which are adjacent across a boundary between the first substrate and the second substrate are disposed so that the respective anodes are opposed to each other and so as to have a pitch equal to or smaller than a pitch of other adjacent light emitting diodes. | 2011-12-29 |
20110316011 | LIGHT EMITTING DEVICE, LIGHT EMITTING DEVICE UNIT, AND METHOD FOR FABRICATING LIGHT EMITTING DEVICE - In a light emitting device, a light emitting device unit, and a method for fabricating a light emitting device according to an embodiment of the present invention, a light emitting device ( | 2011-12-29 |
20110316012 | ORGANIC LIGHT EMITTING DIODE SEGMENT - The invention relates to an organic light emitting diode segment ( | 2011-12-29 |
20110316013 | OLEDS CONNECTED IN SERIES - OLED device ( | 2011-12-29 |
20110316014 | LED MODULE AND LED LIGHTING DEVICE - An LED module includes a substrate including a main surface and a rear surface that are opposed to each other. The LED module also includes a plurality of LED chips arranged on the main surface, a drive circuit chip that is provided on the substrate and that is provided for driving the plurality of LED chips, a first heat dissipator that is provided on the rear surface and that overlaps the plurality of LED chips as viewed in the thickness direction of the substrate, and a second heat dissipator that is provided at a position closer to the drive circuit chip than the first heat dissipator is. The second head dissipator has a thickness greater than that of the first heat dissipator. The LED module emits a uniform amount of light and color. | 2011-12-29 |
20110316015 | PACKAGE FOR A LIGHT EMITTING ELEMENT - A high-brightness LED module includes a substrate with a recess in which a light emitting element is mounted. The recess is defined by a sidewalls and a relatively thin membrane. At least two micro-vias are provided in the membrane and include conductive material that passes through the membrane. A p-contact of the light emitting element is coupled to a first micro-via and an n-contact of the light emitting element is coupled to a second micro-via. | 2011-12-29 |
20110316016 | LED CHIP PACKAGE STRUCTURE - An LED chip package structure includes a substrate; a first circuit pattern disposed on a surface of the substrate, wherein the first circuit pattern is divided into an electrical connection portion and a carrier portion; a second circuit pattern disposed on another surface of the substrate; a plurality of vias disposed in the substrate and connecting the first circuit pattern and the second circuit pattern, wherein the vias are filled with conductive material; and a plurality of LED chips disposed on the carrier portion of the substrate and electrically connected with the electrical connection portion. The vias filled with the conductive material are utilized to enhance heat dissipation of the substrate. | 2011-12-29 |
20110316017 | WAFER-TYPE LIGHT EMITTING DEVICE HAVING PRECISELY COATED WAVELENGTH-CONVERTING LAYER - The invention relates to a wafer-type light emitting device having a substrate, one or more light emitting semiconductors formed on the substrate, one or more frames provided over the one or more light emitting semiconductors, and one or more wavelength-converting layers applied on the one or more light emitting semiconductors and confined by the one or more frames, wherein the wafer-type light emitting device is diced into a plurality of separate light emitting units. | 2011-12-29 |
20110316018 | ENGINEERING EMISSION WAVELENGTHS IN LASER AND LIGHT EMITTING DEVICES - A light emitting device is provided that includes at least one first semiconductor material layers and at least one second semiconductor material layers. At least one near-direct band gap material layers are positioned between the at least one first semiconductor layers and the at least one second semiconductor material layers. The at least one first semiconductor layers and the at least one second material layers have a larger band gap than the at least one near-direct band gap material layers. The at least one near-direct band gap material layers have an energy difference between the direct and indirect band gaps of less than 0.5 eV. | 2011-12-29 |
20110316019 | Nanoelectronic Structure and Method of Producing Such - The present invention relates to semiconductor devices comprising semiconductor nanoelements. In particular the invention relates to devices having a volume element having a larger diameter than the nanoelement arranged in epitaxial connection to the nanoelement. The volume element is being doped in order to provide a high charge carrier injection into the nanoelement and a low access resistance in an electrical connection. The nanoelement may be upstanding from a semiconductor substrate. A concentric layer of low resistivity material forms on the volume element forms a contact. | 2011-12-29 |
20110316020 | EPITAXIAL WAFER FOR LIGHT EMITTING DIODE - An epitaxial wafer for a light emitting diode, including a GaAs substrate, a light emitting unit provided on the GaAs substrate, and a strain adjustment layer provided on the light emitting unit, wherein the light emitting unit has a strained light emitting layer having a composition formula of (Al | 2011-12-29 |
20110316021 | EPITAXIAL GROWTH METHOD AND DEVICES - Epitaxial growth methods and devices are described that include a textured surface on a substrate. Geometry of the textured surface provides a reduced lattice mismatch between an epitaxial material and the substrate. Devices formed by the methods described exhibit better interfacial adhesion and lower defect density than devices formed without texture. Silicon substrates are shown with gallium nitride epitaxial growth and devices such as LEDs are formed within the gallium nitride. | 2011-12-29 |
20110316022 | LED PACKAGE WITH EFFICIENT, ISOLATED THERMAL PATH - Packages for containing one or more light emitting devices, such as light emitting diodes (LEDs), are disclosed with an efficient, isolated thermal path. In one embodiment, LED package can include a thermal element and at least one electrical element embedded within a body. The thermal element and electrical element can have the same and/or substantially the same thickness and can extend directly from a bottom surface of the LED package such that they are substantially flush with or extend beyond the bottom surface of the LED package. The thermal and electrical element have exposed portions which can be substantially flush with lateral sides of the body such that the thermal and electrical element do not have a significant portion extending beyond an outermost edge of the lateral sides of the body. | 2011-12-29 |
20110316023 | Light-Emitting Device Having A Ramp - A light-emitting device includes a light-emitting stacked layer having an active layer, and a composite substrate located under the light-emitting stacked layer. The composite substrate includes a supportive substrate having a top surface and a bottom surface non-parallel to the active layer; a metal substrate located under the supportive substrate; and a reflective layer located between the supportive substrate and the metal substrate. | 2011-12-29 |
20110316024 | LED PACKAGE - An LED package includes a transparent substrate, an LED die, and an encapsulating layer. The transparent substrate has a first surface defining a recess therein, a second surface opposite to the first surface, and a lateral surface interconnecting the first and second surfaces. The LED die is arranged on the bottom of the recess. The encapsulating layer is in the recess and covers the LED die. The LED package further includes a metal layer formed on the second surface and the lateral surface of the substrate. A pair of electrodes is located at the bottom of the recess and extends through the metal layer. An insulated material is filled between the transparent substrate and the electrodes. Light emitted from the LED die is transmitted through the transparent substrate and reflected by the metal layer. | 2011-12-29 |
20110316025 | Light emitting device - A light emitting device includes a light emitting element, a first phosphor which emits a light by being excited by a light emitted from the light emitting element and a second phosphor which emits a light by being excited by the light emitted from the light emitting element and/or the light emitted from the first phosphor. The light emitted from the light emitting element, the light emitted from the first phosphor and the light emitted from the second phosphor are mixed to make an inclination angle of a line, on a chromaticity diagram, connecting a chromaticity coordinate of the light emitted from the first phosphor and a chromaticity coordinate of the light emitted from the light emitting element equal to an inclination angle of an isotemperature line of light of a predetermined color temperature. | 2011-12-29 |
20110316026 | LIGHT EMITTING DIODE - An exemplary embodiment of the present invention relates to a light emitting diode (LED) including a substrate, a first nitride semiconductor layer arranged on the substrate, an active layer arranged on the first nitride semiconductor layer, a second nitride semiconductor layer arranged on the active layer, a third nitride semiconductor layer disposed between the first nitride semiconductor layer or between the second nitride semiconductor layer and the active layer, the third nitride semiconductor layer comprising a plurality of scatter elements within the third nitride semiconductor layer, and a distributed Bragg reflector (DBR) comprising a multi-layered structure, the substrate being arranged between the DBR and the third nitride semiconductor layer. | 2011-12-29 |
20110316027 | CHIP-TYPE LIGHT EMITTING DEVICE HAVING PRECISELY COATED WAVELENGTH-CONVERTING LAYER AND PACKAGED STRUCTURE THEREOF - The invention relates to a chip-type light emitting device including one or more light emitting semiconductors and one or more frames provided over a top of the one or more light emitting semiconductors. | 2011-12-29 |
20110316028 | Optoelectronic Semiconductor Component - An optoelectronic semiconductor component comprising a semiconductor layer sequence ( | 2011-12-29 |
20110316029 | METHOD FOR TREATING INSIDE SURFACE OF GLASS CONTAINER AND GLASS CONTAINER - A lateral light emitting device that is free from variations and degradation in beam quality and reduction in reliability caused by adhesive, can be easily produced, and has a small diameter in order to be usable for a thin blood vessel and the like is developed. | 2011-12-29 |
20110316030 | SEMICONDUCTOR LIGHT EMITTING DIODE AND METHOD OF PRODUCING THE SAME - A semiconductor light emitting diode comprising: a support substrate; an intermediate layer including an intermediate electrode portion, a second conductive semiconductor layer, an active layer, a first conductive semiconductor layer and an upper electrode portion sequentially disposed on the upper surface side of the support substrate in this order; and a lower electrode layer provided on the lower surface side of the support substrate, wherein: the intermediate layer has at least one intermediate electrode portion extending linearly or in an island-like shape; and the upper electrode portion and the intermediate electrode portion are disposed, in a view obtained by projecting these electrode portions, on an imaginary plane in parallel with the upper surface of the support substrate, respectively, in a positional relationship that these electrode portions, are offset from each other. | 2011-12-29 |
20110316031 | TRANSFER SHEET FOR PHOSPHOR LAYER AND LIGHT-EMITTING DEVICE - A transfer sheet for a phosphor layer includes a release substrate, a phosphor layer formed on the release substrate, and an adhesive layer formed on the phosphor layer. | 2011-12-29 |
20110316032 | PHOSPHOR LAYER AND LIGHT-EMITTING DEVICE - A phosphor layer is composed of a resin in which phosphor particles and light scattering particles are dispersed. | 2011-12-29 |
20110316033 | LIGHT EMITTING MODULE, METHOD OF MANUFACTURING THE LIGHT EMITTING MODULE, AND LAMP UNIT - In a light emitting module, a light wavelength conversion member | 2011-12-29 |
20110316034 | Side By Side Light Emitting Diode (LED) Having Separate Electrical And Heat Transfer Paths And Method Of Fabrication - A light emitting diode includes a thermal conductive substrate having at least one electrical isolation layer configured to provide vertical electrical isolation and a heat transfer path through the substrate from a front side (first side) to a back side (second side) thereof. The light emitting diode includes an anode having a through interconnect, and a cathode having a through interconnect, which are arranged side by side on the substrate. The light emitting diode also includes a LED chip mounted to the substrate between the anode and the cathode. A method for fabricating the light emitting diode includes the steps of providing a thermal conductive substrate having an electrical isolation layer, forming an anode via and a cathode via side by side on a first side of the substrate part way through the substrate, forming an anode through interconnect in the anode via and a cathode through interconnect in the cathode via, thinning the substrate from a second side of the substrate to the anode through interconnect and the cathode through interconnect, and mounting a LED chip to the first side in electrical communication with the cathode through interconnect and the anode through interconnect. | 2011-12-29 |
20110316035 | HEAT DISSIPATING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a heat-dissipating substrate, which includes a base substrate including a metal layer, an insulating layer formed on one surface of the metal layer, and a circuit layer formed on the insulating layer, a heat sink layer formed on the other surface of the metal layer, a connector for connecting the base substrate and the heat sink layer to each other, an opening formed in a direction of thickness of the base substrate and into which the connector is inserted, and an anodized layer formed on either or both of the other surface and a lateral surface of the metal layer, and in which the metal layer and the heat sink layer are insulated from each other by means of the anodized layer, thus preventing transfer of static electricity or voltage shock to the metal layer. A method of manufacturing the heat-dissipating substrate is also provided. | 2011-12-29 |
20110316036 | LIGHT EMITTING DEVICE AND SEMICONDUCTOR WAFER - According to one embodiment, a light emitting device includes a substrate, a bonding layer, a plurality of protrusions, a first electrode, a translucent resin layer, and a first overcoat electrode. The bonding layer is provided on the substrate. The plurality of protrusions is provided on the bonding layer and includes a first conductivity type layer, a light emitting layer provided on the first conductivity type layer, and a second conductivity type layer provided on the light emitting layer. The first electrode is provided on the second conductivity type layer. The translucent resin layer is provided around the protrusions. The first overcoat electrode is provided on the translucent resin layer and connects the first electrodes respectively provided on the plurality of protrusions. The substrate, the translucent resin layer, and the first overcoat electrode each are exposed at a side surface of the light emitting device. | 2011-12-29 |
20110316037 | SEMICONDUCTOR LIGHT EMISSION ELEMENT - A semiconductor light emission element ( | 2011-12-29 |
20110316038 | SUBSTRATE COMPRISING ALUMINUM/GRAPHITE COMPOSITE, HEAT DISSIPATION PART COMPRISING SAME, AND LED LUMINESCENT MEMBER - A process for producing a substrate, which comprises processing an aluminum/graphite composite into plates having a thickness of 0.5-3 mm using a multi-wire saw under the following conditions (1) to (4): (1) the wires have abrasive grains bonded thereto which are one or more substances selected from diamond, C—BN, silicon carbide, and alumina and have an average particle diameter of 10-100 μm; (2) the wires have a diameter of 0.1-0.3 mm; (3) the wires are run at a rate of 100-700 m/min; and (4) the composite is cut at a rate of 0.1-2 mm/min. The aluminum/graphite composite has a surface roughness (Ra) of 0.1-3 μm, a thermal conductivity at 25° C. of 150-300 W/mK, a ratio of the maximum to the minimum value of thermal conductivity in three perpendicular directions of 1-1.3, a coefficient of thermal expansion at 25-150° C. of 4×10 | 2011-12-29 |
20110316039 | VERTICAL LED WITH CURRENT GUIDING STRUCTURE - Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided. | 2011-12-29 |
20110316040 | COMPOSITE SUBSTRATE FOR LED LIGHT EMITTING ELEMENT, METHOD OF PRODUCTION OF SAME, AND LED LIGHT EMITTING ELEMENT - A substrate for an LED light emitting element having a small difference of linear thermal expansion coefficient with the III-V semiconductor crystal constituting an LED, having an excellent thermal conductivity, and suitable for high output LEDs. A porous body comprises one or more materials selected from silicon carbide, aluminum nitride, silicon nitride, diamond, graphite, yttrium oxide, and magnesium oxide and has a porosity that is 10 to 50 volume % and a three-point bending strength that is 50 MPa or more. The porous body is infiltrated, by means of liquid metal forging, with aluminum alloy or pure aluminum at an infiltration pressure of 30 MPa or more, cut and/or ground to a thickness of 0.05 to 0.5 mm and to a surface roughness (Ra) of 0.01 to 0.5 μm, then is formed with a metal layer comprising one or more elements selected from Ni, Co, Pd, Cu, Ag, Au, Pt and Sn on its surface to a thickness of 0.5 to 15 μm, so as to thereby produce the composite substrate for the LED light emitting element. | 2011-12-29 |
20110316041 | SAPPHIRE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME AND NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE - A sapphire substrate having one principal surface on which a nitride semiconductor is grown, said one principal surface having a plurality of projections. Each of the projections has a generally pyramidal shape with a not truncated, more sharpened tip and with an inclined surface composed of a crystal growth-suppression surface that lessens or suppresses the growth of the nitride semiconductor and also which has an inclination change line at which an inclination angle discontinuously varies. | 2011-12-29 |
20110316042 | THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD - Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants. | 2011-12-29 |
20110316043 | Thin Group IV Semiconductor Structures - Thin group IV semiconductor structures are provided comprising a thin Si substrate and a second region formed directly on the Si substrate, where the second region comprises either (i) a Ge1 | 2011-12-29 |
20110316044 | DELTA MONOLAYER DOPANTS EPITAXY FOR EMBEDDED SOURCE/DRAIN SILICIDE - Semiconductor structures are disclosed that have embedded stressor elements therein. The disclosed structures include at least one FET gate stack located on an upper surface of a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate at a footprint of the at least one FET gate stack. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. The structure further includes embedded stressor elements located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each of the embedded stressor elements includes, from bottom to top, a first layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, a second layer of a second epitaxy doped semiconductor material located atop the first layer, and a delta monolayer of dopant located on an upper surface of the second layer. The structure further includes a metal semiconductor alloy contact located directly on an upper surface of the delta monolayer. | 2011-12-29 |
20110316045 | LAYOUT DESIGN FOR A HIGH POWER, GaN-BASED FET - A FET includes a substrate, a buffer layer disposed on the substrate, a channel layer disposed over the buffer layer and a barrier layer disposed over the channel layer. Source, gate and drain electrodes are located over the barrier layer and extend in a longitudinal direction thereon. A portion of the channel and barrier layers define a mesa extending in the longitudinal direction and the source and drain electrodes extend beyond an edge of the mesa. The gate electrodes extend along an edge sidewall of the mesa. A conductive source interconnect is disposed over the buffer layer and have a first end electrically connected to the source electrode. A first dielectric layer is disposed over the buffer layer and over the source interconnect. A gate via is formed in the first dielectric layer. A conductive gate node extends along the buffer layer and electrically connects the portion of the gate electrode extending along the sidewall of the mesa. A gate pad is disposed on the first dielectric layer adjacent the mesa. A conductive gate connect strip is located over the gate node and is in contact therewith. The gate strip is in electrical contact with the gate pad. A source via is formed in the first dielectric layer and a source pad is formed in the source via. The conductive source interconnect has a second end in electrical contact with the source pad. | 2011-12-29 |
20110316046 | Field Effect Transistor Device - A method for forming a field effect transistor device includes forming a gate stack portion on a substrate, forming a spacer portion on the gates stack portion and a portion of the substrate, removing an exposed portion of the substrate, epitaxially growing a first silicon material on the exposed portion of the substrate, removing a portion of the epitaxially grown first silicon material to expose a second portion of the substrate, and epitaxially growing a second silicon material on the exposed second portion of the substrate and the first silicon material. | 2011-12-29 |
20110316047 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The objective of the present invention is to provide a semiconductor device of a hetero-junction field effect transistor that is capable of obtaining a high output and a high breakdown voltage and a manufacturing method of the same. The present invention is a semiconductor device of a hetero junction field effect transistor provided with an Al | 2011-12-29 |
20110316048 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - There is provided a semiconductor device and a method for fabricating the same whose withstanding characteristic may be enhanced and whose ON resistance may be reduced. A MIS-type HEMT includes a carrier traveling layer made of a group-III nitride semiconductor and formed on a supporting substrate, a carrier supplying layer made of a group-III nitride semiconductor and formed on the carrier traveling layer, source and drain electrodes formed on the carrier supplying layer, insulating films formed on the carrier supplying layer and a gate electrode formed on the insulating films. The insulating film is formed in a region interposed between the source and drain electrodes and has a trench whose cross-section is inverted trapezoidal and whose upper opening is wider than a bottom thereof. The gate electrode is formed at least from the bottom of the trench onto the insulating films on the side of the drain electrode. | 2011-12-29 |
20110316049 | NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a vertical nitride semiconductor device in which occurrence of leak currents can be suppressed, and a method for manufacturing such nitride semiconductor device. A nitride semiconductor device, which is a vertical HEMT, is provided with an n | 2011-12-29 |
20110316050 | SEMICONDUCTOR DEVICE HAVING A HETEROJUNCTION BIOPOLAR TRANSISTOR AND A FIELD EFFECT TRANSISTOR - A semiconductor device with a heterojunction bipolar transistor (HBT) and a field effect transistor (FET) formed over the same substrate; providing improved HBT characteristics and a lowered HBT collector resistance and also satisfactory etching of the FET gate recess, along with low ON-resistance in the FET. The sub-collector layer of a heterojunction bipolar transistor (HBT) is a laminated structure of multiple semiconductor layers, and moreover with a collector electrode formed on a section projecting out from one collector layer. In two of the FET, at least one semiconductor layer on the semiconductor substrate side of the semiconductor layers forming the sub-collector layer of the HBT also serves as at least a portion of a capacitor layer. The total film thickness of the HBT sub-collector layer is 500 nm or more; and the total film thickness of the FET capacitor layer is between 50 nm and 300 nm. | 2011-12-29 |
20110316051 | SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, AND METHOD OF PRODUCING ELECTRONIC DEVICE - The semiconductor wafer includes: a base wafer; and an inhibition layer that is disposed on the base wafer as one piece or to be separate portions from each other, and inhibits growth of a crystal of a compound semiconductor, where the inhibition layer has a plurality of first opening regions that have a plurality of openings penetrating the inhibition layer and leading to the base wafer, each of the plurality of first opening regions includes therein a plurality of first openings disposed in the same arrangement, some of the plurality of first openings are first element forming openings each provided with a first compound semiconductor on which an electronic element is to be formed, and the other of the plurality of first openings are first dummy openings in which no electronic element is to be formed. | 2011-12-29 |
20110316052 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In addition to a memory macro region and functional circuit regions on a substrate, a semiconductor integrated circuit device includes a dummy pattern region | 2011-12-29 |
20110316053 | MOS transistor structure with easy access to all nodes - A transistor device structured such that the bulk, gate, drain, and source are all accessible from all four edges of the device and such that current distribution is uniform over the device is provided. The transistor is created with a four-metal CMOS process. A bulk connection can be made with Metal | 2011-12-29 |
20110316054 | Method, Apparatus, and System for Micromechanical Gas Chemical Sensing Capacitor - A method for fabrication of capacitive environment sensors is provided in which the sensor elements are integrated in a CMOS structure with electronics through the use of complementary metal oxide semiconductor (CMOS) fabrication methods. Also provided are environment sensors fabricated, for example, by the method, and a measurement system using the environment sensors fabricated by the method. The described method includes etching away one of the metal layers in a CMOS chip to create a cavity. This cavity is then filled with an environment-sensitive dielectric material to form a sensing capacitor between plates formed by the metal adhesion layers or an array of contacts from other metal layers of the CMOS structure. This approach provides improved sensing capabilities in a system that is easily manufactured. | 2011-12-29 |
20110316055 | SUBSTRATE PROVIDED WITH A SEMI-CONDUCTING AREA ASSOCIATED WITH TWO COUNTER-ELECTRODES AND DEVICE COMPRISING ONE SUCH SUBSTRATE - A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode. | 2011-12-29 |
20110316056 | Semiconductor device and method of manufacturing the same - The present invention relates to a method of manufacturing a semiconductor device having a shared contact for connection between a source/drain region and a gate electrode. After formation of a gate electrode via a gate insulating film on a semiconductor substrate, a top surface of the substrate is covered with a cover film. After removal of the cover film from at least one of sidewall surface of the gate electrode and a part of the top surface of the substrate adjacent to the sidewall surface, a semiconductor layer is epitaxially grown on a top surface of an exposed substrate to electrically connect the substrate and the at least one sidewall surface of the gate electrode. Then, a source/drain region is formed in a top surface part of the substrate or the semiconductor layer using the gate electrode as a mask. | 2011-12-29 |
20110316057 | WIRING BOARD, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS THEREOF - It is an object to reduce defective conduction in a wiring board or a semiconductor device whose integration degree is increased. It is another object to manufacture a highly reliable wiring board or semiconductor device with high yield. In a wiring board or a semiconductor device having a multilayer wiring structure, a conductive layer having a curved surface is used in connection between conductive layers used for the wirings. The top of a conductive layer in a lower layer exposed by removal of an insulating layer therearound has a curved surface, so that coverage of the conductive layer in the lower layer with a conductive layer in an upper layer stacked thereover can be favorable. A conductive layer is etched using a resist mask having a curved surface, so that a conductive layer having a curved surface is formed. | 2011-12-29 |
20110316058 | FERRO-ELECTRIC CAPACITOR MODULES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES - Ferro-electric capacitor modules, methods of manufacture and design structures. The method of manufacturing the ferro-electric capacitor includes forming a barrier layer on an insulator layer of a CMOS structure. The method further includes forming a top plate and a bottom plate over the barrier layer. The method further includes forming a ferro-electric material between the top plate and the bottom plate. The method further includes encapsulating the barrier layer, top plate, bottom plate and ferro-electric material with an encapsulating material. The method further includes forming contacts to the top plate and bottom plate, through the encapsulating material. At least the contact to the top plate and a contact to a diffusion of the CMOS structure are in electrical connection through a common wire. | 2011-12-29 |
20110316059 | FLEXIBLE FERROELECTRIC MEMORY DEVICE AND MANUFACTURING METHOD FOR THE SAME - The present disclosure relates to a flexible nonvolatile ferroelectric memory device, a 1T-1R (1Transistor-1Resistor) flexible ferroelectric memory device, and a manufacturing method for the same. | 2011-12-29 |
20110316060 | ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL - An electronic device can include a nonvolatile memory cell that includes a capacitor, a tunnel structure, a state transistor, and an access transistor. In an embodiment, the capacitor and tunnel structure can include upper electrodes, wherein the upper electrode of the capacitor has a first conductivity type, and the upper electrode of the tunnel structure includes at least a portion that has a second conductivity type opposite the first conductivity type. In another embodiment, a process of forming the nonvolatile memory is performed using a single poly process. In a further embodiment, charge carriers can tunnel through a gate dielectric layer of the state transistor during programming and tunnel through a tunnel dielectric of the tunnel transistor during erasing. | 2011-12-29 |
20110316061 | STRUCTURE AND METHOD TO CONTROL BOTTOM CORNER THRESHOLD IN AN SOI DEVICE - Semiconductor structures and methods to control bottom corner threshold in a silicon-on-insulator (SOI) device. A method includes doping a corner region of a semiconductor-on-insulator (SOI) island. The doping includes tailoring a localized doping of the corner region to reduce capacitive coupling of the SOI island with an adjacent structure. | 2011-12-29 |
20110316062 | SEMICONDUCTOR DEVICE - In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level. | 2011-12-29 |
20110316063 | THREE DIMENSIONAL MEMORY AND METHODS OF FORMING THE SAME - Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described. | 2011-12-29 |
20110316064 | Semiconductor Memory Devices And Methods Of Forming The Same - Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region. | 2011-12-29 |
20110316065 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile semiconductor memory device includes a first stack unit with a first selection transistor and a second selection transistor formed on a semiconductor substrate and a second stack unit with first insulating layers and first conductive layers stacked alternately on the upper surface of the first stack unit. The second stack unit includes a second insulating layer formed in contact with side walls of the first insulating layer and the first conductive layer, a charge storage layer formed in contact with the second insulating layer for storing electrical charges, a third insulating layer formed in contact with the charge storage layer, and a first semiconductor layer formed in contact with the third insulating layer so as to extend in a stacking direction, with one end connected to one diffusion layer of the first selection transistor and the other end connected to a diffusion layer of the second selection transistor. | 2011-12-29 |
20110316066 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a tunnel insulating film, a first electrode, an interelectrode insulating film and a second electrode. The tunnel insulating film is provided on the semiconductor substrate. The first electrode is provided on the tunnel insulating film. The interelectrode insulating film is provided on the first electrode. The second electrode is provided on the interelectrode insulating film. The interelectrode insulating film includes a stacked insulating layer, a charge storage layer and a block insulating layer. The charge storage layer is provided on the stacked insulating layer. The block insulating layer is provided on the charge storage layer. The stacked insulating layer includes a first insulating layer, a quantum effect layer and a second insulating layer. The quantum effect layer is provided on the first insulating layer. The second insulating layer is provided on the quantum effect layer. | 2011-12-29 |
20110316067 | ELECTRONIC DEVICE INCLUDING A TUNNEL STRUCTURE - An electronic device can include a tunnel structure that includes a first electrode, a second electrode, and tunnel dielectric layer disposed between the electrodes. In a particular embodiment, the tunnel structure may or may not include an intermediate doped region that is at the primary surface, abuts a lightly doped region, and has a second conductivity type opposite from and a dopant concentration greater than the lightly doped region. In another embodiment, the electrodes have opposite conductivity types. In a further embodiment, an electrode can be formed from a portion of a substrate or well region, and the other electrode can be formed over such portion of the substrate or well region. | 2011-12-29 |
20110316068 | FLASH MEMORY WITH RECESSED FLOATING GATE - A flash memory device wherein the floating gate of the flash memory is defined by a recessed access device. The use of a recessed access device results in a longer channel length with less loss of device density. The floating gate can also be elevated above the substrate a selected amount so as to achieve a desirable coupling between the substrate, the floating gate and the control gate comprising the flash cell. | 2011-12-29 |
20110316069 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a non-memory unit. The memory unit includes a stacked structure including electrode films stacked in a first direction, and a interelectrode insulating film provided between the electrode films, a select gate electrode stacked with the stacked structure along the first direction, a semiconductor pillar piercing the stacked structure and the select gate electrode along the first direction and a pillar portion memory layer provided between the electrode films and the semiconductor pillar. The non-memory unit includes a dummy conductive film including a portion in a layer being identical to at least one of the electrode films, a dummy select gate electrode in a layer being identical to the select gate electrode, a first non-memory unit contact electrode electrically connected to the dummy conductive and a second non-memory unit contact electrode electrically connected to the dummy select gate. | 2011-12-29 |
20110316070 | CHARGE TRAPPING NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MAKING - The present invention provides a charge trapping non-volatile semiconductor memory device and a method of making the device. The charge trapping non-volatile semiconductor memory device comprises a semiconductor substrate, a source region, a drain region, and, consecutively formed over the semiconductor substrate, a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode. The drain region includes a P-N junction, and the source region includes a metal-semiconductor junction formed between the semiconductor substrate and a metal including titanium, cobalt, nickel, platinum or one of their various combinations. The charge trapping non-volatile semiconductor memory device according to the present disclosure has low programming voltage, fast programming speed, low energy consumption, and relatively high device reliability. | 2011-12-29 |
20110316071 | POWER SEMICONDUCTOR DEVICE - Provided is a power semiconductor device including a semiconductor substrate, in which a current flows in a thickness direction of the semiconductor substrate. The semiconductor substrate includes a resistance control structure configured so that a resistance to the current becomes higher in a central portion of the semiconductor substrate than a peripheral portion of the semiconductor substrate. | 2011-12-29 |
20110316072 | SEMICONDUCTOR MEMORY DEVICES INCLUDING ASYMMETRIC WORD LINE PADS - Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the first stack. The first stack may include a plurality of first word lines with a plurality of first line pads stacked in a stair form, and the second stack may include a plurality of second word lines with a plurality of second line pads stacked in a stair form. The second stack may be shifted on the first stack such that sides of the plurality of first word line pads are exposed. | 2011-12-29 |
20110316073 | SOI CMOS DEVICE HAVING VERTICAL GATE STRUCTURE - The present invention discloses an SOI CMOS device having a vertical gate structure, comprising: an SOI substrate, and an NMOS region and a PMOS region grown on the SOI substrate, wherein the NMOS region and the PMOS region share one vertical gate region, said vertical gate region lying in the same plane as the NMOS region and the PMOS region and between the NMOS region and the PMOS region; a gate oxide layer is arranged between the vertical gate region and the NMOS region for isolation; and a gate oxide layer is arranged between the vertical gate region and the PMOS region for isolation. The present invention occupies small area, contains less pattern layers, requires a simple process, has an open body region that can completely avoid the floating effect of the traditional SOI CMOS device, and is convenient to parasitic resistance and capacitance tests. | 2011-12-29 |
20110316074 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A shape of an upper edge of a trench is realized as an upwardly-open tapered surface T | 2011-12-29 |
20110316075 | TRENCH MOSFET WITH TRENCHED FLOATING GATES HAVING THICK TRENCH BOTTOM OXIDE AS TERMINATION - A power semiconductor power device having composite trench bottom oxide and multiple trench floating gates is disclosed. The gate charge is reduced by forming a pad oxide surrounding a HDP oxide on trench bottom. The multiple trenched floating gates are applied in termination for saving body mask. | 2011-12-29 |
20110316076 | Power MOSFET Device with Self-Aligned Integrated Schottky and its Manufacturing Method - A power MOSFET device and manufacturing method thereof, includes the steps of selectively depositing a first conductive material in the middle region at the bottom of a contact trench and contacting with light-doped N-type epitaxial layer to form a Schottky junction and depositing a second conductive material at the side wall and bottom corner of the contact trench and contacting with P-type heavy-doped body region to form an ohmic junction. The first and second conductive materials can respectively optimize the performance of the ohmic contact and the Schottky contact without compromise. Meanwhile, the corner of the contact trench is surrounded by P-type heavy-doped region thereby effectively reducing the leakage currents accumulated at the corner of the contact trench. | 2011-12-29 |
20110316077 | POWER SEMICONDUCTOR STRUCTURE WITH SCHOTTKY DIODE AND FABRICATION METHOD THEREOF - A power semiconductor structure with schottky diode is provided. In the step of forming the gate structure, a separated first polysilicon structure is also formed on the silicon substrate. Then, the silicon substrate is implanted with dopants by using the first polysilicon structure as a mask to form a body and a source region. Afterward, a dielectric layer is deposited on the silicon substrate and an open penetrating the dielectric layer and the first polysilicon structure is formed so as to expose the source region and the drain region below the body. The depth of the open is smaller than the greatest depth of the body. Then, a metal layer is filled into the open to electrically connect to the source region and the drain region. | 2011-12-29 |
20110316078 | SHIELDED LEVEL SHIFT TRANSISTOR - A semiconductor device can include a transistor and an isolation region. The transistor is formed in a semiconductor substrate having a first conductivity type. The transistor includes a drift region extending from a drain region toward a source region and having a second conductivity type. The drift region includes a first resurf region near a working top surface and having the first conductivity type. The high voltage isolation island region includes a first well region laterally offset from the drift region. The first well region has the second conductivity type. An isolation region is located laterally between the drain region and the first well region. The isolation region comprises a portion of the semiconductor substrate extending to the top working surface. | 2011-12-29 |
20110316079 | Shallow Junction Formation and High Dopant Activation Rate of MOS Devices - A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer. | 2011-12-29 |
20110316080 | FIN TRANSISTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein an insulation material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and a bulk semiconductor material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages such as low cost and high heat transfer. | 2011-12-29 |