52nd week of 2013 patent applcation highlights part 16 |
Patent application number | Title | Published |
20130341641 | RECTIFIER CIRCUIT - A rectifier circuit has a rectifier element and a unipolar field-effect transistor connected in series between a first terminal and a second terminal. The rectifier element comprises a first electrode and a second electrode disposed in a direction of a forward current flowing from the first terminal to the second terminal. The field-effect transistor has a gate electrode having a potential identical to a potential at the first electrode, and a source electrode and a drain electrode connected in series to the rectifier element and passing a current depending on the potential at the gate electrode. A breakdown voltage between the gate electrode and drain electrode of the field-effect transistor in a reverse bias mode, where a potential at the second terminal is higher than a potential at the first terminal, being set higher than a breakdown voltage of the rectifier element. | 2013-12-26 |
20130341642 | MOS TRANSISTOR, FABRICATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT - Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a channel region including an asymmetric stressing layer having a stress gradually varied from a compressive stress to a tensile stress or from a tensile stress to a compressive stress from a first end of the channel region adjacent to a source region to a second end of the channel region adjacent to a drain region. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase a source-drain saturation current in a write operation and to reduce a source-drain saturation current in a read operation. Read and write margins of the SRAM can be increased. | 2013-12-26 |
20130341643 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE DEVICE - A first first-conductivity-type impurity region ( | 2013-12-26 |
20130341644 | METHOD AND DESIGN OF AN RF THRU-VIA INTERCONNECT - In summary, a vertical metalized transition in the form of a via goes from the back side of a high thermal conductivity substrate and through any semiconductor layers thereon to a patterned metalized strip, with the substrate having a patterned metalized layer on the back side that is provided with a keep away zone dimensioned to provide impedance matching for RF energy coupled through the substrate to the semiconductor device while at the same time permitting the heat generated by the semiconductor device to flow through the high thermal conductivity substrate, through the back side of the substrate and to a beat sink. | 2013-12-26 |
20130341645 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A collector layer is made of silicon carbide having a first conductivity type. A switching element is provided on the collector layer. The switching element includes a junction gate for controlling a channel having a second conductivity type different from the first conductivity type. | 2013-12-26 |
20130341646 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A silicon carbide semiconductor device includes a silicon carbide substrate and a contact electrode. The silicon carbide substrate includes an n type region and a p type region that makes contact with the n type region. The contact electrode makes contact with the n type region and the p type region. The contact electrode contains Ni atoms and Si atoms. The number of the Ni atoms is not less than 87% and not more than 92% of the total number of the Ni atoms and the Si atoms. Accordingly, there can be provided a silicon carbide semiconductor device, which can achieve ohmic contact with an n type impurity region and can achieve a low contact resistance for a p type impurity region, as well as a method for manufacturing such a silicon carbide semiconductor device. | 2013-12-26 |
20130341647 | SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide semiconductor device includes a silicon carbide substrate, and a contact electrode. The silicon carbide substrate includes an n type region and a p type region in contact with the n type region. The contact electrode forms contact with the silicon carbide substrate. The contact electrode includes a first region containing TiSi, and a second region containing Al. The first region includes an n contact region in contact with the n type region and a p contact region in contact with the p type region. The second region is formed to contact the p type region and the n type region, and to surround the p contact region and the n contact region. Accordingly, there can be provided a silicon carbide semiconductor device including an electrode allowing ohmic contact with both a p type impurity region and an n type impurity region formed at a silicon carbide substrate. | 2013-12-26 |
20130341648 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE - A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided. | 2013-12-26 |
20130341649 | METHOD FOR MAKING A SEMICONDUCTOR STRUCTURE WITH A BURIED GROUND PLANE - The invention relates to a method for making a semiconducting structure, including:
| 2013-12-26 |
20130341650 | PHOTOSENSOR CHIP PACKAGE STRUCTURE - A photosensor chip package structure comprises a substrate, a light-emitting chip and a photosensor chip including an ambient light sensing unit and a proximity sensing unit. The substrate has a first basin, a second basin and a light-guiding channel. The openings of the first and second basins respectively face different directions. One opening of the light-guiding channel and the opening of the first basin face the same direction. The other opening of the light-guiding channel interconnects with the second basin. The light-emitting chip is arranged in the first basin. The photosensor chip is arranged in the second basin. The light-guiding channel conducts the light generated by the light-emitting chip and the ambient light to the photosensor chip. The photosensor chip operates as soon as it receives the light generated by the light-emitting chip and/or the ambient light. | 2013-12-26 |
20130341651 | SENSOR SUBSTRATE AND SENSING DISPLAY PANEL HAVING THE SAME - A sensor substrate includes a base substrate, a black matrix pattern, a sensing electrode pattern, a driving electrode pattern, and at least one bridge line. The black matrix pattern is disposed on the base substrate and divides the base substrate into a light transmission area and a light blocking area. The sensing electrode pattern includes a plurality of first unit patterns arranged in association with a first direction. The driving electrode pattern includes a plurality of second unit patterns arranged in association with a second direction and disposed adjacent to the plurality of first unit patterns. The at least one bridge line is connected between at least two of the plurality of first unit patterns or between at least two of the plurality of second unit patterns. | 2013-12-26 |
20130341652 | LIGHT EMITTING DIODE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - An exemplary light-emitting diode (LED) package includes a first electrode, a second electrode spaced from the first electrode, an electrically insulating substrate sandwiched by and connecting with the first electrode and the second electrode, a first LED chip and a second LED chip mounted on top surfaces of the first and second electrodes respectively, and a reflector covering the top surfaces of the first and second electrodes. The first LED chip mounted on the top surface of the first electrode is above the second LED chip mounted on the top surface of the second surface. L-shaped retaining walls are formed on the top surfaces of the first and second electrodes. By the retaining walls, the LED package can also be used as a side-view LED package. | 2013-12-26 |
20130341653 | SOLID STATE LIGHTING COMPONENT - An LED component comprising an array of LED chips mounted on a planar surface of a submount with the LED chips capable of emitting light in response to an electrical signal. The LED chips comprise respective groups emitting at different colors of light, with each of the groups interconnected in a series circuit. A lens is included over the LED chips. Other embodiments can comprise thermal spreading structures included integral to the submount and arranged to dissipate heat from the LED chips. | 2013-12-26 |
20130341654 | LIGHT EMITTING DEVICE PACKAGE AND LIGHT UNIT HAVING THE SAME - Disclosed is an LED package. The LED package includes a package body, a first frame and a second frame on the package body and a light emitting device chip on the first frame. The first frame is separated from the second frame, and the first frame includes a bottom frame on the package body and at least two sidewall frames extending from the bottom frame and inclined with respect to the bottom frame. | 2013-12-26 |
20130341655 | METHOD FOR PRODUCING AN ELECTRICAL TERMINAL SUPPORT - The invention relates to a method for producing an electrical terminal support for an optoelectronic semiconductor body, comprising the following steps: providing a carrier assembly ( | 2013-12-26 |
20130341656 | Miniature Surface Mount Device - A surface mount LED package includes a lead frame carrying a plurality of LEDs and a plastic casing at least partially encasing the lead frame. The lead frame includes an electrically conductive chip carrier and first, second, and third electrically conductive connection parts separate from the electrically conductive chip carrier. Each of the first, second and third electrically conductive connection parts has an upper surface, a lower surface, and a connection pad on the upper surface. The plurality of LEDs are disposed on an upper surface of the electrically conductive chip carrier. Each LED has a first electrical terminal electrically coupled to the electrically conductive chip carrier. Each LED has a second electrical terminal electrically coupled to the connection pad of a corresponding one of the first, second, and third electrically conductive connection parts. | 2013-12-26 |
20130341657 | LIGHT-EMITTING MODULE AND LUMINAIRE - A light-emitting module includes a substrate in an embodiment. The light-emitting module includes a first light-emitting element mounted on the substrate through a first connecting structure in an embodiment. The light-emitting module includes a second light-emitting element having a light-emitting efficiency that is more sensitive to a change in temperature than that of the first light-emitting element, and mounted on the substrate through a second connecting structure having a higher thermal radiation than the first connecting structure. | 2013-12-26 |
20130341658 | LIGHT-EMITTING DEVICE HAVING DIELECTRIC REFLECTOR AND METHOD OF MANUFACTURING THE SAME - A light-emitting device includes a first conductive semiconductor layer formed on a substrate, a mask layer formed on the first conductive semiconductor layer and having a plurality of holes, a plurality of vertical light-emitting structures vertically grown on the first conductive semiconductor layer through the plurality of holes, a current diffusion layer surrounding the plurality of vertical light-emitting structures on the first conductive semiconductor layer, and a dielectric reflector filling a space between the plurality of vertical light-emitting structures on the current diffusion layer. | 2013-12-26 |
20130341659 | DISPLAY PANEL - A display panel including a substrate, a meshed shielding pattern, and a plurality of light-emitting devices is provided. The meshed shielding pattern is disposed on the substrate so as to define a plurality of pixel regions on the substrate. The light-emitting devices are disposed on the substrate. At least one light-emitting device of the light-emitting devices is disposed in each pixel region of the pixel regions, wherein an area of the pixel region is A1, an area of the light-emitting device is A2, and a ratio of A2 to A1 is below 50%. | 2013-12-26 |
20130341660 | LED MODULE - An exemplary LED module includes an LED and a lens covering the LED. The lens includes a light-guiding portion over the LED and retaining portions protruding downwardly from the light-guiding portion. The LED includes a substrate, a first electrode and a second electrode mounted on the substrate, and an LED chip electrically connecting the first electrode and the second electrode respectively. Through holes are defined in the first electrode and the second electrode, respectively. Each retaining portion includes a first rugged portion and a second rugged portion. The retaining portions are inserted into the through holes correspondingly, the first rugged portion connects glue filled in a corresponding through hole, and the second rugged portion abuts the substrate, whereby the lens and the substrate are securely connected together. | 2013-12-26 |
20130341661 | SEMICONDUCTOR LIGHT EMITTING ELEMENT - A semiconductor light emitting element comprising a light-reflecting layer formed on a support substrate, the light-reflecting layer having light reflectivity and including a bank portion having a particular plane pattern, a first electrode formed on the light-reflecting layer so as to surround the bank portion of the light-reflecting layer, the first electrode having light transparency, a stacked semiconductor layer formed on the first electrode, the stacked semiconductor layer, and a second electrode selectively formed on the stacked semiconductor layer, wherein the bank portion of the light-reflecting layer has a portion that overlaps the second electrode when viewed in plan, a portion that rises up from the first electrode when viewed in cross section, and a side wall surface that reflects light emitted from the active layer to a region of the second semiconductor layer in which the second electrode is not formed. | 2013-12-26 |
20130341662 | Yellow-Green to Yellow-Emitting Phosphors Based on Halogenated-Aluminates - Disclosed herein are yellow-green and yellow-emitting aluminate based phosphors for use in white LEDs, general lighting, and LED and backlighting displays. In one embodiment of the present invention, the cerium-activated, yellow-green to yellow-emitting aluminate phosphor comprises the rare earth lutetium, at least one alkaline earth metal, aluminum, oxygen, at least one halogen, and at least one rare earth element other than lutetium, wherein the phosphor is configured to absorb excitation radiation having a wavelength ranging from about 380 nm to about 480 nm, and to emit light having a peak emission wavelength ranging from about 550 nm to about 600 nm. | 2013-12-26 |
20130341663 | LED WITH SURFACE ROUGHENING - An LED having a p-type layer of material with an associated p-contact, an n-type layer of material with an associated n-contact and an active region between the p-type layer and the n-type layer, includes a roughened emitting-side surface to further enhance light extraction. | 2013-12-26 |
20130341664 | SILICATE PHOSPHORS - The invention relates to compounds of the general formula (I) EA2-xEuxSiO4.aM2B4O7 (I) where EA stands for two or more elements selected from Ca, Sr, Zn and Ba, M stands for Li, Na or K, and a stands for a value from the range 0.01≦a≦0.08, and x stands for a value from the range 0.01≦x≦0.25. | 2013-12-26 |
20130341665 | LED (Light-Emitting Diode) Luminous Source Module - A polymeric optical lens for a light-emitting diode (LED) light source module, and in particular an LED light source module comprising this polymeric optical lens, and an LED lamp comprising this module. More particularly, an optical lens for a light-emitting diode (LED) light source module comprising a polymer selected from the group consisting of cellulose and its derivatives; starch and its derivatives; alginates and their derivatives; guars and their derivatives; chitin and its derivatives; and pectin and its derivatives. | 2013-12-26 |
20130341666 | SEMICONDUCTOR LIGHT EMITTING DEVICE - A semiconductor light emitting device includes: a package which is made of a resin and includes a recess; a lead frame exposed to a bottom of the recess; a semiconductor light emitting element connected to the lead frame in the recess; a phosphor layer over the bottom of the recess; and a second resin layer above the phosphor layer and the semiconductor light emitting element, in which the phosphor layer contains a semiconductor fine particle having an excitation fluorescence spectrum which changes according to a particle size, and the phosphor layer includes a water-soluble or water-dispersible material. | 2013-12-26 |
20130341667 | LIGHT-EMITTING DEVICE - A light-emitting device includes a semiconductor light-emitting stack; a current injected portion formed on the semiconductor light-emitting stack; an extension portion having a first branch radiating from the current injected portion and a second branch extending from the first branch; an electrical contact structure between the second branch and the semiconductor light-emitting stack and having a first width; and a current blocking structure located right beneath the electrical contact structure and having a second width larger than the first width. | 2013-12-26 |
20130341668 | OPTICAL SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A manufacturing method for an optical semiconductor device, including disposing a semiconductor element that has a polarization dependent gain or polarization dependent loss between optical waveguide modes differing in the direction of polarization, positioning a lens at one end face side of the semiconductor element based on an optical coupling loss between the lens and the semiconductor element, and repositioning the lens based on the polarization dependent gain or the polarization dependent loss of the semiconductor element. | 2013-12-26 |
20130341669 | Phosphor Placement In White Light Emitting Diode Assemblies - A white LED assembly includes a blue LED die attached to a substrate. A first volume of a first luminescent material surrounds the blue LED die in a lateral dimension such that none of the first luminescent material is disposed directly over the blue LED die. The first luminescent material includes a relatively inefficient phosphor having a peak emission wavelength longer than 620nm and includes substantially no phosphor having a peak emission wavelength shorter than 620nm. A second volume of a second luminescent material is disposed over the first volume and the blue LED die. The second luminescent material includes a relatively efficient phosphor having a peak emission wavelength shorter than 620nm and includes substantially no phosphor having a peak emission wavelength longer than 620nm. Placement of the first and second luminescent materials in this way promotes removal of heat from the inefficient phosphor and reduces the likelihood of interabsorption. | 2013-12-26 |
20130341670 | LIGHT SOURCE MODULE - The light source module includes a circuit board adapted to be placed on a mounting base of a light source holding member, and a power feeding attachment to supply power to a semiconductor light emitting device, the circuit board including a board part on which the semiconductor light emitting device is mounted, and a conductive circuit formed on a surface of the board part and having a pair of terminal parts and a light source connection part to connect the pair of terminal parts and the semiconductor light emitting device, the power feeding attachment including an electrically-insulating portion and an conductive portion partially embedded in the electrically-insulating portion, the power feeding attachment being adapted to be attached to the light source holding member such that the electrically-insulating portion presses at least a portion of the circuit board against the mounting base. | 2013-12-26 |
20130341671 | SILICONE RESIN COMPOSITION, SEMI-CURED MATERIAL SHEET, PRODUCING METHOD OF SILICONE CURED MATERIAL, LIGHT EMITTING DIODE DEVICE, AND PRODUCING METHOD THEREOF - A silicone resin composition contains a polysiloxane containing at least one pair of condensable substituted groups capable of condensation by heating and at least one pair of addable substituted groups capable of addition by an active energy ray. | 2013-12-26 |
20130341672 | III Nitride Crystal Substrate and Light-Emitting Device - Toward making available III nitride crystal substrates advantageously employed in light-emitting devices, and light-emitting devices incorporating the substrates, a III nitride crystal substrate has a major face whose surface area is not less than 10 cm | 2013-12-26 |
20130341673 | Reverse Conducting IGBT - A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first conductivity type, and a drift region of the second conductivity type arranged in a semiconductor body. The first and second emitter regions are arranged between the drift region and a first electrode and are each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source region and the body region. A floating parasitic region of the first conductivity type is disposed outside the cell region. | 2013-12-26 |
20130341674 | Reverse Conducting IGBT - A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first type, a drift region of the second conductivity type, and a first electrode. The first and second emitter regions are arranged between the drift region and first electrode and each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source and body regions. A parasitic region of the first conductivity type is disposed outside the cell region and includes at least one section with charge carrier lifetime reduction means. | 2013-12-26 |
20130341675 | LATCH-UP FREE ESD PROTECTION - An ESD module having a first portion (FP) and a second portion (SP) in a substrate is presented. The FP includes a FP well of a second polarity type and first and second FP contact regions. The first FP contact region is of a first polarity type and the second FP contact region is of a second polarity type. The SP includes a SP well of a first polarity type and first and second SP contact regions. The first SP contact region is of a first polarity type and the second SP contact region is of a second polarity type. An intermediate portion (IP) is disposed in the substrate between the FP and SP in the substrate. The IP includes a well of the second polarity type. The IP increases trigger current and holding voltage of the module to prevent latch up during normal device operation. | 2013-12-26 |
20130341676 | Methods and Apparatus for Increased Holding Voltage in Silicon Controlled Rectifiers for ESD Protection - Methods and apparatus for increased holding voltage SCRs. A semiconductor device includes a semiconductor substrate of a first conductivity type; a first well of the first conductivity type; a second well of a second conductivity type adjacent to the first well, an intersection of the first well and the second well forming a p-n junction; a first diffused region of the first conductivity type formed at the first well and coupled to a ground terminal; a first diffused region of the second conductivity type formed at the first well; a second diffused region of the first conductivity type formed at the second well and coupled to a pad terminal; a second diffused region of the second conductivity type formed in the second well; and a Schottky junction formed adjacent to the first diffused region of the second conductivity type coupled to a ground terminal. Methods for forming devices are disclosed. | 2013-12-26 |
20130341677 | GAN VERTICAL SUPERJUNCTION DEVICE STRUCTURES AND FABRICATION METHODS - A semiconductor device includes a III-nitride substrate of a first conductivity type, a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate, and a first III-nitride epitaxial structure coupled to a first portion of a surface of the first III-nitride epitaxial layer. The first III-nitride epitaxial structure has a sidewall. The semiconductor device further includes a second III-nitride epitaxial structure of the first conductivity type coupled to the first III-nitride epitaxial structure, a second III-nitride epitaxial layer of the first conductivity type coupled to the sidewall of the second III-nitride epitaxial layer and a second portion of the surface of the first III-nitride epitaxial layer, and a third III-nitride epitaxial layer of a second conductivity type coupled to the second III-nitride epitaxial layer. The semiconductor device also includes one or more dielectric structures coupled to a surface of the third III-nitride epitaxial layer. | 2013-12-26 |
20130341678 | Semiconductor Device with Selectively Etched Surface Passivation - A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel. | 2013-12-26 |
20130341679 | Semiconductor Device with Selectively Etched Surface Passivation - A semiconductor device includes a semiconductor substrate configured to include a channel, first and second ohmic contacts supported by the semiconductor substrate, in ohmic contact with the semiconductor substrate, and spaced from one another for current flow between the first and second ohmic contacts through the channel, and first and second dielectric layers supported by the semiconductor substrate. At least one of the first and second ohmic contacts extends through respective openings in the first and second dielectric layers. The second dielectric layer is disposed between the first dielectric layer and a surface of the semiconductor substrate, and the second dielectric layer includes a wet etchable material having an etch selectivity to a dry etchant of the first dielectric layer. | 2013-12-26 |
20130341680 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a stacked body, a source electrode, a drain electrode, a gate electrode, a dielectric layer and a silicon nitride layer. The stacked layer has a heterojunction made of a nitride semiconductor. The source and drain electrodes are provided on a surface of the stacked body. The gate electrode is provided on the surface of the stacked body between the source and the drain electrodes, and has a field plate portion. The dielectric layer is provided so as to cover an intersection line of a first side surface of the gate electrode and the surface of the stacked body. The silicon nitride layer is provided so as to cover a region between the source electrode and the gate electrode and a region between the dielectric layer and the drain electrode. The field plate portion protrudes from the first side surface. | 2013-12-26 |
20130341681 | HETEROJUNCTION BIPOLAR TRANSISTOR WITH IMPROVED CURRENT GAIN AND A FABRICATION METHOD THEREOF - A heterojunction bipolar transistor (HBT) with improved current gain and the fabrication method thereof, in which the HBT comprises a substrate, a p-type buffer layer, a sub-collector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and an emitter contact layer. Multiple etching processes are used for etching a base electrode contact region and terminated at the base layer. A collector electrode contact region is then formed in the base electrode contact region by an etching process terminated at the sub-collector layer. A base electrode is disposed on the base layer in the base electrode contact region. A collector electrode is disposed on the sub-collector layer in the collector electrode contact region. An emitter electrode is disposed on the emitter layer. | 2013-12-26 |
20130341682 | NITRIDE SEMICONDUCTOR DEVICE - A nitride semiconductor device includes a semiconductor substrate and a nitride semiconductor layer disposed on the semiconductor substrate. The semiconductor substrate includes a normal region, a carrier supplying region, and an interface current blocking region. The interface current blocking region surrounds the normal region and the carrier supplying region. The interface current blocking region and the carrier supplying region include impurities. The carrier supplying region has a conductivity type allowing the carrier supplying region to serve as a source of carriers supplied to or a destination of carriers supplied from a carrier layer generated at an interface between the nitride semiconductor layer and the semiconductor substrate. The interface current blocking region has a conductivity type allowing the interface current blocking region to serve as a potential barrier to the carriers. | 2013-12-26 |
20130341683 | SOLID-STATE IMAGING DEVICE AND CAMERA - A solid-state imaging device includes a photoelectric conversion unit that has a charge accumulation region and is configured to accumulate a charge that is generated in accordance with incident light in the charge accumulation region, and a transfer unit configured to transfer the charge accumulated in the charge accumulation region from the charge accumulation region. A potential distribution having a plurality of steps is formed in the charge accumulation region, and the further away from the transfer unit a step of the plurality of steps is, the greater the magnitude of the step is. | 2013-12-26 |
20130341684 | SOLID-STATE IMAGE PICKUP ELEMENT, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS - A solid-state imaging device, including a semiconductor substrate; a photoelectric conversion region in the semiconductor substrate that generates charges in response to light incident thereon; an electric charge holding region in the semiconductor substrate and capable of holding electric charges accumulated in the photoelectric conversion region until the electric charges are read out from the electric charge holding region; a transfer gate that effects transfer of electric charges generated in the photoelectric conversion region to the electric charge holding region; a light blocking film over an upper surface of the transfer gate; and an insulating layer over the substrate and between the semiconductor substrate and the light blocking film, wherein, a portion of the insulating layer over the photoelectric conversion region is more thinly formed than the insulating layer not over the photoelectric conversion region. | 2013-12-26 |
20130341685 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method for a semiconductor device includes providing a substrate having at least a gate structure formed thereon and a first spacer formed on sidewalls of the gate structure, performing an ion implantation to implant dopants into the substrate, forming a disposal spacer having at least a carbon-containing layer on the sidewalls of the gate structure, the carbon-containing layer contacting the first spacer, and performing a thermal treatment to form a protecting layer between the carbon-containing layer and the first spacer. | 2013-12-26 |
20130341686 | Semiconductor Devices, Transistors, and Methods of Manufacture Thereof - Semiconductor devices, transistors, and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a gate dielectric disposed over a workpiece, a gate disposed over the gate dielectric, and a spacer disposed over sidewalls of the gate and the gate dielectric. A source region is disposed proximate the spacer on a first side of the gate, and a drain region is disposed proximate the spacer on a second side of the gate. A metal layer is disposed over the source region and the drain region. The metal layer extends beneath the spacers by about 25% or greater than a width of the spacers. | 2013-12-26 |
20130341687 | METAL SILICIDE LAYER, NMOS TRANSISTOR, AND FABRICATION METHOD - Exemplary embodiments provide materials and methods for forming a metal silicide layer and/or an NMOS transistor. The metal silicide layer can be formed by heating a metal layer containing at least a tellurium element on a semiconductor substrate. The metal silicide layer can thus contain at least the tellurium element on the semiconductor substrate. The metal silicide layer can be formed in an NMOS transistor. With the addition of tellurium element in the metal silicide layer, Schottky barrier height between the metal silicide layer and the underling semiconductor substrate can be reduced. Contact resistance of the NMOS transistor can also be reduced. | 2013-12-26 |
20130341688 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device and a method for fabricating the semiconductor device. The method for fabricating the semiconductor device comprises steps of: forming a side cliff in a substrate in accordance with a gate mask pattern, the side cliff being substantially vertical to a substrate surface; forming a dielectric layer on the substrate that comprises the side cliff; etching the dielectric layer to have the dielectric layer left only on the side cliff, as a dielectric wall; and burying the side cliff by a substrate growth, the burying is performed up to a level higher than the upper end of the dielectric wall. | 2013-12-26 |
20130341689 | METHOD OF FORMING A SELF-ALIGNED CHARGE BALANCED POWER DMOS - Self-aligned charge balanced semiconductor devices and methods for forming such devices are disclosed. One or more planar gates are formed over a semiconductor substrate of a first conductivity type. One or more deep trenches are etched in the semiconductor self-aligned to the planar gates. The trenches are filled with a semiconductor material of a second conductivity type such that the deep trenches are charge balanced with the adjacent regions of the semiconductor substrate Source and body regions are formed by implanting dopants onto the filled trenches. This process can form self-aligned charge balanced devices with a cell pitch less than 12 microns. | 2013-12-26 |
20130341690 | ULTRA-VIOLET LIGHT SENSING DEVICE AND MANUFACTURING METHOD THEREOF - The present invention provides an ultra-violet light sensing device. The ultra-violet light sensing device includes a first conductivity type substrate, a second conductivity type region, and a first conductivity type high density region. The first conductivity type substrate includes a light incident surface. The second conductivity type region is disposed in the first conductivity type substrate and adjacent to the light incident surface. The first conductivity type high density region is disposed under the second conductivity type region. The present invention also provides another ultra-violet light sensing device, which further includes a first conductivity type high density shallow region which is sandwiched between the light incident surface and the second conductivity type region. Manufacturing methods for these ultra-violet light sensing devices are also disclosed in the present invention. | 2013-12-26 |
20130341691 | PHOTOELECTRIC CONVERSION DEVICE AND FABRICATION METHOD THEREFOR - A photoelectric conversion device comprises a high-refractive-index portion at a position close to a photoelectric conversion element therein. And, the high-refractive-index portion has first and second horizontal cross-section surfaces. The first cross-section surface is at a position closer to the photoelectric conversion element rather than the second cross-section surface, and is larger than an area of the second cross-section surface, so as to guide an incident light into the photoelectric conversion element without reflection. | 2013-12-26 |
20130341692 | Novel [N] Profile in Si-Ox Interface for CMOS Image Sensor Performance Improvement - A semiconductor device including first and second isolation regions supported by a substrate, a first array well supported by the first isolation region, the first array well having a first field implant layer embedded therein, the first field implant layer surrounding a first shallow trench isolation region, a second array well supported by the second isolation region, the second array well supporting a doped region and a drain and having a second field implant layer embedded therein, the second field implant layer surrounding a second shallow trench isolation region, a stack of photodiodes disposed in the substrate between the first and second isolation regions, and a gate oxide formed over an uppermost photodiode of the stack of the photodiodes, the gate oxide and a silicon of the uppermost photodiode forming an interface, a nitrogen concentration at the interface offset from a peak nitrogen concentration. | 2013-12-26 |
20130341693 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device having good properties. Particularly, the semiconductor device is provided which can improve imaging properties. The semiconductor device (CMOS image sensor) includes a plurality of pixels, each having a photodiode PD for generating a charge by receiving light, and a transfer transistor TX for transferring the charge generated by the photodiode PD. The semiconductor device further includes an active region AcTP with the photodiode, and an active region AcG located on an upper side of the region AcTP in the planar direction and having a contact Pg to which a ground potential is applied. A gettering region GET is disposed in the active region AcG. | 2013-12-26 |
20130341694 | PHOTOELECTRIC CONVERTER - A photoelectric converter according to the present invention includes a substrate, a lower electrode layer arranged on the substrate, a compound semiconductor layer of a chalcopyrite structure arranged on the lower electrode layer to cover the lower electrode layer and partitioned into a plurality of pixels, a transparent electrode layer arranged on the compound semiconductor layer, and a shielding layer arranged around each of the pixels on the compound semiconductor layer. | 2013-12-26 |
20130341695 | MANUFACTURING PROCESS FOR ZERO-CAPACITOR RANDOM ACCESS MEMORY CIRCUITS - Embodiments of a manufacturing process flow for producing standalone memory devices that can achieve bit cell sizes on the order of 4F2 or 5F2, and that can be applied to common source/drain, separate source/drain, or common source only or common drain only transistor arrays. Active area and word line patterns are formed as perpendicularly-arranged straight lines on a Silicon-on-Insulator substrate. The intersections of the active area and spaces between word lines define contact areas for the connection of vias and metal line layers. Insulative spacers are used to provide an etch mask pattern that allows the selective etching of contact areas as a series of linear trenches, thus facilitating straight line lithography techniques. Embodiments of the manufacturing process remove first layer metal (metal-1) islands and form elongated vias, in a succession of processing steps to build dense memory arrays. | 2013-12-26 |
20130341696 | METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF - The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor faults a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 2013-12-26 |
20130341697 | TUNNEL TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND A MANUFACTURING METHOD THEREOF - The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient. | 2013-12-26 |
20130341698 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING - According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, and a charge trap layer on the interface insulating layer, and a lower end of a conduction band of the interface insulating layer is higher than a trap level of the charge trap layer and is lower than a lower end of a conduction band of the charge trap layer. | 2013-12-26 |
20130341699 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a first insulating layer on a semiconductor layer, a charge storage layer on the first insulating layer, a second insulating layer on the charge storage layer, and a control gate electrode on the second insulating layer. The charge storage layer includes a floating gate layer on the first insulating layer, an interface insulating layer on the floating gate layer, a first charge trap layer on the interface insulating layer, and a second charge trap layer on the first charge trap layer, and a trap level of the second charge trap layer is lower than a trap level of the first charge trap layer. | 2013-12-26 |
20130341700 | P-TYPE CONTROL GATE IN NON-VOLATILE STORAGE - Non-voltage storage and techniques for fabricating non-volatile storage are disclosed. In some embodiments, at least a portion of the control gates of non-volatile storage elements are formed from p-type polysilicon. In one embodiment, a lower portion of the control gate is p-type polysilicon. The upper portion of the control gate could be p-type polysilicon, n-type polysilicon, metal, metal nitride, etc. P-type polysilicon in the control gate may not deplete even at high Vpgm. Therefore, a number of problems that could occur if the control gate depleted are mitigated. For example, a memory cell having a control gate that is at least partially p-type polysilicon might be programmed with a lower Vpgm than a memory cell formed from n-type polysilicon. | 2013-12-26 |
20130341701 | Vertical Semiconductor Memory Device and Manufacturing Method Thereof - Disclosed are vertical semiconductor devices and methods of manufacturing vertical semiconductor devices. An example method includes providing a semiconductor substrate, and forming a stack of horizontal layers on the semiconductor substrate, where the horizontal layers are substantially parallel to a surface of the semiconductor substrate, and the horizontal layers comprise alternating conductive layers and dielectric layers. The method further includes forming a vertical channel region through the stack of horizontal layers, where the vertical channel region is substantially perpendicular to a surface of the semiconductor substrate, and the vertical channel region comprises sidewall surfaces. The method further includes forming a charge storage layer on regions of the sidewall surfaces of the vertical channel region that are in direct contact with conductive layers in the stack of horizontal layers and, at a distance from the vertical channel region, forming a vertical dielectric region through the stack of horizontal layers. | 2013-12-26 |
20130341702 | Vertical Memory Device and Method for Making Thereof - Described herein is a method for forming a vertical memory device ( | 2013-12-26 |
20130341703 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, the electrode films are provided on the substrate. The first insulating films are provided between the electrode films. The second insulating film is provided on an uppermost electrode film of the electrode films. The select gate is provided on the second insulating film. The channel body extends in a stacking direction in a stacked body. The memory film is provided between the channel body and the electrode films and includes a charge storage film. The memory film includes a block film, the charge storage film, and a tunnel film. The second insulating film includes at least the block film of the memory film. | 2013-12-26 |
20130341704 | VARIABLE GATE WIDTH FOR GATE ALL-AROUND TRANSISTORS - Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active. | 2013-12-26 |
20130341705 | SCHOTTKY DIODE INTEGRATED INTO LDMOS - In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes. | 2013-12-26 |
20130341706 | SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - According to one embodiment, a semiconductor memory device includes a semiconductor laminated film comprising an embedded insulating film, and an SOI layer laminated on a semiconductor substrate. On the embedded insulating film, multiple pillar-shaped gate electrodes embedded in the SOI layer are provided. On the SOI layer, a pillar-shaped gate insulating film is provided to surround the side surface of each of the pillar-shaped gate electrodes. On the SOI layer, multiple first bit lines are arranged. On the pillar-shaped gate electrodes, multiple word lines are arranged. In the word line direction, the adjacent pillar-shaped gate electrodes are electrically connected to each other, and, in a first bit line direction, the adjacent pillar-shaped gate electrodes are electrically insulated from each other. | 2013-12-26 |
20130341707 | SEMICONDUCTOR DEVICE - A semiconductor device includes a first pillar, a second pillar underneath the first pillar, and a third pillar on a top of the first pillar. The second pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface region with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region. The third pillar has a second-conductive type region in a surface thereof except at least a part of a contact surface region with the first pillar, and a first-conductive type region therein and surrounded by the second-conductive type region. The first-conductive type region of each of the second pillar and the third pillar has a length greater than that of a depletion layer extending from a base portion of the second-conductive type region of a respective one of the second pillar and the third pillar. | 2013-12-26 |
20130341708 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A low concentration P-type impurity (LCPI) layer situated over a drain layer has an impurity concentration lower than the drain layer. An N-type impurity base layer is situated over the LCPI layer. A gate insulating film is formed on the lateral side of a trench. A bottom insulation film formed to the bottom and lower portion on the lateral side of the trench has a larger thickness than the gate insulating film. A gate electrode is filled in the trench. At a cross section in the direction of the thickness including the bottom of the trench, a profile of the P-type impurity concentration is substantially constant and the difference between the maximum and minimum values is 10% or less of the average value for the maximum and minimum values. Further, the profile has a maximal value and a minimal value situated from the maximal value to the drain layer. | 2013-12-26 |
20130341709 | SEMICONDUCTOR DEVICE WITH ELECTRODE INCLUDING INTERVENTION FILM - In a semiconductor device including a semiconductor substrate, a trench formed on the semiconductor substrate, an insulating film formed on a side wall of the trench, and an electrode formed on the insulating film. The electrode includes a first film made of first metal nitride, an intervention film made of silicon or of second metal silicide, and a second film made of third metal in this order. | 2013-12-26 |
20130341710 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes forming a first preliminary gate barrier layer and a first preliminary gate electrode recessed to have a first depth from the surface of the substrate within a gate trench, removing an upper portion of the first preliminary gate electrode by means of a first wet etching process using a first etchant to form a second preliminary gate electrode recessed to have a second depth greater than the first depth, and removing an upper portion of the first preliminary gate barrier layer and an upper portion of the second preliminary gate electrode by means of a second wet etching process using a second etchant to form a gate electrode and a gate barrier layer recessed to a third depth greater than the second depth. | 2013-12-26 |
20130341711 | SEMICONDUCTOR DEVICE - A technique for improving the characteristics of a semiconductor device (UMOSFET) is provided. In the UMOSFET in order to grow an epitaxial growth film on a trench side wall with an even film thickness, a channel is arranged in an optimum direction as a growth surface. For example, a trench is formed on an SiC substrate having a {0001} surface 4° off in a <11-20> direction as a main surface so that a channel surface becomes a {1-100} surface. With this configuration, an epitaxial growth with the even thickness can be conducted on the side wall from which the {1-100} surface of the trench is exposed. As a result, the unevenness of a channel resistance, and the insulation failure of a gate insulating film do not occur, and the yield is improved. | 2013-12-26 |
20130341712 | TRENCH SHIELDING STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHOD - A shielding structure for a semiconductor device includes a plurality of trenches. The trenches include passivation liners and shield electrodes, which are formed therein. In one embodiment, the shielding structure is placed beneath a control pad. In another embodiment, the shielding structure is placed beneath a control runner. | 2013-12-26 |
20130341713 | SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME - Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, a method includes forming a first shielding layer on a substrate. The method further includes forming one of source and drain regions, which is stressed, with the first shielding layer as a mask. The method further includes forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask. The method further includes removing a portion of the second shielding layer which is next to the other of the source and drain regions. The method further includes forming a gate dielectric layer, and forming a gate conductor as a spacer on a sidewall of a remaining portion of the second shielding layer. | 2013-12-26 |
20130341714 | SEMICONDUCTOR DEVICE HAVING POWER METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A semiconductor device includes a power metal-oxide-semiconductor (MOS) transistor including a semiconductor substrate, an impurity region on the semiconductor substrate, the impurity region having a first conductivity, a drift region in the impurity region, the drift region having the first conductivity, a body region in the impurity region adjacent to the drift region, the body region having a second conductivity different from the first conductivity, a drain extension insulating layer on the drift region, a gate insulating layer and a gate electrode sequentially stacked across a portion of the body region and a portion of the drift region, a drain extension electrode on the drain extension insulating layer, a drain region contacting a side of the drift region opposite to the body region, the drain region having the first conductivity, and a source region in the body region, the source region having the second conductivity. | 2013-12-26 |
20130341715 | POWER TRANSISTOR AND ASSOCIATED METHOD FOR MANUFACTURING - The present disclosure discloses a lateral transistor and associated method for making the same. The lateral transistor comprises a gate formed over a first portion of a thin gate dielectric layer, and a field plate formed over a thick field dielectric layer and extending atop a second portion of the thin gate dielectric layer. The field plate is electrically isolated from the gate by a gap overlying a third portion of the thin gate dielectric layer and is electrically coupled to a source region. The lateral transistor according to an embodiment of the present invention may have reduced gate-to-drain capacitance, low specific on-resistance, and improved hot carrier lifetime. | 2013-12-26 |
20130341716 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There are provided a semiconductor device having a drain region making a BLDD structure withstandable against a high voltage, sufficiently suppressing a hot-carrier deterioration, and having a high ESD withstandable characteristic, and a method for manufacturing the same. A semiconductor device is formed including a MOS transistor having a source region and a drain region both formed in a semiconductor substrate, and a channel region formed therebetween. At this time, the concentration of holes emitted form P-type impurities injected into the channel region and contributing an electrical conduction is lower at a side close to the drain region than at a side close to the source region. The drain region includes a drift region into which N-type impurities are injected. The drift region extends toward the channel region from the drain region except a nearby area to the surface of the semiconductor substrate. | 2013-12-26 |
20130341717 | Semiconductor Device with Floating RESURF Region - A device includes a semiconductor substrate, a body region in the semiconductor substrate, having a first conductivity type, and including a channel region through which charge carriers flow, a drain region in the semiconductor substrate, having a second conductivity type, and spaced from the body region along a first lateral dimension, a drift region in the semiconductor substrate, having the second conductivity type, and electrically coupling the drain region to the channel region, and a plurality of floating reduced surface field (RESURF) regions in the semiconductor substrate adjacent the drift region, having the first conductivity type, and around which the charge carriers drift through the drift region under an electric field arising from a voltage applied to the drain region. Adjacent floating RESURF regions of the plurality of floating RESURF regions are spaced from one another along a second lateral dimension of the device by a respective gap. | 2013-12-26 |
20130341718 | POWER SEMICONDUCTOR DEVICE - In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate. | 2013-12-26 |
20130341719 | Hybrid High Voltage Device and Manufacturing Method Thereof - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 2013-12-26 |
20130341720 | IMPLEMENTING GATE WITHIN A GATE UTILIZING REPLACEMENT METAL GATE PROCESS - A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage. | 2013-12-26 |
20130341721 | SEMICONDUCTOR WAFER, FIELD-EFFECT TRANSISTOR, METHOD OF PRODUCING SEMICONDUCTOR WAFER, AND METHOD OF PRODUCING FIELD-EFFECT TRANSISTOR - Provided is a semiconductor wafer including a base wafer, a first insulating layer, and a semiconductor layer. Here, the base wafer, the first insulating layer and the semiconductor layer are arranged in an order of the base wafer, the first insulating layer and the semiconductor layer, the first insulating layer is made of an amorphous metal oxide or an amorphous metal nitride, the semiconductor layer includes a first crystal layer and a second crystal layer, the first crystal layer and the second crystal layer are arranged in an order of the first crystal layer and the second crystal layer in such a manner that the first crystal layer is positioned closer to the base wafer, and the electron affinity E | 2013-12-26 |
20130341722 | ULTRATHIN BODY FULLY DEPLETED SILICON-ON-INSULATOR INTEGRATED CIRCUITS AND METHODS FOR FABRICATING SAME - Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing an ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) substrate. A PFET temporary gate structure and an NFET temporary gate structure are formed on the substrate. The method implants ions to form lightly doped active areas around the gate structures. A diffusionless annealing process is performed on the active areas. Further, a compressive strain region is formed around the PFET gate structure and a tensile strain region is formed around the NFET gate structure. | 2013-12-26 |
20130341723 | MEMORY CELL WITH ASYMMETRIC READ PORT TRANSISTORS - A memory cell includes a storage element and a read port. The read port includes a first transistor having a first gate coupled to the storage element, a first source region, and a first drain region. The second transistor includes a second gate, a second source region coupled to the first drain region, and a second drain region. A first dopant profile of the first and second source regions is asymmetric with respect to a second dopant profile of the first and second drain regions. | 2013-12-26 |
20130341724 | FinFET with Body Contact - A semiconductor device has a FinFET with at least two independently controllable FETs on a single fin. The fin may have a body area with a width between two vertical sides, each side has a single FET. The fin also may have a top fin area that is wider than the body area and is electrically independent from the two FETs. The top fin area may be capable of receiving a body contact structure which may be connected to an electrical conductor as to regulate the voltage in the body area of the fin. | 2013-12-26 |
20130341725 | SEMICONDUCTOR CONSTRUCTIONS - Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include OCIT memory having transistor gates entirely over SOI, and methods of forming such OCIT memory. | 2013-12-26 |
20130341726 | MOS TRANSISTOR, FORMATION METHOD THEREOF, AND SRAM MEMORY CELL CIRCUIT - Various embodiments provide an MOS transistor, a formation method thereof, and an SRAM memory cell circuit. An exemplary MOS transistor can include a semiconductor substrate including a first groove on one side of a gate structure and a second groove on the other side of the gate structure. The first groove can have a sidewall perpendicular to a surface of the semiconductor substrate. The second groove can have a sidewall protruding toward a channel region under the gate structure. A stressing material can be disposed in the first groove to form a drain region and in the second groove to form a source region. Stress generated in the channel region of the MOS transistor can be asymmetric. The MOS transistor can be used as a transfer transistor in an SRAM memory cell circuit to increase both read and write margins of the SRAM memory. | 2013-12-26 |
20130341727 | SEMICONDUCTOR DEVICE AND MANUFCTURING METHOD OF THE SAME - Disclosed is a semiconductor device including a first MISFET of an n channel type and a second MISFET of a p channel type, each of the MISFETs being configured with a gate insulating film featuring a silicon oxide film or a silicon oxynitride film and a gate electrode including a conductive silicon film positioned on the gate insulating film. Metal elements such as Hf are introduced near the interface between the gate electrode and the gate insulating film in both the first and second MISFETs such that metal atoms with a surface density of 1×10 | 2013-12-26 |
20130341728 | Semiconductor Device - The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer. | 2013-12-26 |
20130341729 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Provided is a semiconductor element having, while maintaining the same integratability as a conventional MOSFET, excellent switch characteristics compared with the MOSFET, that is, having the S-value less than 60 mV/order at room temperature. Combining the MOSFET and a tunnel bipolar transistor having a tunnel junction configures a semiconductor element that shows an abrupt change in the drain current with respect to a change in the gate voltage (an S-value of less than 60 mV/order) even at a low voltage. | 2013-12-26 |
20130341730 | Semiconductor Devices and Structures - Devices, semiconductor structures and methods are provided, where a substrate is around a semiconductor device is biased via a resistive element. | 2013-12-26 |
20130341731 | Substrate Resistor and Method of Making Same - A semiconductor structure can include a resistor on a substrate formed simultaneously with other devices, such as transistors. A diffusion barrier layer formed on a substrate is patterned to form a resistor and barrier layers under a transistor gate. A filler material, a first connector, and a second connector are formed on the resistor at the same manner and time as the gate of the transistor. The filler material is removed to form a resistor on a substrate. | 2013-12-26 |
20130341732 | SEMICONDUCTOR DEVICE HAVING SILICIDE ON GATE SIDEWALLS IN ISOLATION REGIONS - Provided are a semiconductor device and a method of fabricating the same. According to the semiconductor device, a silicide layer is formed on at least a part of both sidewalls of a gate pattern on a device isolation layer, thereby reducing resistance of the gate pattern. This makes an operation speed of the device rapid. According to the method of the semiconductor device, a sidewall spacer pattern is formed on at least a part of both sidewalls of the gate pattern in following salicide process by entirely or partially removing remaining portions of the sidewall spacer except for portions which are used as an ion implantation mask to form source/drain regions. This can reduce resistance of the gate pattern, thereby fabricating a semiconductor device with a rapid operation speed. | 2013-12-26 |
20130341733 | Plural Differential Pair Employing FinFET Structure - A plural differential pair may include a first semiconductor fin having first and second drain areas. First and second body areas may be disposed on the fin between the first and second drain areas. A source area may be disposed on the fin between the first and second body areas. The plural differential pair may include a first pair of fin field effect (FinFET) transistors and a second pair of FinFET transistors. The plural differential pair may include first and second top fin areas projecting from respective portions of a top side of the first and second body areas of the fin. The first and second top fin areas may each have a width that is wider than the first and second body areas of the fin. | 2013-12-26 |
20130341734 | INTEGRATED CIRCUIT WITH SENSORS AND MANUFACTURING METHOD - Disclosed is an integrated circuit comprising a substrate ( | 2013-12-26 |
20130341735 | ANODICALLY BONDED STRAIN ISOLATOR - A stress isolator that allows a sensor to be attached to materials of the same coefficient of thermal expansion and still provide the required elastic isolation between the sensor and the system to which it is mounted. The isolator is made of two materials, borosilicate glass and silicon. The glass is the same material as the mounting surface of the microelectromechanical system (MEMS) sensors. The silicon makes an excellent isolator, being very elastic and easy to form into complex shapes. The two materials of the isolator are joined using an anodic bond. The construction of the isolator can be specific to different types of MEMS sensors, making the most of their geometry to reduce overall volume. | 2013-12-26 |
20130341736 | Packaging Compatible Wafer Level Capping of MEMS Devices - This invention discloses and claims a cost-effective, wafer-level package process for microelectromechanical devices (MEMS). Specifically, the movable part of MEMS device is encapsulated and protected while in wafer form so that commodity, lead-frame packaging can be used. An overcoat polymer, such as, epoxycyclohexyl polyhedral oligomeric silsesquioxanes (EPOSS) has been used as a mask material to pattern the sacrificial polymer as well as overcoat the air-cavity. The resulting air-cavities are clean, debris-free, and robust. The cavities have substantial strength to withstand molding pressures during lead-frame packaging of the MEMS devices. A wide range of cavities from 20 μm×400 μm to 300 μm×400 μm have been fabricated and shown to be mechanically stable. These could potentially house MEMS devices over a wide range of sizes. The strength of the cavities has been investigated using nano-indentation and modeled using analytical and finite element techniques. Capacitive resonators packaged using this protocol have shown clean sensing electrodes and good functionality. | 2013-12-26 |
20130341737 | PACKAGING TO REDUCE STRESS ON MICROELECTROMECHANICAL SYSTEMS - One example includes an integrated circuit including at least one electrical interconnects disposed on an elongate are extending away from a main portion of the integrated circuit and a microelectromechanical layer including an oscillating portion, the microelectromechanical layer coupled to the main portion of the integrated circuit. | 2013-12-26 |
20130341738 | METHOD FOR MANUFACTURING A COMPONENT HAVING AN ELECTRICAL THROUGH-CONNECTION - A method for manufacturing a component having an electrical through-connection includes: providing a semiconductor substrate having a front side and a back side opposite from the front side; producing, on the front side of the semiconductor substrate, an insulating trench which annularly surrounds a contact area; introducing an insulating material into the insulating trench; producing a contact hole on the front side of the semiconductor substrate by removing the semiconductor material surrounded by the insulating trench in the contact area; and depositing a metallic material in the contact hole. | 2013-12-26 |
20130341739 | PACKAGE STRUCTURE HAVING MICRO-ELECTRO-MECHANICAL SYSTEM ELEMENT AND METHOD OF FABRICATION THE SAME - A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections. | 2013-12-26 |
20130341740 | COMPENSATION OF STRESS EFFECTS ON PRESSURE SENSOR COMPONENTS - Pressure sensors having components with reduced variations due to stresses caused by various layers and components that are included in the manufacturing process. In one example, a first stress in a first direction causes a variation in a component. A second stress in a second direction is applied, thereby reducing the variation in the component. The first and second stresses may be caused by a polysilicon layer, while the component may be a resistor in a Wheatstone bridge. | 2013-12-26 |