52nd week of 2014 patent applcation highlights part 17 |
Patent application number | Title | Published |
20140374846 | INTEGRATED SOI PRESSURE SENSOR HAVING SILICON STRESS ISOLATION MEMBER - In one embodiment a pressure sensor is provided. The pressure sensor includes a housing having an input port configured to allow a media to enter the housing. A support is mounted within the housing, the support defining a first aperture extending therethrough. A stress isolation member is mounted within the first aperture of the support, the stress isolation member defining a second aperture extending therethrough, wherein the stress isolation member is composed of silicon. sensor die bonded to the stress isolation member. The sensor die includes a silicon substrate having an insulator layer on a first side of the silicon substrate; and sensing circuitry disposed in the insulator layer on the first side, wherein a second side of the silicon substrate is exposed to the second aperture of the stress isolation member and the second side is reverse of the first side. | 2014-12-25 |
20140374847 | PACKAGING METHOD FOR MEMS DEVICES - In a method of packaging micro-electro-mechanical systems (MEMS) devices, an interposer board is provided having a first surface and an opposing second surface, with the interposer board including a plurality of electrical contacts on the second surface. A plurality of shim layers are bonded to the first surface of the interposer board, and a plurality of MEMS dies are each separately bonded to a respective one of the shim layers. Each of the MEMS dies are electrically connected to the interposer board by wire bonding. A plurality of covers are attached to the first surface of the interposer board over each of the MEMS dies to produce packaged MEMS devices. Each of the MEMS dies resides in a sealed cavity defined by a respective one of the covers and are substantially isolated from thermal stress. | 2014-12-25 |
20140374848 | SEMICONDUCTOR SENSOR DEVICE WITH METAL LID - A semiconductor sensor device is packaged using a lid in which one or more dies are mounted to a substrate within the lid housing and one or more other dies are mounted to the substrate outside of the lid housing. The dies located outside of the lid housing may be encapsulated in a molding compound. In one embodiment, the lid has a vent hole and an active region of a pressure-sensing die located inside the lid housing is covered by a pressure-sensitive gel that together enable ambient atmospheric pressure immediately outside the sensor device to reach the active region of the pressure-sensing die. The sensor device may also have one or more other types of sensor dies, such as an acceleration-sensing die, to form a multi-sensor device. | 2014-12-25 |
20140374849 | ANGULAR RATE SENSOR WITH QUADRATURE ERROR COMPENSATION - An angular rate sensor includes a substrate, a drive mass flexibly coupled to the substrate, and a sense mass suspended above the substrate and flexibly coupled to the drive mass via flexible support elements. An electrode structure is mechanically coupled to, but electrically isolated from, the drive mass and is spaced apart from the substrate so that it is not in contact with the substrate. The electrode structure is configured to produce a signal that indicates movement of the sense mass relative to the electrode when the sensor is subjected to angular velocity. When the angular rate sensor experiences quadrature error, the drive mass, the sense mass, and the electrode structure move together relative to the sense axis. Since the sense mass and the electrode structure move together in response to quadrature error, there is little relative motion between the sense mass and the electrode structure so that quadrature error is largely eliminated. | 2014-12-25 |
20140374850 | Apparatus and Method for Shielding and Biasing in MEMS Devices Encapsulated by Active Circuitry - One or more conductive shielding plates are formed in a standard ASIC wafer top metal layer, e.g., for blocking cross-talk from MEMS device structure(s) on the MEMS wafer to circuitry on the ASIC wafer when the MEMS device is capped directly by the ASIC wafer in a wafer-level chip scale package. Generally speaking, a shielding plate should be at least slightly larger than the MEMS device structure it is shielding (e.g., a movable MEMS structure such as an accelerometer proof mass or a gyroscope resonator), and the shielding plate cannot be in contact with the MEMS device structure during or after wafer bonding. Thus, a recess is formed to ensure that there is sufficient cavity space away from the top surface of the MEMS device structure. The shielding plate is electrically conductive and can be biased, e.g., to the same voltage as the opposing MEMS device structure in order to maintain zero electrostatic attraction force between the MEMS device structure and the shielding plate. | 2014-12-25 |
20140374851 | MEMS DEVICE AND METHOD FOR FABRICATING MEMS DEVICES | 2014-12-25 |
20140374852 | Electrical Shielding in a MEMS Leadframe Package - A lead frame packaged electronic chip. The packaged electronic chip includes a MEMS device, an integrated circuit and a wire bond electrically coupling the MEMS device and the integrated circuit. The packaged electronic chip is encased in a molding material. The packaged electronic chip further includes a mechanism that shields the wire bond and the input/output pads that couple the MEMS device and the integrated circuit from electromagnetic and radio frequency interference. | 2014-12-25 |
20140374853 | COMPONENT INCLUDING MEANS FOR REDUCING ASSEMBLY-RELATED MECHANICAL STRESSES AND METHODS FOR MANUFACTURING SAME - Measures are provided for stress decoupling between a semiconductor component and its mounting support, these measures being implementable very easily, inexpensively and in a space-saving manner, regardless of the substrate thickness of the component, and not being limited to soldered connections but instead also being usable in conjunction with other mounting and joining techniques. These measures relate to components, which include at least one electrical and/or micromechanical functionality and at least one wiring level, which is formed in a layer structure on a main surface of the component substrate, at least one mounting surface being implemented in the wiring level to establish a mechanical and/or electrical connection of the component to a support. The at least one mounting surface is spring mounted and is separated from the layer structure in at least some areas for this purpose. | 2014-12-25 |
20140374854 | VERTICAL MOUNT PACKAGE AND WAFER LEVEL PACKAGING THEREFOR - Vertical mount packages and methods for making the same are disclosed. A method for manufacturing a vertical mount package includes providing a device substrate with a plurality of device regions on a front surface, and a plurality of through-wafer vias. MEMS devices or integrated circuits are formed or mounted onto the device regions. A capping substrate having recesses is mounted over the device substrate, enclosing the device regions within cavities defined by the recesses. A plurality of aligned through-wafer contacts extend through the capping substrate and the device substrate. The device substrate and capping substrate can be singulated by cutting through the aligned through-wafer contacts, with the severed through-wafer contacts forming vertical mount leads. A vertical mount package includes a device sealed between a device substrate and a capping substrate. At least of the side edges of the package includes exposed conductive elements for vertical mount leads. | 2014-12-25 |
20140374855 | PRESSURE SENSOR AND METHOD OF PACKAGING SAME - A method of packaging a pressure sensor die begins with patterning and etching a metal strip and forming metal traces on the strip. Further build-up is performed to transform the metal strip into a layered substrate. Cavity walls are formed on one side of the strip with a molding process and then the metal on the back side of the strip is removed. Next semiconductor dies are attached to the strip within the cavities and electrically connected to pads formed on the surface of the strip and/or to pads on other ones of the dies. A gel coating is deposited over the dies and then a metal lid is secured over the cavity. The strip is then singulated along ones of the cavity walls to form multiple sensor devices. | 2014-12-25 |
20140374856 | Apparatus and Method for Preventing Stiction of MEMS Devices Encapsulated by Active Circuitry - One or more stopper features (e.g., bump structures) are formed in a standard ASIC wafer top passivation layer for preventing MEMS device stiction vertically in integrated devices having a MEMS device capped directly by an ASIC wafer. A TiN coating may be used on the stopper feature(s) for anti-stiction. An electrical potential may be applied to the TiN anti-stiction coating of one or more stopper features. | 2014-12-25 |
20140374857 | CANTILEVER BEAM STRUCTURE WHERE STRESS IS MATCHED AND METHOD OF MANUFACTURING THE SAME - A cantilever beam structure where stress is matched and a method of manufacturing the same are provided. An example method may comprise depositing a first sub-layer of a first material with a first deposition menu and depositing a second sub-layer of the first material with a second deposition menu different from the first deposition menu. The first sub-layer and the second sub-layer can be disposed adjacent to each other to form a first layer. The method may further comprise depositing a second layer of a second material different from the first material. The first layer and the second layer can be disposed adjacent to each other. The method may further comprise matching stress between the first layer and the second layer by adjusting at least one of thicknesses of the respective sub-layers of the first layer and a thickness of the second layer. | 2014-12-25 |
20140374858 | CAPACITIVE PRESSURE SENSOR AND A METHOD OF FABRICATING THE SAME - The invention discloses a capacitive pressure sensor and a method of fabricating the same. The capacitive pressure sensor includes a fixed plate configured as a back plate, a movable plate configured as diaphragm for sensing pressure, wherein a cavity is formed between the fixed plate and the movable plate, an isolation layer between the fixed plate and the movable plate and electrical contacts thereof for minimizing the leakage current, plurality of damping holes for configuring the contour of the fixed plate as the deflected diaphragm when pressure is exerted, a vent hole extending to the cavity having resistive air path for providing equilibrium to the diaphragm and an extended back chamber for increasing the sensitivity of the capacitive pressure sensor. The capacitive pressure sensor is also configured for minimizing parasitic capacitance. | 2014-12-25 |
20140374859 | SENSOR DEVICE - A sensor device has a substrate, a sensor section provided on an upper surface of the substrate, a circuit section provided on the upper surface of the substrate, a plurality of connection pads that electrically conduct with the sensor section or the circuit section, and a metal protective film covering at least a part of the circuit section from above. | 2014-12-25 |
20140374860 | MAGNETIC SHIELD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR PACKAGE - Provided is a magnetic shield having improved shielding properties from an external magnetic field. A magnetic shield MS | 2014-12-25 |
20140374861 | EPITAXIAL WAFER AND MANUFACTURING METHOD THEREOF - A method for manufacturing an epitaxial wafer for manufacture of an image pickup device, wherein, before the growth of the epitaxial layer, a thickness X of a region where oxygen concentration in the epitaxial layer becomes 4×10 | 2014-12-25 |
20140374862 | CMOS Image Sensor With Integrated Silicon Color Filters - A color photosensor array has photosensors of a first type having a thick overlying silicon layer, photosensors of a second type having a thin overlying silicon layer, and photosensors of a third type having no overlying silicon layer; the photosensors of the first type having peak sensitivity in the red, the photosensors of the second type having peak sensitivity in the green. In particular embodiments, color correction circuitry is provided to enhance color saturation. | 2014-12-25 |
20140374863 | IMAGE PICKUP APPARATUS, METHOD OF DESIGNING THE SAME, AND METHOD OF MANUFACTURING THE SAME - An image pickup apparatus includes a plurality of types of pixels, each of which includes a conversion element configured to convert light into a charge and one of a plurality of types of filters configured to transmit light in different wavelength bands. A type of pixel of the plurality of types of pixels further includes a lightguide configured to guide light entering the pixel to the conversion element. Another type of pixel of the plurality of types of pixels includes no structure corresponding to the lightguide. | 2014-12-25 |
20140374864 | LIGHT-GUIDE UNIT AND IMAGE SENSOR - A light guide unit includes, a first light guide that takes a light incident upon one end surface and emits a light from other end surface and from a light emitter on a side surface of the first light guide, and a second light guide that takes the light emitted from the other end surface of the first light guide then incident upon one end surface of the second light guide, and emits the light from a light emitter on a side surface of the second light guide. The first light guide includes a first mating member, and the second light guide includes a second mating member engaging with a first alignment member such that the side surface of the first light guide having the light emitter and the side surface of the second light guide having the light emitter are flush with each other. | 2014-12-25 |
20140374865 | SEMICONDUCTOR DEVICE AND ELECTRONIC EQUIPMENT - The present technology relates to a semiconductor device and electronic equipment in which a semiconductor device that suppresses the occurrence of noise by a leakage of light can be provided. | 2014-12-25 |
20140374866 | Photo Sensing Chip Having a Plurality of Photo Sensors and Manufacturing Method Thereof - A photo sensing chip and a manufacturing method thereof are disclosed. The photo sensing chip includes a silicon substrate and a plurality of photo sensors formed on the silicon substrate. The photo sensors include a first photo sensor and a second photo sensor. The first photo sensor has a first P-N junction and a first depletion region is formed at first P-N junction for receiving a first light band of an incident light to generate a first photo current. The second photo sensor has a second P-N junction and a second depletion region is formed at second P-N junction for receiving a second light band of the incident light to generate a second photo current. A first process parameter corresponds to the first depletion region and a second process parameter corresponds to the second depletion region, wherein the first process parameter and the second process parameter are different. | 2014-12-25 |
20140374867 | Pinned Photodiode (PPD) Pixel Architecture With Separate Avalanche Region - Described herein is a pinned photodiode pixel architecture having a p-type substrate that is independently biased with respect to a pixel area to provide an avalanche region between an n-type region and a p-type region formed on the substrate. Such a pinned photodiode pixel can be used in imaging sensors that are used in low light level conditions. | 2014-12-25 |
20140374868 | IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME - An image sensor includes a plurality of photo detectors and a plurality of trench isolations configured to isolate the photo detectors from each other. Each of the trench isolations includes a plurality of films in a multi-layer structure. A method of manufacturing an image sensor includes forming a plurality of trench isolations to isolate a plurality of photo detectors from each other, forming a first film in each of the trench isolations, and forming a second film that constructs a multi-layer structure together with the first film. | 2014-12-25 |
20140374869 | DETECTOR MODULE FOR AN IMAGING SYSTEM - A detector module for detecting photons includes a detector formed from a semiconductive material, the detector having a first surface, an opposing second surface, and a plurality of sidewalls extending between the first and second surfaces, and a guard band coupled to the sidewalls, the guard band having a length that extends about a circumference of the detector, the guard band having a width that is greater than a thickness of the detector such that an upper rim segment of the guard band projects beyond the first surface of the detector, the upper rim segment being folded over a peripheral region of the first surface along the circumference of the detector, the guard band configured to reduce recombinations proximate to the edges of the detector. | 2014-12-25 |
20140374870 | IMAGE SENSOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are an image sensor module and a method of manufacturing the same. The image sensor includes: a base substrate having an image sensor mounted groove including a first groove and a second groove having a stepped shape; and an image sensor mounted in a groove of the base substrate. | 2014-12-25 |
20140374871 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which can suppress the influence of the external electric charge and can be efficiently manufactured is provided. The semiconductor device is provided with an active region in which a semiconductor element is disposed and a termination region between the active region and an edge surface of the semiconductor substrate. An insulating layer is disposed on at least a part of an upper surface of the termination region. A plurality of floating electrodes is disposed at an interval in the insulating layer in a direction from the active region toward the edge surface of the semiconductor substrate, and a width of the plurality of floating electrodes in a thickness direction of the semiconductor substrate is greater than a width of the plurality of floating electrodes in the direction from the active region toward the edge surface of the semiconductor substrate. | 2014-12-25 |
20140374872 | Controlled Buckling Structures in Semiconductor Interconnects and Nanomembranes for Stretchable Electronics - In an aspect, the present invention provides stretchable, and optionally printable, components such as semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed, and related methods of making or tuning such stretchable components. Stretchable semiconductors and electronic circuits preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention are adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices. | 2014-12-25 |
20140374873 | METHODS AND APPARATUS FOR CONGESTION-AWARE BUFFERING USING VOLTAGE ISOLATION PATHWAYS FOR INTEGRATED CIRCUIT DESIGNS WITH MULTI-POWER DOMAINS - A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred. | 2014-12-25 |
20140374874 | PROGRAMMABLE FUSE STRUCTURE AND METHODS OF FORMING - Methods of forming an electrically programmable fuse (e-fuse) structure and the e-fuse structure are disclosed. One embodiment of an e-fuse structure includes: a silicon structure; a pair of silicide contact regions overlying the silicon structure; and a silicide link overlying the silicon structure and connecting the pair of silicide regions, the silicide link having a depth less than a depth of each of the pair of silicide contact regions. | 2014-12-25 |
20140374875 | 3D Inductor and Transformer - In accordance with an embodiment, a semiconductor device comprises a semiconductor die, an interposer, and conductive bumps bonding the semiconductor die to the interposer. The semiconductor die comprises a first metallization layer, and the first metallization layer comprises a first conductive pattern. The interposer comprises a second metallization layer, and the second metallization layer comprises a second conductive pattern. Some of the conductive bumps electrically couple the first conductive pattern to the second conductive pattern to form a coil. Other embodiments contemplate other configurations of coils, inductors, and/or transformers, and contemplate methods of manufacture. | 2014-12-25 |
20140374876 | SEMICONDUCTOR DEVICE HAVING AN INDUCTOR - A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor. | 2014-12-25 |
20140374877 | Integrated Circuits With On-Die Decoupling Capacitors - An integrated circuit includes a decoupling capacitor and an internal circuit. The decoupling capacitor is coupled to a first external terminal of the integrated circuit. The internal circuit in the integrated circuit is coupled to a second external terminal of the integrated circuit. The decoupling capacitor is coupled to provide supply voltage current to the internal circuit through the first and the second external terminals and through external conductors. The external conductors are outside the integrated circuit. | 2014-12-25 |
20140374878 | MEMORY CELL WITH INTEGRATED III-V DEVICE - A method including forming an oxide layer on a top of a substrate; forming a deep trench capacitor in the substrate; bonding a III-V compound semiconductor to a top surface of the oxide layer; and forming a III-V device in the III-V compound semiconductor. | 2014-12-25 |
20140374879 | INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WRAP - Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include tensile films. The films can be formed within trenches on the back side of the wafer, which enhances their effect. In some embodiments, the wafers are used to form 3D-IC devices. In some embodiments, the 3D-IC device includes a high voltage or high power circuit. | 2014-12-25 |
20140374880 | DEEP TRENCH CAPACITOR - The present disclosure relates to a method of forming a capacitor structure, including depositing a plurality of first polysilicon (POLY) layers of uniform thickness separated by a plurality of oxide/nitride/oxide (ONO) layers over a bottom and sidewalls of a recess and substrate surface. A second POLY layer is deposited over the plurality of first POLY layers, is separated by an ONO layer, and fills a remainder of the recess. Portions of the second POLY layer and the second ONO layer are removed with a first chemical-mechanical polish (CMP). A portion of each of the plurality of first POLY layers and the first ONO layers on the surface which are not within a doped region of the capacitor structure are removed with a first pattern and etch process such that a top surface of each of the plurality of first POLY layers is exposed for contact formation. | 2014-12-25 |
20140374881 | CONCENTRIC CAPACITOR STRUCTURE - A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates. | 2014-12-25 |
20140374882 | Semiconductor Device with Recombination Centers and Method of Manufacturing - A semiconductor device includes a semiconductor portion with one or more impurity zones of the same conductivity type. A first electrode structure is electrically connected to the one or more impurity zones in a cell area of the semiconductor portion. At least in an edge area surrounding the cell area a recombination center density in the semiconductor portion is higher than in an active portion of the cell area. | 2014-12-25 |
20140374883 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region. | 2014-12-25 |
20140374884 | PHOTO-CURABLE COMPOSITION FOR IMPRINTS, PATTERN FORMING METHOD AND PATTERN - To provide a photo-curable composition for imprints which can ensure high ratio of mold filling and low defect density during mold releasing, and can provide a resist material with high etching durability. A photo-curable composition for imprints comprising a monofunctional monomer, a polyfunctional monomer and a photo-polymerization initiator, having a viscosity at 25° C. of 15 mPa·s or smaller, an Ohnishi parameter of 3.0 or smaller, and a crosslink density calculated by (Formula 1) of 0.6 mmol/cm | 2014-12-25 |
20140374885 | NARROW GAP DEVICE WITH PARALLEL RELEASING STRUCTURE - The present disclosure relates to a method of etching a narrow gap using one or more parallel releasing structures to improve etching performance, and an associated apparatus. In some embodiments, the method provides a semiconductor substrate with a narrow gap having a sacrificial material. One or more parallel releasing structures are formed within the semiconductor substrate at positions that abut the narrow gap. An etching process is then performed to simultaneously remove the sacrificial material from the narrow gap along a first direction from the one or more parallel releasing structures and along a second direction, perpendicular to the first direction. By simultaneously etching the sacrificial material from both the direction of the narrow gap and from the direction of the one or more parallel releasing structures, the sacrificial material is removed in less time, since the etch is not limited by a size of the narrow gap. | 2014-12-25 |
20140374886 | METHOD FOR FABRICATING A SUBSTRATE AND SEMICONDUCTOR STRUCTURE - The invention relates to a method for fabricating a substrate, comprising the steps of providing a donor substrate with at least one free surface, performing an ion implantation at a predetermined depth of the donor substrate to form an in-depth predetermined splitting area inside the donor substrate, and is characterized in providing a layer of an adhesive, in particular an adhesive paste, over the at least one free surface of the donor substrate. The invention further relates to a semiconductor structure comprising a semiconductor layer, and a layer of a ceramic-based and/or a graphite-based and/or a metal-based adhesive provided on one main side of the semiconductor layer. | 2014-12-25 |
20140374887 | COMPOSITION FOR FORMING PASSIVATION FILM, INCLUDING RESIN HAVING CARBON-CARBON MULTIPLE BOND - There is provided a composition for forming a passivation film that satisfies electric insulation, heat-tolerance, solvent-tolerance, and a dry etch back property at the same time. A composition for forming a passivation film, including: a polymer containing a unit structure of Formula (i): | 2014-12-25 |
20140374888 | SEMICONDUCTOR DEVICE - A high frequency signal can be transmitted and received in a semiconductor device. In a QFP, an antenna (frame body) is supported by three suspension leads. The antenna is arranged to be symmetrical with respect to a first virtual diagonal line of a plan view of a sealing body. One of the three suspension leads is arranged on the first virtual diagonal line. With this configuration, discontinuities of a wave of a signal in the antenna can be reduced, as a result of which the high frequency signal of 5 Gbps class can be transmitted and received in the QFP. | 2014-12-25 |
20140374889 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips. | 2014-12-25 |
20140374890 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - In an SOP1 having a semiconductor chip and another semiconductor chip, in wire coupling between the chips, a withstand voltage can be secured by setting an inter-wire distance between a wire in a first wire group that is closest to a second wire group and a wire in the second wire group that is closest to the first wire group to be larger than an inter-wire distance between any wires in the first wire group and the second wire group, which makes it possible to attain improvement of reliability of the SOP1. | 2014-12-25 |
20140374891 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER AND THERMAL SHEET - A semiconductor device includes a die pad and a semiconductor die having a mounting surface attached to the die pad and an opposite, active surface with die external terminals. The device has package external connectors, each having a bond region selectively electrically coupled to the die external terminals with a bond wire. A heat spreader has a first region that encloses an inner recessed region. A thermally conductive sheet is sandwiched between the inner recessed region of the heat spreader and the active surface of the die. At least the die, die external terminals, and the bond region are covered with an encapsulant. | 2014-12-25 |
20140374892 | LEAD FRAME AND SEMICONDUCTOR DEVICE USING SAME - A lead frame for a semiconductor device has a die pad for supporting a semiconductor die and intermediate lead fingers extending from a periphery of the package towards the die pad, and each having a bonding end near the die pad. Outer lead fingers are located adjacent respective tie bars edges, each outer lead finger extending from the periphery of the package towards the die pad. Each outer lead finger has a transverse region coupling two spaced longitudinal regions. The two spaced longitudinal regions each have a bonding region near the die pad. A semiconductor die is attached to the die pad and bond wires electrically couple connection pads of the semiconductor die to the bonding regions of each outer lead finger. Only one of the bond wires is bonded to the bonding region of the second longitudinal region. | 2014-12-25 |
20140374893 | SEMICONDUCTOR PACKAGE - A semiconductor package, comprising: a package substrate including chip regions, a separation region between the chip regions, and an edge region around the chip and separation regions; semiconductor chips disposed on the chip regions of the package substrate; and signal patterns. The package substrate comprises an upper layer substantially adjacent to the semiconductor chips, a lower layer including interconnection structures disposed in the chip regions, and an intermediate layer between the upper and lower layers, the intermediate layer includes through holes disposed only outside of the separation region; and the signal patterns are in contact with the interconnection structures through the through holes. | 2014-12-25 |
20140374894 | PACKAGE ON PACKAGE STRUCTRUE AND METHOD FOR MANUFACTURING SAME - A package on package structure includes a connection substrate having a main body and electrically conductive posts, the main body includes a first surface and an opposite second surface, and each electrically conductive post passes through the first and second surfaces, and each end of the two ends of the electrically conductive post protrudes from the main body; a first package device arranged on a side of the first surface of the connection substrate; a package adhesive arranged on a side of the second surface of the connection substrate; and a second package device arranged on a side of the package adhesive furthest away from the first package device. | 2014-12-25 |
20140374895 | SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of semiconductor elements each having a front surface and a back surface; a front surface-side heatsink that is positioned on a front-surface side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a back surface-side heatsink that is positioned on a back surface-side of the semiconductor elements and dissipates heat generated by the semiconductor elements; a sealing material that covers the semiconductor device except for a front surface of the front surface-side heatsink and a back surface of the back surface-side heatsink; a primer that is coated on at least one of the front surface-side heatsink and the back surface-side heatsink and improves contact with the sealing member; and a protruding portion positioned between the plurality of semiconductor elements, on at least one of the back surface of the front surface-side heatsink and the front surface of the back surface-side heatsink. | 2014-12-25 |
20140374896 | SEMICONDUCTOR DEVICE, METHOD FOR INSTALLING HEAT DISSIPATION MEMBER TO SEMICONDUCTOR DEVICE, AND A METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device is fastened to a heat dissipation member such that a force directed downward acts from a metal substrate onto the heat dissipation member, with a rim portion of a storage region as a fulcrum with respect to the heat dissipation member. As a result, a heat conductive material can be spread into a thinner layer between the metal substrate and the heat dissipation member, improving the heat dissipation between the metal substrate and the heat dissipation member. | 2014-12-25 |
20140374897 | THERMAL INTERFACE MATERIAL FOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING THE SAME - In an embodiment, a thermal interface material (TIM) is provided. The TIM comprises first and a second layers of a first transition metal, and a third layer including a plurality of carbon nanotubes supported in a flexible polymer matrix and a second transition metal coupled to sidewalls of carbon nanotubes. The first and second metal layers are in contact with first and second ends of carbon nanotube. The TIM further comprises fourth and fifth layers of an alloy material coupled to the first and second metal layers, respectively. The carbon nanotube based TIM including the layers with transition metal allow improved heat transfer from an integrated circuit die to a heat spreader. | 2014-12-25 |
20140374898 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE FABRICATION METHOD - A semiconductor device includes a terminal case, a beam portion which has elasticity and is connected to the terminal case, divided insulating substrates with a conductive pattern, a fastener which is disposed at the center of the terminal case, and an elastic sealing resin which fills the terminal case. | 2014-12-25 |
20140374899 | Package with Solder Regions Aligned to Recesses - A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. | 2014-12-25 |
20140374900 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package includes memory I/O bumps and power/ground voltage bumps which are disposed at different positions from each other. In the semiconductor package, memory chips are disposed side by side, and a passivation layer is interposed between a conductive pad and a bump. | 2014-12-25 |
20140374901 | SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A semiconductor package including: a substrate including a grounding pattern and a pad, the grounding pattern and the pad being separated and electrically insulated from each other; a semiconductor chip mounted on the substrate, the semiconductor chip including an active surface and an inactive surface opposite to the active surface; a bump interposed between the active surface and the pad to electrically connect the active surface to the pad; and a conductive member including at least a portion, the at least a portion being disposed on the inactive surface and electrically connected to the grounding pattern. | 2014-12-25 |
20140374902 | STACK TYPE SEMICONDUCTOR PACKAGE - A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate. | 2014-12-25 |
20140374903 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 2014-12-25 |
20140374904 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND SEMICONDUCTOR MANUFACTURING APPARATUS - The present disclosure provides a semiconductor device, including: an insulation layer and a wiring line layer, the wiring line layer including a wiring line having a line width and a line height, at least one of which is 15 nm or less, and containing Ni or Co as a main component thereof. In another embodiment, there is provided a semiconductor device manufacturing method for manufacturing a semiconductor device including an insulation layer and a wiring line layer, including: forming the wiring line layer on the insulation layer, the wiring line layer including a wiring line having a line width and a line height, at least one of which is 15 nm or less, and containing Ni or Co as a main component thereof. | 2014-12-25 |
20140374905 | FORMATION OF CONDUCTIVE CIRCUIT, CONDUCTIVE CIRCUIT, AND CONDUCTIVE INK COMPOSITION - A conductive circuit is formed by printing a pattern of an ink composition and curing the pattern. The ink composition is a substantially solvent-free, liquid, addition curable, ink composition comprising (A) an organopolysiloxane having at least two alkenyl groups, (B) an organohydrogenpolysiloxane having at least two SiH groups, (C) conductive particles having an average particle size ≧5 μm, (D) conductive micro-particles having an average particle size <5 μm, (E) a thixotropic agent, and (F) a hydrosilylation catalyst. | 2014-12-25 |
20140374906 | METHOD FOR PROCESSING A CARRIER AND AN ELECTRONIC COMPONENT - In various embodiments, a method for processing a carrier is provided. The method for processing a carrier may include: forming a first catalytic metal layer over a carrier; forming a source layer over the first catalytic metal layer; forming a second catalytic metal layer over the source layer, wherein the thickness of the second catalytic metal layer is larger than the thickness of the first catalytic metal layer; and subsequently performing an anneal to enable diffusion of the material of the source layer forming an interface layer adjacent to the surface of the carrier from the diffused material of the source layer. | 2014-12-25 |
20140374907 | ULTRA-THIN COPPER SEED LAYER FOR ELECTROPLATING INTO SMALL FEATURES - An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. Modification of an upper portion of a metal seed layer allows for filling of the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free. | 2014-12-25 |
20140374908 | Semiconductor Device and Manufacturing Method Thereof - To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed. | 2014-12-25 |
20140374909 | METHOD FOR FILLING TRENCH WITH METAL LAYER AND SEMICONDUCTOR STRUCTURE FORMED BY USING THE SAME - A method for filling a trench with a metal layer is disclosed. A deposition apparatus having a plurality of supporting pins is provided. A substrate and a dielectric layer disposed thereon are provided. The dielectric layer has a trench. A first deposition process is performed immediately after the substrate is placed on the supporting pins to form a metal layer in the trench, wherein during the first deposition process a temperature of the substrate is gradually increased to reach a predetermined temperature. When the temperature of the substrate reaches the predetermined temperature, a second deposition process is performed to completely fill the trench with the metal layer. The present invention further provides a semiconductor device having an aluminum layer with a reflectivity greater than 1, wherein the semiconductor device is formed by using the method. | 2014-12-25 |
20140374910 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper. | 2014-12-25 |
20140374911 | DEVICE HAVING REDUCED PAD PEELING DURING TENSILE STRESS TESTING AND A METHOD OF FORMING THEREOF - The present disclosure relates to a method for forming a semiconductor device. The method includes forming a first aluminum pad layer on a metal layer, forming an adhesion layer on the first aluminum pad layer, etching the adhesion layer so as to form a patterned adhesion layer, and forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer. | 2014-12-25 |
20140374912 | Micro-Spring Chip Attachment Using Solder-Based Interconnect Structures - Standard solder-based interconnect structures are utilized as mechanical fasteners to attach an IC die in a “flip-chip” orientation to a support structure (e.g., a package base substrate or printed circuit board). Electrical connections between the support structure and the IC die are achieved by curved micro-springs that are disposed in peripheral regions of the IC die and extend through a gap region separating the upper structure surface and the processed surface of the IC die. The micro-springs are fixedly attached to one of the support structure and the IC die, and have a free (tip) end that contacts an associated contact pad disposed on the other structure/IC die. Conventional solder-based connection structures (e.g., solder-bumps/balls) are disposed on “dummy” (non-functional) pads disposed in a central region of the IC die. After placing the IC die on the support structure, a standard solder reflow process is performed to complete the mechanical connection. | 2014-12-25 |
20140374913 | CIRCUIT ARRANGEMENT AND METHOD FOR MANUFACTURING THE SAME - Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second integrated circuit of the plurality of integrated circuits to form a first current path bypassing the carrier; and wherein the first integrated circuit of the plurality of integrated circuits is in electrical contact with the second integrated circuit of the plurality of integrated circuits to form a second current path via the at least one electrically conductive line. | 2014-12-25 |
20140374914 | STRESS COMPENSATION PATTERNING - An apparatus includes a device that includes at least one layer. The at least one layer includes an inter-device stress compensation pattern configured to reduce an amount of inter-device warpage prior to the device being detached from another device. | 2014-12-25 |
20140374915 | INTEGRATION OF OPTICAL COMPONENTS IN INTEGRATED CIRCUITS - Methodologies enabling integration of optical components in ICs and a resulting device are disclosed. Embodiments include: providing a first substrate layer of an IC separated from a second substrate level by an insulator layer; providing a transistor on the second substrate layer; and providing an optical component on the first substrate layer, the optical component being connected to the transistor. | 2014-12-25 |
20140374916 | TSV INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF - A method for forming a through-substrate-via structure includes forming a via hole in a substrate, depositing a conductive material in the via hole, forming an annular groove in the substrate surrounding the conductive material, and depositing a dielectric material in the annular groove with overhang portions of the deposited dielectric material at a top surface of the groove forming an air gap in an interior portion of the groove. | 2014-12-25 |
20140374917 | COMPONENT IN THE FORM OF A WAFER LEVEL PACKAGE AND METHOD FOR MANUFACTURING SAME - A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer. | 2014-12-25 |
20140374918 | ASIC ELEMENT INCLUDING A VIA - In an ASIC element, vias are integrated into the CMOS processing of an ASIC substrate. The ASIC element includes an active front side in which the circuit functions are implemented. The at least one via is intended to establish an electrical connection between the active front side and the rear side of the element. The front side of the via is defined by at least one front-side trench which is completely filled, and the rear side is defined by at least one rear-side trench which is not completely filled. The rear-side trench opens into the filled front-side trench. | 2014-12-25 |
20140374919 | Method for Producing Contact Areas on a Semiconductor Substrate - Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components. | 2014-12-25 |
20140374920 | CD CONTROL - A method includes providing a substrate with a patterned second layer over a first layer. The second layer includes a second layer opening having a first CD equal to the CD produced by a lithographic system (CD | 2014-12-25 |
20140374921 | Ball Height Control in Bonding Process - A package includes a first package component, a second package component over the first package component, and a solder region bonding the first package component to the second package component. At least one ball-height control stud separates the first package component and the second package component from each other, and defines a standoff distance between the first package component and the second package component. | 2014-12-25 |
20140374922 | Alignment in the Packaging of Integrated Circuits - A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package. | 2014-12-25 |
20140374923 | SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM - Provided is a semiconductor apparatus including a plurality of semiconductor chips coupled through an electrical coupling unit. Each of the semiconductor chips includes: a chip ID signal generation unit configured to generate a chip ID signal; and a chip enable signal generation unit configured to receive a clock enable signal in response to the chip ID signal, wherein one of the semiconductor chips shares the received clock enable signal as a transfer clock enable signal with the other semiconductor chips, and the chip enable signal generation unit detects whether or not an error occurs in the chip ID signals of the plurality of semiconductor chips, selects any one of the transfer clock enable signal and the clock enable signal applied, and outputs the selected signal as a chip enable signal. | 2014-12-25 |
20140374924 | Heterogeneous Integration Process Incorporating Layer Transfer in Epitaxy Level Packaging - Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes. | 2014-12-25 |
20140374925 | COMPONENT ASSEMBLY USING A TEMPORARY ATTACH MATERIAL - A method of attaching a die to a carrier using a temporary attach material is disclosed. The method comprises attaching the temporary attach material between a surface of the die and a surface of the carrier. The temporary attach material attaches the die to the carrier. The method comprises bonding at least one connector to the die and the carrier. The connector includes a first end bonded to the carrier and a second end bonded to the die. The method further comprises encapsulating at least a portion of the die and at least a portion of the at least one connector by an encapsulation material. | 2014-12-25 |
20140374926 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having an electrode, a connector having a chip contact surface, an interconnecting portion, and an external electrode terminal contact surface, the chip contact surface being electrically connected to the electrode, and a first connection material disposed between the chip contact surface and the electrode, the first connecting material having a surface area that is greater than a surface area of the chip contact surface. | 2014-12-25 |
20140374927 | COMBINED COLLECTOR AND DISTRIBUTOR - A combined collector and distributor for a distillation column that includes a collector portion connected to a distributor portion. The distributor portion includes a channel-like distributor to distribute liquid into an underlying packing The collector portion has spaced rows of collection elements that cover the open spaces and distribution elements of the distributor portion and one or more rectangular sumps into which descending liquid drains from the collection elements. The liquid in turn drains from the rectangular sump or sumps into a pre-distribution box located within a header of the distributor portion. The collection elements that cover the open spaces are set at higher positions than the collection elements covering the distribution elements to form chimneys to allow the ascending vapor to escape from the collector portion. | 2014-12-25 |
20140374928 | TUBE DIFFUSER - Aspects of the invention are directed to an apparatus comprising a proximal end adapter, a distal end adapter, a support tube, and a flexible diffuser membrane. The support tube is disposed between the proximal end adapter and the distal end adapter, and comprises an outward facing surface that defines a series of ridges thereon. The diffuser membrane, in turn, defines a plurality of perforations, and surrounds at least a respective portion of each of the proximal end adapter, the distal end adapter, and the support tube. | 2014-12-25 |
20140374929 | HUMIDITY CONTROL MODULE AND HUMIDITY CONTROL APPARATUS - A humidity control module, in which liquid absorbent exchanges air and moisture, reduces a temperature change in the liquid absorbent. A humidity control module includes a partition member and a heat transfer member. The partition member separates an air passage from an absorbent passage. The partition member is wholly or partially formed by a moisture permeable membrane. The liquid absorbent flowing through the absorbent passage exchanges the moisture with the air flowing through the air passage via the moisture permeable membrane. The heat transfer member is provided in the absorbent passage and surrounded by the liquid absorbent. A heat medium flowing through the heat transfer member exchanges heat with the liquid absorbent flowing through the absorbent passage. | 2014-12-25 |
20140374930 | METHOD FOR TRANSFERRING OBJECTS ONTO A SUBSTRATE USING A COMPACT PARTICLE FILM, INCLUDING A STEP OF PRODUCING CONNECTORS ON THE OBJECTS - A method for transferring objects onto a substrate, or running substrate, the objects to be transferred being placed in a transfer area containing a carrier liquid forming a conveyor, the objects being held by a compact film of particles floating on the carrier liquid of the transfer area, within which the objects are displaced with the film of particles to be transferred onto the substrate, making at least one connector on at least one of the objects, the connector being made by a substance comprising a polymerizable compound, put in contact with the object arranged within the transfer area, and then by polymerization of the substance. | 2014-12-25 |
20140374931 | METHOD FOR PRODUCING TRANSPARENT CERAMIC OBJECTS BY MEANS OF FLUIDIZED BED GRANULATION - A method for producing transparent ceramic objects having an RIT>10% in the wave length range of 300 nm to 4000 nm and a wall thickness of 2 mm. Said method consists of the following steps: producing a slip by dispersing a ceramic powder, the particle size of which is d50<5 μm, preferably between 5 nm and 500 nm; producing a granular material, the particle size of which is d50<1 mm, preferably between 50 μm and 500 μm, more preferably between 80 μm and 300 μm, from the slip by means of fluidised bed granulation; pressing the granular material in a simple, non-cyclical manner to form a green body; sintering the green body to form a sintered body; and re-densifying the sintered body. | 2014-12-25 |
20140374932 | METHOD OF MANUFACTURING PLASTIC LENS, AND METHOD FOR MANUFACTURING MOLD FOR FORMING OPTICAL LENS - A method for manufacturing a plastic lens that can enhance productivity by shortening the cooling time without affecting transferability even if the temperature of a mold is set low and may be applicable to an existing injection molding apparatus. When a plastic lens having a prescribed lens shape is manufactured by injecting and filling a molten resin in a cavity | 2014-12-25 |
20140374933 | METHODS AND APPARATUS FOR MOBILE ADDITIVE MANUFACTURING OF ADVANCED STRUCTURES AND ROADWAYS - The present disclosure provides various aspects for mobile and automated processing utilizing additive manufacturing and the methods for their utilization. In some examples, the mobile additive manufacturing apparatus may perform surface treatments that support the building of walls. Other examples may involve the support of creating and repairing advanced roadways. | 2014-12-25 |
20140374934 | METHOD FOR STRENGTHENING SEMICONDUCTOR MANUFACTURING TOOLS - A method for strengthening semiconductor manufacturing tools is provided. The method includes providing a mold insert, forming a native oxide layer, attaching a release agent film, and forming a glass bonded SiO | 2014-12-25 |
20140374935 | METHODS AND APPARATUS FOR MOBILE ADDITIVE MANUFACTURING - The present disclosure provides various aspects for mobile and automated processing utilizing additive manufacturing. The present disclosure includes methods for the utilization of mobile and automated processing apparatus. In some examples, the mobile additive manufacturing apparatus may perform surface treatments that alter the topography of an existing surface. Other examples may involve the processing of dimensionally large layers which may be joined together to create large pieces with three dimensional shape. | 2014-12-25 |
20140374936 | Porous Media Heat Transfer for Injection Molding - The cooling of injection molded plastic is targeted. Coolant flows into a porous medium disposed within an injection molding component via a porous medium inlet. The porous medium is thermally coupled to a mold cavity configured to receive injected liquid plastic. The porous medium beneficially allows for an increased rate of heat transfer from the injected liquid plastic to the coolant and provides additional structural support over a hollow cooling well. When the temperature of the injected liquid plastic falls below a solidifying temperature threshold, the molded component is ejected and collected. | 2014-12-25 |
20140374937 | BATTERY SEPARATORS WITH VARIABLE POROSITY - A porous polymer battery separator is provided that includes variable porosity along its length. Such battery separators can increase the uniformity of the current density within electrochemical battery cells that may normally experience higher current density and higher temperatures near their terminal ends than they do near their opposite ends. By disposing a variable porosity separator between the electrodes of an electrochemical cell such that its terminal end has a lower porosity than its opposite end, the transport of ions, such as lithium ions, through the separator can be more restricted in normally high current regions and less restricted in normally low current regions, thereby increasing the overall uniformity of current density within the battery cell. Variable porosity battery separators may be produced by a dry-stretching process or by a wet process. These processes may include forming a polymer-containing film, producing a uniform distribution of pore sites within the film, and reforming the polymer-containing film to a uniform thickness. | 2014-12-25 |
20140374938 | PROCESS FOR MAKING A CERAMIC ARTICLE - Disclosed is a process for producing ceramic particles, such as proppants, that have at least 10 percent total porosity. The process includes forming a particle precursor that includes 5 percent to 30 percent of a first ceramic material and at least 40 percent of a second ceramic material. The sintering temperature of the first ceramic material may be lower than the sintering temperature of a second ceramic material. Heating the precursor to a maximum temperature above the sintering temperature of the first material and below the sintering temperature of the second material. Also disclosed is a ceramic article that has a particular combination of chemistry and alumina crystalline phase. | 2014-12-25 |
20140374939 | MANUFACTURING METHOD OF LENS DEVICE - A manufacturing method of a lens device includes steps of: injecting an outer-layer material into a mold; injecting an inner-layer material into the mold, wherein the inner-layer material is enclosed by the outer-layer material; and solidifying the outer-layer material and the inner-layer material. The lens device made by the manufacturing method of this invention can exert the advantage of decreasing the cost. | 2014-12-25 |
20140374940 | FOAMING DIE DEVICE ADAPTED TO EFFECT FOAMING IN TRIM COVER ASSEMBLY INTEGRALLY TO FORM HEADREST, AND FOAMING PROCESS FOR FORMING HEADREST BY EFFECTING FOAMING IN TRIM COVER ASSEMBLY INTEGRALLY, USING THE FOAMING DIE DEVICE - A foaming die device for forming a headrest is provided, which comprises a lower die having a first protrusion and an upper die having a second protrusion. The lower and upper dies are used for accommodating a trim cover assembly with a headrest stay portion extending outwardly through a stay passage hole formed in the trim cover assembly. The first and second protrusions are adapted to press and turn over a projected area created about the stay hole into the inside of that trim cover assembly. Also, a foaming process for forming the headrest, using this foaming die device, is provided, in which the projected area is turned over by the first and second protrusions into the trim cover assembly when placing the trim cover assembly in the dies. Hence, conventional preliminary steps using cylindrical stick to turn over the projected area into the trim cover assembly are eliminated. | 2014-12-25 |
20140374941 | ENHANCING AND PRESERVING ANTI-MICROBIAL PERFORMANCE IN FIBERS WITH PIGMENTS - A method for producing fibers with improved color and anti-microbial properties is described. One embodiment includes a method for generating a halogen stable anti-microbial synthetic fiber, the method comprising creating a mixture that includes a polymer, an anti-microbial agent, and a non-halogen pigment, and extruding the mixture to form an anti-microbial synthetic fiber. | 2014-12-25 |
20140374942 | MANUFACTURING METHOD OF BAG BODY - A manufacturing method of a bag body that has a bag-shaped member made of an elastic and airtight material, and a granular substance filled inside of the bag-shaped member, includes a step of preparing a core for forming the bag-shaped member, by hardening the granular substance; a step of forming the bag-shaped member by forming a covering made of the elastic and airtight material around the core; and a step of breaking up the core that is inside of the bag-shaped member. | 2014-12-25 |
20140374943 | METHOD FOR PRODUCING BANDAGES - In a method for producing bandages such as support bandages for knee and elbow joints, an elastic fabric material layer is provided on which reinforcement elements are placed and an uncured elastomer is applied to the fabric material in several layers or sprayed onto the fabric material layer so as to completely cover and embed the reinforcement elements which are firmly engaged thereby with the fabric material layer and form three-dimensional stabilising structures projecting from the surface of the fabric material layer. | 2014-12-25 |
20140374944 | HIGH BARRIER HEAT SEALABLE FILM WITH LINEAR TEAR PROPERTIES - A monoaxially oriented film including a metallized layer; a gas barrier layer; and a propylene-based random copolymer and at least about 3 wt % of a low density polyethylene which is oriented at least about 2.5 times in one direction and exhibits excellent linear directional tear properties parallel to the orientation direction and excellent heat seal performance in terms of high heat seal strengths and low seal initiation temperature. This film formulation and orientation is suitable for pouch applications requiring high gas and moisture barrier, an “easy-tear” linear tear feature, and excellent hermetic seal properties. | 2014-12-25 |
20140374945 | GASKET ASSEMBLY WITH IMPROVED LOCATING AND RETENTION PIN AND METHOD OF CONSTRUCTION THEREOF - A gasket assembly and method of construction is provided. The assembly includes a carrier body having opposite planar surfaces with at least one media-conveying opening extending through the planar surfaces with at least one through opening spaced radially from the at least one media-conveying opening. Further, the carrier body has at least one projection formed of the material of the carrier body. The at least one projection extends from the at least one through opening outwardly from at least one of the planar surfaces. The assembly further includes an elastomeric material encapsulating the projection. | 2014-12-25 |