52nd week of 2008 patent applcation highlights part 22 |
Patent application number | Title | Published |
20080315888 | INDUCTION COIL RESISTANCE TESTER - Inventive subject matter described herein includes an induction coil resistance tester, comprising: a base effective for absorbing vibration; a mechanism for moving a sample in x, y, and z directions; a scale for measuring weight of the sample; and an ohmmeter for measuring resistance of the sample. | 2008-12-25 |
20080315889 | FAULT ISOLATION IN INTERCONNECT SYSTEMS - A loopback connector for a system can include a connector arrangement connectable to connector of a system component and/or a cable. The loopback connector can include loopback logic for simulating cable and/or system component functionality. In an example implementation the loopback connector can also operate to protect a system component and/or cable connector during shipping. | 2008-12-25 |
20080315890 | Image Display Device - An image display device includes a black spot defect position determination circuit which determines a position of a black-spot defective pixel of a self-luminous display panel. A detection-use current source in the black spot defect position determination circuit is connected to pixels during a period separate from a display period of data signals thus determining a black spot defect. The position of the black spot defect is stored in a storing circuit and is transmitted to a display and detection control circuit. The display and detection control circuit corrects the data signals to the pixels around the defective pixel based on a black spot defect position, and drives a data line drive circuit based on the corrected data signals thus visually correcting the black spot defect. | 2008-12-25 |
20080315891 | Transmission line pulse testing with reflection control - A Transmission Line Pulse (TLP) testing system is disclosed that has a negative pulse inverter circuit that prevents large negative reflections which typically occur after the initial TLP pulse is applied to a low impedance device under test (DUT). Avoiding repetitive reflections, which naturally occur in TLP systems, prevents inducing DUT damage and confusing testing results. The pulse inverter circuit reduces reflections to lower levels than prior art TLP configurations, and can also be combined with known techniques to further reduce reflections for different impedance DUTs. | 2008-12-25 |
20080315892 | Methods and apparatus using one or more supernodes when testing for shorts between nodes of a circuit assembly - A method of testing for shorts between nodes of a circuit assembly includes parsing circuit design data to identify positional data for nodes of a circuit assembly, and using the positional data to classify ones of the nodes as members of a supernode, where each member of the supernode is unlikely to be shorted to any other member of the supernode. Tests for shorts in a set of nodes that includes the supernode and a plurality of other nodes of the circuit assembly are then conducted, by iteratively i) stimulating a particular one of the set of nodes, and ii) while stimulating the particular node, grounding at least one other node in the set of nodes and monitoring a current flow through the particular node. When stimulating or grounding a supernode, all of the nodes that are members of the supernode are stimulated or grounded. If a current flow is detected through one of the stimulated nodes, the circuit assembly is indicated to be defective. Other embodiments are also disclosed. | 2008-12-25 |
20080315893 | Contact and connecting apparatus - A contact and a connecting apparatus are provided to enable miniaturization and shortening and cost reduction in response to further miniaturization and finer pitch of inspection objects. The contact is one electrically for contacting a terminal of a wire and includes a one-side plunger portion, an other-side plunger portion, and an elastic deformation portion provided between the plunger portions. The elastic deformation portion is made of an annular and conductive elastic member integrally connected to the one-side plunger portion and the other-side plunger portion. The plurally arranged elastic deformation portions are disposed in a zigzag shape in the up-down direction with their adjacent heights different from each other. The connecting apparatus includes the plurality of contacts electrically contacting terminals disposed on an inspection object and a contact plate for integrally supporting the respective contacts to make the contacts contact with the respective terminals of the inspection object. | 2008-12-25 |
20080315894 | Testing Adapter - The invention relates to a testing adapter suitable for testing a wireless telecommunication device. The testing adapter comprises a first contact member and a second contact member, the first contact member and the second contact member having at least one degree of freedom relative to each other and arranged to provide an attachable and detachable mechanical coupling with a surface of a component recess of the wireless telecommunication device on the basis of the at least one degree of freedom. | 2008-12-25 |
20080315895 | TEST METHOD AND APPARATUS FOR SPARK PLUG INSULATOR - There is provided a test method for detecting the presence or absence of a defect in a spark plug insulator, including a reference voltage determination process, a test area determination process, a test voltage determination process and a current detection process. In the reference voltage determination process, a reference voltage V | 2008-12-25 |
20080315896 | TECHNIQUES AND APPARATUS FOR THE MEASUREMENT OF MUTUAL INDUCTANCE IN A SWITCHED RELUCTANCE MACHINE - A system and technique for measuring the mutual inductance in a switched reluctance machine (SRM). In a first example embodiment of the technique, a voltage pulse is applied to primary coil when the machine is stationery. By measuring current in the primary coil and measuring induced voltages in adjacent open circuited coils mutual inductance may be determined. In another example embodiment, a voltage pulse is applied to the primary coil when the machine is stationery. The secondary coil is allowed to freewheel current through the phase. By measuring time taken by the primary phase to reach a preset value, the mutual inductance for the known position of a rotor can be determined. | 2008-12-25 |
20080315897 | INDUCTION COIL RESISTANCE TESTER - Inventive subject matter described herein includes an induction coil resistance tester, comprising: a base effective for absorbing vibration; a mechanism for moving a sample in x, y, and z directions; a scale for measuring weight of the sample; and an ohmmeter for measuring resistance of the sample. | 2008-12-25 |
20080315898 | Acquiring Test Data From An Electronic Circuit - Methods, systems, and computer program products are disclosed for acquiring test data from an electronic circuit by mounting a probe adjacent to a capture point on an electronic circuit board, capturing by the probe an electronic signal of the electronic circuit, digitizing by the probe the captured signal, and transmitting by the probe the digitized signal from the probe through a data communications connection to a remote device. Acquiring test data from an electronic circuit also includes storing by the probe the digitized signal in the probe. Acquiring test data from an electronic circuit may include processing by the probe the digitized signal. Acquiring test data from an electronic circuit also may include synchronizing acquisition of test data by the probe with acquisition of test data by one or more other probes. | 2008-12-25 |
20080315899 | Test Apparatus for Testing a Semiconductor Device, and Method for Testing the Semiconductor Device - A test apparatus for testing a semiconductor device having contact pads on its top and its back, and to a method for testing the semiconductor device is disclosed. In one embodiment, the test apparatus has a test socket which is mounted on a test printed circuit board. Internal through-contact elements of the test socket can be used to test contact pads on the top of the semiconductor device. The contact pads on the back of the semiconductor device can be connected for the purpose of testing the semiconductor device using external through-contact elements which are arranged outside of the locating seat. | 2008-12-25 |
20080315900 | HIGH TEMPERATURE CERAMIC SOCKET CONFIGURED TO TEST PACKAGED SEMICONDUCTOR DEVICES - A test socket assembly is for use in testing integrated circuits. A single piece socket is formed substantially of an insulating material and having a plurality of holes formed therein configured to receive a plurality of electrically conductive springs. Each hole of the single piece socket has therein a separate one of the electrically conductive springs. A test socket includes a plurality of pins configured to receive leads of an integrated circuit, the pins of the test socket extending into the plurality of holes of the single piece socket with each pin engaging a spring, wherein the single piece socket is positioned on a circuit board with the plurality of holes being in alignment with electrical contacts on the circuit board such that the plurality of springs are electrically interconnecting the contacts and the plurality of pins. The single -piece socket is comprised substantially of a high-temperature insulating material, such as ceramic. | 2008-12-25 |
20080315901 | MULTILAYER WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME AND PROBE APPARATUS - The present invention provides a multilayer wiring board in which resistive elements each of whose error from a desired value is smaller than in a conventional case are built, a method for manufacturing the same, and a probe apparatus utilizing the multilayer wiring board. The present invention is based on a basic concept of forming a flat surface on a surface of a multilayer wiring layer on which a resistive element material is to be deposited and depositing the resistive element material on the flat surface. The multilayer wiring board comprises a multilayer wiring layer on whose surface convexo-concave is formed, a dummy layer burying the convexo-concave within a desired area of the surface of the multilayer wiring layer and having an approximately flat surface, a resistance material layer made of an electrical resistance material deposited on the dummy layer and at an area going beyond the dummy layer, and a wire made of a conductive material deposited on the resistance material layer and ranging from the area going beyond the dummy layer to a part of the flat surface area of the dummy layer, wherein a resistive element is formed at an area of the resistance material layer that the wire does not reach. | 2008-12-25 |
20080315902 | TEST DEVICE, TEST CARD, AND TEST SYSTEM - A test device to be connected to a multi-card slot of an electronic apparatus performs test for connection between a card inserted into the multi-card slot and the multi-card slot with a plurality of connection terminals. The test device includes a test card and a connection unit. The test card includes a plurality of contact portions to be connected to all of the plurality of connection terminals of the multi-card slot and is inserted into the multi-card slot. The connection unit includes the plurality of cards and connects the plurality of cards to the test card. | 2008-12-25 |
20080315903 | METHOD FOR MEASUREMENT OF A DEVICE UNDER TEST - A method is disclosed for measurement of wafers and other semiconductor components in a probe station, which serves for examination and testing of electronic components. The device under test is held by a chuck and at least one electric probe by a probe support and the device under test and the probe are selectively positioned relative to each other by a positioning device with electric drives and the device under test is contacted. The drive of the positioning device remains in a state of readiness until establishment of contact and is switched off after establishment of contact and before measurement of the device under test. | 2008-12-25 |
20080315904 | METHOD FOR REGISTERING PROBE CARD AND A STORAGE MEDIUM STORING PROGRAM THEREOF - A probe card registration method is for registering a probe card for use in inspecting electrical characteristics of a target object in a probe apparatus for performing the inspecting. The probe card registration method includes detecting a height of a load sensor provided at a mounting table for mounting thereon the target object by using a first imaging unit disposed above the mounting table; contacting the load sensor with a probe by moving the load sensor by the mounting table; and stopping the movement of the load sensor when the load sensor starts to make contact with the probe. The method further includes calculating a height of a needle of the probe based on a height of the load sensor and a stop height thereof. | 2008-12-25 |
20080315905 | Electrical Connecting Apparatus - The present invention provides an electrical connecting apparatus that does not cause lack of mechanical strength in a probe board. The electrical connecting apparatus comprises a probe board spaced from a support member and arranged with its one surface opposed to the support member. On one surface of the probe board is provided a fixed portion having an opened screw hole at its top portion, and on the other surface are provided probes that are connected to a tester. The electrical connecting apparatus comprises a cylindrical spacer keeping a distance from the support member to a top surface of the fixed portion and a male screw member screwed in the screw hole for the purpose of tightening the support member and the probe board at a distance in accordance with the length of the spacer. The probe board has a support plate in which a plurality of conductive paths penetrating in the plate thickness direction and connected to the tester are formed and a wiring plate in which wiring paths connected to the corresponding conductive paths are formed, whose one surface is fixed to the support plate, and on the other surface of which are provided the probes corresponding to the wiring paths. The fixed portion is constituted by a female screw member fixed to the support plate at an area where no conductive paths are formed. | 2008-12-25 |
20080315906 | FAULTY DANGLING METAL ROUTE DETECTION - A system is provided that facilitates locating long dangling metal routes in a semiconductor chip design. The system includes mechanisms for partitioning metal features of the chip design to discover dangling metal routes that could be potential violations. The system further comprises mechanisms for determining if the dangling metal routes of the chip design exceed a length limit that could result antenna violations, undesired noise in the circuit, circuitry breakdown or the like. The system enables excessively long dangling metal routes to be allowed as exceptional cases. Machine learning is provided to receive feedback to refine the exceptional cases and enable more efficient fault detection. | 2008-12-25 |
20080315907 | Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like - An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring FET is interconnected with a first biasing terminal. The first drain-source terminals of the FETS to be tested are interconnected with a second biasing terminal. A state machine is coupled to the gates of the FETS to be tested and the gate of the first measuring FET. The state machine is configured to energize the gate of the first measuring FET and to sequentially energize the gates of the FETS to be tested, so that an output voltage appears on the output terminal. Circuitry to compare the output voltage to a reference value is also provided. The gate of the first measuring field effect transistor is energized; the gates of the field effect transistors to be tested are sequentially energized, whereby an output voltage appears on the output terminal; and the output voltage is compared to the reference value. | 2008-12-25 |
20080315908 | DIRECT DETECT SENSOR FOR FLAT PANEL DISPLAYS - Each sensor of a linear array of sensors includes, in part, a sensing electrode and an associated feedback circuit. The sensing electrodes are adapted to be brought in proximity to a flat panel having formed thereon a multitude of pixel electrodes in order to capacitively measure the voltage of the pixel electrodes. Each feedback circuit is adapted to actively drive its associated electrode via a feedback signal so as to maintain the voltage of its associated electrode at a substantially fixed bias. Each feedback circuit may include an amplifier having a first input terminal coupled to the sensing electrode and a second input terminal coupled to receive a biasing voltage. The output signal of the amplification circuit is used to generate the feedback signal that actively drives the sensing electrode. The biasing voltage may be the ground potential. | 2008-12-25 |
20080315909 | Method of detecting a malfunction of an encoder for a vehicle drive system - A method of detecting a malfunction of an encoder used in a vehicle drive system includes determining an error of a motor speed based on an estimated motor speed, wherein the estimated motor speed is a function of measured current over a predetermined interval of time. The method further includes determining a maximum allowable error of the motor speed at the measured current. Yet further, the method includes comparing the error of the motor speed with the maximum allowable error of the motor speed, thereby detecting the malfunction of the encoder. | 2008-12-25 |
20080315910 | INDICATOR ROD - An indicator rod responsive to environmental variations is disclosed. A handle defines an elongated cavity having a linear axis. A pin is received within the cavity substantially along the linear axis, and is adapted to rotate about the linear axis. An indicator member is secured to the pin such that the pin extends in a substantially non-parallel orientation from the indicator member. | 2008-12-25 |
20080315911 | Receiver circuit - In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved. | 2008-12-25 |
20080315912 | Logic circuit including a plurality of master-slave flip-flop circuits - According to an aspect of an embodiment, a logic circuit includes a first master latch included in one of the master-slave flip-flop circuits, the first master latch having a first scan data input for receiving scan data, the first master latch latching the scan data and outputting latched scan data, a second master latch included in another of the master-slave flip-flop circuits, the second master latch having a second scan data input operatively connected to receive an output of the first master latch, the second master latch latching the scan data inputted into the second scan data input and outputting latched scan data and a slave latch included in one of the master-slave flip-flop circuits, the slave latch having a scan data input operatively connected to receive an output of the second master latch. | 2008-12-25 |
20080315913 | Apparatus for measuring on-die termination (ODT) resistance and semiconductor memory device having the same - An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The pull-up signals are enabled in response to the decoding signals and the first test mode signal, and the pull-down signals are enabled in response to the decoding signals and the second test mode signal. The driver receives the pull-up signals and the pull-down signals to drive a data terminal. At least one of the decoding signals is enabled by a mode register set (MRS) for setting an ODT mode. | 2008-12-25 |
20080315914 | Data transmission device and method thereof - A data transmission device may include a transmission chip, a plurality of reception chips and/or a pair of transmission lines. The transmission chip may transmit data and the reception chips may receive the data from the transmission chip. One of the plurality of reception chips may provide a corresponding terminal resistance when it receives the data. The transmission lines may be coupled between the transmission chip and the reception chips, and the transmission lines may have a daisy-chain configuration. Therefore, a data transmission device may provide a fixed terminal resistance in impedance matching and increase a transmission speed. | 2008-12-25 |
20080315915 | Semiconductor device - When a plurality of output buffer circuits are provided, chip layout size, power consumption, and number of pins of an LSI circuit are reduced. A voltage generation circuit generates reference voltages corresponding respectively to the output buffer circuits. A comparison circuit compares the reference voltages with an output voltage of a dummy buffer circuit. A counter counts a clock signal until a comparison result of the comparison circuit matches. The dummy buffer circuit adjusts output impedance corresponding respectively to the output buffer circuits based on a count value of the counter. Adjustment value holders hold respective count values when a comparison result of the comparison circuit, obtained based on respective corresponding reference voltages, matches. The output buffer circuits respectively adjust output impedances based on respectively held count values. | 2008-12-25 |
20080315916 | CONTROLLING MEMORY DEVICES THAT HAVE ON-DIE TERMINATION - A memory controller for controlling integrated circuit memory devices that have on-die termination. The memory controller includes an output driver to output a first data signal onto a data line, and termination control circuitry to output termination control signals to integrated circuit memory devices coupled to the data line. The termination control signals control coupling and decoupling of termination elements to the data line according to which of the plurality of integrated circuit memory devices is selected to receive the first data signal. In particular, the termination control signals specify coupling a termination element having an impedance indicated by a first termination value to the data line within one of the plurality of integrated circuit memory devices selected to receive the first data signal, and wherein the termination control signals further specify coupling a termination element having an impedance indicated by a second termination value to the data line within at least one other of the plurality of integrated circuit memory devices. | 2008-12-25 |
20080315917 | Programmable computing array - Methods, devices, and systems for programmable computing arrays have been described. One or more embodiments include programming both a first and a second floating gate of a combined memory and logic element to one of at least two states, wherein programming the floating gates to one of the at least two states causes the combined memory and logic element to operate as a first logic gate type. One or more embodiments also include programming both the first and the second floating gates of the combined memory and logic element to another of the at least two states, wherein programming the floating gates to another of the at least two states causes the combined memory and logic element to operate as a second logic gate type, the second logic gate type being different from the first logic gate type. | 2008-12-25 |
20080315918 | Thin film transistor logic - A thin-film logic circuit, which can be fabricated entirely of TFTs of the same conductivity type, includes a logic stage connected to a supply voltage and a level shifter connected to a wider voltage range provided by the supply voltage and ground. The logic circuit produces output signals with full rail-to-rail signal range from ground to the supply voltage and can implement or include a basic logic component such as an inverter, a NAND gate, or a NOR gate or more complicated circuits in which many basic logic components are cascaded together. Such logic circuits can be fabricated directly on flexible structures or large areas such as in flat panel displays. | 2008-12-25 |
20080315919 | LOGIC STATE CATCHING CIRCUITS - A number of logic state catching circuits are described which use a logic circuit with a first input, a second input, and an output. The logic circuit is configured to respond to a change in state of a data value coupled to the first input causing a representative value of the data value to be generated on the output. The second input receives a latched version of the data value to hold the representative value on the output after the data value has returned to its original state. A latching element is configured to respond to the change in state of the data value by latching the data value and to couple the latched version of the data value to the second input. A reset element is configured to respond to a change in state of a clock input by resetting the latching element. | 2008-12-25 |
20080315920 | SIGNAL ENCODER AND SIGNAL DECODER - A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal. | 2008-12-25 |
20080315921 | DIGITAL FREQUENCY DETECTOR AND DIGITAL PHASE LOCKED LOOP USING THE DIGITAL FREQUENCY DETECTOR - A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information. | 2008-12-25 |
20080315922 | COMPENSATED COMPARATOR FOR USE IN LOWER VOLTAGE, HIGHER SPEED NON-VOLATILE MEMORY - Briefly, in accordance with one or more embodiments, an offset compensated comparator is capable of being utilized for higher speed, lower voltage use. The comparator comprises a cross-coupled latch comprising n type devices and p type devices. The threshold mismatch between n type devices is captured on capacitors coupled to the gates of the n type devices to capture the mismatch between the devices. After the threshold mismatch is captured, the comparator can be used as a typical cross coupled latch. | 2008-12-25 |
20080315923 | COMPENSATING A PUSH-PULL TRANSMIT DRIVER - An interface such a PCI-E interface may comprise a transmitter and a compensation circuit. In one embodiment, the transmitter may comprise a transmit driver, which may use a push-pull configuration. The transmit driver may require stable voltages such as (Vdd/2+0.25) and (Vdd/2−0.25) Volts. The compensation circuit may comprise a voltage generator circuit and a dummy driver circuit. The dummy driver may be a replica of the transmit driver. A correction module may generate correction factors based on the deviation of the voltages generated by the dummy driver from the voltages generated by the voltage generator. The voltages provided to the transmit driver are corrected based on the correction factors to compensate for the deviation. | 2008-12-25 |
20080315924 | COMPARATOR WITH LOW OFFSET VOLTAGE - A differential comparator is provided. The comparator receiving two differential signals and generating a comparison result represented by an output signal on one of two output terminals respectively on two current paths. The comparator comprises two pairs of latch transistors respectively disposed on the two current paths and two pairs of input transistors respectively disposed on the two current paths, wherein gates of the latch transistors on one of the current paths are commonly coupled to the output terminal between the latch transistors on the other current path, gates of the input transistors on one of the current paths respectively receives an input signal of one of the differential signals and a reference signal of the other differential signal and each of the input transistors is disposed between the output terminal and one of the latch transistors on the current path thereof. | 2008-12-25 |
20080315925 | ISOLATOR CIRCUIT INCLUDING A VOLTAGE REGULATOR - An apparatus includes a regulator circuit that generates a voltage in response to an input current being supplied to an input terminal and functional circuitry, powered by the voltage generated by the regulator circuit. The functional circuitry, e.g., an oscillator, generates a signal using the generated voltage, the signal indicative that the current is being supplied to the apparatus. The signal can be provided over an isolation link to provide a control signal for controlling a high voltage driver circuit. | 2008-12-25 |
20080315926 | Frequency Synthesizer - Disclosed is a frequency synthesizer. The frequency synthesizer includes a phase frequency detector for generating an up signal and a down signal by detecting frequency and phase differences between a reference signal and a comparison signal, a charge pump for outputting a control signal according to the up signal and the down signal, a voltage controlled oscillator for outputting an oscillation output signal according to the control signal, a duty cycle correction circuit connected with the voltage controlled oscillator to compensate for a duty cycle of the oscillation output signal, and a feedback divider for providing the comparison signal to the phase frequency detector by dividing a frequency of the oscillation output signal. | 2008-12-25 |
20080315927 | FREQUENCY ADJUSTING APPARATUS AND DLL CIRCUIT INCLUDING THE SAME - A frequency adjusting apparatus includes a frequency control signal generating unit that generates a multi-bit frequency control signal, which is changed in level bit by bit, in response to a reference clock signal, and a frequency adjusting unit that adjusts the frequency of the reference clock signal in response to the multi-bit frequency control signal. | 2008-12-25 |
20080315928 | DIGITAL PHASE LOCKED LOOP WITH DITHERING - An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels. | 2008-12-25 |
20080315929 | AUTOMATIC DUTY CYCLE CORRECTION CIRCUIT WITH PROGRAMMABLE DUTY CYCLE TARGET - A duty cycle correcting circuit for an integrated circuit memory automatically corrects the duty cycle of an input clock by measuring the relative difference between the high time and low time of the input signal and using this measurement to achieve a same-frequency, duty cycle adjusted output signal. The duty cycle correcting circuit includes a duty cycle adjust circuit that uses two series-connected N-channel transistors to control the pull-up slew rate of a signal and another N-channel transistor to control the pull-down slew rate of the same signal, two dual-slope integrator circuits, and input and output signal buffering. | 2008-12-25 |
20080315930 | DUTY CYCLE ERROR CALCULATION CIRCUIT FOR A CLOCK GENERATOR HAVING A DELAY LOCKED LOOP AND DUTY CYCLE CORRECTION CIRCUIT - A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes. | 2008-12-25 |
20080315931 | Semiconductor integrated circuit having active and sleep modes and non-retention flip-flop that is initialized when switching from sleep mode to active mode - A semiconductor integrated circuit has an active mode and a sleep mode. The semiconductor integrated circuit is constructed by alternately connecting a plurality of combinational logic circuits and a plurality of flip-flops. The flip-flops include a retention flip-flop that is supplied with electric power and retains the data in the sleep mode, and a non-retention flip-flop that is not supplied with electric power during the sleep mode. The non-retention flip-flop includes an initializing circuit that initializes the non-retention flip-flop when the semiconductor integrated circuit is switched from the sleep mode to the active mode. | 2008-12-25 |
20080315932 | PULSED STATE RETENTION POWER GATING FLIP-FLOP - A flip-flop includes a functional latch and a retention latch. The functional latch is configured to maintain a logic state of the flip-flop in a power-up mode and the retention latch is configured to maintain the logic state of the flip-flop in a power-down mode. The retention latch is selectively coupled to the functional latch and the retention latch is configured to maintain the logic state in the power-down mode irrespective of a level of an associated clock signal when the power-down mode is entered. A clock pulse that clocks the flip-flop is derived from the associated clock signal. | 2008-12-25 |
20080315933 | PULSE SYNTHESIS CIRCUIT - A high-level period of each of n first pulse signals partially or wholly overlaps a period during which all of n second pulse signals are at the low level. A high-level period of each of the n second pulse signals partially or wholly overlaps a period during which all of the n first pulse signals are at the low level. Each of n first drive transistors includes a source connected to a ground node, a drain connected to a first node, and a gate receiving a corresponding one of the first pulse signals. Each of n second drive transistors includes a source connected to the ground node, a drain connected to a second node, and a gate receiving a corresponding one of the second pulse signals. A current mirror circuit allows a current corresponding to a current flowing through the second node to flow through the first node. | 2008-12-25 |
20080315934 | Integrated Circuit Comprising a Mixed Signal Single-Wire Interface and Method for Operating the Same - The invention relates to an integrated circuit ( | 2008-12-25 |
20080315935 | Digital Acquistion Device for an Amplitude Modulation Signal - The invention relates to a digital acquisition device for an amplitude modulation signal of a carrier. The acquisition device digitally acquires a useful signal. The useful signal modulates the amplitude of a carrier HF | 2008-12-25 |
20080315936 | Level Shifting - Various aspects are described, such as a method for operating a level shifter, in which the level shifter is coupled to a first supply voltage and a second supply voltage different from the first supply voltage. The method may include detecting whether the first supply voltage is present, and decoupling an input of the level shifter from an output of the level shifter responsive to detecting that the first supply voltage is not present. | 2008-12-25 |
20080315937 | APPARATUS FOR GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage. | 2008-12-25 |
20080315938 | DRIVING CIRCUIT FOR SWITCHING ELEMENTS - A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of a switching terminal, are obtained differentially and integrated, and, in case these pulse signals equal or exceed stipulated integrated values, are transmitted as regular control signals controlling the on/off state. | 2008-12-25 |
20080315939 | ANTI-LOGARITHMIC AMPLIFIER DESIGNS - An anti-exponential amplifier produces an output signal that is an exponential/anti-logarithmic function of an input signal. The amplifier includes three function generators and a low-pass filter. The first function generator produces a periodic exponential waveform based upon a resistor-capacitor time constant, with the magnitude of the periodic exponential waveform exponentially increasing to a maximum value in each period. A second function generator produces a ramp waveform from the exponential waveform. The ramp waveform has a period and maximum amplitude substantially equal to those of the exponential signal. The third function generator produces a hybrid waveform with a first portion and a second portion, with the duration of the first period determined in response to the ramp waveform. A low pass filter produces the anti-logarithmic output signal as a function of the hybrid waveform. The resulting amplifier could be useful in a brightness or other parameter control for a display. | 2008-12-25 |
20080315940 | Mixing device for plural digital data having different sampling rates - A method of mixing a first digital data having a first sampling rate and a second digital data having a second sampling rate includes converting the second digital data, by using a first coefficient obtained by multiplying a sampling coefficient with a volume coefficient for the second digital data, to produce a converted second digital data which has the same sampling coefficient as the first digital data, converting the first digital data, by using a volume coefficient for the first digital data, to produce a converted first digital data and mixing the converted second digital with the converted first digital data. | 2008-12-25 |
20080315941 | Flat Substrate Having an Electrically Conductive Structure - The description is of a flat substrate with an electrically conductive structure integrated inside the flat substrate or applied to a surface of the flat substrate and/or with a technically improved surface. | 2008-12-25 |
20080315942 | Vt Stabilization of TFT's In OLED Backplanes - In a method of reducing or undoing progressive threshold shift in a thin-film-transistor (TFT) circuit, first and second voltages applied to source and gate terminals of a first transistor cause the first transistor to conduct and apply the first voltage to the gate terminal of the second transistor. The first voltage applied to the gate terminal of the second transistor coacts with a reference voltage coupled to the source terminal of the second transistor via an LED element to cause the second transistor to not conduct whereupon the LED element does not receive electrical power. After a first predetermined period of time sufficient to reduce or undo a progressive threshold shift in the second transistor, the application of the first voltage to the gate terminal of the second transistor is terminated. | 2008-12-25 |
20080315943 | Anti-Jitter Circuits - An anti jitter circuit for reducing time jitter in an input pulse train comprises an integrator, a DC removal circuit and a comparator. The anti jitter circuit also has a feedback loop effective to suppress phase deviation of the output pulse train in response to jitter. | 2008-12-25 |
20080315944 | SPATIALLY-FED HIGH POWER AMPLIFIER WITH SHAPED REFLECTORS - A spatially-fed high-power amplifier comprises one or more shaped reflectors to reflect an initial wavefront, and an active array amplifier to amplify the reflected wavefront to generate a high-power planar wavefront. The shaped reflectors provide the reflected wavefront with substantially uniform amplitude when incident on the active array amplifier. The initial wavefront may be a substantially spherical wavefront, and the shaped reflectors may compensate for any amplitude taper of the initial wavefront to provide the reflected wavefront with substantially uniform amplitude components for incident on the active array amplifier. In some embodiments, the shaped reflectors may also contour the illumination to fit the shape of the active array amplifier to help minimize spillover. | 2008-12-25 |
20080315945 | Arrangement for Amplifying a Pwm Input Signal - A pulse-width modulation (PWM) amplifier comprises a feedback loop for reshaping the pulses of the PWM input signal to correct timing and amplitude errors in the class D output stage of the amplifier by means of an error correction signal. In such an amplifier the feedback loop gives a substantial amount of base-band noise when the pulse-period of the PWM input signal is not constant, which is especially the case when the PWM signal originates from a noise shaper. The invention reduces this noise by modifying the reshaping gain of the amplifier with a pulse-period proportional signal. | 2008-12-25 |
20080315946 | Combiner-Less Multiple Input Single Output (MISO) Amplification with Blended Control - Multiple-Input-Single-Output (MISO) amplification and associated VPA control algorithms are provided herein. According to embodiments of the present invention, MISO amplifiers driven by VPA control algorithms outperform conventional outphasing amplifiers, including cascades of separate branch amplifiers using conventional power combiner technologies. MISO amplifiers can be operated at enhanced efficiencies over the entire output power dynamic range by blending the control of the power source, source impedances, bias levels, outphasing, and branch amplitudes. These blending constituents are combined to provide an optimized transfer characteristic function. | 2008-12-25 |
20080315947 | Controller-Assisted Method and Controller-Assisted Device for Determining a Characteristic of a Compensation Member in a Level Control Circuit - In a controller-assisted device for determining a characteristic of a compensation element in a level control circuit, the compensation element is serially mounted inside the level control circuit for a high-frequency signal (SHF) in a signal channel with respect to said signal channel. The characteristic of the compensation element has a characteristic which the inverse of the non-linear transmission characteristic of the signal channel in the event of ideal compensation. In the controller-assisted method for the determination of a characteristic of the compensation element in a level control circuit, each ordinate value of the characteristic of the compensation element arises, in the event of a bridged compensation element, from the corrective signal value (P | 2008-12-25 |
20080315948 | Circuit architecture having differential processing for use in half bridges and full bridges and methods therefore - Circuit architecture is disclosed that includes one or more half bridges, the one or more half bridges including signal processing circuitry including first and second inputs and one or more outputs. The circuit architecture also includes a driver stage coupled to the one or more outputs of the signal processing circuitry and configured to create at least one output, one of the at least one outputs suitable to couple to a load. The circuit architecture further includes a first feedback loop coupling the at least one output of the driver stage to a first input of the signal processing stage, and includes a second feedback loop coupling the at least one output of the driver stage to a second input of the signal processing stage, where signals on the first and second feedback loops have inverted polarity. Methods and computer-readable media are also disclosed. | 2008-12-25 |
20080315949 | VARIABLE GAIN AMPLIFIER INSENSITIVE TO PROCESS VOLTAGE AND TEMPERATURE VARIATIONS - An improved VGA design offering a purely ratiometric mechanism for controlling gain by current-steering. A control loop delivers a reference voltage to a control amplifier that steers current and match the common mode output voltage (CMOV) with said predefined reference voltage. The VGA is designed so that, although the absolute gain varies over process, voltage, and temperature (PVT), the gain steps retain their values. Moreover, a method for controlling the gain in a VGA in a way that is insensitive to PVT is also disclosed. First, a voltage representing the required gain of the VGA in injected to the outputs of the VGA. Then, the CMOV of the VGA is sampled. Finally, the CMOV is subtracted by a predefined reference voltage and is fed back as bias to bases of the transistors of the VGA, thus controlling it gain, until the CMOV and the reference voltage become equal. | 2008-12-25 |
20080315950 | Integrated Circuit Amplifiers Having Switch Circuits Therein that Provide Reduced 1/f Noise - Integrated circuit devices include a pair of field effect transistors having shared source terminals, shared drain terminals and shared gate terminals, which may be treated herein as being electrically coupled in parallel. A switch circuit is also provided, which is configured to drive a body terminal of a first one of the pair of field effect transistors with an alternating sequence of first and second unequal body voltages. This alternating sequence is synchronized with a first clock signal. The switch circuit is also configured to drive a body terminal of a second one of the pair of field effect transistors with an alternating sequence of third and fourth unequal body voltages, which is synchronized with a second clock signal. The first and third body voltages may have equivalent magnitudes and the second and fourth body voltages may have equivalent magnitudes. The first and second clock signals may have 50% duty cycles and may be 180 degrees out-of-phase relative to each other. | 2008-12-25 |
20080315951 | CLASS AB DIFFERENTIAL AMPLIFIER WITH OUTPUT STAGE COMMON MODE FEEDBACK - A differential amplifier includes an output stage, a first common mode feedback circuit; and a current source. The output stage includes first and second complimentary output terminals. The first common mode feedback circuit is operable to determine an average voltage across the first and second complimentary output terminals. The current source is coupled to the output stage, and the common mode feedback circuit is operable to control the current source based on the average voltage. A method includes determining an average voltage across a positive output terminal and a negative output terminal of a differential amplifier output stage and controlling current injected into the output stage based on the average voltage. | 2008-12-25 |
20080315952 | POWER AMPLIFIER SYSTEM PROVIDED WITH IMPROVED PROTECTION FUNCTION - A power amplifier system including a power terminal, a ground terminal, an output terminal, a ripple terminal, a control terminal to which a control signal is supplied from outside, a power amplifier circuit connected between the power terminal and the ground terminal, a negative potential detection circuit connected to the output terminal, and a bias circuit which supplies a bias voltage to the power amplifier circuit, and a bias start-up circuit controlling the startup operation of the bias circuit. | 2008-12-25 |
20080315953 | Variable Gain Mixer - There is provided a variable gain mixer capable of controlling a gain at a low source voltage in a wide range without additional current consumption. | 2008-12-25 |
20080315954 | Integrated Power Amplifier - Methods to implement low cost, high efficiency, low loss power combiner with novel matching circuits are disclosed. A narrow band power combiner enables a high power and high efficiency radio frequency power amplifier to be realized using multiple low voltage CMOS transistors or micro power amplifiers. The power combiner may be printed on a package substrate and realized either using single layer substrate through edge coupling or multiple layers substrate through broadside coupling. The micro power amplifiers may be fabricated using low voltage CMOS technology and electrical connections between the outputs from the micro power amplifiers and the power combiner may be provided through stud bumps in a flip chip technology. With the tunable matching circuits, the present invention allows the narrow band power combiner to be tuned to different frequencies. | 2008-12-25 |
20080315955 | CLASS L AMPLIFIER - A new Class L amplifier which dynamically switches between multiple pairs of power rails, and has the ability to select the most advantageous combination of rails for the minimization of power dissipation in the amplifier. In one embodiment, a bridged amplifier system includes two Class L amplifiers to drive a load. | 2008-12-25 |
20080315956 | Saturation Handling - Saturation handling for preventing a power amplifier from going into a saturation condition is disclosed. | 2008-12-25 |
20080315957 | ULTRA-WIDEBAND LOW NOISE AMPLIFIER AND AMPLIFICATION METHOD THEREOF - An ultra wideband low noise amplifier (UWB LNA) and amplification method thereof, providing a substantially achieved bandwidth extension by pole-zero cancellation and utilized to transform input impedance matching up to 50 ohm for gaining low noise figure. The ultra-wideband low noise amplifier is composed of a capacitive-feedback amplifier, a resistive-feedback amplifier, an inductive-feedback amplifier, and a buffer amplifier. | 2008-12-25 |
20080315958 | PHASE-LOCKED LOOP CIRCUIT, PHASE-LOCKED LOOP CONTROL APPARATUS, AND PHASE-LOCKED LOOP CONTROL METHOD - According to one embodiment, a phase-locked loop circuit comprises a phase difference detection unit which detects a phase error between a reproduced binary data and extracted clock and generates phase error pulse signals each having an amplitude corresponding to the phase error, a phase sifter sensitivity adjusting unit which generates a first adjustment pulse signal produced by adjusting the phase error pulse signal, and a loop filter unit which generates a pulse train signal for feedback control to generate the extracted clock from the first adjustment signal, wherein the phase shifter sensitivity adjusting unit comprises a first pulse doubler unit which generates an expanded pulse signal which doubles a time width of the phase error pulse signal, and a first amplifying unit which amplifies the amplitude of the expanded pulse signal and generates the first adjustment pulse signal. | 2008-12-25 |
20080315959 | Low Power All Digital PLL Architecture - A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals. | 2008-12-25 |
20080315960 | Digital Phase Locked Loop with Gear Shifting - An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A programmable filter is connected to receive the phase error samples and connected to provide a filtered output having a gain and a phase margin to the controllable oscillator. The programmable filter includes a proportional loop gain control having a programmable loop gain coefficient (alpha-α) and an integral loop gain control having a programmable loop gain coefficient (rho-ρ). Alpha and rho are configured to be programmatically changed simultaneously and are selected such that the gain is changed and the phase margin remains substantially unchanged | 2008-12-25 |
20080315961 | Quality of Phase Lock and Loss of Lock Detector - A system, apparatus and method for providing phase lock conditions detection such as a quality of phase lock and loss of lock detection. A phase locked loop (PLL) circuit may comprise an oscillator for providing an output frequency, as well as a detector for detecting the output frequency of the oscillator, comparing the output frequency with a reference signal and outputting a first and second signals as a function of the comparison. The PLL circuit may further include an amplifying circuit for receiving the first and second signals, monitoring a deviation of the first and second signals from a predetermined threshold, and generating a third signal as a function of the deviation. The PLL circuit may further comprise a comparison circuit for receiving the third signal, comparing the third signal to a window threshold, and generating a fourth signal as a function of the comparison. The window threshold may be a function of apriori knowledge of at least one loop variable, wherein the window threshold is set based on a predetermined loop variable. An alarm circuit may receive the fourth signal and provide an alarm. | 2008-12-25 |
20080315962 | APPARATUS FOR PROVIDING OSCILLATOR FREQUENCY STABILITY - An apparatus for providing oscillator frequency stability is disclosed. The apparatus includes an internally ovenized oscillator module having an oscillator and an inner heater to maintain the oscillator at a first temperature during operation. The apparatus also includes a thermally conductive cover for forming a first compartment to contain the internally ovenized oscillator module along with multiple heaters. The heaters are in thermal communication with the thermally conductive cover and the substrate to form an oven to keep the internally ovenized oscillator module at a stable second temperature during operation. In addition, the apparatus includes a thermally insulative cover for forming a second compartment to contain the first compartment. | 2008-12-25 |
20080315963 | DIRECT DIGITAL INTERPOLATIVE SYNTHESIS - A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider. | 2008-12-25 |
20080315964 | Voltage controlled oscillator using tunable active inductor - A tunable active inductor and a voltage controlled oscillator (VCO) are provided. The tunable active inductor includes a first current source coupled to a power source, a first metal-oxide semiconductor (MOS) transistor including a drain coupled to the first current source and a gate coupled to a first bias voltage, a second MOS transistor including a drain coupled to the power source and a gate coupled to the drain of the first MOS transistor, the gate of the second MOS and the drain of the first MOS being coupled to a second bias voltage, a resonator coupled to a source of the second MOS transistor, and a second current source coupled to the resonator. The VCO employs the tunable active inductor to freely vary the oscillation range of the VCO in a high frequency band. | 2008-12-25 |
20080315965 | THIRD OVERTONE CRYSTAL OSCILLATOR - A third overtone crystal oscillator has an oscillator IC and a crystal element accommodated in a container. The IC includes transistor grounded at its emitter, a first capacitor connected to the base of the transistor via a DC blocking capacitor and to the ground potential, and a second capacitor connected between the collector of the transistor and the ground potential. Both ends of the crystal element are connected to non-grounded ends of the first and second capacitors, respectively. A spiral inductor forming a parallel resonant circuit together with the first capacitor, is provided at the container, using a printing process, for example, being independent of the IC. The parallel resonant frequency of the parallel resonant circuit is set higher than the oscillation frequency at the fundamental wave of the crystal element, and lower than the oscillation frequency at the third overtone of the crystal element. | 2008-12-25 |
20080315966 | OSCILLATOR - An oscillation circuit induces a first inverter, a second inverter, a first inductive load, a second inductive load and a capacitive load. A first inverter and a second inverter receive a first signal and a second signal, and invert the first and the second signal to output a first inverted signal and a second inverted signal respectively. An output end of the first inverter is electrically connected to a first inductive load, and an output end of the second inverter is electrically connected to a second inductive load. Further, a capacitive load is electrically connected to the output end of the first inverter and the output end of the second inverter, so as to receive the first and the second inverted signal respectively. The capacitance of the capacitive load changes with a control signal. | 2008-12-25 |
20080315967 | VARIABLE PULSE-WIDTH MODULATION WITH ZERO D.C. AVERAGE IN EACH PERIOD - Pulse-width modulation (PWM) finds wide use in many applications including motor control, communication systems, music synthesizers, power supplies, class-D and digital amplifiers, among others. The Fourier series expansion of each period of a pulse waveform includes an additive term that is a function of the pulse width in that period. As the pulse width is varied, this additive term varies, which can be problematic in many applications. In an embodiment, a single-pulse per period pulse width modulated waveform comprising a zero d.c. term in each period regardless of pulse width is generated. In various realizations these waveforms may be generated by electronic circuitry without the use of capacitive coupling or may be generated by algorithms. Further aspects include “through-zero” pulse width modulation and zero-centered asymmetric triangle waveforms and use in instrumentation for measurement of a phase angle of an exogenous system or phenomena. | 2008-12-25 |
20080315968 | HIGH-FREQUENCY COMPOSITE COMPONENT - A high-frequency composite component for selectively switching a GSM-system signal path and a DCS-system signal path for a signal transmitted to or received from an antenna terminal by a diplexer. Transmission-side input terminals and reception-side balanced output terminals to be switched by high-frequency switches are included in the GSM and the DCS systems. Matching elements include inductors and capacitors that are inserted between the reception-side balanced output terminals and the output side of surface acoustic wave filters. | 2008-12-25 |
20080315969 | Waveguide Correlation Unit and a Method for its Manufacturing - A waveguide correlation unit and a method for manufacturing the same are disclosed. The waveguide correlation unit includes stacked first and second waveguide plates having an identical configuration, wherein a central coupling plate is disposed therebetween. Due to the identical configuration of the first and second waveguide plates, mechanical uncertainties may significantly be reduced, since both plates may be formed in a common process without the repositioning activities during the manufacturing process. | 2008-12-25 |
20080315970 | Filter with a Fuse, for Use in a Lamppost - It is disclosed that a lamppost ( | 2008-12-25 |
20080315971 | Power Line Data Signal Attenuation Device and Method - A device and method for attenuating high frequency signals on a power line carrying power is provided. In one embodiment the device may include a toroid shaped core formed of magnetically permeable material and having an inner surface to be disposed substantially around the entire circumference of the power line and a winding formed of a conductor that encircles the toroid. The conductor may include a first spiral coil comprised of a plurality of insulated loops such as concentric loops. The first coil is configured to act as an impedance to high frequency signals traversing the conductor and to allow signals below one hundred hertz to traverse the conductor substantially unimpeded to thereby prevent saturation of the core by the power carried by the power line. | 2008-12-25 |
20080315972 | Acoustic Wave Transducer and Filter Comprising Said Transducer - A transducer includes an acoustic track in which an acoustic wave can be propagated, the acoustic track having a transversal fundamental mode, the acoustic track being subdivided in a transversal direction into an excitation area and two peripheral areas. The transducer also includes a first outside area and a second outside area bordering the acoustic track such that the acoustic track is arranged in the transversal direction between the first and second outside area. The transducer also includes peripheral areas configured such that the longitudinal phase velocity v | 2008-12-25 |
20080315973 | SURFACE ACOUSTIC WAVE FILTER, BOUNDARY ACOUSTIC WAVE FILTER, AND ANTENNA DUPLEXER USING SAME - A surface acoustic wave filter includes a piezoelectric substrate including lithium niobate, a series resonator including a first interdigital transducer electrode provided on the piezoelectric substrate, and a parallel resonator including a second interdigital transducer electrode provided on the piezoelectric substrate and being electrically connected to the series resonator. An apodized weighting factor of the first interdigital transducer electrode is smaller than an apodized weighting factor of the second interdigital transducer electrode. This surface acoustic wave filter has a small loss. | 2008-12-25 |
20080315974 | MECHANICAL TEMPERATURE-COMPENSATING DEVICE FOR A PHASE-STABLE WAVEGUIDE - The present invention relates to a mechanical compensating device for a waveguide ( | 2008-12-25 |
20080315975 | SIGNAL TRANSMISSION CIRCUIT, IC PACKAGE, AND MOUNTING BOARD - Provided is a signal transmission circuit capable of realizing the same effects as those in a conventional manner that employs a complicated circuit by using no complicated circuit, that is, by a simple circuit. The signal transmission circuit includes: a transmission path having a first impedance; a terminating resistor having a predetermined resistance; a transmission path having a second impedance, which is connected to the transmission path and the terminating resistor, the second impedance being higher than both of the first impedance and the predetermined resistance; and an input buffer for receiving a signal at a connection portion of the transmission path and the transmission path. | 2008-12-25 |
20080315976 | SYSTEM AND METHOD OF ASSEMBLING A TRAPPED ACOUSTIC WAVE SYSTEM - Embodiments of the present invention provide a trapped acoustic wave system and a method of assembling such a system. The system may include a substrate having an acoustic wave cavity and a transducer mounted on the substrate. The transducer is configured to resonate the acoustic wave cavity. An acoustically transmissive adhesive secures a first portion of the transducer to the substrate. An additional adhesive, which is separate and distinct from the acoustically transmissive adhesive, anchors at least a second portion of the transducer to the substrate. | 2008-12-25 |
20080315977 | Low loss RF transmission lines - A transmission structure having high propagation velocity and a low effective dielectric loss. The structure comprises a dielectric, a first reference conductor disposed below the dielectric, a signal conductor disposed above the dielectric, and a second reference conductor disposed over the signal conductor. The second reference conductor has a recess portion facing the signal conductor, the recess portion defining a gap between the second reference conductor and the signal conductor. The gap may be filled with air which has a relative dielectric constant approximately equal to one (1). Because of the physical and dielectric constant characteristics of the gap, the structure concentrates an electric field in the gap resulting in an effective dielectric constant approximately (approaching) one (1) and an effective dielectric loss approximately equal to zero (0). Thus, the structure exhibits a propagation velocity approximately equal to the speed of light. | 2008-12-25 |
20080315978 | METHOD AND APPARATUS FOR NON-CONDUCTIVELY INTERCONNECTING INTEGRATED CIRCUITS - A method and apparatus for constructing, repairing and operating modular electronic systems utilizes peripheral half-capacitors (i.e., conductive plates on the outside of the modules) to communicate non-conductively between abutting modules. Such systems provide lower cost, improved testability/reparability and greater density than conventional modular packaging techniques, such as printed circuit boards and multi-chip modules. The non-conductive interconnection technique of the invention can be applied to all levels in the packaging hierarchy, from bare semiconductor dies to complete functional sub-units. Numerous exemplary systems and applications are described | 2008-12-25 |
20080315979 | WAVEGUIDE QUICK DISCONNECT CLAMP - A waveguide quick disconnect clamp includes a first arm and a second arm, both arms having a first end, a second end, and a jaw pivotally connected to the second end. Each of the first and second arm jaws has a generally flat engaging face defining two generally parallel elongated sections and a waveguide receiving recess therebetween. The second arm second end is pivotally connected to the first arm at a position intermediate the first arm first and second ends, and a threaded nut is pivotally connected to the first arm first end. The waveguide quick disconnect clamp also has an adjustment screw having a first end, a second end, and a threaded portion therebetween. The adjustment screw first end pivotally engages the second arm at a point intermediate the second arm first and second ends, and the threaded portion of the screw engages the threaded nut. | 2008-12-25 |
20080315980 | MEMS MICRO-SWITCH ARRAY BASED ON CURRENT LIMITING ENABLED CIRCUIT INTERRUPTING APPARATUS - The present invention comprises a micro-electromechanical system (MEMS) micro-switch array based current limiting enabled circuit interrupting apparatus. The apparatus comprising an over-current protective component, wherein the over-current protective component comprises a switching circuit, wherein the switching circuit comprises a plurality of micro-electromechanical system switching devices. The apparatus also comprises a circuit breaker or switching component, wherein the circuit breaker or switching component is in operable communication with the over-current protective component. | 2008-12-25 |
20080315981 | HIGH VOLTAGE TRANSFORMER WITH HIGH MAGNETIC LEAKAGE AND DUAL HIGH VOLTAGE OUTPUT - The present invention relates to a high voltage transformer with high magnetic leakage and dual high voltage output, comprising a base and a core set, wherein the base contains a hollow support into which a first core of the core set pierces, and primary coils are wound on both sides of the hollow support, while a plurality of isolation channels is installed for winding first and second secondary coils on external sides of primary coils. First and second slots are opened between the primary coils and the first and second secondary coils respectively, and both slots cut into an internal through hole. When a second core of the core set is placed at one end of the hollow support, extensions at both ends of the second core go through both sides of the first core, together with first and second protrusive parts between the two extensions that are installed within the first and second slots and combined with the first core to form multiple magnetic paths. Then the magnetic path, formed by magnetic flux of the primary coils flowing from the first and second protrusive parts to the first core, is considered as a bypass to generate magnetic leakage, thus mitigating the coupling effect between primary coils and secondary coils and enhancing leakage inductance. Meanwhile, the creepage distance between primary coils and secondary coils is enlarged by design of first and second isolation plates on a protection cover to achieve the purpose of providing dual high voltage output from one high voltage transformer. | 2008-12-25 |
20080315982 | COUPLED-INDUCTOR CORE FOR UNBALANCED PHASE CURRENTS - An embodiment of a coupled-inductor core includes first and second members and first and second forms extending between the first and second members. The first form has a parameter (e.g., length) of a first value, and is operable to conduct a first magnetic flux having a first density that depends on the first value of the parameter. The second form is spaced apart from the first form, has the parameter (e.g., length) of a second value different from the first value, and is operable to conduct a second magnetic flux having a second density that depends on the second value of the parameter. Because two or more of the forms of such a core may have different values for the same parameter, the core may be suitable for use in a multiphase power supply where the currents through the phases are unbalanced. | 2008-12-25 |
20080315983 | Safety Device For Preventing Propagation in Fracture of Ceramic Element - The present invention relates to a safety device for preventing propagation when a ceramic element is failed. An angle is formed such that elastic terminals contacted at both faces of the ceramic element do not face each other and an elastic terminal of one lateral face of the ceramic element is formed without one leg so as not to be contacted with the ceramic element, and therefore when an unsustainable force is applied to the ceramic element by an excessive thermal stress or an excessive current caused by an external abnormal power supply is applied to the ceramic element, the ceramic element performs an immediate failure and thus a rapid cut-off capability of circuit. The upper case is provided with a receiving space for accommodating a ceramic element such that the ceramic element remains upright inside of the receiving space, or the ceramic element is mounted inside of an insulator such that the insulator supports an off-set force by a connection force of the elastic terminal to allow the ceramic element to remain upright. A wedge is formed integrally with the upper case so as to be contacted with the elastic terminal mounted at both sides of the upper case, which supports the elastic terminal, thereby supporting the elastic terminal. Even after the operation of the safety device, the scattered ceramic element is captured by the wall face of the receiving space inside of the upper case, thereby providing a capability of stable circuit cut-off. A case protrusion is formed at both lower portions of the upper case to which the ceramic element is mounted, thereby providing a gradient to allow the ceramic element to remain upright. The tab terminal and the elastic terminal are connected by means of a rivet or welding, and the elastic terminal is provided with an embossing to reinforce the elasticity of the elastic terminal material, thereby enabling to be replaced by a thinner elastic terminal and thus reduce the manufacturing cost. | 2008-12-25 |
20080315984 | Thermal Release - The invention relates to a thermal tripping device which is heated indirectly by means of a heating winding and which comprises a release strip made of thermostatic bimetal, a form memory alloy or similar. An insulating intermediate layer is arranged between the heating winding and the release strip and one of the ends of the heating winding is connected to a supply conductor. The heating winding is embodied in an identically meandering manner for all current intensities and is folded about the insulating intermediate layer. In order to modify the resistance of the heating winding for other current intensities, the discharge is connected to a wiring point between the ends of the heating windings. | 2008-12-25 |
20080315985 | MULTI-SWITCH CHASSIS - In a switch system L groups of the line switch elements are connectable to cables that include L links such that each of the L links within a cable connect to a switch element of a respective one of the L groups. Fabric switch elements are connected such that a fabric switch element is connected to the line switch elements of one of the group of line switch elements. | 2008-12-25 |
20080315986 | Use of Local User Interface in a Signal Processing Device - The present invention provides a method and system of controlling a plurality of signal processing devices from a first signal processing device, wherein the first signal processing device generates a signal representing an on-screen display, including enabling an on-screen display associated with a user interface for one of the plurality of signal processing devices at the first signal processing device, selecting a control feature of one of the plurality of signal processing devices and providing feedback at the user interface of one of the plurality of signal processing devices associated with the selected control feature. | 2008-12-25 |
20080315987 | System and Method for Controlling at Least One Device - System and method for controlling at least one device ( | 2008-12-25 |