52nd week of 2009 patent applcation highlights part 14 |
Patent application number | Title | Published |
20090315037 | COMPOUND SEMICONDUCTOR DEVICE AND ITS MANUFACTURE METHOD - A vertical type GaN series field effect transistor having excellent pinch-off characteristics is provided. A compound semiconductor device includes a conductive semiconductor substrate, a drain electrode formed on a bottom surface of the conductive semiconductor substrate, a current blocking layer formed on a top surface of the conductive semiconductor substrate, made of high resistance compound semiconductor or insulator, and having openings, an active layer of compound semiconductor burying the openings and extending on an upper surface of the current blocking layer, a gate electrode formed above the openings and above the active layer, and a source electrode formed laterally spaced from the gate electrode and formed above the active layer. | 2009-12-24 |
20090315038 | COMPOUND SEMICONDUCTOR ELEMENT RESISTIBLE TO HIGH VOLTAGE - A compound semiconductor element is provided which electrically connects an electrode | 2009-12-24 |
20090315039 | Trench MOS type silicon carbide semiconductor device - A trench MOS type SiC semiconductor device includes a first conductivity semiconductor substrate, a first conductivity drift layer on the substrate, a second conductivity base layer on the drift layer, a first conductivity source layer on the base layer, a stripe shaped trench reaching from the surface of the source layer to the drift layer and having a gate electrode via a gate oxide film, a second conductivity layer on the bottom of the trench, and a second conductivity type region thereon on across-the-width side walls of at least one end of the trench, electrically coupling the second conductivity layer with the base layer. The device allows a low on-resistance without newly forming an electrode connected to the second conductivity layer even in the case of a device in which the second conductivity layer has to be grounded. | 2009-12-24 |
20090315040 | WIDE BANDGAP DEVICE IN PARALLEL WITH A DEVICE THAT HAS A LOWER AVALANCHE BREAKDOWN VOLTAGE AND A HIGHER FORWARD VOLTAGE DROP THAN THE WIDE BANDGAP DEVICE - A method and device for protecting wide bandgap devices from failing during suppression of voltage transients. An improvement in avalanche capability is achieved by placing one or more diodes, or a PNP transistor, across the blocking junction of the wide bandgap device. | 2009-12-24 |
20090315041 | OPTICAL MEMBER AND METHOD FOR MANUFACTURING OF OPTICAL MEMBER - There is provided an optical member | 2009-12-24 |
20090315042 | OPTICAL MODULE AND OPTICAL PICKUP APPARATUS - An optical module includes: a base plate; a light emitting element mounted on the base plate; an integrated circuit element of the light receiving element built-in type mounted on the base plate by bonded wires and having a light receiving portion for receiving returning light originating from light emitted from the light emitting element; and a circuit board having a window for allowing light to pass therethrough and connected to the integrated circuit element in a state wherein the light receiving portion is exposed through the window. | 2009-12-24 |
20090315043 | ORGANIC LIGHT-EMITTING TRANSISTOR AND DISPLAY DEVICE - An organic light-emitting transistor having a source electrode layer; a drain electrode layer facing the source electrode layer; an organic light-emitting layer formed between the source electrode layer and the drain electrode layer; a semiconductor layer formed between the organic light-emitting layer and the source electrode layer; and a gate electrode layer deposited to face through a gate insulation film to one face of the source electrode layer opposite to the other face facing the drain electrode layer. The organic light-emitting transistor further comprises: a charge-carrier suppression layer formed between the organic light-emitting layer and the source electrode layer to have an aperture; and a relay region formed between the charge-carrier suppression layer and the source electrode layer to relay charge-carriers from the source electrode layer to the aperture. | 2009-12-24 |
20090315044 | ELECTRO-OPTIC DISPLAYS, AND COMPONENTS FOR USE THEREIN - An electro-optic display comprises a substrate ( | 2009-12-24 |
20090315045 | INTEGRATED SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME - An integrated compound semiconductor light-emitting-device capable of emitting light as a large-area plane light source, exhibiting excellent in-plane uniformity in an emission intensity is provided. The light-emitting-device comprising a plurality of light-emitting-units formed over a substrate, wherein the light-emitting-unit has a compound semiconductor thin-film crystal layer | 2009-12-24 |
20090315046 | GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, METHOD OF MANUFACTURING GROUP-III NITRIDE COMPOUND SEMICONDUCTOR LIGHT-EMITTING DEVICE, AND LAMP - The present invention provides a group-III nitride compound semiconductor light-emitting device having high productivity and good emission characteristics, a method of manufacturing a group-III nitride compound semiconductor light-emitting device, and a lamp. A method of manufacturing a group-III nitride compound semiconductor light-emitting device includes a step of forming on a substrate 11 a semiconductor layer made of a group-III nitride compound semiconductor including Ga as a group-III element using a sputtering method. The substrate 11 and a sputtering target are arranged so as to face each other, and a gap between the substrate 11 and the sputtering target is in the range of 20 to 100 mm. In addition, when the semiconductor layer is formed by the sputtering method, a bias of more than 0.1 W/cm | 2009-12-24 |
20090315047 | Warm white light-emitting diode and thin film and its red phosphor powder - The invention discloses a red phosphor powder which is based on strontium (Sr) aluminiate and using europium (Eu) as exciting agent, and is characterized by that its chemical equivalence formula is (SrO) | 2009-12-24 |
20090315048 | Optoelectronic Semiconductor Chip - An optoelectronic semiconductor chip ( | 2009-12-24 |
20090315049 | OPTICAL SEMICONDUCTOR ELEMENT MOUNTING PACKAGE, AND OPTICAL SEMICONDUCTOR DEVICE USING THE SAME - An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes. | 2009-12-24 |
20090315050 | SEMICONDUCTOR LIGHT EMITTING DEVICE - Disclosed is a semiconductor light emitting device. The semiconductor light emitting device comprises a first semiconductor layer, a second semiconductor layer, an active layer formed between the first semiconductor layer and the second semiconductor layer, a first reflective electrode on the first semiconductor layer to reflect incident light, and a second reflective electrode on the second semiconductor layer to reflect the incident light. | 2009-12-24 |
20090315051 | PHOTOELECTRIC SEMICONDUCTOR DEVICE CAPABLE OF GENERATING UNIFORM COMPOUND LIGHTS - A transparent layer and a phosphor layer are covered on the LED chip for increasing light emission efficiency and evenness of the LED. Based on angle-dependent emission strength of the LED chip, the phosphor layer is designed with different thickness or contains different phosphor powder concentration in different section. The lights emitted with different strength from different angle of the LED chip are transformed into uniform compound lights after passing through the phosphor layer that has different thickness or phosphor powder concentration. Micro structures capable of destroying the full reflection occurred on the incident lights are further configured on both the inner and outer surfaces of the phosphor layer to increase the light emission efficiency. | 2009-12-24 |
20090315052 | LIGHT EMITTING DIODE LIGHT SOURCE AND BACKLIGHT HAVING SAME - An LED light source includes an LED die and a transparent encapsulation. The LED die includes a die emitting surface. The transparent encapsulation includes a reflective surface and an encapsulation emitting surface. The LED die is encapsulated by the transparent encapsulation such that the die emitting surface faces the encapsulation emitting surface. The transparent encapsulation is generally convex albeit having a concave recessed portion. The recessed portion is aligned with the die emitting surface and shaped so as to increase an effect of total internal reflection of light rays generated by the light emitting diode die and incident thereon. | 2009-12-24 |
20090315053 | LIGHT EMITTING DEVICE - The present invention provides a light emitting device, comprising a first light emitting diode for emitting light in an ultraviolet wavelength region; at least one phosphor arranged around the first light emitting diode and excited by the light emitted from the first light emitting diode to emit light having a peak wavelength longer than the wavelength of the light emitted from the first light emitting diode; and at least one second light emitting diode for emitting light having a wavelength different from the peak wavelength of the light emitted from the phosphor. According to the present invention, there is provided a white light emitting device, wherein using a light emitting diode for emitting light different in wavelength from light that is ex-cititively emitted from the phosphor, an excitation light source, i.e., light in the ultraviolet region for exciting the phosphor is effectively used, thereby improving energy conversion efficiency and improving reliability. | 2009-12-24 |
20090315054 | Light emitting elements, light emitting devices including light emitting elements and methods of manufacturing such light emitting elements and/or devices - An emitting device including a first electrode, a second electrode spaced apart from the first electrode, an emitting pattern including a portion between the first electrode and the second electrode, and a block pattern including a portion between the emitting pattern and the first electrode and/or on a same level as the first electrode. | 2009-12-24 |
20090315055 | PHOTOELECTROCHEMICAL ROUGHENING OF P-SIDE-UP GaN-BASED LIGHT EMITTING DIODES - A method for photoelectrochemical (PEC) etching of a p-type gallium nitride (GaN) layer of a heterostructure, comprising using an internal bias in a semiconductor structure to prevent electrons from reaching a surface of the p-type layer, and to promote holes reaching the surface of the p-type layer, wherein the semiconductor structure includes the p-type layer, an active layer for absorbing PEC illumination, and an n-type layer. | 2009-12-24 |
20090315056 | SEMICONDUCTOR DEVICE PACKAGE - A semiconductor device package is provided. The semiconductor device package comprises a package body, a plurality of electrodes, a paste member, and a semiconductor device. The electrodes comprise a first electrode disposed on the package body. The paste member is disposed on the first electrode and comprises at least one of an inorganic filler and metal powder. The semiconductor device is die-bonded on the paste member. | 2009-12-24 |
20090315057 | LIGHT-EMITTING APPARATUS, SURFACE LIGHT SOURCE, AND METHOD FOR MANUFACTURING PACKAGE FOR LIGHT-EMITTING APPARATUS - A light-emitting apparatus of the present invention has (i) a semiconductor device which emits light toward a higher position than a substrate and (ii) a plurality of external connection terminals, and includes: a light-reflecting layer, provided on the substrate, which reflects the light emitted by the semiconductor device; and a covering layer which covers at least the light-reflecting layer and which transmits the light reflected by the light-reflecting layer. Further, the semiconductor device is provided on the covering layer, and is electrically connected to the external connection terminals via connecting portions, and the semiconductor device and the connecting portions are sealed with a sealing resin so as to be covered. Therefore, the light-emitting apparatus has increased efficiency with which light is taken out, and can prevent a reflecting layer from being altered, deteriorating, and decreasing in reflectance. | 2009-12-24 |
20090315058 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a nitride semiconductor light emitting device and a method of manufacturing the same, the device including: a first conductivity type nitride semiconductor layer formed on a substrate; an active layer formed on the first conductivity type nitride semiconductor layer; a second conductivity type nitride semiconductor layer formed on the active layer; a light-transmitting low refractive index layer formed on the second conductivity type nitride semiconductor layer, the light-transmitting low refractive index layer having a plurality of openings through which the second conductivity type nitride semiconductor layer is partially exposed and formed of a material having a refractive index lower than a refractive index of the second conductivity type nitride semiconductor layer; and a high conductivity ohmic contact layer formed on the light-transmitting low refractive index layer and connected to the second conductivity type nitride semiconductor layer through the openings of the light-transmitting low refractive index layer. | 2009-12-24 |
20090315059 | LIGHT EMITTING DIODE - A light-emitting diode includes a substrate having a main surface, a light-emitting diode device arranged on the main surface, a translucent sealing resin portion sealing the light-emitting diode device so that the light-emitting diode device is implemented as an independent convex portion projecting from the main surface, and a reflector arranged on the main surface so as to surround an outer perimeter of the sealing resin portion with an inclined surface at a distance from the outer perimeter. | 2009-12-24 |
20090315060 | LIGHT EMITTING DIODE PACKAGE - Provided is an LED package. It is easy to control luminance according to the luminance and an angle applicable. Since heat is efficiently emitted, the LED package is easily applicable to a high luminance LED. The manufacturing process is convenient and the cost is reduced. The LED package includes a substrate, an electrode, an LED, and a heatsink hole. The electrode is formed on the substrate. The LED is mounted in a side of the substrate and is electrically connected to the electrode. The heatsink hole is formed to pass through the substrate, for emitting out heat generated from the LED. | 2009-12-24 |
20090315061 | METHODS OF ASSEMBLY FOR A SEMICONDUCTOR LIGHT EMITTING DEVICE PACKAGE - Methods of assembly for a semiconductor light emitting device package may include positioning a submount on a mounting substrate with a flux material therebetween and at least substantially free of solder material therebetween. The submount has a metal bonding layer facing the mounting substrate. A semiconductor light emitting device is positioned on a top side of the submount with a flux material therebetween to provide an assembled stack. The assembled stack is reflowed to attach the metal bonding layer of the submount to the mounting substrate and to attach the light emitting device to the submount. | 2009-12-24 |
20090315062 | Light Emitting Diode Submount With High Thermal Conductivity For High Power Operation - This invention relates to the thermal management, extraction of light, and cost effectiveness of Light Emitting Diode, or LED, electrical circuits. An integrated circuit LED submount is described, for the packaging of high power LEDs. The LED submount provides high thermal conductivity while preserving electrical insulation. In particular, a process is described for anodizing a high thermal conductivity aluminum alloy sheet to form a porous aluminum oxide layer and a non-porous aluminum oxide layer. This anodized aluminum alloy sheet acts as a superior electrical insulator, and also provides surface morphology and mechanical properties that are useful for the fabrication of high-density and high-power multilevel electrical circuits. | 2009-12-24 |
20090315063 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - There are provided a light emitting device and a method of manufacturing the same. A light emitting device according to the present invention includes a substrate; an N-type semiconductor layer, an active layer and a P-type semiconductor layer, sequentially formed on the substrate; one or more trenches formed to expose the N-type semiconductor layer by partially removing at least the P-type semiconductor and active layers; a first insulating layer formed on sidewalls of the trenches; and a conductive layer filled in the trenches having the first insulating layer formed therein. According to the present invention, it is possible to obtain a characteristic of uniform current diffusion, and thus, light is uniformly emitted to thereby enhance the light emitting efficiency. | 2009-12-24 |
20090315064 | Light emission device - A light emission device includes a substrate, at least one light-emitting diode (LED), and a plurality of electrical connection elements. The substrate defines a plurality of pilot holes, each having a conductive layer formed in a circumference thereof. The LED is set on the substrate and has a plurality of terminals each forming a through hole corresponding to a respective pilot hole of the substrate. Each electrical connection element is arranged between the conductive layer of each pilot hole of the substrate and each terminal of the LED. The electrical connection element is molten by being heated to form an electric connection portion, which attaches to the conductive layer of the pilot hole and the terminal of the light-emitting diode. In this way, precise positioning between the substrate and the LED is realized, bonding strength is enhanced, and overall thickness is reduced. | 2009-12-24 |
20090315065 | NITRIDE SEMICONDUCTOR LIGHT-EMITTING DIODE AND METHOD OF MANUFACTURING THE SAME - Provided are a nitride semiconductor light-emitting diode including an n-type nitride semiconductor layer, a p-type nitride semiconductor layer and a nitride semiconductor active layer set between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, and having a first transparent electrode layer containing indium tin oxide and a second transparent electrode layer containing tin oxide on a surface of the p-type nitride semiconductor layer opposite to the side provided with the nitride semiconductor active layer and a method of manufacturing the nitride semiconductor light-emitting diode. | 2009-12-24 |
20090315066 | Electro-Optical Device - An object of the present invention is to realize a numerical aperture higher than that of a pixel having a conventional construction by using a pixel circuit having a novel construction in an electro-optical device. Therefore, it is utilized that the electric potential of a gate signal line in a row except for an i-th row is set to a constant electric potential in a period except for when a gate signal line ( | 2009-12-24 |
20090315067 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND STRUCTURE THEREOF - A semiconductor device fabrication method is disclosed. A buffer layer is provided and a first semiconductor layer is formed on the buffer layer. Next, a first intermediate layer is formed on the first semiconductor layer by dopant with high concentration during an epitaxial process. A second semiconductor layer is overlaid on the first intermediate layer. A semiconductor light emitting device is grown on the second semiconductor layer. The formation of the intermediate layer and the second semiconductor layer is a set of steps. | 2009-12-24 |
20090315068 | LIGHT EMITTING DEVICE - A light emitting device includes: a light emitting element; a first lead including a die pad portion at its one end portion, the light emitting element being bonded to the die pad portion; a second lead with its one end portion being opposed to the one end portion of the first lead; and a resin molded body including a recess with at least part of the die pad portion being exposed to the bottom thereof so that emission light from the light emitting element can be emitted upward, a lower surface with at least part of the lower surface of the first lead and at least part of the lower surface of the second lead being exposed thereto, and a lateral surface with at least part of the lateral surface of the die pad portion being exposed thereto, the resin molded body embedding the first lead and the second lead so that the other end portion of the first lead and the other end portion of the second lead are projected in directions opposite to each other. The at least part of the lateral surface of the die pad portion which is exposed is located on a first plane which is generally coplanar with the lateral surface of the other end portion of the first lead and the lateral surface of the other end portion of the second lead. | 2009-12-24 |
20090315069 | THIN GALLIUM NITRIDE LIGHT EMITTING DIODE DEVICE - Disclosed is a light emitting diode (LED) device that comprises a crystal structure of a sapphire substrate-free gallium nitride (GaN) LED, wherein the crystal structure is mounted on a first surface of a sub-mount substrate in the form of a unit chip, and the first surface of the sub-mount substrate has a surface area greater than the surface area of a region in which the unit chip is bonded. Preforms for manufacturing the LED device and a method for manufacturing the LED device are also disclosed. The sapphire substrate, on which the crystal structure of the light emitting diode has grown, is processed into a unit chip before being removed. Thus, any crack in the crystal structure of the light emitting diode that may occur during the removal of the sapphire substrate can be prevented. Therefore, a thin light emitting diode device can be manufactured in a mass production system. | 2009-12-24 |
20090315070 | SEMICONDUCTOR DEVICE - A power semiconductor device is provided, that realizes high-speed turnoff and soft switching at the same time, includes n-type main semiconductor layer including lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer arranged alternately and repeatedly between p-type channel layer and field stop layer and in parallel to the first major surface of n-type main semiconductor layer. Extremely lightly doped n-type semiconductor layer is doped more lightly than lightly doped n-type semiconductor layer. Lightly doped n-type semiconductor layer prevents a space charge region from expanding at the time of turnoff. Extremely lightly doped n-type semiconductor layer expands the space charge region at the time of turnoff to eject electrons and holes quickly further to realize high-speed turnoff. The pattern of arrangement of the lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer is independent of the arrangement pattern of the gate electrode structure. | 2009-12-24 |
20090315071 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a semiconductor device 10 includes forming a plurality of second conductive second semiconductor regions at specific intervals on one main surface of a first conductive first semiconductor region, the plurality of second conductive second semiconductor regions being opposite to the first conductive first semiconductor region, forming a plurality of the first conductive third semiconductor regions on a main surface of the second semiconductor region, the plurality of the first conductive third regions being separated from each other, forming a plurality of holes at specific intervals on an another main surface which faces the one main surface of the first semiconductor region, the plurality of holes being separated from each other, forming a pair of adjacent second conductive fourth semiconductor regions which are alternately connected at a bottom part of the hole within the first semiconductor region, and burying an electrode within the hole. | 2009-12-24 |
20090315072 | Semiconductor Device, Semiconductor Integrated Circuit Equipment Using the Same for Driving Plasma Display, and Plasma Display Unit - In a lateral IGBT structure equipped with an emitter terminal, comprising two or more second conductivity type base layers, per one collector terminal, the second conductivity type base layer in the emitter region is covered by a first conductivity type layer which has a higher impurity concentration than the drift layer, and width L1 of the gate electrode located between two adjacent emitters is 4 μm or less, or in addition to that, width L2 of the opening for leading out an emitter electrode located between two adjacent gate electrodes is 3 μm or less. | 2009-12-24 |
20090315073 | Avalanche Photodiode - The present invention changes layer polarities of an epitaxy structure of an avalanche photodiode into n-i-n-i-p. A transport layer is deposed above an absorption layer to prevent absorbing photon and producing electrons and holes. A major part of electric field is concentrated on a multiplication layer for producing avalanche and a minor part of the electric field is left on the absorption layer for transferring carrier without avalanche. Thus, bandwidth limit from a conflict between RC bandwidth and carrier transferring time is relieved. Meanwhile, active area is enlarged and alignment error is improved without sacrificing component velocity too much. | 2009-12-24 |
20090315074 | Process for Fabricating Silicon-on-Nothing MOSFETs - A semiconductor device includes a gate stack; an air-gap under the gate stack; a semiconductor layer vertically between the gate stack and the air-gap; and a first dielectric layer underlying and adjoining the semiconductor layer. The first dielectric layer is exposed to the air-gap. | 2009-12-24 |
20090315075 | SEMICONDUCTOR DEVICE - A semiconductor device is, constituted by: a nitride group semiconductor functional layer which includes a first nitride group semiconductor region, a second nitride group semiconductor region provided on the first nitride group semiconductor region by a hetero junction, and a two-dimensional carrier gas channel near the hetero junction of the first nitride group semiconductor region; a first main electrode and a second main electrode connected to the two-dimensional carrier gas channel by ohmic contact; and a gate electrode disposed between the first main electrode and the second main electrode. The nitride group semiconductor region has different thicknesses between the second main electrode and the gate electrode, and between the first main electrode and the gate electrode. | 2009-12-24 |
20090315076 | TRANSISTOR GATE ELECTRODE HAVING CONDUCTOR MATERIAL LAYER - Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material. | 2009-12-24 |
20090315077 | MULTI-LAYER STRUCTURE WITH A TRANSPARENT GATE - A multi-layer structure with a transparent gate includes a MHEMT device structure comprising a GaAs substrate, a Schottky layer and a cap layer formed on the Schottky layer; a transparent gate formed on the Schottky layer being an indium tin oxide, ITO; and a drain and a source formed on the cap layer. Moreover, the MHEMT device structure includes a graded buffer, a buffer layer, a first spacer layer, a channel layer, and a second spacer layer formed between the GaAs substrate and the Schottky layer in a stacked fashion. The multi-layer structure is a transparent gate HEMT employing indium tin oxide which can make HEMT more sensitive to the light wave. | 2009-12-24 |
20090315078 | INSULATING GATE AlGaN/GaN HEMT - AlGaN/GaN HEMTs are disclosed having a thin AlGaN layer to reduce trapping and also having additional layers to reduce gate leakage and increase the maximum drive current. One HEMT according to the present invention comprises a high resistivity semiconductor layer with a barrier semiconductor layer on it. The barrier layer has a wider bandgap than the high resistivity layer and a | 2009-12-24 |
20090315079 | Layout Architecture for Improving Circuit Performance - An integrated circuit structure includes an integrated circuit structure including a PMOS transistor including a first gate electrode; a first source region; and a first drain region; an NMOS transistor including a second gate electrode, wherein the first gate electrode and the second gate electrode are portions of a gate electrode strip; a second source region; and a second drain region. No additional transistors are formed between the PMOS transistor and the NMOS transistor. The integrated circuit further includes a VDD power rail connected to the first source region; a VSS power rail connected to the second source region; and an interconnection port electrically connected to the gate electrode strip. The interconnection port is on an outer side of a MOS pair region including the PMOS transistor, the NMOS transistor, and the region between the PMOS transistor and the NMOS transistor. The portion of the gate electrode strip in the MOS pair region is substantially straight. | 2009-12-24 |
20090315080 | TRANSISTOR ARRAY WITH SHARED BODY CONTACT AND METHOD OF MANUFACTURING - An array of transistors arranged next to each other on a semiconductor material forming a substrate, the substrate comprising p-well or n-well diffusions forming a body, which diffusions are used as the body regions of the transistors, each transistor comprising a source, a drain and a gate, wherein the array of transistors further comprises at least one electrical connection to the body, wherein said electrical connection is shared by at least two transistors of said array. Also disclosed is a semiconductor device comprising at least one source, at least one drain, at least one gate between the at least one source and the at least one drain, and at least one structure of the same material as the at least one gate which does not have a connection means for electrical connection to the at least one gate. | 2009-12-24 |
20090315081 | PROGRAMMABLE CIRCUIT WITH CARBON NANOTUBE - A semiconductor device has a programming circuit that includes an active device and a programmable electronic component. The programmable electronic component includes a carbon nanotube having a segment with an adjusted diameter. The programmable electronic component has a value that depends upon the adjusted diameter. The programming circuit also includes interconnects that couple the active device to the programmable electronic component. The active device is configured to control a current transmitted to the programmable electronic component. | 2009-12-24 |
20090315082 | LATERAL JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties. | 2009-12-24 |
20090315083 | Structure and Method for Forming a Thick Bottom Dielectric (TBD) for Trench-Gate Devices - A semiconductor structure which includes a trench gate FET is formed as follows. A plurality of trenches is formed in a semiconductor region using a mask. The mask includes (i) a first insulating layer over a surface of the semiconductor region, (ii) a first oxidation barrier layer over the first insulating layer, and (iii) a second insulating layer over the first oxidation barrier layer. A thick bottom dielectric (TBD) is formed along the bottom of each trench. The first oxidation barrier layer prevents formation of a dielectric layer along the surface of the semiconductor region during formation of the TBD. | 2009-12-24 |
20090315084 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE - A semiconductor device includes a semiconductor substrate, a gate pattern disposed on the semiconductor substrate, a body region disposed on the gate pattern and a first impurity doping region and a second impurity doping region. The gate pattern is disposed below the body region and the first impurity doping region and the second impurity doping region. | 2009-12-24 |
20090315085 | SEMICONDUCTOR DEVICE - In order to realize a higher reliability TFT and a high reliability semiconductor device, an NTFT of the present invention has a channel forming region, n-type first, second, and third impurity regions in a semiconductor layer. The second impurity region is a low concentration impurity region that overlaps a tapered potion of a gate electrode with a gate insulating film interposed therebetween, and the impurity concentration of the second impurity region increases gradually from the channel forming region to the first impurity region. And, the third impurity region is a low concentration impurity region that does not overlap the gate electrode. | 2009-12-24 |
20090315086 | IMAGE SENSOR AND CMOS IMAGE SENSOR - An image sensor includes a first electrode for applying a voltage to a charge storage portion, a second electrode for applying a voltage to a charge increasing portion, a third electrode provided between the first electrode and the second electrode and an impurity region of a first conductive type for forming a path through which the signal charges are transferred, wherein an impurity concentration of a region of the impurity region corresponding to a portion located under the second electrode is higher than an impurity concentration of a region of the impurity region corresponding to a portion located under the third electrode. | 2009-12-24 |
20090315087 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing an image sensor includes forming an isolation area in a semiconductor substrate, forming a plurality of gate insulating layers and a plurality of gates over a transistor area of the semiconductor substrate, forming a photodiode over the semiconductor substrate between the gates and the isolation area, forming a nitride layer over the semiconductor substrate such that tensile stress is applied to the transistor area of the semiconductor substrate, forming a floating diffusion layer over the semiconductor substrate between the gates, and removing the nitride layer over the photodiode, and forming an oxide layer over the photodiode. | 2009-12-24 |
20090315088 | FERROELECTRIC MEMORY USING MULTIFERROICS - Ferroelectric memory using multiferroics is described. The multiferrroic memory includes a substrate having a source region, a drain region and a channel region separating the source region and the drain region. An electrically insulating layer is adjacent to the source region, drain region and channel region. A data storage cell having a composite multiferroic layer is adjacent to the electrically insulating layer. The electrically insulating layer separated the data storage cell form the channel region. A control gate electrode is adjacent to the data storage cell. The data storage cell separates at least a portion of the control gate electrode from the electrically insulating layer. | 2009-12-24 |
20090315089 | ATOMIC LAYER DEPOSITED BARIUM STRONTIUM TITANIUM OXIDE FILMS - Apparatus and methods of forming the apparatus include a dielectric layer containing barium strontium titanium oxide layer, an erbium-doped barium strontium titanium oxide layer, or a combination thereof. Embodiments of methods of fabricating such dielectric layers provide dielectric layers for use in a variety of devices. Embodiments include forming barium strontium titanium oxide film using atomic layer deposition. Embodiments include forming erbium-doped barium strontium titanium oxide film using atomic layer deposition. | 2009-12-24 |
20090315090 | Isolation Trenches with Conductive Plates - Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material. | 2009-12-24 |
20090315091 | GATE STRUCTURE, AND SEMICONDUCTOR DEVICE HAVING A GATE STRUCTURE - A gate structure can include a polysilicon layer, a metal layer on the polysilicon layer, a metal silicide nitride layer on the metal layer and a silicon nitride mask on the metal silicide nitride layer | 2009-12-24 |
20090315092 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device provided with a field-effect transistor, the field-effect transistor including: a active region defined by element isolating region | 2009-12-24 |
20090315093 | ATOMIC LAYER DEPOSITION OF METAL CARBIDE FILMS USING ALUMINUM HYDROCARBON COMPOUNDS - Methods of forming metal carbide films are provided. In some embodiments, a substrate is exposed to alternating pulses of a transition metal species and an aluminum hydrocarbon compound, such as TMA, DMAH, or TEA. The aluminum hydrocarbon compound is selected to achieve the desired properties of the metal carbide film, such as aluminum concentration, resistivity, adhesion and oxidation resistance. In some embodiments, the methods are used to form a metal carbide layer that determines the work function of a control gate in a flash memory. | 2009-12-24 |
20090315094 | Nonvolatile Memory Device - Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string. | 2009-12-24 |
20090315095 | Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof - In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs. | 2009-12-24 |
20090315096 | NON-VOLATILE MEMORY AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a non-volatile memory is provided. An insulating layer, a conductive material layer and a polish stop layer are sequentially on a substrate. Trenches are formed in a portion of the substrate, the polish stop layer, the conductive material layer and the insulating layer, and the conductive material layer is segmented to form conductive blocks. A dielectric material layer is formed to cover the polish stop layer and fill the trenches. A chemical mechanical polishing process is performed until exposing a surface of the polish stop layer. A portion of the dielectric layer is removed to form trench isolation structures. A portion of sidewalls of each conductive block is removed to form floating gates. A width of each floating gate is decreased gradually from bottom to top. | 2009-12-24 |
20090315097 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A semiconductor device and a method for manufacturing the semiconductor device is disclosed. The semiconductor device includes a bit line formed to extend into a semiconductor substrate, a charge storage layer formed on the semiconductor substrate, a word line formed above the charge storage layer to extend across the bit line, a gate electrode formed on the charge storage layer under the word line and between bit lines, a first insulating film formed over the bit line and to extend in the direction of the bit line and a second insulating film that includes a different material than that of the first insulating film and formed to adjoin a side surface of the first insulating film. In addition, the semiconductor device includes an interlayer insulating film that includes a different material from that of the second insulating film that is formed on the first insulating film and the second insulating film and a contact plug coupled to the bit line and formed to penetrate through the first insulating film and the interlayer insulating film and to be sandwiched by the second insulating film. | 2009-12-24 |
20090315098 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device is disclosed. The method includes forming a shallow trench isolation (STI) region extending in a first direction on a semiconductor substrate, forming a mask layer extending in a second direction that intersects with the first direction on the semiconductor substrate and forming a trench on the semiconductor substrate by using the STI region and the mask layer as masks. In addition, the method includes forming a charge storage layer so as to cover the trench and forming a conductive layer on side surfaces of the trench and the mask layer. Word lines are formed from the conductive layer on side surfaces of the trench that oppose in the first direction by etching. The word lines are separated from each other and extend in the second direction. | 2009-12-24 |
20090315099 | METHOD OF MAKING FLASH MEMORY CELLS AND PERIPHERAL CIRCUITS HAVING STI, AND FLASH MEMORY DEVICES AND COMPUTER SYSTEMS HAVING THE SAME - An integrated circuit includes flash memory cells, and peripheral circuitry including low voltage transistors (LVT) and high voltage transistors (HVT). The integrated circuit includes a tunnel barrier layer comprising SiON, SiN or other high-k material. The tunnel barrier layer may comprise a part of the gate dielectric of the HVTs. The tunnel barrier layer may constitute the entire gate dielectric of the HVTs. The corresponding tunnel barrier layer may be formed between or upon shallow trench isolation (STIs). Therefore, the manufacturing efficiency of a driver chip IC may be increased. | 2009-12-24 |
20090315100 | METHOD OF MANUFACTURING SEMICONDUCTUR DEVICE - Disclosed is a method of manufacturing a semiconductor device. The method includes forming an oxide-nitride-oxide (ONO) layer over a semiconductor substrate, and forming a recess over the semiconductor substrate by etching the ONO layer, forming a vertical structure pattern being higher than the ONO layer over the recess, sequentially forming a spacer oxide film and a first gate poly over the side wall of the vertical structure pattern, and forming a nitride film spacer at a partial region of the side wall of the first gate poly, removing the nitride film spacer, and forming a second gate poly in a spacer shape over the side wall of the first gate poly, and forming a first split gate and a second split gate, symmetrically divided from each other, by removing the vertical structure pattern. | 2009-12-24 |
20090315101 | NOTCHED-BASE SPACER PROFILE FOR NON-PLANAR TRANSISTORS - A method of forming a notched-base spacer profile for non-planar transistors includes providing a semiconductor fin having a channel region on a substrate and forming a gate electrode adjacent to sidewalls of the channel region and on a top surface of the channel region, the gate electrode having on a top surface a hard mask. a spacer layer is deposited over the gate and the fin using a enhanced chemical vapor deposition (PE-CVD) process. A multi-etch process is applied to the spacer layer to form a pair of notches on laterally opposite sides of the gate electrode, wherein each notch is located adjacent to sidewalls of the fin and on the top surface of the fin. | 2009-12-24 |
20090315102 | Process and system for manufacturing a MOS device with intercell ion implant - A process for manufacturing a MOS device includes forming a semiconductor layer having a first type of conductivity; forming an insulated gate structure having an electrode region ( | 2009-12-24 |
20090315103 | TRENCH MOSFET WITH SHALLOW TRENCH FOR GATE CHARGE REDUCTION - A power MOS device includes shallow trench structure for reduction of gate charge. To counteract the increase of Rds may caused by decreasing the depth of trench, the power MOS device further includes an arsenic Ion Implantation area underneath each trench bottom when N+ red phosphorus substrate is applied, and the concentration of said arsenic doped area is higher than that of epitaxial layer. As the shallow trench is performed, the gate contact trench could be easily etched over to penetrate the gate oxide, which will lead to a shortage of tungsten plug filled in gate contact trench to epitaixial layer. To prevent from this problem, a terrace poly gate is designed in a preferred embodiment of present invention. By using this method, the gate contact trench is lifted to avoid the shortage problem. | 2009-12-24 |
20090315104 | Trench MOSFET with shallow trench structures - A trench MOSFET with shallow trench structure is disclosed. The improved structure resolves the problem of degradation of BV caused by the As Ion Implantation in termination surface and no additional mask is needed which further enhance the avalanche capability and reduce the manufacture cost. | 2009-12-24 |
20090315105 | High-voltage vertical transistor structure - In one embodiment, a transistor includes a pillar of semiconductor material arranged in a racetrack-shaped layout having a substantially linear section that extends in a first lateral direction and rounded sections at each end of the substantially linear section. First and second dielectric regions are disposed on opposite sides of the pillar. First and second field plates are respectively disposed in the first and second dielectric regions. First and second gate members respectively disposed in the first and second dielectric regions are separated from the pillar by a gate oxide having a first thickness in the substantially linear section. The gate oxide being substantially thicker at the rounded sections. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. | 2009-12-24 |
20090315106 | Integrated trench Mosfet and Schottky Rectifier with trench contact structure - A trench MOSFET in parallel with trench Schottky barrier rectifier is formed on a single substrate. The present invention solves the constrains brought by planar contact of Schottky, for example, the large area occupied by planar structure. As the size of present device is getting smaller and smaller, the trench Schottky structure of this invention is able to be shrink and, at the same time, to achieve low specific on-resistance. By applying a double epitaxial layer in trench Schottky barrier rectifier, the device performance is enhanced for lower Vf and lower reverse leakage current Ir is achieved. | 2009-12-24 |
20090315107 | INTEGRATED TRENCH MOSFET AND JUNCTION BARRIER SCHOTTKY RECTIFIER WITH TRENCH CONTACT STRUCTURES - A trench MOSFET in parallel with trench junction barrier Schottky rectifier with trench contact structures is formed in single chip. The present invention solves the drawback brought by some prior arts, for example, the large area occupied by planar contact structure and high gate-source capacitance. As the electronic devices become more miniaturized, the trench contact structures of this invention are able to be shrunk to achieve low specific on-resistance of Trench MOSFET, and low Vf and reverse leakage current of the Schottky Rectifier. | 2009-12-24 |
20090315108 | SEMICONDUCTOR DEVICE WITH FIELD ELECTRODE AND METHOD - A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction. | 2009-12-24 |
20090315109 | SEMICONDUCTOR DEVICE HAVING OTP CELLS AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a deep N-type well region which may be formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of a semiconductor substrate over which an oxide film is formed, a dwell region which may be formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of the N-type well region, a shallow N-type well region and a drain region which may be respectively formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of the deep N-type well region, a source region which may be formed by applying an ion-implantation process, using a mask, to a predetermined pattern over a portion of the dwell region, a contact hole which may be formed by being filled with a metal after forming an inter-metal dielectric layer over a portion of the semiconductor substrate over which the source region is formed, and a metal line formed over a portion of the contact hole. | 2009-12-24 |
20090315110 | High voltage MOS array with gate contact on extended drain region - In an extended drain MOS device used in high voltage applications, switching characteristics are improved by providing for at least one base contact in the active region in the extended drain space. | 2009-12-24 |
20090315111 | SEMICONDUCTOR DEVICE HAVING BURIED OXIDE FILM - An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region. | 2009-12-24 |
20090315112 | Forming ESD Diodes and BJTs Using FinFET Compatible Processes - A method of forming an electrostatic discharging (ESD) device includes forming a first and a second semiconductor fin over a substrate and adjacent to each other; epitaxially growing a semiconductor material on the first and the second semiconductor fins, wherein a first portion of the semiconductor material grown from the first semiconductor fin joins a second portion of the semiconductor material grown from the second semiconductor fin; and implanting a first end and a second end of the semiconductor material and first end portions of the first and the second semiconductor fins to form a first and a second implant region, respectively. A P-N junction is formed between the first end and the second end of the semiconductor material. The P-N junction is a junction of an ESD diode, or a junction in an NPN or a PNP BJT. | 2009-12-24 |
20090315113 | Low side zener reference voltage extended drain SCR clamps - In a CMOS implemented free or parasitic pnp transistor, triggering is controlled by introducing a low side zener reference voltage. | 2009-12-24 |
20090315114 | STRESS IN TRIGATE DEVICES USING COMPLIMENTARY GATE FILL MATERIALS - Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device. | 2009-12-24 |
20090315115 | Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement - A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance. | 2009-12-24 |
20090315116 | SEMICONDUCTOR DEVICE WITH HETERO JUNCTION - A semiconductor device includes: a semiconductor substrate made of first semiconductor having a first lattice constant; an isolation region formed in the semiconductor substrate and defining active regions; a gate electrode structure formed above each of the active regions; dummy gate electrode structures disposed above a substrate surface and covering borders between one of the active regions on both sides of the gate electrode structure and the isolation region; recesses formed by etching the active regions between the gate electrode structure and dummy gate electrode structures; and semiconductor layers epitaxially grown on the recesses and made of second semiconductor having a second lattice constant different from the first lattice constant. | 2009-12-24 |
20090315117 | CMOS DEVICES HAVING REDUCED THRESHOLD VOLTAGE VARIATIONS AND METHODS OF MANUFACTURE THEREOF - Stress enhanced transistor devices and methods of fabricating the same are provided. In one embodiment, a transistor device comprises: a gate conductor disposed above a semiconductor substrate between a pair of dielectric spacers, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the recessed regions undercut the dielectric spacers to form undercut areas of the channel region; and epitaxial source and drain regions disposed in the recessed regions of the semiconductor substrate and extending laterally underneath the dielectric spacers into the undercut areas of the channel region. | 2009-12-24 |
20090315118 | TRANSMISSION GATE WITH BODY EFFECT COMPENSATION CIRCUIT - A transmission gate circuit includes a first PMOS device, a first NMOS device, a second PMOS device, a second NMOS device, and a third transistor. A gate electrode, a first electrode and a second electrode of the first PMOS device are coupled to a first control signal, an input end, and an output end, respectively. A gate electrode, a first electrode and a second electrode of the first NMOS device are coupled to a second control signal, the input end, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the second PMOS device are coupled to the first control signal, an input end, and a body electrode of the first PMOS device, respectively. A gate electrode, a first electrode, and a second electrode of the second NMOS device are coupled to the second control signal, a body electrode of the first PMOS device, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the third PMOS device are coupled to a second control signal, a first supply voltage, and the body electrode of the first PMOS device, respectively. | 2009-12-24 |
20090315119 | CMOS CIRCUITS SUITABLE FOR LOW NOISE RF APPLICATIONS - A CMOS circuit comprises CMOS MOSFETs having n-type and p-type gates on the same substrate, wherein the substrate is divided into regions of n-type and p-type diffusions, and those diffusions are contained within a deeper n-type diffusion, used to junction isolate components within the deeper n-type diffusion from components outside of the deeper n-type diffusion. | 2009-12-24 |
20090315120 | RAISED FACET- AND NON-FACET 3D SOURCE/DRAIN CONTACTS IN MOSFETS - An apparatus comprising a semiconductor substrate; a conductively doped source or drain (source/drain) region at the surface of the substrate; a raised semiconductor layer deposited over the source/drain region to form a raised source/drain region; a via formed in the raised source/drain region having substantially vertical sidewalls reaching partly or substantially to the source/drain region; and a metal contact filling the via. | 2009-12-24 |
20090315121 | STABLE STRESS DIELECTRIC LAYER - An integrated circuit is provided having a substrate and a transistor in an active region of the substrate. The substrate also has an isolation region having a dielectric material. In one embodiment, a pre-metal dielectric (PMD) layer is disposed over the substrate and the transistor. At least one of the isolation region or the PMD layer includes O | 2009-12-24 |
20090315122 | SEMICONDUCTOR DEVICE HAVING OHMIC RECESSED ELECTRODE - The present invention provides a semiconductor device having a recess-structured ohmic electrode, in which the resistance is small and variation in the resistance value caused by manufacturing irregularities is small. In the semiconductor device of the present invention, a two-dimensional electron gas layer is formed on the interface between a channel-forming layer and a Schottky layer by electrons supplied from the Schottky layer. The ohmic electrode comprises a plurality of side faces in ohmic contact with the two-dimensional electron gas layer. At least a part of side faces of the ohmic electrodes are non-parallel to a channel width direction. In a preferred embodiment of the present invention, the side faces have a saw tooth form or a comb tooth form. Since the contact area between the ohmic electrode and the two-dimensional electron gas layer is increased, ohmic resistance is reduced. | 2009-12-24 |
20090315123 | HIGH VOLTAGE DEVICE WITH CONSTANT CURRENT SOURCE AND MANUFACTURING METHOD THEREOF - A high voltage device with constant current source and the manufacturing method thereof. The device includes a P type silicon substrate ( | 2009-12-24 |
20090315124 | WORK FUNCTION ENGINEERING FOR EDRAM MOSFETS - Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD | 2009-12-24 |
20090315125 | SEMICONDUCTOR DEVICES AND METHODS WITH BILAYER DIELECTRICS - A semiconductor device is disclosed that includes: a substrate; a first dielectric layer formed over the substrate and formed of a first high-k material, the first high-k material selected from the group consisting of HfO | 2009-12-24 |
20090315126 | Bonded Microfluidic System Comprising Thermal Bend Actuated Valve - A microfluidic system comprising a MEMS integrated circuit bonded to a microfluidics platform. The microfluidics platform comprises a polymeric body having at least one microfluidic channel defined therein. The MEMS integrated circuit comprises at least one thermal bend actuator. The microfluidic system is configured such that movement of the actuator causes closure of the channel. | 2009-12-24 |
20090315127 | METHOD AND APPARATUS FOR IMPROVING MEASUREMENT ACCURACY OF MEMS DEVICES - A system for improving the performance of a microelectromechanical systems (MEMS) device that is housed in a package and implemented on a printed circuit board (PCB) comprises a footprint, an isolation channel, and a bridge. A portion of the isolation channel is removed to mechanically isolate the MEMS device. | 2009-12-24 |
20090315128 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO | 2009-12-24 |
20090315129 | INTEGRATED CIRCUIT DISTRIBUTED OVER AT LEAST TWO NON-PARALLEL PLANES AND ITS METHOD OF PRODUCTION - An integrated circuit includes a first plate-shaped part and at least a plate-shaped second part separate from the first part and attached to the first part by deformable mechanical connection defining a non-zero angle with the first part. A method of producing the integrated circuit includes depositing deformable connecting means in contact with a first portion of the structure and a second portion of the structure, etching the structure to separate the first portion and the second portion, relatively moving the first and second portions to deform the connecting means and fastening together the first portion and the second portion. | 2009-12-24 |
20090315130 | Solid-state imaging apparatus and method for manufacturing the same - A solid-state imaging apparatus and method for manufacturing the imaging apparatus. A solid-state imaging apparatus with reduced thickness and/or mounting area by forming an aperture in a board and placing a solid-state semiconductor imaging chip, an image processing semiconductor chip, and/or a combination imaging/processing chip within the aperture. | 2009-12-24 |
20090315131 | SENSOR STRUCTURE FOR OPTICAL PERFORMANCE ENHANCEMENT - The present disclosure provides an image sensor semiconductor device. The image sensor semiconductor device includes an image sensor disposed in a semiconductor substrate, an inter-level dielectric (ILD) layer disposed on the semiconductor substrate, inter-metal-dielectric (IMD) layers and multi-layer interconnects (MLI) formed on the ILD layer, and a color filter formed in at least one of the IMD layers and overlying the image sensor. | 2009-12-24 |
20090315132 | SOLID-STATE IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING SAME - In a solid-state image pick up device, a first conduction type semiconductor layer which has a first surface side. A second surface side which is located the opposite side of the first surface side and an image sensor area. A photo-conversion area which is configured in the first surface side and charges electron by photoelectric conversion. A first diffusion area of second conduction type for isolation, wherein the first diffusion area surrounds the photo-conversion area and extends from the first surface side to the middle part of the semiconductor layer and a second diffusion area of second conduction type for isolation, wherein the second diffusion area extends from the second surface side to the bottom of the first diffusion layer. | 2009-12-24 |
20090315133 | IMAGE SENSOR MODULE AND CAMERA MODULE HAVING SAME - An exemplary image sensor module includes a heat pipe and an image sensor. The heat pipe includes a main body and a working fluid. The main body includes a top flat cover, an opposite bottom flat cover and a chamber cooperatively defined between the top cover and the bottom cover. The working fluid is filled in the chamber. The image sensor is in thermal contact with an evaporation end of the heat pipe. | 2009-12-24 |
20090315134 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A solid-state imaging device having a high sensitivity and a structure in which a miniaturized pixel is obtained, and a method for manufacturing the solid-state imaging device in which an interface is stable, a spectroscopic characteristic is excellent and which can be manufactured with a high yield ratio are provided. The solid-state imaging device includes at least a silicon layer formed with a photo sensor portion and a wiring layer formed on the front-surface side of the silicon layer, and in which light L is made to enter from the rear-surface side opposite to the front-surface side of the silicon layer and the thickness of the silicon layer | 2009-12-24 |
20090315135 | Shallow-Trench-Isolation (STI)-Bounded Single-Photon CMOS Photodetector - Techniques and apparatus for using single photon avalanche diode (SPAD) devices in various applications. | 2009-12-24 |
20090315136 | PHOTOELECTRIC CONVERSION ELEMENT AND SOLID-STATE IMAGING DEVICE - A photoelectric conversion element includes a pair of electrodes, a photoelectric conversion layer provided between the pair of electrodes and a stress buffer layer provided between the photoelectric conversion layer and at least one of the electrodes, and the stress buffer layer has a stack structure comprising a crystalline sublayer. | 2009-12-24 |