51st week of 2013 patent applcation highlights part 46 |
Patent application number | Title | Published |
20130337596 | Back Channel Etch Metal-Oxide Thin Film Transistor and Process - A method is provided for fabricating an organic light emitting diode (OLED) display. The method includes forming a thin film transistor (TFT) substrate including a first metal layer and a second metal layer. The method also includes depositing a first passivation layer over the second metal layer, and forming a third metal layer over a channel region and a storage capacitor region. The third metal layer is configured to connect to a first portion of the second metal layer that is configured to connect to the first metal layer in a first through-hole through a gate insulator and the first passivation layer. The method further includes depositing a second passivation layer over the third metal layer, and forming an anode layer over the second passivation layer. The anode is configured to connect to a second portion of the third metal layer that is configured to connect to the second metal layer in a second through-hole of the first passivation layer and the second passivation layer. | 2013-12-19 |
20130337597 | VAPOR DEPOSITION DEVICE, VAPOR DEPOSITION METHOD, AND ORGANIC EL DISPLAY DEVICE - A vapor deposition device includes a vapor deposition source ( | 2013-12-19 |
20130337598 | MANUFACTURING PROCESS OF VERTICAL TYPE SOLID STATE LIGHT EMITTING DEVICE - A manufacturing process of a vertical type solid state light emitting device is provided. A substrate is provided. M metal nitride buffer layer is formed on the substrate, and a breakable structure containing M metal droplet structures is formed on the buffer layer. A first type semiconductor layer, an active layer and a second type semiconductor layer are sequentially formed on the breakable structure. A second type electrode is formed on the second type semiconductor layer. The first type semiconductor layer, the active layer, the second type semiconductor layer and the second type electrode are stacked to form a light emitting stacking structure. The breakable structure is damaged to separate from the light emitting stacking structure, so that a surface of the first type semiconductor layer of the light emitting stacking structure is exposed. A first type electrode is formed on the surface of the first type semiconductor layer. | 2013-12-19 |
20130337599 | LASER LIFTOFF STRUCTURE AND RELATED METHODS - Light-emitting devices, and related components, systems, and methods associated therewith are provided. | 2013-12-19 |
20130337600 | METHOD OF PROCESSING A SEMICONDUCTOR ASSEMBLY - A method for processing a semiconductor assembly is presented. The method includes thermally processing a semiconductor assembly in a non-oxidizing atmosphere at a pressure greater than about 10 Torr. The semiconductor assembly includes a semiconductor layer disposed on a support, and the semiconductor layer includes cadmium and sulfur. | 2013-12-19 |
20130337601 | STRUCTURES AND METHODS FOR HIGH EFFICIENCY COMPOUND SEMICONDUCTOR SOLAR CELLS - Methods and structures are provided for the growth and separation of a relatively thin layer crystalline compound semiconductor material containing III-V device layers, including but not limited to Gallium Arsenide (GaAs), on top of a crystalline silicon template wafer. Solar cell structures and manufacturing methods based on the crystalline compound semiconductor material are described. | 2013-12-19 |
20130337602 | Sputtering Target Including a Feature to Reduce Chalcogen Build Up and Arcing on a Backing Tube - A sputtering target has a cylindrical backing tube having two edges and a sidewall comprising a middle portion located between two end portions. The sputtering material is on the backing tube. The sputtering material does not cover at least one end portion of the backing tube. The sputtering target also has a feature which prevents or reduces at least one of chalcogen buildup and arcing at the at least one end portion of the backing tube not covered by the sputtering material. | 2013-12-19 |
20130337603 | METHOD FOR HYDROGEN PLASMA TREATMENT OF A TRANSPARENT CONDUCTIVE OXIDE (TCO) LAYER - A method for fabricating a thin film solar device that includes providing a substrate having a transparent conductive oxide (TCO) layer deposited on a surface of the substrate, the TCO layer having an as deposited sheet resistance. At least a portion of a surface of the TCO layer is exposed to a hydrogen plasma under conditions which result in a treated TCO layer having a reduced sheet resistance which is at least 10% less than the as deposited sheet resistance. | 2013-12-19 |
20130337604 | METHOD OF MANUFACTURING THICK-FILM ELECTRODE - A method of manufacturing a thick-film electrode comprising the steps of: applying onto a substrate a conductive paste comprising a conductive powder, a glass frit, 3.5 to 12.5 weight percent of an organic polymer, and a solvent, wherein the weight percent is based on the total weight of the conductive powder, the glass frit, and the organic polymer; firing the applied conductive paste to form the thick-film electrode, wherein thickness of the thick-film electrode is 1 to 10 μm; and soldering a wire to the thick-film electrode. | 2013-12-19 |
20130337605 | SUBSTRATE PLASMA-PROCESSING APPARATUS - A substrate plasma-processing apparatus for plasma-processing a surface of an electrode of an organic light emitting device. The substrate plasma-processing apparatus may adjust the distance between a first electrode and a substrate and adjust the distance between a second electrode and the substrate. | 2013-12-19 |
20130337606 | Nonvolatile Memory Device Using a Tunnel Nitride As A Current Limiter Element - Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises a resistive material that is configured to improve the switching performance and lifetime of the resistive switching memory element. The electrical properties of the current limiting layer are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the resistive switching memory element found in the nonvolatile memory device. In one embodiment, the current limiting component comprises a tunnel nitride that is a current limiting material that is disposed within a resistive switching memory element in a nonvolatile resistive switching memory device. | 2013-12-19 |
20130337607 | DEPOSITION METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaO | 2013-12-19 |
20130337608 | SEMICONDUCTOR DEVICE, AND PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to the present invention, a structure of a semiconductor device in which adhesive deposits are reduced and yield is excellent; and a process for manufacturing the same can be provided. A process for manufacturing a semiconductor device according to the present invention includes: a step of arranging plural semiconductor elements ( | 2013-12-19 |
20130337609 | LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 2013-12-19 |
20130337610 | METHOD OF FABRICATING ELECTRONIC COMPONENT - A method of fabricating an electronic component includes: mounting a device chip on an upper surface of an insulative substrate; forming a sealing portion that seals the device chip; cutting the insulative substrate and the sealing portion; and forming a plated layer covering the sealing portion by barrel plating. | 2013-12-19 |
20130337611 | Thermally Enhanced Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 2013-12-19 |
20130337612 | HEAT DISSIPATION METHODS AND STRUCTURES FOR SEMICONDUCTOR DEVICE - A semiconductor device with efficient heat dissipating structures is disclosed. The semiconductor device includes a first semiconductor chip that is flip-chip mounted on a first substrate, a heat absorption portion that is formed between the first semiconductor chip and the first substrate, an outer connection portion that connects the first semiconductor chip to an external device and a heat conduction portion formed between the heat absorption portion and the outer connection portion to dissipate heat generated by the first semiconductor chip. | 2013-12-19 |
20130337613 | POWER MODULE PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a power module package and a method for manufacturing the same. The power module package includes first and second lead frames disposed to face each other; ceramic coating layers formed on a portion of a first surface of both or one of both of the first and second lead frames; and semiconductor devices mounted on second surfaces of the first and second lead frames. | 2013-12-19 |
20130337614 | METHODS FOR MANUFACTURING A CHIP PACKAGE, A METHOD FOR MANUFACTURING A WAFER LEVEL PACKAGE, AND A COMPRESSION APPARATUS - Various embodiments provide a method for manufacturing a chip package, the method including: forming an encapsulation material over a chip; compressing an encapsulation material over a chip by a film arranged over the encapsulation material, thereby molding the encapsulation material over the chip; wherein a material from the film is deposited over at least part of the encapsulation material. | 2013-12-19 |
20130337615 | POLYMER HOT-WIRE CHEMICAL VAPOR DEPOSITION IN CHIP SCALE PACKAGING - Embodiments of the present invention provide a vapor phase organic polymer film deposited using a CVD process at low temperature during a process sequence for wafer-level chip scale packaging (WL-CSP), including system-in package (SiP), Package-on-Package (PoP) and Package-in-Package (PiP). | 2013-12-19 |
20130337616 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES AND UNDERFILL EQUIPMENT FOR THE SAME - A method of fabricating a semiconductor device comprises loading a circuit board including a semiconductor chip into underfill equipment, positioning the circuit board on a depositing chuck of the underfill equipment, filling an underfill material in a space between the semiconductor chip and the circuit board placed on the depositing chuck; transferring the circuit board including the underfill material so that it is positioned on a post-treatment chuck of the underfill equipment; heating the underfill material of the circuit board placed on the post-treatment chuck in a vacuum state, and unloading the circuit board, of which the underfill material has been heated in the vacuum state, from the underfill equipment. | 2013-12-19 |
20130337617 | LIQUID CRYSTAL DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A liquid crystal display device includes a gate line and a gate electrode connected to the gate line, on a substrate; a gate insulating layer on the gate electrode and the gate line; an active layer on the gate insulating layer over the gate electrode; an ohmic contact layer on the active layer; first source and drain electrodes on the ohmic contact layer; second source and drain electrodes connected to the first source and drain electrodes, respectively; a data line extending from the source electrode and crossing the gate line to define a pixel region; and a pixel electrode in the pixel region and extending from the second drain electrode. | 2013-12-19 |
20130337618 | TRANSISTOR DEVICE WITH REDUCED GATE RESISTANCE - A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided. | 2013-12-19 |
20130337619 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A compound semiconductor device includes: a compound semiconductor region having a surface in which a step is formed; a first electrode formed so as to overlie the upper surface of the step, the upper surface being a non-polar face; and a second electrode formed along a side surface of the step so as to be spaced apart from the first electrode in a vertical direction, the side surface being a polar face. | 2013-12-19 |
20130337620 | TRANSPORT CONDUITS FOR CONTACTS TO GRAPHENE - An apparatus comprises at least one transistor. The at least one transistor comprises a substrate, a graphene layer formed on the substrate, and first and second source/drain regions spaced apart relative to one another on the substrate. The graphene layer comprises at least a first portion and a second portion, the first portion being in contact with the first source/drain region and the second portion being in contact with the second source/drain region. One or more cuts are formed in at least one of the first and second portions of the graphene layer. The apparatus allows for lowered contact resistance in graphene/metal contacts. | 2013-12-19 |
20130337621 | NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES - A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure. | 2013-12-19 |
20130337622 | SEMICONDUCTOR PROCESS - A semiconductor process is provided, including following steps. A polysilicon layer is formed on a substrate. An asymmetric dual-side heating treatment is performed to the polysilicon layer, wherein a power for a front-side heating is different from a power for a backside heating. | 2013-12-19 |
20130337623 | QUANTUM-WELL-BASED SEMICONDUCTOR DEVICES - Quantum-well-based semiconductor devices and methods of forming quantum-well-based semiconductor devices are described. A method includes providing a hetero-structure disposed above a substrate and including a quantum-well channel region. The method also includes forming a source and drain material region above the quantum-well channel region. The method also includes forming a trench in the source and drain material region to provide a source region separated from a drain region. The method also includes forming a gate dielectric layer in the trench, between the source and drain regions; and forming a gate electrode in the trench, above the gate dielectric layer. | 2013-12-19 |
20130337624 | METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR (MOSFET) GATE TERMINATION - A method of forming a semiconductor device is provided that includes forming an oxide containing isolation region in a semiconductor substrate to define an active semiconductor region. A blanket gate stack including a high-k gate dielectric layer may then be formed on the active semiconductor region. At least a portion of the blanket gate stack extends from the active semiconductor device region to the isolation region. The blanket gate stack may then be etched to provide an opening over the isolation region. The surface of the isolation region that is exposed by the opening may then be isotropically etched to form an undercut region in the isolation region that extend under the high-k gate dielectric layer. An encapsulating dielectric material may then be formed in the opening filling the undercut region. The blanket gate stack may then be patterned to form a gate structure. | 2013-12-19 |
20130337625 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device including a metal compound film formation process based on an atomic layer deposition (ALD) with repeating a plurality of cycles in which a supply time of a metallic source gas at the first time of the cycles is longer than a supply time of the source gas at the second time or later of the cycles, the ALD including, as one cycle, supplying the metallic source gas to adsorb a metallic source onto a foundation; purging the metallic source gas from a film-forming space; supplying a reactant gas to convert the metallic source into a corresponding metal compound; and purging the reactant gas. | 2013-12-19 |
20130337626 | Monolithic Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench. | 2013-12-19 |
20130337627 | METHOD OF MANUFACTURING ELECTRONIC COMPONENT - According to one embodiment, a lower wiring layer is formed by using a sidewall transfer process for forming a sidewall film having a closed loop along a sidewall of a sacrificed or dummy pattern and, after removing the sacrificed pattern to leave the sidewall film, selectively removing the base material with the sidewall film as a mask. One or more upper wiring layers are formed in an upper layer of the lower wiring layer via another layer using the sidewall transfer process. Etching for cutting each of the lower wiring layer and the upper wiring layers is collectively performed, whereby closed-loop cut is applied to the lower wiring layer and the upper wiring layers. | 2013-12-19 |
20130337628 | RESISTANCE CHANGE MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a resistance-change memory of embodiment includes a first interconnect line extending in a first direction, a second interconnect line extending in a second direction intersecting with the first direction, and a cell unit. The cell unit is provided at an intersection of the first interconnect line and the second interconnect line. The cell unit includes a non-ohmic element having a silicide layer on at least one of first and second ends thereof, and a memory element to store data in accordance with a reversible change in a resistance state. The silicide layer includes a 3d transition metal element which combines with an Si element to form silicide and which has a first atomic radius, and at least one kind of an additional element having a second atomic radius greater than the first atomic radius. | 2013-12-19 |
20130337629 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches. | 2013-12-19 |
20130337630 | Methods of Forming a Span Comprising Silicon Dioxide - Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. | 2013-12-19 |
20130337631 | Semiconductor Structure and Method - A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur. | 2013-12-19 |
20130337632 | Method for Producing Group III Nitride Crystal - A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates | 2013-12-19 |
20130337633 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, semiconductor die are singulated from a semiconductor wafer by forming trenches along singulation lines and initiating a cracks from within the trenches, which propagate through the semiconductor wafer in a more controlled manner. | 2013-12-19 |
20130337634 | FABRICATION METHOD FOR PRODUCING SEMICONDUCTOR CHIPS WITH ENHANCED DIE STRENGTH - A fabrication method for producing semiconductor chips with enhanced die strength comprises following steps: forming a semiconductor wafer with enhanced die strength by comprising the substrate, the active layer on the front side of the substrate and the backside metal layer on the backside of the substrate, wherein at least one integrated circuit forms in the active layer; forming a protection layer on a front side of the semiconductor wafer; dicing the semiconductor wafer by at least one laser dicing process and removing the laser dicing residues and removing said protection layer by at least one etching process, whereby plural semiconductor chips with enhanced die strength are produced, and wherein the backside metal layer of said semiconductor chip fully covers the backside of said semiconductor chip after dicing. | 2013-12-19 |
20130337635 | FILM DEPOSITION APPARATUS, SUBSTRATE PROCESSING APPARATUS AND FILM DEPOSITION METHOD - A film deposition apparatus configured to perform a film deposition process on a substrate in a vacuum chamber includes a turntable configured to rotate a substrate loading area to receive the substrate, a film deposition area including at least one process gas supplying part configured to supply a process gas onto the substrate loading area and configured to form a thin film by depositing at least one of an atomic layer and a molecular layer along with a rotation of the turntable, a plasma treatment part provided away from the film deposition area in a rotational direction of the turntable and configured to treat the at least one of the atomic layer and the molecular layer for modification by plasma, and a bias electrode part provided under the turntable without contacting the turntable and configured to generate bias potential to attract ions in the plasma toward the substrate. | 2013-12-19 |
20130337636 | CARBON DOPING OF GALLIUM ARSENIDE VIA HYDRIDE VAPOR PHASE EPITAXY - Methods for growing layers of carbon doped GaAs are provided. Methods include exposing a substrate to a gas mixture comprising a source of Ga, a source of As and a dopant comprising a haloalkane under conditions sufficient to grow a layer of carbon doped GaAs on the substrate via hydride vapor phase epitaxy. The haloalkane can include a bromoalkane, a bromochloroalkane, an iodoalkane or combinations thereof. The concentration of carbon in the layer can be 1×10 | 2013-12-19 |
20130337637 | STRAINED SILICON AND STRAINED SILICON GERMANIUM ON INSULATOR METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS (MOSFETS) - A method of forming a semiconductor device that includes providing a first strained layer of a first composition semiconductor material over a dielectric layer. A first portion of the layer of the first composition semiconductor material is etched or implanted to form relaxed islands of the first composition semiconductor material. A second composition semiconductor material is epitaxially formed over the relaxed island of the first composition semiconductor material. The second composition semiconductor material is intermixed with the relaxed islands of the first composition semiconductor material to provide a second strained layer having a different strain than the first strained layer. | 2013-12-19 |
20130337638 | METHOD OF MANUFACTURING EPITAXIAL SILICON WAFER AND EPITAXIAL SILICON WAFER MANUFACTURED BY THE METHOD - A method of manufacturing an epitaxial silicon wafer including a silicon wafer having a surface added with phosphorus and an epitaxial film provided on the surface includes adjusting an in-plane thickness distribution of the epitaxial film formed on the surface of the silicon wafer based on an in-plane resistivity distribution of the silicon wafer before an epitaxial growth treatment. | 2013-12-19 |
20130337639 | Method for Substrate Pretreatment To Achieve High-Quality III-Nitride Epitaxy - The present invention relates to a method for producing a modified surface of a substrate that stimulates the growth of epitaxial layers of group-III nitride semiconductors with substantially improved structural perfection and surface flatness. The modification is conducted outside or inside a growth reactor by exposing the substrate to a gas-product of the reaction between hydrogen chloride (HCl) and aluminum metal (Al). As a single-step or an essential part of the multi-step pretreatment procedure, the modification gains in coherent coordination between the substrate and group-III nitride epitaxial structure to be deposited. Along with epilayer, total epitaxial structure may include buffer inter-layer to accomplish precise substrate-epilayer coordination. While this modification is a powerful tool to make high-quality group-III nitride epitaxial layers attainable even on foreign substrates having polar, semipolar and nonpolar orientation, it remains gentle enough to keep the surface of the epilayer extremely smooth. Various embodiments are disclosed. | 2013-12-19 |
20130337640 | METHOD FOR FABRICATING A POROUS SEMICONDUCTOR BODY REGION - A method for fabricating a porous semiconductor body region, including producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and filling the trench with a semiconductor material of the semiconductor body. | 2013-12-19 |
20130337641 | PLASMA DOPING METHOD AND APPARATUS - A plasma doping method and an apparatus which have excellent reproducibility of the concentration of impurities implanted into the surfaces of samples. In a vacuum container, in a state where gas is ejected toward a substrate on a sample electrode through gas ejection holes provided in a counter electrode, gas is exhausted from the vacuum container through a turbo molecular pump as an exhaust device, and the inside of the vacuum container is maintained at a predetermined pressure through a pressure adjustment valve, the distance between the counter electrode and the sample electrode is set sufficiently small with respect to the area of the counter electrode to prevent plasma from being diffused outward, and capacitive-coupled plasma is generated between the counter electrode and the sample electrode to perform plasma doping. The gas used herein is a gas with a low concentration which contains impurities such as diborane or phosphine. | 2013-12-19 |
20130337642 | METHODS AND DEVICES FOR FORMING NANOSTRUCTURE MONOLAYERS AND DEVICES INCLUDING SUCH MONOLAYERS - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). | 2013-12-19 |
20130337643 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes etching a substrate to form a field trench defining an active region and a lower gate pattern on the active region, the lower gate pattern including a tunneling insulating pattern and a lower gate electrode pattern, filling a field insulating material in the field trench to form a field region, forming an upper gate pattern on the lower gate pattern, sequentially forming a stopping layer and a buffer layer on the field region and the upper gate pattern, forming a first resistive pattern on the buffer layer of the field region, and forming a second resistive pattern on the buffer layer on the upper gate pattern, forming an interlayer insulating layer covering the first and second resistive patterns, and performing a planarization process to remove a top surface of the interlayer insulating layer and to remove the second resistive pattern. | 2013-12-19 |
20130337644 | Method and Apparatus for Forming a Semiconductor Gate - The present disclosure provides an apparatus and method for fabricating a semiconductor gate. The apparatus includes, a substrate having an active region and a dielectric region that forms an interface with the active region; a gate electrode located above a portion of the active region and a portion of the dielectric region; and a dielectric material disposed within the gate electrode, the dielectric material being disposed near the interface between the active region and the dielectric region. The method includes, providing a substrate having an active region and a dielectric region that forms an interface with the active region; forming a gate electrode over the substrate, the gate electrode having an opening near a region of the gate electrode that is above the interface; and filling the opening with a dielectric material. | 2013-12-19 |
20130337645 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of processing a substrate is provided. The method includes: providing a substrate, wherein the substrate includes a silicon layer; etching the substrate to form a cavity; filling a first conductor in part of the cavity; performing a first thermal treatment on the first conductor; filling a second conductor in the cavity to fill-up the cavity; and performing a second thermal treatment on the first conductor and the second conductor. | 2013-12-19 |
20130337646 | METHOD FOR FORMING STAIRCASE WORD LINES IN A 3D NON-VOLATILE MEMORY HAVING VERTICAL BIT LINES - A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction over a semiconductor substrate. It has vertical local bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. Methods of forming a slab of multi-plane memory with staircase word lines include processes with one masking and with two maskings for forming each plane. | 2013-12-19 |
20130337647 | METHODS OF FORMING A SEMICONDUCTOR DEVICE - The methods include forming a semiconductor substrate pattern by etching a semiconductor substrate. The semiconductor pattern has a first via hole that exposes side walls of the semiconductor substrate pattern, and the side walls of the semiconductor substrate pattern exposed by the first via hole have an impurity layer pattern. The methods further include treating upper surfaces of the semiconductor substrate pattern, the treated upper surfaces of the semiconductor substrate pattern being hydrophobic; removing the impurity layer pattern from the side walls of the semiconductor substrate pattern exposed by the first via hole; forming a first insulating layer pattern on the side walls of the semiconductor substrate pattern exposed by the first via hole; and filling a first conductive layer pattern into the first via hole and over the first insulating layer pattern. | 2013-12-19 |
20130337648 | METHOD OF MAKING CAVITY SUBSTRATE WITH BUILT-IN STIFFENER AND CAVITY - The present invention relates to a method of making a cavity substrate. In accordance with a preferred embodiment, the method includes: providing a sacrificial carrier and optionally an electrical pad that extends from the sacrificial carrier in the first vertical direction; providing a dielectric layer that covers the sacrificial carrier in the first vertical direction; removing a selected portion of the sacrificial carrier; attaching a stiffener to the dielectric layer from the second vertical direction; forming a build-up circuitry from the first vertical direction; and removing the remaining portion of the sacrificial carrier to expose electrical contacts from the second vertical direction. A semiconductor device can be mounted on the cavity substrate and electrically connected to the electrical contacts within the built-in cavity of the cavity substrate. The stiffener can provide mechanical support for the build-up circuitry and the semiconductor device. | 2013-12-19 |
20130337649 | COMPOUND FOR FORMING ORGANIC FILM, AND ORGANIC FILM COMPOSITION USING THE SAME, PROCESS FOR FORMING ORGANIC FILM, AND PATTERNING PROCESS - The invention provides a compound for forming an organic film having a partial structure represented by the following formula (i) or (ii), | 2013-12-19 |
20130337650 | METHOD OF MANUFACTURING DUAL DAMASCENE STRUCTURE - A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings. | 2013-12-19 |
20130337651 | Double Patterning Strategy for Contact Hole and Trench in Photolithography - A method of lithography patterning includes forming a first etch stop layer, a second etch stop layer, and a hard mask layer on a material layer. The materials of the first etch stop layer and the second etch stop layer are selected by the way that there is a material gradient composition between the second etch stop layer, the first etch stop layer, and the material layer. Hence, gradient etching rates between the second etch stop layer, the first etch stop layer, and the material layer are achieved in an etching process to form etched patterns with smooth and/or vertical sidewalls within the second and the first etch stop layers and the material layer. | 2013-12-19 |
20130337652 | MASK PATTERN FOR HOLE PATTERNING AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns. | 2013-12-19 |
20130337653 | SEMICONDUCTOR PROCESSING APPARATUS WITH COMPACT FREE RADICAL SOURCE - A semiconductor processing apparatus ( | 2013-12-19 |
20130337654 | CLAMPED MONOLITHIC SHOWERHEAD ELECTRODE - An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode. | 2013-12-19 |
20130337655 | ABATEMENT AND STRIP PROCESS CHAMBER IN A DUAL LOADLOCK CONFIGURATION - Embodiments of the present invention provide a dual load lock chamber capable of processing a substrate. In one embodiment, the dual load lock chamber includes a chamber body defining a first chamber volume and a second chamber volume isolated from one another. Each of the lower and second chamber volumes is selectively connectable to two processing environments through two openings configured for substrate transferring. The dual load lock chamber also includes a heated substrate support assembly disposed in the second chamber volume. The heated substrate support assembly is configured to support and heat a substrate thereon. The dual load lock chamber also includes a remote plasma source connected to the second chamber volume for supplying a plasma to the second chamber volume. | 2013-12-19 |
20130337656 | STRUCTURE AND METHOD FOR DUAL WORK FUNCTION METAL GATE CMOS WITH SELECTIVE CAPPING - A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming. | 2013-12-19 |
20130337657 | APPARATUS AND METHOD FOR FORMING THIN PROTECTIVE AND OPTICAL LAYERS ON SUBSTRATES - A method and apparatus are provided for plasma-based processing of a substrate based on a plasma source having at least two adjacent electrodes positioned with the long dimensions parallel to define a first gap minimum between the two electrodes of from 5 millimeters to 40 millimeters. A second gap minimum is defined between the two electrodes and the substrate. AC power is provided to the two electrodes through separate electrical circuits from a common supply with the phase difference therebetween. A first gas and a second are injected into the plasma-containing volume between the two electrodes are different positions relative to the substrate. A lower electrode with a lower electrode width that is less than the combined width of the two electrodes is powered from a separately controllable ac power supply at an ac frequency different from that supplied to the two electrodes. | 2013-12-19 |
20130337658 | FILM DEPOSITION METHOD - A film deposition method includes a first step and a second step. In the first step, a first reaction gas is supplied from a first gas supply part to a first process area, and a second reaction gas capable of reacting with the first reaction gas is supplied from a second gas supply part to a second process area, while rotating a turntable and supplying a separation gas to separate the first process area and the second process area from each other. In the second step, the second reaction gas is supplied from the second gas supply part to the second process area without supplying the first reaction gas from the first gas supply part for a predetermined period, while rotating the turntable and supplying the separation gas to separate the first process area and the second process area from each other. | 2013-12-19 |
20130337659 | NOVEL GROUP IV-B ORGANOMETALLIC COMPOUND, AND METHOD FOR PREPARING SAME - The present invention relates to novel 4B group metalorganic compounds represented by following formula I and the preparation thereof. Specifically, the present invention relates to a thermally and chemically stable 4B group organo-metallic compound utilized in chemical vapor deposition (CVD) or atomic layer deposition (ALD), and the preparation thereof. A 4B group metalorganic compound prepared according to the present invention volatiles easily and is stable at high temperature, and can be used effectively in manufacturing 4B group metal oxide thin films. | 2013-12-19 |
20130337660 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - Provided: forming a specific element-containing layer by supplying a source gas to the substrate heated in a processing vessel, under a condition that a thermal decomposition reaction of the source gas is caused; changing the specific element-containing layer to a nitride layer by supplying a nitrogen-containing gas to the substrate; and changing the nitride layer to an oxynitride layer by supplying an oxygen-containing gas to the substrate, the source gas is sprayed in parallel to a surface of the substrate more strongly than a case of spraying the inert gas in parallel to the surface of the substrate in purging the inside of the processing vessel, by supplying an inert gas or a hydrogen-containing gas through the nozzle. | 2013-12-19 |
20130337661 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH LIGHT - A surface of a semiconductor wafer with a gate of a high dielectric constant film formed thereon is heated to a target temperature for a short time by irradiating the surface with a flash of light. This promotes the crystallization of the high dielectric constant film while suppressing the growth of an underlying silicon dioxide film. Subsequently, the temperature of the semiconductor wafer subjected to the flash heating is maintained at an annealing temperature by irradiating the semiconductor wafer with light from halogen lamps. An annealing process after the flash heating is performed in an atmosphere of a gas mixture of hydrogen gas and nitrogen gas. The annealing process is performed on the semiconductor wafer in the atmosphere of the hydrogen-nitrogen gas mixture, so that defects present near the interfaces of the high dielectric constant film are eliminated by hydrogen termination. | 2013-12-19 |
20130337662 | PIVOT CONNECTOR, POWER INPUT ASSEMBLY, ELECTRICAL CONNECTOR APPARATUS, AND METHOD OF PIVOTING ELECTRICALLY CONNECTING APPARATUS - A pivot connector comprising a body element and a retention element that comprises a body element interface structure (comprising at least a first pivot alignment structure), the body element comprising a retention element interface region that comprises a pivot alignment structure-receiving region. A power input assembly comprising a pivot connector, an electrical connector region and an electrical conductor that extends through an internal space defined by the retention element and that is electrically connected to the electrical connector region. An electrical connector apparatus comprising a power input assembly, a second electrical connector region and a power input assembly engagement region. A method comprising pivoting a retention element relative to a body element. | 2013-12-19 |
20130337663 | CONNECTOR - One lane is formed by a combination of two signal pins S and adjacent one or two ground pins G of a connector that handles differential signals. When allocating differential signals to pins staggered in two rows, for pin allocation on the board soldering side, (SGS) is allocated to a left end of a first row to form a first lane and then (SGS) is allocated to odd-numbered lanes and (GSSG) to even-numbered lanes while (GSSG) is allocated to a left end of a second row to form a first lane and then (GSSG) is allocated to odd-numbered lanes and (SGS) to even-numbered lanes. | 2013-12-19 |
20130337664 | ELECTRICAL CONNECTOR ASSEMBLY HAVING INDEPENDENT LOADING MECHANISM FACILITATING INTERCONNECTIONS FOR BOTH CPU AND CABLE - An electrical connector assembly ( | 2013-12-19 |
20130337665 | Midplane Especially Applicable to an Orthogonal Architecture Electronic System - A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line. | 2013-12-19 |
20130337666 | SUBSTRATE EMBEDDED ELECTRICAL INTERCONNECT - Electronic assemblies and methods including the formation of interconnect assemblies are described. An electrical interconnection assembly may include a contact structure and a printed circuit board electrically coupled to the contact structure, the printed circuit board including an opening therein. The contact structure is positioned to extend within the opening in the printed circuit board and is movable in relation to the printed circuit board when a sufficient force is applied to the contact structure. Other embodiments are described and claimed. | 2013-12-19 |
20130337667 | ELECTRICAL CONNECTOR HAVING GROUNDING MATERIAL - An electrical connector is provided having a housing. Contact modules are positioned within the housing. The contact modules each have a dielectric body holding at least one conductive lead. The at least one conductive lead extends between a mating end and a mounting end. The mating end is configured to be electrically connected to an electrical component. The mounting end is configured to be electrically connected to a circuit board. Ground plates are positioned within the housing between corresponding contact modules. The contact modules and the ground plates form a contact assembly held by the housing. A conductive elastomeric material extends through the contact modules and engages the ground plates to electrically interconnect the ground plates. | 2013-12-19 |
20130337668 | Low Voltage Power Supply with Magnetic Connections - A low voltage power assembly may comprise a track that includes one or more conductive plates and one or more metal plates, wherein the track is powered from a low voltage power source; and a power connector assembly that connects to the track, wherein the one or more conductive plates connect to the power assembly providing a low voltage power connection, and further wherein the one or more metal plates connect to the power assembly providing a magnetic connection. The power connector assembly may be configured to provide low voltage power through the track to a low voltage power device. The low voltage power assembly may include a configuration of ferrous material, conductive material, and nonconductive materials arranged in such a way as to provide a method for power and/or signal distribution to a mating device, such as to a set of magnetic LED modules. | 2013-12-19 |
20130337669 | LOCKING DEVICE FOR ELECTRIC VEHICLE CHARGING CONNECTOR - A latch-locking device for an electric vehicle charging connector having a movable latching element for engaging a matching latching element on a charging station, or on an electric vehicle. The latch-locking device includes a movable latch-locking element mounted adjacent the matching latching element on the charging station or an electric vehicle for movement, in a direction transverse to the direction of movement of the movable latching element, between a retracted position spaced away from the matching latching element and an advanced position where the latch-locking element overlaps at least a portion of the movable latching element when the movable latching element is engaged with the matching latching element. An actuator is coupled to the latch-locking element for moving the locking element between the retracted and advanced positions. | 2013-12-19 |
20130337670 | COVER FOR CABLE CONNECTORS - A cover and a system of covers/boots for placement in sealed relation over a connector or pair of connectors that is or are adapted to terminate a cable or splice together a pair of cables, preferably cables that carry signals received by a receiving apparatus on a cell tower. The covers include a cable end that sealingly receives a cable therein, an elongated body that provides secure cover to a cable connector, and an end that abuts a bulkhead or sealingly engages with a second cover when used in a splicing application. | 2013-12-19 |
20130337671 | LATCH ASSEMBLIES FOR CONNECTOR SYSTEMS - A connector system includes a base mount and a slider latch received in the base mount. The slider latch has a profiled groove configured to latchably receive a cam of a connector module. A faceplate is coupled to the base mount. The faceplate has an opening providing access to the slider latch. An ejector button is operatively coupled to the slider latch to move the slider latch from a latched position to an unlatched position. The slider latch is configured to eject the connector module as the slider latch moves between the latched and unlatched positions. A spring engages the slider latch and acts on the slider latch in a biasing direction. The spring forces the slider latch to return to the latched position after the ejector button is released. | 2013-12-19 |
20130337672 | ELECTRICAL CARD CONNECTOR - An electrical card connector includes an insulative housing, a plurality of contacts retained in the insulative housing, a push-push mechanism and a metal shell. The push-push mechanism includes a slider and a link rod. The slider has an outer surface at a laterally side thereof, a heart-shape groove with a heart-shaped block located in a middle thereof depressing from the outer surface and a straight guiding groove communicating with the heart-shape groove. The link rod has a first end portion assembled to the insulative housing and a second end portion sliding in the heart-shape groove and the straight guiding groove. The slider further has an engaging surface depressing from a part of the outer surface in front of the heart-shaped groove, and the heart-shape groove with the heart-shaped block is also retracted from the outer surface together with the engaging surface. | 2013-12-19 |
20130337673 | POWER CONNECTION SYSTEM - An AC cord/plug is “dead” while disconnected and goes “live” only when connected. The plug has a set of spring-loaded, normally-open contacts, each having two sets of fixed contacts and a single set of movable contacts. The movable contacts are in a spring-loaded assembly that has an iron core opposite the contacts, and the fixed contacts are in a hermetically sealed compartment shielding them from the plug's exterior. The AC plug inputs (L | 2013-12-19 |
20130337674 | Adapter For Mechanically And Electrically Connecting An Implantable Electrode To At Least One Test Terminal Contact - An adapter for mechanically/electrically connecting an implantable electrode, via the proximal connector thereof including at least one connecting contact for the electrode, to at least one test terminal contact of a measuring device, includes an electrically insulating adapter housing, a connector receiving element adapted to connector shape, and at least one contact element disposed in the adapter housing establishing contact between the at least one connecting contact of the connector and the at least one test terminal. A receiving tray, having the receiving element for the connector, is mounted on the adapter housing and variable between open and closed contact positions. In the open position, the connector is inserted in the receiving element in a defined position and removed therefrom. In the contact position, the at least one connecting contact of the connector is brought in contact with the contact element in the adapter housing in a defined manner. | 2013-12-19 |
20130337675 | ANTI-LOOSE SOCKET AND PULL-OUT LOCKING MECHANISM THEREOF - The present invention relates to an anti-loose socket and a pull-out locking mechanism thereof, wherein inside the anti-loose socket, there are a pull-out locking mechanism composed of a bevelled sleeve ( | 2013-12-19 |
20130337676 | Cable Connector - A cable connector is introduced herein, which includes a conductive shell, a plurality of rows of terminals and at least one insulated body, wherein an elastic contact section formed on each of the terminals is extended into a central slot of the at least one insulated body to electrically contact with an electronic device, and the conductive shell is positioned outside the at least one insulated body and has at least one grounding finger extended toward at least one passage in the at least one insulated body and thereby being electrically connected with either the elastic contact section or a soldering section of corresponding terminal accommodated within the at least one passage. | 2013-12-19 |
20130337677 | IN-LINE SEALED ELECTRICAL CONNECTOR APPARATUS HAVING A CONNECTOR APPARATUS POSITION ASSURANCE DEVICE, AND LOCKING METHOD THEREOF - A connector apparatus position assurance device ensures that a male connector assembly and a female connector assembly of an in-line sealed electrical connector apparatus of the present invention remain engaged. The connector apparatus position assurance device has contiguous parts that engage various parts of a retention clip of the male connector assembly at different levels of insertion of the connector apparatus position assurance device into the male connector assembly. The insertion of the connector apparatus position assurance device is also accomplished at various stages (i.e., from pre-lock position to final lock position) depending on the insertion level of the female connector assembly into the male connector assembly. Consequently, the effect of the level of insertion of the female connector assembly ensures that the male and female connector assemblies remain engaged. | 2013-12-19 |
20130337678 | Electrical Engagement Apparatus, System and Method - A device for securing a first electrical connector to a second electrical connector, comprising a bracket body; and at least one engaging portion extending from the bracket body to the second electrical connector and coupling to a portion of the second electrical connector. Also provided is a method of securing one electrical connector to another electrical connector and an interconnect system comprising a first connector, a second connector, a third connector, and an engaging device. | 2013-12-19 |
20130337679 | ELECTRICAL CONNECTORS AND ASSEMBLY THEREOF WITH IMPROVED GUIDING STRUCTURES - An electrical connector assembly includes mateable plug connector and receptacle connector. The plug connector includes a U-shaped first tongue and a number of first contacts with flat and rigid contacting portions exposed on the first tongue. The receptacle connector includes a U-shaped receiving cavity configured to receive the first tongue. The first tongue includes a pair of curved outer guiding surfaces and the receiving cavity includes a pair of curved inner guiding surfaces for mating with the curved outer guiding surfaces when the plug connector and the receptacle connector are mated together. Under the guidance of the guiding surfaces, the plug connector can be easily and stably inserted into the receptacle connector. | 2013-12-19 |
20130337680 | MODULAR PLUG CONNECTORS - The invention relates to a plug connector ( | 2013-12-19 |
20130337681 | BOARD TO BOARD CONNECTOR WITH ENHANCED METAL LOCKING FEATURES - An electrical connector includes an insulative housing defining a mating slot, a number of contacts and a pair of metal hold downs fastened in the insulative housing. Each contact includes a contacting portion extending into the mating slot. Each metal hold down includes a first portion, a second portion perpendicular to the first portion and a connecting portion connecting the first portion and the second portion. The first portion defines a first hole, the second portion defines a second hole for maintaining solders, and the connecting portion defines a third hole connecting the first hole and the second hole. The first portion and the connecting portion are insert molded in the insulative housing with material of the insulative housing filling in the first and the third holes. | 2013-12-19 |
20130337682 | VARIABLE IMPEDANCE COAXIAL CONNECTOR INTERFACE DEVICE - A variable impedance interface device for connecting a coaxial connector to an external component is disclosed. The interface device has a housing having a first end adapted to receive a coaxial connector and a second end having an interface where the housing is attachable to an external component, such as a printed circuit board. A cavity within the housing is defined by an inner surface and has a cavity first end and a cavity second end. The inner surface tapers between the cavity first end and the cavity second end. A mating position in the cavity has a certain dimension due to the taper of the inner surface. The mating position defines a location at which a coaxial connector received by the housing positions. An impedance of the housing is based on the mating position and may be varied due to the impedance of the interface such that signal degradation at the interface is reduced. | 2013-12-19 |
20130337683 | Coaxial Connectors withPressure-Enhanced Continuity - Axially compressible, F-connectors for conventional installation tools for interconnection with coaxial cable include biasing fingers for promoting electrical continuity despite inadequate nut tightening. Each connector has a rigid nut, a post penetrating the nut, a tubular body, and an end cap. The conductive post coaxially extends through the connector, linking the nut and body. A post end penetrates the coaxial cable. Each connector body comprises a plurality of radially, spaced apart biasing fingers for pressuring the nut to insure mechanical and electrical contact with the post. In one form of the invention the fingers border spaced apart notches in the body, and extend parallel with the axis of the connector. In an alternative embodiment, fingers are defined between radially spaced-apart slots on a flange associated with the body. | 2013-12-19 |
20130337684 | Stage Pin Connector - An electrical connector having a connector top and a connector base is provided. The electrical connector further includes a contact carrier module, wherein the contact carrier module defines a module cavity and includes a module top opening communicated with a module bottom opening via the module cavity. Additionally, the electrical connector includes a electrical conductor located within the module cavity to be communicated with the module top opening and the module bottom opening and a connector housing, wherein the connector housing includes a pre-mold material and an outer-mold material, wherein the pre-mold material covers at least a portion of the contact carrier module and at least a portion of the electrical cable, and the outer-mold material covers the pre-mold material and the contact carrier module, such that the module top opening is uncovered. | 2013-12-19 |
20130337685 | ELECTRICAL CONNECTOR WITH DETECT FUNCTION - The utility model discloses a USB socket connector, including an insulated body, several terminals and a shield housing covering the insulated body, wherein the insulated body is provided with a space for accepting plugs. The terminals includes a conductive terminal, an earth terminal and a signal detection terminal, wherein the signal detection terminal is extended to the space and is electrically connected with the ground terminal According to the utility model, the earth terminal is electrically connected with the signal detection terminal, and the signal detection terminal is extended to the space, such that the USB plug is inserted into the space, the external metal housing of the USB plug is electrically connected with the signal detection terminal and the shield housing to earth, so as to effectively shield external interference. | 2013-12-19 |
20130337686 | MEMORY CARD MODULE WITH ELECTROMAGNETIC RADIATION SHIELD - A memory card module includes a memory card, a socket including a connecting portion and a main body protruding from the connecting portion, two locking members, and a shielding member made of electromagnetic shielding material. The shielding member covers the memory card and the main body. The locking members are pivotably attached to opposite sides of the main body respectively. Each locking member includes a locking portion. The shielding member includes a top plate, two end plates extending down from opposite ends of the top plate, and two side plates extending down from opposite sides of the top plate. A number of vents are defined in each end plate. A block protrudes from each side plate. The locking portion of each locking member abuts against the block of the corresponding side plate, to mount the shielding member to the socket. | 2013-12-19 |
20130337687 | TELECOMMUNICATION JACK COMPRISING A SECOND COMPENSATING PRINTED CIRCUIT BOARD FOR REDUCING CROSSTALK - A telecommunications jack ( | 2013-12-19 |
20130337688 | ELECTRICAL CONNECTOR ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - An electrical connector assembly comprises: a metallic housing having a receiving space extending along a longitudinal and two openings respectively formed on top and bottom surfaces thereof and communicated with the receiving space; a pair of flexible printed circuit boards (FPCs) received into the receiving space and arranged in a back-to-back manner. Each of the FPC defines a protuberant portion extending into the corresponding opening. And each of the protuberant portion has a plurality of contacts formed on one side thereof and communicated with an exterior. A pair of supporting pieces are received into the receiving space and attached to another side of the protuberant portion. And a spacer is received into the receiving space and sandwiched between the pair of flexible printed circuit boards and supporting pieces. | 2013-12-19 |
20130337689 | ELECTRICAL CONNECTOR AND A PRINTED CIRCUIT BOARD FORMED IN SAID ELECTRICAL CONNECTOR - An electrical connector comprises a metallic housing; and a printed circuit board receiving in the metallic housing and defining a mating portion formed on a front end thereof. The mating portion defines a plurality of conductive pads formed on a top surface thereof, the plurality of conductive pads comprises a plurality of first grounding contacts, a plurality of pairs of differential signal contacts and a plurality of second grounding contacts, each of pair of differential signal contacts are intervened between two adjacent grounding contacts, each of second grounding contact is located in front of the pair of differential signal contacts and electrically and mechanically connected with two front ends of two first grounding contacts. | 2013-12-19 |
20130337690 | CONNECTOR - A connector has a tube ( | 2013-12-19 |
20130337691 | THERMAL DISCONNECTION DEVICE - The invention relates to a thermal disconnection device, comprising a first conductor section and a second conductor section, wherein the first conductor section is guided in a surrounding insulating body at least in some sections, wherein the first conductor section and the second conductor section are connected to each other at a detachable contact point, wherein the first conductor section is subjected to a force so that the first conductor section is moved into the surrounding insulating body when the contact point is detached. | 2013-12-19 |
20130337692 | ELECTRICAL CONNECTOR FOR CONNECTING TO CABLES - An electrical connector includes an insulative housing, a contact module inserted into the insulative housing, a metal shell locked to the insulative housing, a number of cables and an outer shell over-molding the metal shell and the cables. The contact module includes an insulative block and a number of contacts embedded in the insulative block. The contacts include a plurality of cantilevered contacting portions extending beyond the insulative block and a plurality of soldering pads exposed on the insulative block. The cantilevered contacting portions of all the contacts overlap each other from a side view, while the soldering pads of all the contacts are alternately arranged in two parallel planes, respectively, from the side view. | 2013-12-19 |
20130337693 | CONNECTOR - A connector includes: a terminal; a housing; a rear holder; and a rubber plug. A terminal receiving chamber of the housing is provided with: a first receiving portion receiving a wire connecting portion, an electric wire connected to the wire connecting portion, and a rubber plug; a second receiving portion; and a step wall interposed between the first and second receiving portions and allowing a flange portion formed on the wire connecting portion to abut on the step wall. The rubber plug is composed of a ring-shaped packing attached to the electric wire and keeping a space between an outer peripheral wall of the electric wire and an inner wall of the first receiving portion watertight, and a resin member. The resin member is provided with a buried portion buried in the packing, and a cylinder portion extended from the buried portion and interposed between the flange and the packing. | 2013-12-19 |
20130337694 | Card Edge Cable Connector Assembly - A card edge connector assembly is disclosed. The card edge connector assembly includes an insulating housing, a first circuit board, a line transmission device, and a covering body. A plurality of first terminals and second terminals are inserted into the insulating housing. The first terminals and the second terminals are electrically connected to the line transmission device via the first circuit board. The first terminals are above the second terminals and mating portions of the first terminals and the second terminals stretch into a plug space of the insulating housing. In this way, the plug space can be used for the second circuit board to plug in such that the first terminals and the second terminals are electrically connected to the second circuit board. | 2013-12-19 |
20130337695 | ELECTRICAL CONNECTOR HAVING IMPROVED HOUSING - An electrical connector ( | 2013-12-19 |