51st week of 2013 patent applcation highlights part 30 |
Patent application number | Title | Published |
20130335991 | MOTOR VEHICLE COMPONENT WITH MOUNTING CLIP - A motor vehicle component is provided, in particular turn signal lamp, having a clip for mounting to edges of motor vehicle supports, in particular fenders, having different wall thicknesses, wherein the clip has a first mounting face, which is provided for mounting to an edge having a first wall thickness, and a second mounting face, which is stepped with respect to this, which is provided for mounting to an edge having a second wall thickness that is different. | 2013-12-19 |
20130335992 | SOLID STATE LIGHT SOURCE FOR PHOTOCURING - A compact passively-cooled solid state illumination system is provided as a replacement for conventional arc light, metal halide and Xenon white-light sources for photocuring applications. The solid state illumination system utilizes LED modules to generate high intensity light output suitable for photocuring. The light output is continuous in the visible spectrum from 380 nm to 530 nm and is suitable for photocuring using a wide range of photoinitiators. A touchscreen interface allows programming of spectral output, intensity and duration. Output can be initiated using the touchscreen interface and/or a foot pedal. | 2013-12-19 |
20130335993 | LIGHT SOURCE APPARATUS - A light source apparatus includes a plurality of light source modules each including at least one light source unit, light guide lines connected respectively to the light source units, and a casing accommodating the plurality of light source modules and the plurality of light guide lines. The light guide lines are led from the light source units so as not to intervene in the plurality of light source modules when viewed in a direction perpendicular to an array direction of the plurality of light source modules. The plurality of light source modules are separately attachable and detachable in the direction perpendicular to the array direction of the plurality of light source modules. | 2013-12-19 |
20130335994 | ILLUMINATED ACCESSORY UNIT - A lighted assembly includes a LED that emits light at a first frequency. The lighted assembly further includes an elongated light transmitting assembly having at least one illuminated area, and a non-illuminated area surrounding the illuminated area. The elongated light transmitting assembly includes a cover member on the outer side, a backing member on the inner side, and an intermediate member disposed between the cover member and the backing member. Light from the LED is transmitted along an optical path to the illuminated area. A layer of photo reactive material is disposed along the optical path. The photo reactive material produces light at a second frequency that is lower than the first frequency and provides a mixed light having a required color. | 2013-12-19 |
20130335995 | LIGHT RESOURCE MODULE WITH LARGER ILLUMINATION AREA AND A LIGHTING FIXTURE THEREOF - The present invention is provided with a light resource module with larger illumination area, wherein comprising a curve light guide column, the surface of which is formed with several microstructures with light scattering, light refraction or light reflex functions; and two LED light resources, which are corresponding to the two ends of the light guide column The present invention is further provided with a lighting fixture, which comprising at least a light guide column, a heat emission element and a heat conduction element. The present invention of a light resource module with larger illumination area and a lighting fixture thereof have advantages that light is guided to the rear area of the light resource module to enlarge illumination area and reduce unavailable area, making the light resource module and the lighting fixture with larger illumination area. | 2013-12-19 |
20130335996 | ILLUMINATION DEVICE HAVING TWO LIGHT SOURCES WITH ROTATIONAL AND PLANAR MOVEMENT CAPABILITIES - A portable illumination device having two directable light sources each having rotational and planar (i.e., pivotal) movement capabilities. Each light source is housed in an enclosed housing assembly attached at one end to a power source enclosed in a handle casing for providing power to the light sources, a switch mechanism enabling a user to selectively actuate or deactuate one and/or both light source arrays, a magnet base capable of being mounted on a metal platform, and multiple hooks for suspension. | 2013-12-19 |
20130335997 | ILLUMINATED CHROMATIC VEHICLE EMBLEM - An illuminated vehicle emblem assembly is provided that includes a power source, a backing member, and a light-producing assembly coupled to the power source and supported by the backing member. The light-producing assembly may include an electroluminescent light source. The illuminated vehicle emblem assembly further includes a translucent base region over the light source, a chromatic layer over the translucent base region, and a translucent sealing structure configured to seal the backing member, the light producing assembly, and the chromatic layer. The illuminated vehicle emblem assembly exhibits a chrome- or mirror-like finish when viewed under ambient lighting conditions. Further, the illuminated vehicle emblem assembly possesses a glowing appearance when activated under low-light or night-time conditions. | 2013-12-19 |
20130335998 | ELECTRONIC DEVICE AND METHOD OF GUIDING LIGHT IN THE SAME - An electronic device is provided which is capable of reducing variations in the brightness of lights emitted from the light emitting parts. The electronic device has: a housing; a plurality of light sources provided within the housing, each light source emitting light along a light axis, the light axes of the light sources being directed in the same direction; and plurality of light guide plates provided within the housing, the light guide plates guiding the lights emitted from the light sources, respectively. Each light guide plate has a light incident plane on which the light emitted from the light source is incident and a light emitting part that is exposed at an outer surface of the housing. One of the light guide plates has a light incident plane angle that is different from the light incident plane angle of another light guide plate so that light axes of the lights that are guided within the light guide plates pass through the light emitting parts, wherein the light incident plane angle is an acute angle that is formed between the normal line of the light incident plane and the light axis of the light that is incident on the light incident plane. | 2013-12-19 |
20130335999 | Displays With Rounded-Tip Turning Films - An electronic device may be provided with a display having backlight structures. The backlight structures may include a light source. Light from the light source may be coupled into an edge of a light guide plate. The backlight structures may include layers such as a diffuser layer and one or more layers of brightness enhancing film. The brightness enhancing film layers may be used to collimate light scattered from the light guide plate and thereby enhance backlight efficiency. Brightness enhancing films may be formed from transparent substrates such as layers of polyester. A patterned polymer layer such as a layer of patterned cured resin may be formed on the transparent substrate of a backlight enhancing film. A roller-based manufacturing process may be used to form the patterned polymer layer on the substrate. The patterned polymer layer may include a series of parallel ridges with rounded peaks. | 2013-12-19 |
20130336000 | LED LIGHT BAR AND SIDE-EDGE BACKLIGHT MODULE USING SAME - An LED light bar includes a PCB and a plurality of LED lamps mounted to and electrically connected with the PCB. Each of the LED lamps has a light emission face that is perpendicular to the PCB. The LED lamps at two opposite ends are arranged to have the light emission faces thereof angularly shifted in directions away from the light emission faces of the LED lamps in the middle to thereby increase light irradiation range of the LED light bar. With the LED lamps at two ends of the LED light bar being arranged to have light emission faces thereof angularly shifted so as to form a predetermined included angle between the light emission faces of the LED lamps and a light incidence face of the light guide plate, the irradiation range of light from the LED light bar is increased. | 2013-12-19 |
20130336001 | Free form lighting module - The invention provides an illumination device comprising a waveguide having a first face, a second face, and a waveguide edge. The device further comprises a LED light source, wherein the LED light source is arranged to couple at least part of the light source light into the waveguide element. The device also comprises a first transmissive reflector, arranged at the first face side, and a second transmissive reflector, arranged at the second face side. The LED light source, the waveguide, the first transmissive reflector, and the second transmissive reflector, are arranged to generate the first and second light in a direction away from the first face and in a direction away from the second face, respectively. Such an illumination device may allow lighting of a room, for instance via the ceiling with uplight, and lighting of a specific area in the room with downlight. | 2013-12-19 |
20130336002 | BACKLIGHT MODULE - A backlight module has a light guide plate, a notch structure, a light absorption layer, and at least one light source. The light guide plate has a light-emitting surface and at least one side surface forming an angle with the light-emitting surface. The notch structure is continuously formed on the side surface and concave towards the inside of the light guide plate. The light absorption layer is distributed on an area substantially overlapping the notch structure, and the light source is stored in the notch structure. | 2013-12-19 |
20130336003 | BACKLIGHT MODULE - A backlight module is disclosed in the present invention. The backlight module includes a light guiding plate, a light source, a transformer and a constrainer. The transformer is disposed between the light guiding plate and the light source. The transformer is for transforming a first beam emitted from the light source into a second beam, so as to transmit the second beam to the light guiding plate, wherein a spectrum of the first beam is different from a spectrum of the second beam. The constrainer is connected to the light source for constraining a movement of the transformer. The constrainer includes a first fixing portion disposed on the light source and a second fixing portion connected to the first fixing portion, the second fixing portion being disposed on the transformer to fix the transformer relative to the light source. | 2013-12-19 |
20130336004 | FLEXIBLE LIGHT PIPE - A flexible light assembly includes a plurality of light guides that may be operably connected to one or more LED light sources. The light guides may include smooth surfaces that internally reflect light except at selected areas having irregular surface features that permit the escape of light to provide illuminated letters, numbers, designs, or the like. The light guides and LED light source may be disposed within a flexible housing. | 2013-12-19 |
20130336005 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE USING THE SAME - A light guide plate, including a bottom surface, an incident surface, a plurality of guiding structures distributed on the bottom surface and extending along the incident surface is provided. The guiding structures have a trapezoidal shape including a bottom portion, a top portion, a first slant surface and a second slant surface disposed oppositely, wherein both of the first and second slant surfaces connect to the bottom portion and the top portion. The bottom portions of the guiding structures are protruded from the bottom surface of the light guide plate. Alternatively, a patterned structure is formed between the adjacent guiding structures and concave to the bottom surface of the light guide plate. A backlight module includes the light guide plate as described above and at least one light source disposed beside the light guide plate. | 2013-12-19 |
20130336006 | Backlight Device, Backlight System, and Flat Panel Display Device - The present invention introduces a backlight device, a backlight system, and a flat panel display device incorporated with the backlight device. The backlight device is configured by at least two backlight units detachably and electrically interconnected. The backlight unit comprises at least first and second leadframes each including longitudinal first and second ends and an intermediate portion located between the ends. A light emitting device is disposed at the intermediate portion. And at least a pair of first and seconds leads with the first pair of leads arranged at the first end, and the second pair of leads located at the second end. The backlight, backlight system, and the flat panel display device can be readily lengthened or shortened according to the field requirements. It features a simple configuration, while is easy to assemble, and is beneficial to cost down. | 2013-12-19 |
20130336007 | BACKLIGHT MODULE FOR 3D DISPLAYING AND LED LIGHT BAR THEREOF - The present invention relates to a backlight module for 3D displaying and an LED light bar thereof. The backlight module for 3D displaying includes a light guide plate and at least one LED light bar. The LED light bar is arranged at one edge of the light guide plate. The LED light bar includes a plurality of LEDs and a substrate. The LEDs are arranged in a line and are mounted to the substrate in a mutually spaced manner. The LEDs and the substrate of the LED light bar are arranged in a plurality of sections to correspond to a predetermined backlight scanning arrangement. LED spacing set in each of the sections is less than LED spacing set between the section and an adjacent section. The present invention also provides an LED light bar of backlight module for 3D displaying. | 2013-12-19 |
20130336008 | Lighting Device - The present invention relates to an edge-type lighting device using an LED light source which has high light-emitting efficiency regardless of thermal expansion of a light guide plate. An LED light source ( | 2013-12-19 |
20130336009 | Light Guide Plate for 3D Displaying - A light guide plate includes upper microstructures forming an upper surface. The upper microstructures are distributed in a successive convex-concave alternating arrangement in a direction perpendicular to propagation direction of light in the light guide plate. The light guide plate is divided according to the distance from the light source in the light propagation direction into a proximal side and a remote side. With H indicating height of shape features of the upper microstructures and P indicating spacing between the shape features of the upper microstructures, the shape features of the upper microstructures show a distribution that is variable in the light propagation direction in such a way that the variation satisfies the condition that aspect ratio H/P of the upper microstructures at the proximal side of the light guide plate is less than aspect ratio H/P of the upper microstructures at the remote side of the light guide plate. | 2013-12-19 |
20130336010 | SYSTEMS AND METHODS FOR OPERATING AN AC/DC CONVERTER WHILE MAINTAINING HARMONIC DISTORTION LIMITS - Alternating current to direct current (AC/DC) converter control systems and methods are operable to source high values of DC loads or source low values of DC loads while maintaining harmonic distortion limits. An exemplary embodiment receives direct current (DC) load information corresponding to a DC load drawn from an alternating current (AC) network by an AC/DC converter, wherein the AC network also sources a plurality of AC loads, and wherein harmonics output from the AC/DC converter is limited to at least a specified harmonic distortion limit; compares the DC load information with a load threshold; in response to the DC load information being at least equal to the load threshold, operates the AC/DC converter under continuous conduction mode (CCM) control; and in response to the DC load information being less than the load threshold, operates the AC/DC converter under critical conduction mode (CRM) control. | 2013-12-19 |
20130336011 | Switched Mode Power Supply and a Method for Operating a Switched Mode Power Supply - A switched mode power supply includes a first switch connected to an input terminal for inputting an input voltage, a second switch, an inductor and an output capacitor, a transformer connected to the first switch, and a pulse generator connected to the switch. | 2013-12-19 |
20130336012 | Switched-Mode Power Supply and a Two-Phase DC to DC Converter - The switched-mode power supply includes a first switch connected to an input terminal for receiving an input voltage, a second switch, a first node between the first switch and the second switch. The switched-mode power supply further includes a third switch connected to the input terminal, a fourth switch, and a second node between the third switch and the fourth switch. A first inductor is connected between the first node and an output terminal, a second inductor is connected between the second node and the output terminal, at least one third inductor is connected between the first node and the second node, and a capacitor is connected to the output terminal. | 2013-12-19 |
20130336013 | DC-to-DC Converter and Method for Operating a DC-to-DC Converter - The disclosure relates to a method for operating a DC-to-DC converter with two bridge arrangements with bridge switches, of which at least one is in the form of a switchable bridge arrangement which may be operated either as a full bridge or as a half bridge. The converter further includes a series resonant circuit, wherein the first and second bridge arrangements are coupled to one another via the series resonant circuit. At least one switchable bridge arrangement is operated as a full bridge in at least one time segment and as a half bridge in at least one further time segment within a half-period of a periodic switching of the bridge switches. The disclosure furthermore relates to a DC-to-DC converter and an inverter and a power generation installation including such a DC-to-DC converter. | 2013-12-19 |
20130336014 | ELECTRIC POWER CONVERSION CIRCUIT - A DC-DC converter generates PWM signals PWM | 2013-12-19 |
20130336015 | Fluorescent Lamp Power Supply - Various embodiments of a fluorescent lamp power supply are disclosed herein. In one embodiment, a power supply includes a power input connected to a pulse generator. The power supply also includes a filter connected to a variable pulse width output on the pulse generator and to the power input. The filter is adapted to substantially block at least one harmonic frequency component of the variable pulse width output and to substantially pass a fundamental frequency component of the variable pulse width output. The power supply also includes a power output connected to the filter, wherein an amplitude at the power output is related to the pulse width at the variable pulse width output. | 2013-12-19 |
20130336016 | SWITCHING POWER-SUPPLY DEVICE - A half-bridge converter circuit generates an output voltage from an input voltage, by switching first and second FETs. A subsequent-stage switching control circuit alternately subjects the first and second FETs in the half-bridge converter circuit to on/off control with a fixed on-duty ratio and with a switching frequency corresponding to the weight of a load and a dead time sandwiched therebetween. A boost converter circuit includes an inductor, a smoothing capacitor, and a third FET switching the energization of the inductor. A previous-stage switching control circuit subjects the third FET in the boost converter circuit to on/off control with a controlled on-duty ratio, and adjusts the output voltage of the half-bridge converter circuit. | 2013-12-19 |
20130336017 | SWITCHING POWER-SUPPLY DEVICE - A resonant converter circuit generates an output voltage from an input voltage by switching first and second FETs. A subsequent-stage switching control circuit alternately subjects the first and second FETs in the resonant converter circuit to on/off control with a fixed on-duty ratio and a fixed switching frequency. A boost converter circuit includes an inductor, a smoothing capacitor, and a third FET arranged to switch the energization of the inductor. A previous-stage switching control circuit subjects the third FET in the boost converter circuit to on/off control with a controlled on-duty ratio, and adjusts an output voltage to the resonant converter circuit. | 2013-12-19 |
20130336018 | CONVERTER - A converter is configured with a transformer that has a primary coil and a secondary coil, a first switching element that is serially connected to the primary coil, a control circuit that controls the first switching element, and a firs rectifying element that supplies electric power to the control circuit. A ground potential of the control circuit and the first rectifying element are connected to the primary coil at different points. Accordingly, an inverter is miniaturized and manufacturing costs are reduced. | 2013-12-19 |
20130336019 | METHOD AND APPARATUS FOR DETERMINING ZERO-CROSSING OF AN AC INPUT VOLTAGE TO A POWER SUPPLY - An example controller for a power supply includes a first circuit and a drive signal generator. The first circuit receives a first signal representative of a switch current flowing through a switch of the power supply and then generates a second signal in response the switch current not reaching a current threshold within an amount of time. The second signal indicates when a dimming circuit at an input of the power supply is utilized. The drive signal generator generates a drive signal to control switching of the switch in response to the second signal, where energy is transferred across an energy transfer element of the power supply in response to the switching of the switch. | 2013-12-19 |
20130336020 | METHOD AND APPARATUS TO REDUCE AUDIO FREQUENCIES IN A SWITCHING POWER SUPPLY - An example power supply regulator includes an energy transfer element, a switch, and a controller. The controller includes a switch signal generator, a modulation circuit, and a multi-cycle modulator circuit. The modulation circuit modulates the period of a modulation switching signal when an equivalent switching frequency is greater than a reference frequency and fixes the switching period when the equivalent switching frequency is less than the reference frequency. The multi-cycle modulator circuit enables the switch signal generator to provide a switch signal uninterrupted if the equivalent switching frequency is greater than the reference frequency and disables the switch signal generator for a first time period and then enables the switch signal generator for a second time period when the equivalent frequency is less than the reference frequency. The multi-cycle modulator circuit varies the first time period to regulate the output. | 2013-12-19 |
20130336021 | VARIABLE FREQUENCY TIMING CIRCUIT FOR A POWER SUPPLY CONTROL CIRCUIT - A timing circuit of a controller generates a clock signal having a switching period for use by a pulse width modulation (PWM) circuit to control a switch of a power supply. The switching period of the clock signal is based on a charging time plus a discharging time of a capacitor included in the timing circuit. A first current source charges the capacitor while the timing circuit is in a normal charging mode. A second current source charges the capacitor while the timing circuit is in an alternative charging mode that is when the on time of the switch exceeds a threshold time. The current provided by the second current source is less than the current provided by the first current source such that the switching period of the clock signal is increased in response to the timing circuit entering the alternative charging mode. | 2013-12-19 |
20130336022 | SAMPLE AND HOLD BUFFER - This relates to sampling a feedback signal representative of an output of a power converter. The sampling is performed using a buffer sampling circuit having three sample and hold stages coupled in series to sense and store the feedback signal. The first stage is coupled to sample and hold the feedback signal on a capacitor. If the output diode is conducting, the sampled signal is transferred to the second stage. If the output diode is conducting, the first stage will sample the feedback signal and the sampled signal will be transferred to be sampled and held by the second stage. When the output diode stops conducting, the sampled voltage held by the second stage is transferred to the third stage. The third stage stores the sampled voltage on a capacitor. As such, the controller may sample the feedback signal near the end of the output diode conduction time. | 2013-12-19 |
20130336023 | POWER CONVERSION DEVICE - A power conversion device according to embodiments includes a plurality of switch groups, a plurality of inductors, and a snubber circuit. The switch groups are respectively provided for input phases and each of the switch groups has a plurality of one-way switches that connects the corresponding input phase and output phases. The plurality of inductors are respectively connected between the input phases and the switch groups, and are coupled to one another so that current flowing through the one-way switch of one switch group moves to and continues to flow through the turned-on one-way switch of the other switch group when the one-way switch of the one switch group is turned off. The snubber circuit clamps a voltage based on the maximum voltage occurring on the plurality of inductors to a predetermined value. | 2013-12-19 |
20130336024 | Power Conversion System Including Two Transformers with Two Secondary Windings, and Drive Chain Comprising Such a Conversion System - The power conversion system comprises:
| 2013-12-19 |
20130336025 | POWER CONVERSION APPARATUS - A power conversion apparatus includes an inverter circuit, a system voltage measurement unit measuring a system voltage, a voltage drop detector detecting a voltage drop of a power system, based on the system voltage, a direct current power measurement unit measuring a direct current power to be input into the inverter circuit, an alternating current command value calculator calculating an alternating current command value to control an alternating current output from the inverter circuit, based on the direct current power and the system voltage, and a current limiter that decrease a current limit value to limit the alternating current command value, when the voltage drop is detected. | 2013-12-19 |
20130336026 | POWER CONVERSION APPARATUS - A power conversion apparatus includes an inverter circuit including a switching element, a system voltage measurement unit measuring a system voltage of a power system, a voltage drop detector detecting a voltage drop of the power system, a carrier wave generator generating a carrier wave, a carrier wave frequency modulator increasing a frequency of the carrier wave, when the voltage drop is detected, a signal wave generator generating a signal wave to control the inverter circuit, a gate signal generator comparing the carrier wave with the signal wave, and generating a gate signal, and a power conversion controller controlling the inverter circuit, based on the gate signal. | 2013-12-19 |
20130336027 | POWER ADAPTOR - A power adaptor is provided. The power adaptor includes a connector, a rectifier, a filter, a regulator and a switching unit coupled between the rectifier and the filter. The connector receives an alternating current (AC) power. The rectifier provides a direct current (DC) power according to the AC power. The filter filters the DC power to generate a filtered signal. The regulator provides an output voltage according to the filtered signal. A switching state of the switching unit corresponds to the DC power. | 2013-12-19 |
20130336028 | ELECTRIC-POWER CONVERSION SYSTEM - The number of constituent components is reduced so as to provide a small-size and inexpensive electric-power conversion system. The electric-power conversion system is provided with an inverter circuit ( | 2013-12-19 |
20130336029 | SYSTEM AND METHOD PROVIDING OVER CURRENT PROTECTION BASED ON DUTY CYCLE INFORMATION FOR POWER CONVERTER - System and method for protecting a power converter. The system includes a duty-cycle detection component configured to receive a modulation signal, determine a first duty cycle corresponding to a first period of the modulation signal, compare the first duty cycle with a threshold duty cycle, and generate a duty-cycle comparison signal. Additionally, the system includes a threshold generator configured to receive the duty-cycle comparison signal and generate a threshold signal corresponding to a second period of the modulation signal, the second period being after the first period, and a comparator configured to receive the threshold signal and a first signal and to generate a first comparison signal. The first signal is associated with an input current for a power converter. Moreover, the system includes a pulse-width-modulation component configured to receive the first comparison signal and generate the modulation signal for adjusting the input current for the power converter. | 2013-12-19 |
20130336030 | SOLAR POWER GENERATION SYSTEM - There is provided a solar power generation system including a solar cell, an inverter converting a direct current power generated by the solar cell into an alternating current power, a system voltage measurement unit measuring a system voltage, a voltage drop detector detecting a voltage drop of a power system, based on the system voltage, a first direct current voltage controller controlling a direct current voltage of the inverter to enhance a power generation efficiency of the solar cell, when the voltage drop is not detected, and a second direct current voltage controller controlling the direct current voltage of the inverter to suppress a current output from the inverter, when the voltage drop is detected. | 2013-12-19 |
20130336031 | AC/DC Power Conversion Methods and Apparatus - An AC/DC power conversion apparatus comprises an AC/DC converter for converting AC power to DC power for a load and a controller that maintains a power factor of the load as the load varies. The AC/DC converter includes an inductor and a plurality of switches that alternately connects and disconnects the inductor to and from an AC power source, to generate the DC power for the load. The plurality of switches is controlled by a plurality of switch drive signals generated by the controller, based on comparisons of an AC voltage from the AC power source to a DC output voltage produced by the AC/DC converter. To maintain the power factor of the load, the controller is configured to adjust the frequency of the plurality of switch drive signals in response to variations in the load while holding the duty cycles of the switch drive signals constant. | 2013-12-19 |
20130336032 | METHOD OF CONTROLLING SINGLE-PHASE VOLTAGE SOURCE AC/DC CONVERTER AND INTERCONNECTION SYSTEM - A method of controlling a single-phase voltage source AC/DC converting circuit has internal equivalent impedance as seen from an AC terminal, for converting power from a DC voltage source connected to a DC terminal to single-phase AC power or for converting single-phase AC power from a single-phase AC source connected to the AC terminal to DC power in accordance with a pulse width of a gate signal generated based on a PWM command. | 2013-12-19 |
20130336033 | Integrated Power Semiconductor Component, Production Method and Chopper Circuit Comprising Integrated Semiconductor Component - A monolithically integrated power semiconductor component includes a semiconductor body having first and second regions each extending from a first surface of the semiconductor body to a second opposing surface of the body. A power field effect transistor structure formed in the first region has a first load terminal on the first surface and a second load terminal on the second surface. A power diode formed in the second region has a first load terminal on the first surface and a second load terminal on the second surface. The second load terminals of the power field effect transistor structure and power diode are formed by a common load terminal. An edge termination structure is arranged adjacent to the first surface and in a horizontal direction between the first load terminal of the power field effect transistor structure and the first load terminal of the power diode. | 2013-12-19 |
20130336034 | Data and Power System Based on CMOS Bridge - A signal processing circuit includes an input inverter and an output inverter. Each inverter has a signal input for receiving an input rectangular signal, a signal output for providing an inverted output rectangular signal, and a pair of voltage outputs for developing a rectified dc output voltage. A first circuit input terminal is connected to the output of the input inverter and the input of the output inverter. A second circuit input terminal is connected to the input of the input inverter and the output of the output inverter, wherein the signal input terminals receive an input signal having a data component. A pair of supply voltage output terminals is connected to the voltage output terminals of the inverters for providing a rectified dc supply voltage output. A first circuit output terminal is connected to one of the supply voltage output terminals, and a second circuit output terminal connected to the second circuit input terminal, wherein the circuit output terminals provide an output signal including the data component. | 2013-12-19 |
20130336035 | SYSTEM FOR DRIVING A PIEZOELECTRIC LOAD AND METHOD OF MAKING SAME - A system for driving a piezoelectric load includes a direct current (DC) voltage source and a bi-directional DC-to-DC converter having a primary side coupled to the DC voltage source and a secondary side and comprising a control input configured to receive a first control signal configured to control conversion of a first voltage on the primary side of the bi-directional DC-to-DC converter to a second voltage on the secondary side of the bi-directional DC-to-DC converter. The driver system also includes a capacitor coupled to the secondary side of the bi-directional DC-to-DC converter and configured to remove a DC offset of the second voltage and includes a reactive load having a first terminal coupled to the capacitor and a second terminal coupled to the secondary side of the bi-directional DC-to-DC converter. | 2013-12-19 |
20130336036 | NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH BIT LINE VOLTAGE CONTROL AND METHODS THEREOF - In a 3D memory with vertical local bit lines, each local bit line is switchably connected to a node on a global bit line having first and second ends, the local bit line voltage is maintained at a predetermined reference level in spite of being driven by a bit line driver from a first end of the global bit line that constitutes variable circuit path length and circuit serial resistance. This is accomplished by a feedback voltage regulator comprising a voltage clamp at the first end of the global bit line controlled by a bit line voltage comparator at the second end of the global bit line. The comparator compares the bit line voltage sensed from the second end with the predetermined reference level and outputs a control voltage to control the voltage clamp In this way the voltage at the local bit line is regulated at the reference voltage. | 2013-12-19 |
20130336037 | 3D MEMORY HAVING VERTICAL SWITCHES WITH SURROUND GATES AND METHOD THEREOF - A vertical switching layer of a 3D memory device serves to switch a set of vertical local bit lines to a corresponding set of global bit lines, the vertical switching layer being a 2D array of TFT channels of vertical thin-film transistors (TFTs) aligned to connect to an array of local bit lines, each TFT switching a local bit line to a corresponding global bit line. The TFTs in the array have a separation of lengths Lx and Ly along the x- and y-axis respectively such that a gate material layer forms a surround gate around each TFT in an x-y plane and has a thickness that merges to form a row select line along the x-axis while maintaining a separation of length Ls between individual row select lines. The surround gate improves the switching capacity of the TFTs. | 2013-12-19 |
20130336038 | NON-VOLATILE MEMORY HAVING 3D ARRAY ARCHITECTURE WITH STAIRCASE WORD LINES AND VERTICAL BIT LINES AND METHODS THEREOF - In a 3D nonvolatile memory with memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes from a bottom plane to a top plane stacked in the z-direction over a semiconductor substrate; a plurality of local bit lines elongated in the z-direction through the plurality of layers and arranged in a two-dimensional rectangular array of bit line pillars having rows in the x-direction and columns in the y-direction; the 3D nonvolatile memory further having a plurality of staircase word lines spaced apart in the y-direction and between and separated from the plurality of bit line pillars at a plurality of crossings, individual staircase word lines each having a series of alternating steps and risers elongated respectively in the x-direction and z-direction traversing across the plurality of planes in the z-direction with a segment in each plane. | 2013-12-19 |
20130336039 | MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE - A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin. | 2013-12-19 |
20130336040 | ALTERNATE CONTROL SETTINGS - An integrated circuit, that may be a part of an electronic system, may include a first set of storage cells to store settings and a second set of storage cells to store alternate settings. At least one control cell may also be included in the integrated circuit. The at least one control cell may indicate whether to use the settings stored in the first set of storage cells, or the alternate settings stored in the second set of storage cells, to control one or more operating parameters of the integrated circuit. Methods for using the alternate setting are also described. | 2013-12-19 |
20130336041 | Structure and Method for a Forming Free Resistive Random Access Memory with Multi-Level Cell - The present disclosure provides one embodiment of a method for operating a multi-level resistive random access memory (RRAM) cell having a current-controlling device and a RRAM device connected together. The method is free of a “forming” step and includes setting the RRAM device to one of resistance levels by controlling the current-controlling device to one of current levels. The setting the RRAM device includes applying a first voltage to a top electrode of the RRAM device and applying a second voltage to a bottom electrode of the RRAM device. The second voltage is higher than the first voltage. | 2013-12-19 |
20130336042 | RESISTIVE MEMORY DEVICE AND MEMORY APPARATUS AND DATA PROCESSING SYSTEM HAVING THE SAME - A resistive memory device operable with low power consumption and a memory apparatus and data processing system including the same are provided. The resistive memory includes a chalcogenide compound containing 10 to 60 wt % (atomic weight) of selenium (Se) or tellurium (Te). | 2013-12-19 |
20130336043 | RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE DEVICE - A resistance change memory has a resistance change device and a control circuit for controlling application of voltage to the resistance change device. The resistance change device has a first electrode, a second electrode, and a resistance change layer interposed between the first electrode and the second electrode. A material for the second electrode includes one of members selected from the group consisting of W, Ti, Ta, and nitrides thereof. During forming of the resistance change device, the control circuit performs a second forming treatment succeeding to a first forming treatment. The first forming treatment includes application of voltage such that the potential of the first electrode is higher than the potential of the second electrode. The second forming treatment includes application of voltage such that the potential of the second electrode is higher than the potential of the first electrode. | 2013-12-19 |
20130336044 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor. | 2013-12-19 |
20130336045 | SPIN TRANSFER TORQUE MEMORY (STTM) DEVICE WITH HALF-METAL AND METHOD TO WRITE AND READ THE DEVICE - Spin transfer torque memory (STTM) devices with half-metals and methods to write and read the devices are described. For example, a magnetic tunneling junction includes a free magnetic layer, a fixed magnetic layer, and a dielectric layer disposed between the free magnetic layer and the fixed magnetic layer. One or both of the free magnetic layer and the fixed magnetic layer includes a half-metal material at an interface with the dielectric layer. | 2013-12-19 |
20130336046 | NON-VOLATILE MEMORY DEVICE HAVING MULTI-LEVEL CELLS AND METHOD OF FORMING THE SAME - A non-volatile memory device including multi-level cells is provided. The device includes first and second conductive patterns. Additionally, the device includes an electrode structure and a data storage pattern between the first and second conductive patterns. The data storage pattern may include a phase change material and a first vertical thickness of a first portion of the data storage pattern may be less than a second vertical thickness of a second portion of the data storage pattern. The electrode structure may include first and second electrodes and a vertical thickness of the first electrode may be greater than that of the second electrode. | 2013-12-19 |
20130336047 | Cell Refresh in Phase Change Memory - A memory in which a comparison of PCM memory elements storing logical values to a trigger resistance or to each other can be used to determine the extent of resistance drift since the PCM memory elements were last written. If the comparison determines that the resistance drift has passed a sense margin threshold or a trigger resistance, a memory refresh is triggered and pre-drift resistances corresponding to the stored logical values are written to the PCM memory elements. | 2013-12-19 |
20130336048 | Processors and Systems Using Cell-Refreshed Phase-Change Memory - Systems in which PCM is used, including memory systems, as well as methods for operating such systems. A comparison of PCM memory elements storing logical values to a trigger resistance or to each other can be used to determine the extent of resistance drift since the PCM memory elements were last written. If the comparison determines that the resistance drift has passed a sense margin threshold or a trigger resistance, a memory refresh is triggered and pre-drift resistances corresponding to the stored logical values are written to the PCM memory elements. | 2013-12-19 |
20130336049 | Robust Initialization with Phase Change Memory Cells in Both Configuration and Array - The present application discloses phase-change memory architectures and methods, in which an additional test is performed, after the normal power-valid signal, to assure that the phase-change memory components which are used for storing configuration data are able to operate correctly. Surprisingly, the inventor has discovered that this additional test is highly desirable when using phase-change memory for configuration data. | 2013-12-19 |
20130336050 | Processors and Systems with Read-Qualified-on-Startup Phase-Change Memory - Systems in which PCM is used, including memory systems, as well as methods for operating such systems. A test of PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read PCM. This can be used to accelerate availability of memory states residing in PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 2013-12-19 |
20130336051 | MULTIBIT MEMORY WITH READ VOLTAGE QUALIFICATION AT STARTUP - Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 2013-12-19 |
20130336052 | Processors and Systems With Read Voltage Qualification of Multibit Phase-Change Memory - Systems in which multi-bit PCM is used, including memory systems, as well as methods for operating such systems. A test of multi-bit PCM memory elements with known states can be used to determine whether immediately available voltage levels can reliably read multi-bit PCM. This can be used to accelerate availability of memory states residing in multi-bit PCM with respect to, for example, redundancy address storage, other startup state information, and parameters for which nonvolatile storage is useful. | 2013-12-19 |
20130336053 | Paralleled Drive Devices Per Bitline in Phase-Change Memory Array - Methods and systems for phase change memory having high RESET currents. In some sample embodiments, PCM elements share access devices in parallel between bit lines, permitting higher RESET currents to be shared between several access devices without overdriving. Lower individual current densities permit smaller access devices and smaller memories having greater reliability and longer retention. In some sample embodiments, hybrid arrays connect bit lines on only a few word lines, using the shared bits e.g. only for critical information. In some sample embodiments, several PCM elements share a single larger access device which can pass higher currents while still reducing the total memory size. | 2013-12-19 |
20130336054 | Programmable Resistance Memory with Feedback Control - A programmable resistance memory employs a feedback control circuit to regulate the programming current supplied to a selected programmable resistance memory element. The programmable resistance memory may be a phase change memory. The feedback control circuit monitors and controls the characteristics of a current pulse employed to program a memory cell. | 2013-12-19 |
20130336055 | PHASE CHANGE MEMORY WORD LINE DRIVER - A method for improving sub-word line response comprises generating a variable substrate bias determined by at least one user parameter. The variable substrate bias is applied to a sub-word line driver in a selected sub-block of a memory. A voltage disturbance on a sub-word line in communication with the sub-word line driver is minimized by modifying a variable substrate bias of the sub-word line driver to change a transconductance of the sub-word line driver thereby. | 2013-12-19 |
20130336056 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A control circuit for a nonvolatile semiconductor storage device, during a write operation, configures multiple bit lines so that bit lines that are adjacent to select bit lines are nonselect bit lines. The control circuit applies a first voltage to a write bit line that is included in the select bit lines, and also applies a second voltage that is higher than the first voltage, to a write inhibit bit line that is included in the select bit lines. Then, the control circuit applies a third voltage that is higher than the second voltage to the nonselect bit lines. As a result, the control circuit raises the voltage of the write inhibit bit line, while maintaining the write bit line at the first voltage. Next, the control circuit applies a fourth voltage for the write operation to the drain-side select gate line. | 2013-12-19 |
20130336057 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of programming selected memory cells to a plurality of target states comprises applying a first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to at least one target state, applying a program voltage to the selected memory cells, and applying a second verification voltage lower than the first verification voltage to the selected memory cells to perform a verification read operation on memory cells programmed to the at least one target state, wherein the second verification voltage is provided in a specified program loop and subsequent program loops. The second verification voltage is set such that a number of slow bits in the at least one target state is different from the number of slow bits in another target state. | 2013-12-19 |
20130336058 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A nonvolatile memory device comprises a nonvolatile memory chip comprising a static latch, first and second dynamic latches that receive the data stored in the static latch through a floating node, and a memory cell configured to store multi-bit data. The nonvolatile memory device performs a refresh operation on the first dynamic latch where externally supplied first single bit data is stored in the first dynamic latch, performs a refresh operation on the second dynamic latch where externally supplied second single bit data is stored in the second dynamic latch, and programs the memory cell using the data stored in the first and second dynamic latches after the first and second single bit data are stored in the respective first and second dynamic latches. | 2013-12-19 |
20130336059 | BLOCK LEVEL GRADING FOR RELIABILITY AND YIELD IMPROVEMENT - A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes. | 2013-12-19 |
20130336060 | MEMORY DEVICE AND REDUNDANCY METHOD THEREOF - A memory device includes at least one memory, a controller controlling the at least one memory and a connect unit. The at least one memory includes a memory region comprising a plurality of memory cells, a redundant memory region comprising a plurality of memory cells and a redundancy information memory unit. The redundancy information memory unit stores redundancy information of the memory cells of the memory region. The controller includes a control unit. The control unit controls data read-out from the at least one memory and data to be written-in to the at least one memory according to the redundancy information stored in the redundancy information memory unit. | 2013-12-19 |
20130336061 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF AND MEMORY SYSTEM INCLUDING THE SAME - A method of operating a non-volatile memory device includes storing one or more addresses of word lines (WLs), but not the entire addresses of the WLs, into a latch, the WLs disposed between a string selection line (SSL) and a ground selection line (GSL), selecting a first WL from the latch, performing an erasing operation on memory cells associated with the string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation on memory cells associated with the selected first WL. | 2013-12-19 |
20130336062 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - In performing a read operation of a memory transistor, a control circuit supplies a first voltage to a selected word line connected to a selected memory transistor. A second voltage is supplied to a non-selected word line connected to a non-selected memory transistor other than the selected memory transistor, the second voltage being higher than the first voltage. A third voltage is supplied to a bit line. A fourth voltage lower than the third voltage is supplied to, among source lines, a selected source line connected to a memory string including the selected memory transistor in a selected memory block. A fifth voltage substantially the same as the third voltage is supplied to, among the source lines, a non-selected source line connected to a non-selected memory string in the selected memory block. | 2013-12-19 |
20130336063 | Non-Volatile Semiconductor Memory with Page Erase - In a nonvolatile memory, less than a full block maybe erased as one or more pages. A select voltage is applied through pass transistors to each of plural selected wordlines and an unselect voltage is applied through pass transistor to each of plural unselected wordlines of a selected block. A substrate voltage is applied to the substrate of the selected block. A common select voltage may be applied to each selected wordline and the common unselect voltage may be applied to each unselected wordline. Select and unselect voltages may be applied to any of the wordlines of a select block. A page erase verify operation may be applied to a block having plural erased pages and plural nonerased pages. | 2013-12-19 |
20130336064 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block. | 2013-12-19 |
20130336065 | ARCHITECTURE FOR 3-D NAND MEMORY - Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area. | 2013-12-19 |
20130336066 | SENSE AMPLIFIER CIRCUIT - A sense amplifier ( | 2013-12-19 |
20130336067 | NONVOLATILE STORAGE SYSTEM, POWER SUPPLY CIRCUIT FOR MEMORY SYSTEM, FLASH MEMORY, FLASH MEMORY CONTROLLER, AND NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories. | 2013-12-19 |
20130336068 | RANDOM TELEGRAPH SIGNAL NOISE REDUCTION SCHEME FOR SEMICONDUCTOR MEMORIES - Embodiments are provided that include a method including providing a first pulsed gate signal to a selected memory cell, wherein the pulsed gate signal alternates between a first voltage level and a second voltage level during a time period and sensing a data line response to determine data stored on the selected memory of cells. Further embodiments provide a system including a memory device, having a regulator circuit coupled to a plurality of access lines of a NAND memory cell, and a switching circuit configured to sequentially bias at least one of the plurality of the access lines between a first voltage level and a second voltage level based on an input signal. | 2013-12-19 |
20130336069 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - The present disclosure relates to a semiconductor device and a method of operating the semiconductor device, and particularly to a semiconductor memory device including a memory cell array and a method of operating the semiconductor memory device. The memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit configured to program a selected memory cell into a target program state, wherein the peripheral circuit performs a program operation by applying a bit line voltage determined according to the threshold voltage to a bit line of the selected memory cell when a threshold voltage of the selected memory cell is higher than a first verification voltage and is lower than a second verification voltage. | 2013-12-19 |
20130336070 | APPARATUSES AND METHODS TO MODIFY PILLAR POTENTIAL - Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described. | 2013-12-19 |
20130336071 | NONVOLATILE MEMORY DEVICE AND METHOD OF IMPROVING A PROGRAM EFFICIENCY THEREOF - A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation. | 2013-12-19 |
20130336072 | ADAPTIVE VOLTAGE RANGE MANAGEMENT IN NON-VOLATILE MEMORY - A method for adaptive voltage range management in non-volatile memory is described. The method includes establishing an adaptive voltage range for a memory element of an electronic memory device. The memory element includes at least two states. The adaptive voltage range comprises a lower state and an upper state. The method also includes establishing an adjustment process to implement a first adjustment of an abode characteristic of a first state and to implement a second adjustment of an abode characteristic of a second state in the adaptive voltage range in response to a trigger event, wherein the first adjustment of an abode characteristic of the first state is different from the second adjustment of an abode characteristic of the second state. | 2013-12-19 |
20130336073 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device selecting a half page based on a particular bit of a row address includes: an input unit for receiving the particular bit; a control signal generation unit for outputting a mode control signal in response to a signal related to a mode for selecting a whole page; first and second mode control units for transferring first and second output signals of the input unit corresponding to the particular bit and its inverse signal; a row precharge pulse generation unit for generating a row precharge pulse enabled in an initial period of a precharge duration; a first driving unit for pull-up/pull-down driving an output terminal corresponding to a first pre-decoding signal; a second driving unit for pull-up/pull-down driving an output terminal corresponding to a second pre-decoding signal; and first and second latch units for latching output signals of the first and second driving units. | 2013-12-19 |
20130336074 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 2013-12-19 |
20130336075 | MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A memory device includes a decoder circuit configured to activate a setting signal and a write signal if a setting command is applied when a reference mode is set; a delay circuit configured to delay and to generate a delayed write signal; and a setting circuit configured to perform a setting operation in response to the delayed write signal and an input signal of a predetermined pad at the time of setting of the reference mode and to perform the setting operation in response to the setting signal when the reference mode is not set. | 2013-12-19 |
20130336076 | MEMORY DEVICE, OPERATION METHOD THEREOF, AND MEMORY SYSTEM HAVING THE SAME - A method of repairing a word line of a memory device includes receiving a row address, comparing a received row address with a row address of a defective cell, enabling a normal word line and a redundant word line, which correspond to the row address, according to a result of the row address comparison, receiving a column address, comparing a received column address with a column address of the defective cell, and performing a memory access operation on one of the normal word line and the redundant word line according to a result of the column address comparison. | 2013-12-19 |
20130336077 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME - A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array | 2013-12-19 |
20130336078 | SEMICONDUCTOR DEVICE, METHOD OF RETRIEVING DATA, AND MICROCOMPUTER - A semiconductor device includes a data memory cell for storing data; a reference data memory cell for storing reference data to be compared with the data; an inverted data memory cell for storing inverted data of the reference data; a sense amplifier unit; and a data output unit. In a first retrieving process, the sense amplifier unit differentially amplifies the data and the reference data, and adjusts an output thereof when a voltage difference between the data and the reference data becomes a predetermined retrievable voltage difference. In a second retrieving process, the sense amplifier unit differentially amplifies the data and the inverted data, and adjusts an output thereof when a voltage difference between the data and the inverted data becomes the predetermined retrievable voltage difference. The data output unit determines and outputs the data according to a result of the first retrieving process and the second retrieving process. | 2013-12-19 |
20130336079 | MEMORY DEVICE, OPERATION METHOD THEREOF AND MEMORY SYSTEM HAVING THE SAME - A memory refresh method includes selecting at least one bank from among N banks of a memory device, and activating K word lines from among a plurality of word lines included in the at least one bank during one of L refresh cycles of a refresh period. Each of the N banks comprises M word lines, N, K and M are each a natural number greater than or equal to two, L is a natural number less than or equal to M, and K is equal to M*N/L. | 2013-12-19 |
20130336080 | TIMING-DRIFT CALIBRATION - The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit. Additionally, the memory system contains a memory controller which can transmit a request to the memory device to trigger the memory device to measure the frequency of the oscillator circuit. The memory controller is also configured to receive the measured frequency from the memory device and uses the measured frequency to determine the timing drift in the memory device. | 2013-12-19 |
20130336081 | STATE-MONITORING MEMORY ELEMENT - Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage. | 2013-12-19 |
20130336082 | AREA AND POWER EFFICIENT CLOCK GENERATION - Die-to-die interconnect structures are leveraged to form the inductive component of an LC oscillator, thus yielding an LC tank distributed across multiple IC dies rather than lumped in a single die. By this arrangement, reliance on area/power-consuming on-chip inductors may be reduced or eliminated, and phase-aligned clocks may be extracted from the LC tank within each of the spanned IC dies, obviating multiple oscillator instances or complex phase alignment circuitry. | 2013-12-19 |
20130336083 | DYNAMIC MIXER - A dynamic mixer for a plurality of fluid components contains a housing and a rotor element which is rotatably arranged in the housing, with the housing having an inlet opening for at least one respective component and having at least one outlet opening. A ring-shaped intermediate space is provided between the rotor element and the housing in which a mixing element connected to the rotor element is arranged. The mixing element has a vane element which is formed as a directing element for conveying the components from the inlet opening to the outlet opening. The vane element is a directing element and has a directing surface which has a concave curvature with respect to the outlet opening and is further remote from the outlet opening at the onflow side than at the outflow side. | 2013-12-19 |
20130336084 | Static Mixer - A static mixer may include a conduit section having a channel, an injector opening through an inner wall thereof, a tab having a main portion extending from the inner wall adjacent and downstream of the opening and extending radially inwardly at an angle away from the opening in the downstream direction, and having at least one finger extending at a non-zero angle from the main portion, the main portion and the at least one finger being configured such that a second fluid injected through the injector opening and into a first fluid flowing through the conduit section flows radially along the main portion toward a center of the conduit section, and radially outward from the main portion along the at least one finger, whereby the first and second fluids are thoroughly mixed as a result of turbulence imparted by the tab to the fluids. | 2013-12-19 |
20130336085 | Method and Apparatus for Mixing Drinks - An improved mixing bottle comprised of at least two chambers, a top chamber and a bottom chamber. Said chambers may be separated from one another, on the outside, by a freshness seal and, on the inside, by a permeable membrane. The top chamber interior will contain a wide mouth funnel with a wide end and a narrow end. While the freshness seal is still in tact, the narrower end of the funnel may point towards the bottom chamber and be situated somewhere just above the permeable membrane. | 2013-12-19 |
20130336086 | ITEM VALIDATION - A method and apparatus are disclosed for determining if an item of media is invalid. The method includes providing an ultrasound image of an item of media, determining a plurality of regions of the image that satisfy a pre-determined condition and determining that an item of media is invalid if the location of said regions satisfies a pre-determined condition. | 2013-12-19 |
20130336087 | MARINE VIBRATOR SWEEPS - Marine seismic survey using one or more marine seismic vibrators, where the vibrator sweep function is based on a quality requirement, which may be a final image quality requirement or an environmental requirement. The sweep function may be nonlinear and the energy spectrum may not match the energy spectrum of an airgun. | 2013-12-19 |
20130336088 | OBJECT INFORMATION ACQUIRING APPARATUS AND CONTROL METHOD THEREOF - Provided is an object information acquiring apparatus generating image data inside an object on the basis of an acoustic wave propagating inside the object, which uses an object information acquiring apparatus having an acoustic detector receiving the acoustic wave, an object information distribution processor generating an object information distribution representing a property of inside of the object by using the acoustic wave, a reliability distribution generator generating a reliability distribution by using the object information distribution, a similarity distribution generator generating a similarity distribution indicating similarity between template data indicating a relation between a real image and an artifact in the image data, and the object information distribution, and a combination processor performing combination processing of the reliability distribution and the similarity distribution. | 2013-12-19 |
20130336089 | ULTRASONIC IMAGING APPARATUS FOR READING AND DECODING MACHINE-READABLE MATRIX SYMBOLS - There is provided an apparatus and method for reading matrix codes comprising an ultrasound transducer | 2013-12-19 |
20130336090 | ULTRASONIC WADING DETECTION FOR A VEHICLE - A wading sensor for a vehicle comprises an ultrasonic parking distance control. An embodiment detects wading by sensing the difference in the settling time of the diaphragm of a transmitter/receiver, in water and in air. Other embodiments are disclosed. | 2013-12-19 |