51st week of 2013 patent applcation highlights part 21 |
Patent application number | Title | Published |
20130335091 | MULTI-CAPACITOR SYSTEM FOR ELECTROMAGNETIC LOGGING TOOL - An apparatus for estimating a property of an earth formation penetrated by a borehole includes: a borehole carrier; a first switchable-magnet; a first energy storage device coupled to the first switchable magnet; a second switchable-magnet; a second energy storage device coupled to the second switchable-magnet; at least one voltage source having a first polarity and a second polarity opposite of the first polarity; and an electrical circuit configured to charge the first energy storage device and the second energy storage device at the same time and to sequentially discharge the first energy storage device and the second energy storage device, the electrical circuit being further configured to charge the first and second energy storage devices to the first polarity and then charge the first and second energy storage devices to the second polarity after the first and second energy storage devices are discharged. | 2013-12-19 |
20130335092 | Fracture Aperture Estimation Using Multi-Axial Induction Tool - A method for estimating fracture aperture from multi-axial electromagnetic induction measurements made in a wellbore includes determining a fracture indicator and a fracture orientation indicator. The value of the fracture indicator is determined from components of the measurements made transverse to the tool axis. A relationship between the value of the fracture indicator and the fracture aperture for the subsurface formation is determined by estimating the fracture indicator using a plurality of values of fracture aperture and a resistivity of drilling fluid in the wellbore over a background formation with estimated horizontal resistivity and vertical resistivity. The fracture aperture is determined using the determined fracture indicator and the determined relationship. | 2013-12-19 |
20130335093 | METHOD FOR MEASURING THE LIGHT PROPERTIES OF LIGHT-EMITTING DIODES - The invention relates to a method for measuring the light properties of light-emitting diodes (LEDs) in an arrangement of a plurality of channels connected in parallel, each having at least one LED per channel and a driver for driving the channels by means of pulse width modulation (PWM), in such a way that at least one pulse of predetermined width can be generated for each channel within a PWM period, wherein the LED of a selected channel is measured during a measurement interval, the measurement interval overlapping a pulse, lying within the PWM period, of a selected channel. | 2013-12-19 |
20130335094 | VIBRATORY ANALYSIS OF BATTERIES - Methods and apparatuses for determining the charge of a battery are disclosed. Embodiments include determining the charge in batteries that exhibit mass diffusion during charging or discharging, such as by evaluating the response of the battery to vibration. Alternate embodiments include evaluating the amplitude response of the battery and the phase shift response of the battery. Still other embodiment include evaluating the H | 2013-12-19 |
20130335095 | VOLTAGE MONITORING MODULE AND VOLTAGE MONITORING SYSTEM - The voltage monitoring module ( | 2013-12-19 |
20130335096 | BATTERY HAVING CELL VOLTAGE AND BATTERY CURRENT DETECTION AND COMPRISING ONLY ONE ELECTRICAL ISOLATION DEVICE - A battery includes a plurality of battery cells connected in series between a positive terminal and a negative terminal and a resistor connected in series with the battery cells. The battery also includes a plurality of cell voltage detection units which each include a plurality of voltage measurement inputs connected to a respective group of the battery cells. The battery is configured to determine cell voltages of the battery cells connected to the respective cell voltage detection unit. The cell voltage detection units are connected to each other by a communication bus and are configured to transmit, via the communication bus, the determined cell voltages to a microcontroller which is galvanically decoupled from the cell voltage detection units by an electrical isolation device. The resistor includes a first connection connected to a selected voltage measurement input of one of the cell voltage detection units. | 2013-12-19 |
20130335097 | Method And Device For Enhancing The Reliability Of Generator Ground Fault Detection On A Rotating Electrical Machine - A method for enhancing the reliability of generator ground fault detection based on a signal injection scheme, wherein the generator includes a winding. The method includes injecting a test signal at a predefined frequency to the winding, measuring an electrical quantity of a response signal in the winding resulted from the injected test signal, and detecting a ground fault based on the measured value of the electrical quantity. The method further includes continuously determining the frequency of the response signal, and discarding the present measured value corresponding to the determined frequency when the determined frequency deviates from the predefined frequency with a first threshold value. | 2013-12-19 |
20130335098 | Method For Adaptation Of Ground Fault Detection - A method for adapting a ground fault detection to a change of an electrical machine condition, wherein the machine includes a winding. The electrical machine is in a first machine condition, a first reference value being defined for measured values of an electrical quantity. The ground fault detection includes continuously measuring the electrical quantity in the winding and detecting a ground fault based on the measured values of the electrical quantity and the first reference value. The method includes receiving a signal, detecting a change of machine condition based on the received signal, and changing to a second reference value for the measured values of the electrical quantity, the second reference value being different from the first reference value when the change of machine condition is detected. | 2013-12-19 |
20130335099 | STRUCTURE AND METHOD FOR DYNAMIC BIASING TO IMPROVE ESD ROBUSTNESS OF CURRENT MODE LOGIC (CML) DRIVERS - An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad. | 2013-12-19 |
20130335100 | Method for Checking the Proper Method of Operation of a Current Sensor - The disclosure describes a method for checking the proper method of operation of a current sensor which is designed to measure a battery current. During a precharge phase which begins at a time at which at least one electrical component is connected to a battery and during which the electrical component is precharged by a precharge current, at least one measured value provided by the current sensor is compared with an expected current value determined from an expected temporal profile of the precharge current. The disclosure also describes a computation unit and a battery which are designed to carry out the method according to the disclosure. | 2013-12-19 |
20130335101 | TEST APPARATUS - A test apparatus for testing a device under test, includes a low-speed comparator, a high-speed comparator that is operable faster than the low-speed comparator, and a switching section that switches, according to a signal output from the device under test, which one of the low-speed comparator and the high-speed comparator is used to measure a signal under measurement output from the device under test. The test apparatus may further include a termination resistance that is arranged in parallel with the high-speed comparator. | 2013-12-19 |
20130335102 | SECURE JACKET - A secured cable system for protecting an inner cable is disclosed. The secured cable system includes a cable security system having a first security tape including a tape portion upon which a plurality of detection lines are arranged. The security system may also include a detection box in electrical or optical communication with each of the detection lines in the first security tape. In one embodiment, the security tape is spiral wrapped about the inner cable in a first direction along a length of the inner cable, the security tape being overlapped upon itself at a predetermined overlap factor. The secured cable system may also include a second security tape including a tape portion upon which a plurality of detection lines are arranged in a pattern wherein the second security tape is wrapped about the first security tape in a second direction opposite the first direction. | 2013-12-19 |
20130335103 | LINE IMPEDANCE STABILIZATION NETWORK - A line impedance stabilization network (LISN) includes a power port for connecting to a power supply, an equipment under test (EUT) connection port for connecting to an EUT, and a first inductor connected between the power port and the EUT connection port. The coil includes a first end, an opposite second end, a wire connected between the first end and the second end, and a first resistor. The wire includes a plurality of coils, and the first resistor is connected between two different coils of the wire. | 2013-12-19 |
20130335104 | OPEN SENSOR FOR TESTING A COMPOSITE MEDIUM - An open sensor is provided for testing a split sample of a composite medium. The open sensor generally includes a longitudinal section of a tube and a plurality of serpentine conductors which are successively layered on top of each other. The interior surface of the tube section forms a trough into which the split sample of the composite medium can be disposed. The number of serpentine conductors is two or greater. | 2013-12-19 |
20130335105 | DETECTING DEVICE AND DETECTING METHOD - The present technology relates to a detecting device and a detecting method that enable a state change of power lines to be detected with a simple circuit configuration. For example, when electronic devices | 2013-12-19 |
20130335106 | RESISTIVE VOLTAGE DIVIDER MADE OF A RESISTIVE FILM MATERIAL ON AN INSULATING SUBSTRATE - A resistive voltage divider includes first and second resistors, which are electrically connected in series and are made of a resistive film material which is applied in the form of a trace onto an insulating substrate. The divider's voltage ratio has a value between ten and one million. To improve the accuracy of the voltage divider, the first and second resistors are made of the same resistive film material, have a trace length above a corresponding specific trace length, and have approximately the same trace width. | 2013-12-19 |
20130335107 | CONTINUITY TEST IN ELECTRONIC DEVICES WITH MULTIPLE-CONNECTION LEADS - An electronic device includes an electronic component having terminals including a set of first terminals and a set of second terminals, a protective package embedding the electronic component, leads exposed from the protective package including a set of first leads and a set of second leads, for each first lead a first electrical connection inside the protection package between the first lead and a corresponding one of the first terminals, and for each second lead electrical connections inside the protective package each one between the second lead and a corresponding one of the second terminals. For each second lead the electronic component includes test structures, each being coupled between a corresponding one of the second terminals connected to the second lead and a corresponding test one of the first terminals connected to a test one of the first leads. | 2013-12-19 |
20130335108 | DEVICE AND METHOD FOR TESTING ELECTRONIC COMPONENT DEVICES ON A CARRIER OR A SUBSTRATE - A device for testing electronic component devices on a carrier or a substrate, having a positioning and holding device for the earner or the substrate, a test head and a test socket connected thereto, with which multiple simultaneous electronic component devices on the carrier or the substrate are contactable. At least one additional test socket is connected to the test head. | 2013-12-19 |
20130335109 | METHOD OF TEST PROBE ALIGNMENT CONTROL - A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value. | 2013-12-19 |
20130335110 | PLANAR CIRCUIT TEST FIXTURE - There is provided a test fixture for testing a planar circuit. The test fixture comprises a body adapted to retain therein the planar circuit and to be connected to test equipment. The body provides a transition between the planar circuit and the test equipment and comprises a base member having a first surface and a fixation member having a second surface and connected to the base member through a first connection allowing movement along a first axis of the fixation member relative to the base member, a spacing defined between the first surface and the second surface for retaining therein an end of the planar circuit, the fixation member movable along the first axis relative to the base member for adjusting the spacing. | 2013-12-19 |
20130335111 | EDDY CURRENT INSPECTION PROBE - A probe for transporting a nondestructive inspection sensor through a tube, that employs wheels to reduce friction. The radial travel of the wheels are mechanically linked through a cam and axially reciprocal plunger arrangement that centers the probe at tube diameter transitions. Internal wire bending is minimized and a dynamic seal is provided to facilitate an insertion force at the probe and reduce or eliminate compressive load buckling of the flexible cable carried by the probe. Like the wheel arrangement, radial travel of the seal segments are mechanically linked to provide probe centering. | 2013-12-19 |
20130335112 | DEVICE FOR TESTING ELECTRONIC COMPONENT DEVICES - A device for testing electronic component devices mounted on a substrate, having test pins which can be placed on contact surfaces of the substrate. A frame-like support structure is provided, which supports the substrate such that the individual component devices are located in open spaces of the support structure. | 2013-12-19 |
20130335113 | METHOD FOR IMPROVED TESTING OF TRANSISTOR ARRAYS - An electronic test system to evaluate the pixel and array properties of active-matrix displays that use charge or current sensitive circuits attached to the array data lines is described. Leakage-current, charging time, and other metrics can be measured for all pixels in the array without electrical or optical connection to the interior of the array. Charge or current sensitive amplifiers and selected voltage drivers may be used in conjunction with variable timing and voltages to determine individual transistor properties over an entire array in just a few seconds. Signals to be measured may be injected in several ways. Ultimately, an output signal for each pixel is measured. Thus, based on the output signal, the charging time or current, the leakage time or current, and other pixel or transistor parameters may be characterized for the entire array. | 2013-12-19 |
20130335114 | IMPLEMENTING LINEARLY WEIGHTED THERMAL CODED I/O DRIVER OUTPUT STAGE CALIBRATION - A method and circuit for implementing calibration of a linearly weighted, thermal coded I/O driver output stage, and a design structure on which the subject circuit resides are provided. The circuit includes a PFET calibration impedance matching function determining calibration PVTP bits for calibrating output stage PFETs of the linearly weighted, thermal coded I/O driver output stage, an NFET calibration impedance matching function determining calibration bits PVTN for calibrating output stage NFETs of the linearly weighted, thermal coded I/O driver output stage once the PFET calibration is complete and an output latch function providing the calibration PVTP and PVTN outputs for the I/O driver output stage to match an impedance of an external calibration resistor. A clock logic function generates an output latch clock and an internal reset signal completing calibration. | 2013-12-19 |
20130335115 | INTEGRATED CIRCUIT AND METHOD FOR OPERATING THE SAME - A integrated circuit includes a clock control signal generation circuit configured to generate a clock control signal using transition of a control signal, a clock control unit configured to activate a control clock in an activated period of the clock control signal, and to deactivate the control clock in a deactivated period of the clock control signal, and a control circuit configured to operate in response to the control signal and in synchronization with the control clock. | 2013-12-19 |
20130335116 | RECONFIGURABLE CIRCUIT AND METHOD FOR REFRESHING RECONFIGURABLE CIRCUIT - A reconfigurable circuit ( | 2013-12-19 |
20130335117 | PRE-DRIVER AND DIFFERENTIAL SIGNAL TRANSMITTER USING THE SAME - A pre-driver and a differential signal transmitter using the same are provided. The pre-driver includes a latch circuit and a driver buffer. The latch circuit includes latch units, first inverters, and second inverters. The latch units are coupled in series between a pair of differential input terminals and a pair of differential latch terminals, receive a pair of differential input signals through the pair of differential input terminals, and latch the pair of differential input signals according to a clock signal to provide a pair of differential latch signals through the pair of differential latch terminals. The first and second inverters are respectively coupled in series between the pair of differential latch terminals and a pair of differential output terminals. The driver buffer is coupled to the pair of differential output terminals to receive a pair of differential output signals, and accordingly provides a pair of differential pre-driver output signals. | 2013-12-19 |
20130335118 | ELECTRONIC DEVICE AND METHODE FOR IMPLEMENTING LOGIC FUNCTIONS AND FOR GUIDING CHARGED PARTICLES - A device and method are presented for implementing one or more logic functions. The device comprises one or more basic blocks, each comprising a predetermined number of charged particle inputs, at least one interaction zone defining a function space, and at least one charged particle output at a certain distance from the interaction zone. The logic function is a result of an affected interaction between the charged particles. | 2013-12-19 |
20130335119 | Bi-Directional Comparator - A bi-directional comparator compares two input signals and applies a hysteresis level to the smaller input signal only after the output signal switches logical states and when the two input signals are within a predetermined range of each other. In one embodiment, the hysteresis applied to the smaller input signal is removed when the two input signals are no longer within the predetermined range of each other. | 2013-12-19 |
20130335120 | SOURCE SERIES TERMINATED DRIVER CIRCUIT WITH PROGRAMMABLE OUTPUT RESISTANCE, AMPLITUDE REDUCTION, AND EQUALIZATION - A source-series terminated (‘SST’) driver circuit that includes: one or more data signal inputs; one or more control signal inputs; a driver output; and a plurality of driver cells, the driver cells coupled in parallel to one another, outputs of the driver cells coupled together to form the driver output of the SST driver circuit, where output resistance of the SST driver circuit varies in dependence upon activation of one or more of the parallel driver cells, activation of each driver cell controlled by control signals received at the control signal inputs. | 2013-12-19 |
20130335121 | ELECTRONIC SWITCH FOR LOW-VOLTAGE AND HIGH SWITCHING SPEED APPLICATIONS - An electronic switch may include transfer transistor having a first conduction terminal for receiving an input signal, a second conduction terminal, and a control terminal. The transfer transistor may enable/disable a transfer of the input signal from the first conduction terminal to the second conduction terminal according to a control signal. The control signal may take a first value and a second value different from the first value, a difference between the first value and the second value defining, in absolute value, an operative value of the control signal. The electronic switch may further comprise a driving circuit for receiving the input signal and the control signal, and for providing a driving signal equal to the sum between the input signal and the operative value of the control signal to the control terminal of the transfer transistor. | 2013-12-19 |
20130335122 | ELECTRONIC DEVICE, METHOD OF MANUFACTURING THE ELECTRONIC DEVICE, AND METHOD OF DRIVING THE ELECTRONIC DEVICE - An electronic device includes: a base member; a conductive film including a first end portion and a second end portion fixed to the base member, the conductive film being movable in a lateral direction of the base member between the first end portion and the second end portion; a first driving electrode, which is provided in the base member at a position opposed to a first main surface of the conductive film, and to which a first driving voltage is applied; a second driving electrode, which is provided in the base member at a position opposed to a second main surface of the conductive film, and to which a second driving voltage is applied; and a terminal provided in the base member at a position where the terminal enables to come into contact with the second main surface of the conductive film. | 2013-12-19 |
20130335123 | DRIVER IC CHIP AND PAD LAYOUT METHOD THEREOF - Provided is a driver IC chip of a liquid crystal display (LCD). The driver IC chip has a layout of power pads, which may uniformly apply an adhesive force on the entire adhesion surface of the driver IC chip, when the driver IC chip is mounted on a display panel according to a chip-on-glass (COG) technique. | 2013-12-19 |
20130335124 | DOWN CONVERTER AND CONTROL METHOD OF THE SAME - A down converter has two down converter circuits. The one down converter circuit has a first mixer, a first ½ frequency-divider, and a first PLL. The other down converter circuit has a second mixer, a second ½ frequency-divider, and a second PLL. A difference frequency between a frequency of a local oscillation frequency signal of the second PLL and a frequency of a frequency-divided signal of the first ½ frequency-divider is higher than an upper limit of a receive frequency band of a tuner. | 2013-12-19 |
20130335125 | INPUT SIGNAL PROCESSING DEVICE - An input signal processing device includes an oscillator circuit, a signal processing circuit, and a control circuit. The oscillator circuit performs an oscillation operation to output a clock signal. The signal processing circuit operates based on the clock signal outputted from the oscillator circuit. The signal processing circuit performs a predetermined process to an input signal when a level of the input signal changes and outputs a signal after the predetermined process. The control circuit instructs the oscillator circuit to start the oscillation operation based on a level change of the input signal. The control circuit instructs the oscillator circuit to stop the oscillation operation when the signal processing circuit finishes the predetermined process. | 2013-12-19 |
20130335126 | CLOCK GENERATOR - A clock generator includes a delay circuit to have 2N delays, in which a delay time from a first delay of the 2N delays to a last delay is set to a length of one cycle of an input; a first phase-detector to detect a first phase-difference between the input and an output from the last delay; a first charge-pump to generate a first current according to the first phase-difference; a first loop-filter to adjust a delay amount of each of the 2N delays, based on a voltage of the first current; a second phase-detector to detect a second phase-difference between the input and an output from an Nth delay; a second charge-pump to generate a second current according to the second phase-difference; and a second loop-filter to adjust a duty ratio of an output from each of the 2N delays, based on a voltage of the second current. | 2013-12-19 |
20130335127 | I/O DATA RETENTION DEVICE - An apparatus for controlling retention of data includes a logic circuit, a retention control cell circuit, and an I/O cell circuit. The logic circuit generates at least one retention enable signal before a chip enters a reduced power mode. The retention control cell circuit latches the retention enable signal and outputs a retention enable control signal based on a first power signal of the logic circuit and a detection result of a second power signal for input/output (I/O). And, the I/O cell circuit latches data based on the retention control signal. | 2013-12-19 |
20130335128 | SEQUENTIAL LATCHING DEVICE WITH ELEMENTS TO INCREASE HOLD TIMES ON THE DIAGNOSTIC DATA PATH - A latching device includes input and output latching elements to receive and output data values wherein the input and output elements are configured to receive a first and second clocks, respectively. The clocks have the same frequency but are inverted. The elements are transparent and transmit data between an input and an output in response to the first value of a received clock and are opaque and hold the data value in response to a second value of the received clock, such that in response to the first and second clocks the input data value is clocked through the input and output elements to the output. The device includes a device for selecting an operational data value or a diagnostic data value for input to the input element in response to a value of a diagnostic enable signal indicating a functional mode or a diagnostic mode. | 2013-12-19 |
20130335129 | Current Mode Logic Latch - A current mode logic latch may include a first hold stage transistor coupled at its drain terminal to the drain terminal of a first sample stage transistor. A second hold stage transistor is coupled at its drain terminal to the drain terminal of a second sample stage transistor, coupled at its gate terminal to the drain terminal of the first hold stage transistor, and coupled at its drain terminal to a gate terminal of the first hold stage transistor. A first hold stage current source is coupled to a source terminal of the first hold stage transistor. A second hold stage current source is coupled to a source terminal of the second hold stage transistor. The hold stage switch is coupled between the source terminal of the first hold stage transistor and the source terminal of the second hold stage transistor. | 2013-12-19 |
20130335130 | APPARATUS AND METHOD FOR PROVIDING TIMING ADJUSTMENT OF INPUT SIGNAL - An apparatus for providing time adjustment of an input signal includes a coarse timing digital-to-analog converter (DAC), a replica delay element and an interpolator. The coarse timing DAC has multiple delay settings for providing a coarse timing adjustment of the input signal, and outputs a first delayed signal by delaying the input signal by a first delay time corresponding to a selected setting of the multiple delay settings. The replica delay element receives the first delayed signal from the coarse timing DAC and outputs a second delayed signal by delaying the first delayed signal by a predetermined second delay time. The interpolator blends either the input signal and the first delayed signal or the first delayed signal and the second delayed signal for providing a fine timing adjustment of the input signal, and outputs a timing adjusted output signal including the coarse timing adjustment and the fine timing adjustment. | 2013-12-19 |
20130335131 | System and Method for a Switched Capacitor Circuit - In an embodiment, a circuit includes a forward path circuit having an auto-zero switch coupled between an input of an amplifier and an output of the amplifier, a first chopping circuit having an input coupled to an input of the forward path circuit and an output coupled to the input of the amplifier, and a second chopping circuit having an input coupled to the output of the amplifier and an output coupled to an output of the forward path circuit. The circuit further includes a feedback circuit that has a feedback switch, a feedback capacitor including a first end coupled to an output of the amplifier, a third chopping circuit coupled between the input of the forward path circuit and a first end of a feedback switch, and a fourth chopping circuit coupled between a second end of the feedback switch and a second end of the feedback capacitor. | 2013-12-19 |
20130335132 | CIRCUIT SHARING TIME DELAY INTEGRATOR - The present invention discloses a circuit sharing time delay integrator structure. The major composing elements of this circuit sharing time delay integrator structure are: a sharing circuit, a first control block, a plurality of second control blocks and a timing set generated by a timing generator circuit. The sharing circuit can be an OP-AMP, an active load, or any of a variety of combinations used in signal accumulation applications. With the implementation of the present invention to applications of signal accumulations, the necessity of an adder circuitry is eliminated, the overall circuitry and hence the total amount of transistors required when producing the integrated circuit is massively reduced, and thus a great cost reduction and better timing and power efficiency can all be thereof achieved. | 2013-12-19 |
20130335133 | Power Switch Acceleration Scheme for Fast Wakeup - A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup. | 2013-12-19 |
20130335134 | SEMICONDUCTOR DEVICE AND SYSTEM USING THE SAME - There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state. | 2013-12-19 |
20130335135 | CALIBRATION CIRCUIT, INTEGRATED CIRCUIT HAVING CALIBRATION CIRCUIT, AND CALIBRATION METHOD - A calibration circuit for calibrating a device to be calibrated includes a variable current generator, a device under test and a control unit. The variable current generator is coupled to a first node of a reference voltage and configured to generate a variable current responsive to variations of the reference voltage. The device under test is a copy of at least one portion of the device to be calibrated, and coupled to the variable current generator to derive, at a second node, a voltage dependent on the variable current. The control unit is coupled to the second node to receive the derived voltage and configured to compare the derived voltage with the reference voltage and to generate, based on a comparison result, at least one calibration signal for adjusting an adjustable electrical parameter of the device under test and the device to be calibrated. | 2013-12-19 |
20130335136 | TEMPERATURE COMPENSATION CIRCUIT - A temperature compensation circuit is disclosed. A temperature compensation circuit may include a temperature coefficient generator configured to generate a first signal and a second signal, wherein the first signal is proportional-to-absolute-temperature (ptat) and the second signal is negatively-proportional-to-absolute-temperature (ntat), a first programmable element configured to multiply at a first programmable ratio an amplitude of a third signal having a negative temperature coefficient from a first temperature to a second temperature, and a second programmable element configured to multiply at a second programmable ratio an amplitude of a fourth signal having a positive temperature coefficient from the second temperature to a third temperature. | 2013-12-19 |
20130335137 | ELECTRONIC SYSTEMS, SLAVE ELECTRONIC DEVICES AND SIGNAL TRANSMISSION METHODS - A slave electronic device is provided, including a capture unit, at least one low-speed unit and an embedded control unit. The capture unit is coupled to a host electronic device through a transmission lane to filter out a high-frequency signal part from a control signal outputted by the host electronic device to generate a low-frequency control signal, wherein the control signal has a plurality of periods and the control signal respectively has a low-frequency signal part and the high-frequency signal part during odd periods and even periods of the periods. The low-speed unit is coupled to the capture unit to operate according to the low-frequency control signal. The embedded control unit is coupled to the transmission lane for communicating with the host electronic device using a predetermined communications protocol via the high-frequency signal part. | 2013-12-19 |
20130335138 | SIGNAL PROCESSING APPARATUS AND SIGNAL PROCESSING METHOD - Digital signals with higher resolution are generated from dual-phase encode signals indicating phase changes of a position or an angle of a target. A signal processing apparatus for processing dual-phase encode signals indicating changes in position of a target, comprises: a first noise reduction unit configured to remove high frequency noise from each of the dual-phase encode signals before interpolation processing; an interpolating unit configured to apply interpolation processing to the dual-phase encode signals output from the first noise reduction unit to generate dual-phase encode signals with higher resolution; and a second noise reduction unit configured to remove noise from the dual-phase encode signals output from the interpolating unit. | 2013-12-19 |
20130335139 | Isolator Circuit - An isolator circuit ( | 2013-12-19 |
20130335140 | AMPLIFICATION DEVICE AND AMPLIFICATION METHOD - An amplification device includes a first filter configured to pass a predetermined frequency component of a first digital signal phase-modulated with a constant amplitude; a first distortion compensator configured to compensate the signal output from the first filter in advance for distortion occurring in an amplified signal, based on a first distortion compensation coefficient dependent on an amplitude of the signal output from the first filter; a first converter configured to convert the signal compensated by the first distortion compensator into a first analog signal; and a first amplifier configured to amplify the first analog signal. | 2013-12-19 |
20130335141 | APPARATUS AND METHODS FOR ELECTRONIC AMPLIFICATION - Apparatus and methods for electronic amplification are provided. In one embodiment, a method of electronic amplification includes amplifying a differential input voltage signal to generate a feed-forward signal, chopping the feed-forward signal at a chopping frequency to generate a chopped feed-forward signal, notch filtering the chopped feed-forward signal at the chopping frequency to generate a notched signal, generating an input offset correction signal based at least partly on the notched signal, and amplifying the differential input voltage signal using a signal amplification block to generate an output signal. Amplifying the differential input voltage signal using the signal amplification block includes chopping the input signal at the chopping frequency to generate a chopped input signal and combining the chopped input signal and the offset correction signal to reduce input offset error of the signal amplification block. | 2013-12-19 |
20130335142 | METHOD AND APPARATUS FOR DECREASING POWER CONSUMPTION OF POWER AMPLIFIER - Embodiments of the present invention relate to the communication field and disclose a method and an apparatus for decreasing power consumption of a power amplifier, which minimize the power consumption of the power amplifier and extend the operation time of a mobile terminal. The method includes: obtaining a compensation power control value, where the compensation power control value is a power control value that is input to the power amplifier, and the minimum value of the input voltage is a minimum input voltage that can guarantee normal operation of the power amplifier when a preset power control value is input to the power amplifier; and inputting the minimum value of the input voltage and the compensation power control value to the power amplifier to control the power amplifier to output the preset power value of the antenna port. | 2013-12-19 |
20130335143 | CLASS-D POWER AMPLIFIER CAPABLE OF REDUCING ELECTROMAGNETIC INTERFERENCE AND TRIANGULAR WAVE GENERATOR THEREOF - A class-D power amplifier capable of reducing electromagnetic interference includes an integrator, a triangular wave generator, a comparator, a gate driver, a feedback circuit, and an output stage circuit. The integrator is used for receiving an input signal and potential of ground, and outputting a first voltage. The comparator is used for comparing the first voltage with a triangular wave generated by the triangular wave generator to output a pulse-width modulation signal. The gate driver is used for driving the output stage circuit to output an output voltage according to the pulse-width modulation signal. Therefore, the class-D power amplifier reduces the electromagnetic interference by the triangular wave. | 2013-12-19 |
20130335144 | APPARATUS AND METHODS FOR NOTCH FILTERING - Apparatus and methods for notch filtering are provided. In certain implementations, an amplifier includes amplification stages for providing signal amplification, chopper circuitry for generating a chopped signal by chopping an amplified signal associated with the amplification stages at a chopping frequency, and a time-interleaved finite impulse response (FIR) notch filter for notching frequency components of the chopped signal near the chopping frequency. The time-interleaved FIR notch filter includes a plurality of FIR filters configured to sample the chopped signal at a sampling rate of about twice the chopping frequency. The FIR filters are interleaved in time to reduce sampling error. Additionally, the time-interleaved FIR notch filter includes an infinite impulse response (IIR) filter configured to average samples taken by respective ones of the FIR filters and to integrate the averaged samples to generate the time-interleaved FIR notch filter's output signal. | 2013-12-19 |
20130335145 | HIGH-SPEED TRANSIMPEDANCE AMPLIFIER - A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to be coupled to an input signal. A second inverter has a second input node and a second output node. The second input node is configured to receive a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. | 2013-12-19 |
20130335146 | GAIN CONTROL CIRCUIT, COMMUNICATION DEVICE, ELECTRONIC APPLIANCE, AND GAIN CONTROL METHOD - The present technology relates to a gain control circuit, a communication device, an electronic appliance, and a gain control method which aim to provide a technology capable of suppressing intermodulation distortion. The gain control circuit includes a first amplifier for amplifying an input signal, and a signal determination unit for determining an input signal to be input to the first amplifier, and controlling an amplification factor of the first amplifier based on the determination result. The communication device includes a first amplifier for amplifying a received signal, a receiving unit for performing a receiving process based on a signal output from the first amplifier, and a signal determination unit for determining a received signal to be input to the first amplifier, and controlling the amplification factor of the first amplifier based on the determination result. In the gain control method, an input signal to be input to a first amplifier for amplifying an input signal is determined, and the amplification factor of the first amplifier is controlled by a feed forward system based on the determination result. | 2013-12-19 |
20130335147 | Power Amplifier and Linearization Techniques Using Active and Passive Devices - Designs and techniques for improving the linearity of the power amplifiers, especially of the non-linear types, operated in microwave and millimeter-wave frequency using method through purposely designed active transistors or passive devices or both, are disclosed. The techniques use the manipulation of transistors' cut-off frequencies (fT) design, attached loaded linearization stub and characteristics of space attenuation of microwave signals individually or in combination of them. The disclosed techniques provide the advantages to compromise the performance among linearity, gain and power consumption in a wide range of power amplifier types, such as Class- AB, B, C, D, E and F in the different application scenarios. | 2013-12-19 |
20130335148 | OSCILLATION FREQUENCY ADJUSTING CIRCUIT - According to one embodiment, a first oscillator has an oscillation frequency that is changed depending on a temperature. A second oscillator has different temperature characteristics from the first oscillator. An on-chip heater heats the first oscillator and the second oscillator. A counter counts a first oscillation signal of the first oscillator. An ADPLL generates a third oscillation signal on the basis of a second oscillation signal of the second oscillator and corrects the frequency of the third oscillation signal on the basis of a count value of the counter. | 2013-12-19 |
20130335149 | THE EFFICIENCY OF CLIPPED PULSE GENERATION - The disclosed embodiments provide a resonant oscillator circuit. The resonant oscillator circuit includes a clipping mechanism configured to clip an output voltage of a signal pulse generated by the resonant oscillator circuit to a predefined constant level. The resonant oscillator circuit also includes a feedback path configured to return energy from the clipping mechanism to an input of the resonant oscillator circuit. | 2013-12-19 |
20130335150 | PHASE-LOCKED LOOP (PLL) CIRCUIT AND COMMUNICATION APPARATUS - According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal. | 2013-12-19 |
20130335151 | SPREAD SPECTRUM CLOCKING METHOD FOR WIRELESS MOBILE PLATFORMS - According to some embodiments, a method and apparatus are provided to vary a clock signal frequency for a first time period between a lower limit of a range of problematic frequencies and a frequency lower than the lower limit, and vary the clock signal frequency for a second period of time between an upper limit of the range of problematic frequencies and a frequency greater than the upper limit. | 2013-12-19 |
20130335152 | Dynamic Level Shifter Circuit and Ring Oscillator Using the Same - A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters. | 2013-12-19 |
20130335153 | OSCILLATOR AND IC CHIP - There is provided an oscillator capable of lowering the power supply voltage without degrading the phase noise, while employing the conventional circuit configuration. According to one aspect of the present invention, there is provided an oscillator comprising: an oscillation circuit; a bias generation circuit for generating a bias signal to drive the oscillation circuit; and a booster circuit for boosting a power supply voltage to generate a boosted voltage for driving the bias generation circuit. In addition, the oscillation circuit, the bias generation circuit, and the booster circuit are provided in a single IC chip, and the booster circuit may receive the power supply voltage VDD from the power supply arranged at the exterior of the IC chip. | 2013-12-19 |
20130335154 | Frequency Stabilization of An Atomic Clock Against Variations of the C-Field - The frequency of an atomic clock may be stabilized against C-field variation by applying a rf magnetic field perpendicular to the C-field to cause a coherent population transfer between Zeeman states that compensates for quadratic frequency shift of transitions of the clock. The cancellation, provided by a feed-forward mechanism, is exact. The invention can be implemented in any atomic clock by including an electrode in the clock generating a magnetic field perpendicular to the C-field, and providing an electronic circuit to send rf signals to the electrode. | 2013-12-19 |
20130335155 | SURFACE-EMITTING LASER ELEMENT, ATOMIC OSCILLATOR, AND SURFACE-EMITTING LASER ELEMENT TESTING METHOD - A disclosed surface-emitting laser element includes a lower DBR formed on a substrate, an active layer formed on the lower DBR, an upper DBR formed on the active layer, a wavelength-adjusting layer formed above the active layer, and a plurality of surface-emitting lasers configured to emit respective laser beams having different wavelengths by changing a thickness of the wavelength-adjusting layer. In the surface-emitting laser element, the wavelength-adjusting layer includes one of a first film having alternately layered GaInP and GaAsP and a second film having alternately layered GaInP and GaAs, the thickness of the wavelength-adjusting layer being changed by partially removing each of the alternating layers of a corresponding one of the first and second films. | 2013-12-19 |
20130335156 | OSCILLATOR COMPRISING AN RC-CIRCUIT AND A PUSH-PULL STAGE AND ELECTRONIC DEVICE COMPRISING THE OSCILLATOR - Oscillator and electronic device comprising an oscillator, wherein the oscillator has an RC-circuit and a push-pull stage. A tapping point of the RC-circuit is coupled to an input of the push-pull stage and an output of the push-pull stage is fed back to a switching transistor which is coupled to the tapping point of the RC-circuit. | 2013-12-19 |
20130335157 | RESONATING ELEMENT, RESONATOR, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING BODY - A resonating element includes a resonator element that includes a vibrating portion and an excitation electrode provided on both main surfaces of the vibrating portion, an intermediate substrate in which the resonator element is mounted so as to be spaced from the excitation electrode, and a spiral electrode pattern that is provided on at least one main surface of the intermediate substrate, in which the electrode pattern is electrically connected to the excitation electrode. | 2013-12-19 |
20130335158 | CRYSTAL OSCILLATOR WITH REDUCED ACCELERATION SENSITIVITY - A crystal oscillator having a plurality of quartz crystals that are manufactured so that the directional orientation of the acceleration sensitivity vector is essentially the same for each crystal. This enables convenient mounting of the crystals to a circuit assembly with consistent alignment of the acceleration vectors. The crystals are aligned with the acceleration vectors in an essentially anti-parallel relationship and can be coupled to the oscillator circuit in either a series or parallel arrangement. Mounting the crystals in this manner substantially cancels the acceleration sensitivity of the composite resonator and oscillator, rendering it less sensitive to vibrational forces and shock events. | 2013-12-19 |
20130335159 | ELECTRONIC COMPONENT - An electronic component includes a laminate including a plurality of insulator layers and a mounting surface. The mounting surface is defined by the outer edges of the plurality of insulator layers that are continuously joined together. An LC parallel resonator is embedded in the laminate, and includes a coil and a capacitor. An unbalanced signal is inputted to the LC parallel resonator. A coil is embedded in the laminate. The coil is electromagnetically coupled to the coil, and outputs balanced signals. Outer electrodes are provided on the mounting surface, and are grounded. A ground conductor layer of the capacitor is connected to an outer electrode by extending to the mounting surface. | 2013-12-19 |
20130335160 | ANTENNA SWITCHING CIRCUITRY - This disclosure relates to antenna switching circuitry and other radio frequency (RF) front-end circuitry. In one embodiment, the antenna switching circuitry includes a multiple throw solid-state transistor switch (MTSTS) and a multiple throw microelectromechanical switch (MTMEMS). The MTSTS is configured to selectively couple a first pole port to any one of a first set of throw ports and to selectively couple a second pole port to any one of a second set of throw ports. The MTMEMS is configured to selectively couple a third pole port to any one of a third set of throw ports. The third pole port of the MTMEMS is coupled to a first throw port in the first set of throw ports and a second throw port in the second set of throw ports of the MTSTS. Accordingly, the MTSTS is capable of routing multiple RF signals to and from the MTMEMS. | 2013-12-19 |
20130335161 | ANTENNA SWITCHING CIRCUITRY FOR MIMO/DIVERSITY MODES - This disclosure relates to antenna switching circuitry and other radio frequency (RF) front-end circuitry. In one embodiment, the antenna switching circuitry includes a multiple throw solid-state transistor switch (MTSTS), a multiple throw microelectromechanical switch (MTMEMS), and a control circuit. The MTSTS is configured to selectively couple a first pole port to any one of a first set of throw ports and to selectively couple a second pole port to any one of a second set of throw ports. The MTMEMS is configured to selectively couple a third pole port to any one of a third set of throw ports. The control circuit is configured to control the selective coupling of the MTSTS and the MTMEMS. In this manner, the control circuit may operate the antenna switching circuitry so that RF signals may be routed in accordance with Long Term Evolution (LTE) Multiple-Input and Multiple-Output (MIMO) and/or LTE diversity specifications. | 2013-12-19 |
20130335162 | INNER CONNECTING ELEMENT OF A CAVITY POWER DIVIDER, CAVITY POWER DIVIDER AND MANUFACTURING METHOD THEREOF - Embodiments of the present disclosure disclose an inner connecting element of a cavity power divider, the cavity power divider and a manufacturing method thereof Two ends of the inner connecting element of the cavity power divider are respectively an input end and an output end, and the inner connecting element of the cavity power divider is in a sheet form. The cavity power divider comprises a cavity and at least three connectors. The cavity is provided with one connector at an input end thereof and with at least two connectors at an output end thereof The connecting element is included in the cavity, with the input end and the output end of the connecting element being connected respectively with the connectors at the input end and the output end of the cavity. | 2013-12-19 |
20130335163 | METHODS AND APPARATUSES FOR IMPLEMENTING VARIABLE BANDWIDTH RF TRACKING FILTERS FOR RECONFIGURABLE MULTI-STANDARD RADIOS - A variable bandwidth filter comprises a first filter branch in parallel with a second filter branch. The first filter branch comprises a first resistance in series with an input and a first output, and N parallel paths across the first output, each path comprising a corresponding capacitor in series with a corresponding switch and a common terminal. The second filter branch comprises a second resistance in series with the input and a second output, and N parallel paths across the second output, each path comprising an RC network in series with a switch and a common terminal. A clock tunes the first and second filter branches to a center frequency by controlling the switches of the first and second filter branches. A combiner produces a difference signal comprising a difference between the output of the first filter branch and the output of the second filter branch to provide a filter output having an adjustable bandwidth with reference to a center frequency. The bandwidth is adjusted by changing a value of at least one resistor or at least one capacitor in one or more of the first filter branch or the second filter branch. | 2013-12-19 |
20130335164 | FILTER ARRANGEMENT AND METHOD FOR PRODUCING A FILTER ARRANGEMENT - The invention relates to a filter arrangement ( | 2013-12-19 |
20130335165 | Waveguide Busbar - A waveguide busbar for converting a plurality of high-frequency input signals into high-frequency output signals, includes a waveguide, a plurality of input ports, which are arranged along the waveguide, such that each input port is intended to receive a high-frequency input signal, an output port on the waveguide for delivering the high-frequency output signal and at least one parallel resonator, which is connected to the waveguide busbar between two input ports. The parallel resonator has a mechanically adjustable volume with which a phase relation of the waveguide is adjustable between the two input ports. | 2013-12-19 |
20130335166 | DEVICES HAVING A TUNABLE ACOUSTIC PATH LENGTH AND METHODS FOR MAKING SAME - A tunable acoustic resonator device has a piezoelectric medium as a first thin film layer and a tunable crystal medium as a second thin film layer. The tunable crystal medium has a first acoustic behavior over an operating temperature range under a condition of relatively low applied stress and a second acoustic behavior under a condition of relatively high applied stress. The acoustic behaviors are substantially different and, consequently, the different levels of applied stress are used to tune the acoustic resonator device. Compared with the tunable resonator device consisting of only tunable crystal medium, a device having both the piezoelectric and tunable crystal medium has advantages such as larger inherent bandwidth and less nonlinearity with AC signals. The device also requires a smaller applied stress (i.e. bias voltage) to achieve the required frequency tuning. | 2013-12-19 |
20130335167 | DE-NOISE CIRCUIT AND DE-NOISE METHOD FOR DIFFERENTIAL SIGNALS AND CHIP FOR RECEIVING DIFFERENTIAL SIGNALS - A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value. | 2013-12-19 |
20130335168 | RF Device and Method for Tuning an RF Device - An RF device includes a substrate and a series circuit of a tunable RF component and a DC blocking capacitor. The series circuit is arranged on the substrate and couples an RF signal terminal to a fixed voltage terminal that is electrically isolated from the RF signal terminal. The tunable RF component is coupled to the RF signal terminal, the DC blocking capacitor is coupled to the fixed voltage terminal and a driver terminal is coupled to the tunable RF component. | 2013-12-19 |
20130335169 | Optimal Acoustic Impedance Materials for Polished Substrate Coating to Suppress Passband Ripple in BAW Resonators and Filters - A bulk acoustic wave (BAW) resonator is constructed to reduce phase and amplitude ripples in a frequency response. The BAW resonator is fabricated on a substrate 400 μm thick or less, preferably approximately 325 μm, having a first side and a polished second side with a peak-to-peak roughness of approximately 1000 A. A Bragg mirror having alternate layers of a high acoustic impedance material, such as tungsten, and a low acoustic impedance material is fabricated on the first side of the substrate. A BAW resonator is fabricated on the Bragg mirror. A lossy material, such as epoxy, coats the second side of the substrate opposite the first side. The lossy material has an acoustic impedance in the range of 0.01× to 1.0× the acoustic impedance of the layers of high acoustic impedance material. | 2013-12-19 |
20130335170 | ACOUSTIC WAVE ELEMENT AND ACOUSTIC WAVE DEVICE USING SAME - A SAW element has a substrate, electrode fingers on an upper surface of the substrate, and mass-adding films on upper surfaces of the electrode fingers. When viewing the cross-sections perpendicular to the extending directions of the electrode fingers, the mass-adding films have the narrowest widths at an upper sides in the cross-sections. By arranging the mass-adding films having such shape on the upper surfaces of the electrode fingers, the electromechanical coupling factor can be made high. | 2013-12-19 |
20130335171 | ELECTRONIC COMPONENT - An electronic component includes a support layer that surrounds an element region on a principal surface of a piezoelectric substrate, when viewed in plan from a z-axis direction. A surface acoustic wave element is provided in the element region. A cover layer is provided on the support layer, and is opposed to the principal surface. A pillar member connects the principal surface and the cover layer in a space surrounded by the principal surface, the support layer, and the cover layer, and does not contact with the support layer. | 2013-12-19 |
20130335172 | ACOUSTIC WAVE FILTER - An acoustic wave filter has a first signal line connecting one among the plurality of first IDT electrodes and the first balanced signal terminal; a second signal line connecting the other first IDT electrode with the second balanced signal terminal; a third signal line connecting one among the plurality of second IDT electrodes with the second balanced signal terminal; and a fourth signal line connecting the other second IDT electrode with the first balanced signal terminal. The fourth signal line has an intersection portion three-dimensionally intersecting with a part of the second signal line. The intersection portion extends in a direction inclined relative to the second signal line on the major surface. | 2013-12-19 |
20130335173 | TUNABLE CAVITY RESONATOR - A tunable cavity resonator includes a housing, a post, and a controllably variable capacitive coupling. The housing defines an interior and has at least one side wall, a first end, and a second end. The post is located within the interior and extends from the first end to the second end. The post and the housing define a resonating cavity. The controllably variable capacitive coupling is disposed in the housing. | 2013-12-19 |
20130335174 | ELETROMAGNETIC OPENING/CLOSING DEVICE - An electromagnetic opening/closing device A | 2013-12-19 |
20130335175 | CONTACT MECHANISM AND ELECTROMAGNETIC CONTACTOR USING THE SAME - A contact mechanism where a shape of at least one of a fixed contactor including a pair of fixed contact portions and a movable contactor including a pair of movable contact portions capable of contacting with and separating from the pair of fixed contact portions is set to a shape that generates a Lorentz force resisting electromagnetic repulsion in a contactor opening direction generated between the fixed contact portions and the movable contact portions when a current is applied, has the fixed contactor and the movable contactor being inserted in a current path. Magnetic bodies are disposed on at least one of the fixed contactor and the movable contactor for suppressing a force driving arcs, which are generated between the pair of fixed contact portions and the pair of movable contact portions, to the fixed contactor on the opposite side. | 2013-12-19 |
20130335176 | ELECTROMAGNETIC SWITCHING DEVICE - Disclosed is an electromagnetic switching device. The electromagnetic switching device includes a case defining an outer appearance; a fixed contact point assembly received in the case and including a fixed contact point; a coil terminal assembly detachably coupled to one side of the fixed contact point assembly and including a coil; and a shaft assembly detachably inserted into the coil terminal assembly, wherein the shaft assembly includes a shaft movable in the coil terminal assembly. | 2013-12-19 |
20130335177 | CONTACT DEVICE - An electromagnet device is configured to generate a magnetic attractive force between a stationary core and a movable core when electricity is applied to a coil, so that the movable core is moved in a direction for coming into contact with the stationary core, and a movable shaft is moved in a direction in which a first end face of the movable shaft separates from a movable terminal. After the movable contact comes in contact with the fixed contact, the movable core moves further in a direction for coming into contact with the stationary core. A yoke made of a magnetic body is disposed between the movable terminal and the first end of the movable shaft. | 2013-12-19 |
20130335178 | DYNAMICALLY BIASED INDUCTOR - An inductor apparatus includes an inductor winding, a core defining a magnetic circuit for a magnetic flux generated by a current flowing through the inductor winding, at least one permanent magnet magnetically biasing the core by its permanent magnetization, and a magnetization device operable for adjusting a desired magnetization of the permanent magnet. The at least one permanent magnet is arranged within the magnetic circuit of the magnetic flux generated by the current flowing through the inductor winding. The magnetization device includes a magnetization winding and a circuitry configured to subject the magnetization winding to magnetization current pulses, thereby generating at a location of the permanent magnet a magnetic field which is able to change the permanent magnetization of the permanent magnet. | 2013-12-19 |
20130335179 | HIGH-CORROSION RESISTANT SINTERED NDFEB MAGNET AND PREPARATION METHOD THEREFOR - High corrosion resistant sintered NdFeB magnets are provided with a composition by mass % of Nd | 2013-12-19 |
20130335180 | RARE EARTH MAGNET AND PROCESS FOR PRODUCING SAME - A process for producing a rare earth magnet comprises: an adhesion step of causing a diffusion element capable of diffusing inwardly to adhere to the surface part of a magnet material comprising a compact or sintered body of rare earth alloy particles; and an evaporation step of heating the magnet material in vacuum to evaporate at least a portion of the diffusion element having been retained on or in the surface part of the magnet material. | 2013-12-19 |
20130335181 | COIL ASSEMBLY FOR A CONTROL ROD DRIVER HAVING IMPROVED THERMAL RESISTANCE, AND METHOD FOR MANUFACTURING THE SAME - Provided is a coil assembly having improved heat resistance for use in a control rod driver, in which the heat resistance of coils is improved to increase the lifespan thereof and the deterioration of the coils and the fall of a control rod are thus securely prevented from occurring due to continuous operations of the control rod driver during an automatic load follow operation, thereby improving the safety and economic feasibility of a nuclear power plant, and a method for manufacturing the same. The coil assembly includes a covered wire ( | 2013-12-19 |
20130335182 | RADIO FREQUENCY TRANSMISSION LINE TRANSFORMER - Radio frequency (RF) transmission line transformers are disclosed. Unlike conventional transformers that employ magnetic cores that transmit energy from input to output through magnetic flux linkages, the embodiments of the RF transmission line transformer disclosed herein transfer energy by configuring transformer coils as balanced transmission lines. More specifically, the RF transmission line transformers have a primary transformer coil that forms at least one primary winding and a secondary transformer coil that forms at least a pair of secondary windings. The primary winding of the primary transformer coil is disposed between the pair of secondary windings so that the primary winding forms a different balanced transmission line with each one of the pair of secondary windings. This results in greater bandwidth and higher transformer power efficiency (TPE) at RF frequencies. Furthermore, the arrangement allows for reduced parasitic inductances and capacitances and thus is particularly advantageous when utilized in laminated substrates. | 2013-12-19 |
20130335183 | METHOD FOR MAKING AN ELECTRICAL INDUCTOR AND RELATED INDUCTOR DEVICES - A method is for making an electrical inductor. The method includes forming a first subunit having a sacrificial substrate, and an electrically conductive layer defining the electrical inductor and including a first metal on the sacrificial substrate. The method includes forming a second subunit having a dielectric layer and an electrically conductive layer thereon defining electrical inductor terminals and having the first metal, and coating a second metal onto the first metal of one of the first and second subunits. The method includes aligning the first and second subunits together, heating and pressing the aligned first and second subunits to form an intermetallic compound of the first and second metals bonding adjacent metal portions together, and removing the sacrificial substrate. | 2013-12-19 |
20130335184 | MULTI-LAYERED CHIP ELECTRONIC COMPONENT - There is provided a multi-layered chip electronic component including: a multi-layered body including a 2016-sized or less and a plurality of magnetic layers; conductive patterns electrically connected in a stacking direction to form coil patterns, within the multi-layered body; and non-magnetic gap layers formed over a laminated surface of the multi-layered body between the multi-layered magnetic layers and having a thickness Tg in a range of 1 μm≦Tg≦7 μm, wherein the number of non-magnetic gap layers may have the number of gap layers in a range between at least four layers among the magnetic layers and a turns amount of the coil pattern. | 2013-12-19 |
20130335185 | MULTI-LAYERED CHIP ELECTRONIC COMPONENT - There is provided a multi-layered chip electronic component, including: a multi-layered body including a plurality of first magnetic layers on which conductive patterns are formed; and second magnetic layers interposed between the first magnetic layers within the multi-layered body, wherein the conductive patterns are electrically connected to form coil patterns in a stacking direction, and when a thickness of the second magnetic layer is defined as Ts and a thickness of the conductive pattern is defined as Te, 0.1≦Ts:Te≦0.3 is satisfied. | 2013-12-19 |
20130335186 | ELECTROMAGNETIC COMPONENT AND FABRICATION METHOD THEREOF - An electromagnetic component includes a coil portion with a multi-layer stack structure, a molded body encapsulating the coil portion, and two electrodes respectively coupled to two terminals of the coil portion. The coil portion is fabricated using plating, laminating and/or pressing manufacturing techniques. | 2013-12-19 |
20130335187 | CIRCUIT PROTECTION DEVICE - A circuit protection device includes a conductive layer which is connected to first and second terminals. A spring is electrically connected to the first and second terminals. When an over-voltage or over-temperature condition occurs within a charging circuit, one or more heat generating resistive elements melts material associated with one or more of the ends of the spring thereby releasing the spring to create an open circuit. | 2013-12-19 |
20130335188 | Safety Fuse Arrangement - A safety fuse arrangement may include at least a first safety fuse element and a second safety fuse element electrically connected to each other in parallel. The safety fuse arrangement further comprises a ceramic fuse body having at least a first locating space for locating and holding the first safety fuse element and a second locating space for locating and holding the second safety fuse element. The locating spaces are physically separated from each other by the fuse body. In this way, a compact safety fuse arrangement comprising a plurality of safety fuse elements which are electrically connected to each other in parallel can be realized as a structural unit that is inexpensive to manufacture and is suitable for higher rated currents. | 2013-12-19 |
20130335189 | COMPONENT WITH COUNTERMEASURE AGAINST STATIC ELECTRICITY AND METHOD OF MANUFACTURING SAME - An electrostatic discharge (ESD) protector includes a first high heat-conductive substrate, a second high heat-conductive substrate, a varistor layer, and a plurality of via-hole electrodes. The first high heat-conductive substrate is provided with a plurality of first through-holes. The second high heat-conductive substrate is provided with a plurality of second through-holes. The varistor layer that is mainly composed of zinc oxide is disposed between the first high heat-conductive substrate and the second high heat-conductive substrate. The varistor layer includes internal electrodes. Each of via-hole electrodes penetrates the varistor layer and fills both one of the first through-holes and one of the second through-holes to couple both the ones to each other. | 2013-12-19 |
20130335190 | TUNABLE RESISTANCE COATINGS - A method and article of manufacture of intermixed tunable resistance composite materials. A conducting material and an insulating material are deposited by such methods as ALD or CVD to construct composites with intermixed materials which do not have structure or properties like their bulk counterparts. | 2013-12-19 |