51st week of 2015 patent applcation highlights part 42 |
Patent application number | Title | Published |
20150363269 | ERASURE CODING AND REPLICATION IN STORAGE CLUSTERS - A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated. | 2015-12-17 |
20150363270 | CONVEYING VALUE OF IMPLEMENTING AN INTEGRATED DATA MANAGEMENT AND PROTECTION SYSTEM - A system and method are described for conveying to a user the value it would receive by implementing an integrated system to protect and manage its data. An integrated system can combine archiving, backup, snapshot management, reporting, secure data access, eDiscovery and data analytics, among other functions, thus simplifying data protection and data management for an organization. The system generates a value dashboard, exhibiting value data, including data and graphics portraying the benefits to a user of implementing an integrated data management and protection system. Value may be evaluated with reference to simplification and efficiency, risk reduction, and unlocking data value. | 2015-12-17 |
20150363271 | RESTORING DATA IN A HIERARCHICAL STORAGE MANAGEMENT SYSTEM - The present disclosure provides a hierarchical storage management system for storing data. A first controller receives a request to migrate a data item to a first storage tier. The data item is associated with at least an initial object ID. The first controller, in response to the request, generates a new object ID and identifies a first record in a data structure, wherein the initial object ID is identical to an object ID of the first record and to a parent object ID of the first record. The first controller replaces the object ID of the first record with the new object ID, creates in the data structure a new record that is associated with the data item, sets an object ID of the new record and a parent object ID of the new record to the initial object ID, and stores the data item to the first storage tier. | 2015-12-17 |
20150363272 | COMPUTING SYSTEM WITH ADAPTIVE BACK-UP MECHANISM AND METHOD OF OPERATION THEREOF - A computing system includes: an adaptive back-up controller configured to calculate an adaptive back-up time based on a reserve power source for backing up a volatile memory to a nonvolatile memory; and a processor core, coupled to the adaptive back-up controller, configured to back up at least a portion of the volatile memory to the nonvolatile memory within the adaptive back-up time. | 2015-12-17 |
20150363273 | CONTROL DEVICE AND METHOD FOR CONTROLLING STORAGE DEVICES - A control device includes a processor configured to copy a part of data stored in a first volume to a second volume, copy whole data stored in the first volume to a destination volume, and receive a request to read first data stored in the second volume. The processor is configured to read the first data from the second volume when the first data has been partially copied to the second volume. The processor is configured to read, when the first data has not been partially copied to the second volume, the first data from the first volume on basis of association information associating the first volume with the second volume. The processor is configured to identify, upon failing to read the first data from the first volume, the equivalent volume on basis of recovery information related to the destination volume as an equivalent volume of the first volume. | 2015-12-17 |
20150363274 | STORING BACKUP DATA SEPARATE FROM CATALOG DATA - Techniques for storing backup data separate from catalog data are described in various implementations. An example method that implements the techniques may include receiving backup data that is to be backed up on a tape medium. The method may also include causing the backup data to be written to a first tape medium. The method may also include generating catalog data associated with the backup data, the catalog data including position information indicating where the backup data is stored on the first tape medium. The method may also include causing the catalog data to be written to a second tape medium that is different from the first tape medium. | 2015-12-17 |
20150363275 | TECHNIQUES FOR IMPROVING CLOUD INFRASTRUCTURE BACKUP IN A SHARED STORAGE ENVIRONMENT - A technique for cloud infrastructure backup in a virtualized environment utilizing shared storage includes obtaining a workload input/output (I/O) profile to the shared storage over a time period. An attempt to locate one or more time windows in the workload I/O profile for which a cloud infrastructure backup can be staged is initiated. In response to determining the cloud infrastructure backup can be staged during at least one of the time windows, staging of the cloud infrastructure backup is scheduled during a selected one of the time windows. In response to determining the cloud infrastructure backup cannot be staged during at least one of the time windows, an interference tolerance approach is employed for accessing the shared storage for active workloads and the cloud infrastructure backup during the staging of the cloud infrastructure backup. | 2015-12-17 |
20150363276 | MULTI-SITE DISASTER RECOVERY MECHANISM FOR DISTRIBUTED CLOUD ORCHESTRATION SOFTWARE - Multi-site disaster recovery mechanism performed by the following steps: (i) providing a disaster recovery (DR) system that includes a plurality of sites where each site of the plurality of sites actively serves infrastructure-as-a-service to a set of tenant(s); (ii) for each site of the plurality of sites, determining the following characteristics of the site: workloads that require DR, workloads characteristics, tenants and capabilities; (iii) for each site of the plurality of sites, determining a plurality of associated sites; and (iv) on condition that a disaster occurs which impacts a first site of the plurality of sites, distributing a primary site workload of the first site across the associated sites of the first site. The determination of the plurality of associated sites associated with each site is based upon at least one of the following characteristics: capacity, workloads that require DR, workloads characteristics, tenants and/or capabilities. | 2015-12-17 |
20150363277 | CHECKPOINT TRIGGERING IN A COMPUTER SYSTEM - According to an aspect, a method for triggering creation of a checkpoint in a computer system includes executing a task in a processing node of the computer system and determining whether it is time to read a monitor associated with a metric of the task. The monitor is read to determine a value of the metric based on determining that it is time to read the monitor. A threshold for triggering creation of the checkpoint is determined based on the value of the metric. Based on determining that the value of the metric has crossed the threshold, the checkpoint including state data of the task is created to enable restarting execution of the task upon a restart operation. | 2015-12-17 |
20150363278 | VIRTUAL RESOURCE-BASED BACKUP - A device may receive a virtual image of a first state of a first virtual machine. Session information of the state of the first virtual machine may be synchronized with a second state of a second virtual machine. The second state of the second virtual machine may become active when the first virtual machine becomes unavailable. The device may identify that the first virtual machine is unavailable; and output, based on the identifying, the virtual image of the first state to a particular third virtual machine, to cause the particular third virtual machine to restore the first state of the first virtual machine. The second state of the second virtual machine may become inactive when the first state is restored to the third virtual machine. | 2015-12-17 |
20150363279 | RESTORATION DETECTING METHOD, RESTORATION DETECTING APPARATUS, AND RESTORATION DETECTING PROGRAM - A restoration detecting method includes receiving, by a processor, from a monitoring target virtual machine, file size information indicating a file size of a specific file, the file size of which cumulatively increases as the virtual machine runs, and detecting, by a processor, restoration of the virtual machine on a basis of the received file size information. | 2015-12-17 |
20150363280 | Conditional Storage - In one aspect of the present disclosure, a method involves obtaining, by a body-mountable device, sensor data, where the body-mountable device includes a data storage. The method further involves making a determination that each condition in a condition set has been satisfied. In addition, the method involves responsive to making the determination that each condition in the condition set has been satisfied, storing the obtained sensor data in the data storage. | 2015-12-17 |
20150363281 | METHOD AND SYSTEM FOR AUTOMATICALLY DETECTING AND RESOLVING INFRASTRUCTURE FAULTS IN CLOUD INFRASTRUCTURE - Systems and methods are provided for any party in a cloud ecosystem (cloud providers of such resources, the intermediate management software for such resources, and the end user of such resources) to detect and resolve faulty resources synchronously or asynchronously, before said faults adversely affect the users' workloads. The system requests a service or set of one or more resources within a cloud, automatically checking the infrastructure for various faults that would cause it to be non-functional, including pre-defined and user-defined checks, and resolving them before including the infrastructure in the working service cluster of resources. The system presents an API to the user that returns only functional, production-quality resources that are not in a faulty state. An API that tests and resolves bad infrastructure can be registered during the request or a preceding/subsequent API call, removing the need for the end-user to deal with various types of infrastructure faults. | 2015-12-17 |
20150363282 | RESILIENCY DIRECTOR - Systems and methods of orchestrating recoveries of virtual machines protected by a data management systems from a primary system to a secondary system, such that performing the recoveries depends on relationships between the virtual machines. First data indicative of a recovery plan associated with a failover of at least one group of virtual machines is received. The recovery plan includes an application group with data indicative of a hierarchical relationship between the virtual machines wherein each of the virtual machines is associated with an order based on the second data. A plurality of sequences is created in the application group to designate an order of executing a plurality of recoveries for each of the virtual machines. A first recovery is executed in parallel for each of the virtual machines associated with a first sequence and a subsequent recovery is executed in parallel for each of a subsequent set of sequences. | 2015-12-17 |
20150363283 | MULTI-THREADED SERVER CONTROL AUTOMATION FOR DISASTER RECOVERY - Systems and methods for multi-threaded server control automation for disaster recovery are described. A method may include initiating a disaster recovery sequence on two or more processors, wherein the disaster recovery sequence comprises a plurality of subsequences. The method may also include implementing the disaster recovery sequence on the two or more processors in parallel, wherein one or more subsequences of the disaster recovery sequence are implemented on the two or more processors in parallel. Upon completion of the disaster recovery sequence, at least one server partition is repurposed from a first configuration, such as a test configuration, to a second configuration, such as a production configuration. | 2015-12-17 |
20150363284 | SHARED STORAGE SYSTEM AND METHOD FOR CONTROLLING ACCESS TO STORAGE DEVICE - According to one embodiment, a shared storage system includes a plurality of host servers, a plurality of storage devices, and a management server. The management server manages each of a plurality of logical units using first address management information, and manages a revision of the first address management information using first revision data. The host servers each hold respective copies of the first address management information and first revision data. When a first host server has requested a first storage device to execute access, based on a copy (second revision data) of the first revision data, the first storage device executes the requested access on condition that the second revision data coincides with revision data notified by the management server. | 2015-12-17 |
20150363285 | METHODS AND SYSTEMS FOR USING A WRITE CACHE IN A STORAGE SYSTEM - Methods and systems for storing data at a storage device of a storage system are provided. The data is first temporarily stored at a first write cache and an input/output request for a persistence storage device used as a second write cache is generated, when an I/O request size including the received data has reached a threshold value. The data from the first cache is transferred to the persistence storage device and a recovery control block with a location of the data stored at the persistence storage device is updated. An entry is added to a linked list that is used to track valid data stored at the persistence storage device and then the data is transferred from the persistence storage device to the storage device of the storage system. | 2015-12-17 |
20150363286 | ESTABLISHING COPY PAIRS FROM PRIMARY VOLUMES TO SECONDARY VOLUMES IN MULTIPLE SECONDARY STORAGE SYSTEMS FOR A FAILOVER SESSION - Provided are a computer program product, system, and method for establishing copy pairs from primary volumes to secondary volumes in multiple secondary storage systems for a failover session. For each of the copy pairs, data is mirrored from the primary storage system to the associated secondary storage system in the copy pair. A failure is detected at the primary storage system. Selection is made of a selected secondary storage system of the secondary storage systems in response to detecting the failure, wherein a plurality of the secondary storage systems are available for selection. The selected secondary storage system is indicated as a new primary storage system to which host requests are directed. | 2015-12-17 |
20150363287 | BANK-LEVEL FAULT MANAGEMENT IN A MEMORY SYSTEM - According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including a plurality of memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition. | 2015-12-17 |
20150363288 | REDUNDANCIES FOR RECONSTRUCTION IN MASS DATA STORAGE SYSTEMS - A mass data storage system includes a redundancy manager that uses a physical position map to select a subset of storage resources having a physical distribution satisfying at least one resource distribution rule. The physical position map identifies physical positions of storage resources relative to a number of power supply units. A read/write manager writes data redundancies to select storage resources of the selected subset to provide a predetermined level of data protection that allows for reconstruction of lost data in a number of diverse circumstances. | 2015-12-17 |
20150363289 | Mobile device application monitoring software - A software application for monitoring the performance of other software applications on mobile devices using efficient crowd sourced data and recommending third party software apps based on a user's demographics and mobile device data. | 2015-12-17 |
20150363290 | DATA ACQUISITION - A data acquisition system can include a central controller to provide a data acquisition signal. The data acquisition system can also include a cabinet to receive the data acquisition signal. The cabinet can have an array of modules installed therein. The cabinet can include a backplane connected to each module of the array of modules. The backplane can provide a status request signal to a given module in the array of modules if the given module is assigned a module address identified by the data acquisition signal. The given module can provide status data characterizing an operational status of the given module in response to the status request. | 2015-12-17 |
20150363291 | OPTIMIZING THE NUMBER OF SHARED PROCESSES EXECUTING IN A COMPUTER SYSTEM - A system optimizes a number of shared server processes executing on a processor. The system creates, in a memory, a data array for storing a plurality of performance metric values, each associated with a number of shared server processes. The system selects a value for an optimized number of shared server processes according to a first procedure based on the performance metric, observes a performance metric associated with the selected optimized number, and stores, in the data array, the observed performance metric. The system repeats the selecting, observing and storing until at least a predetermined number of contiguous data values are stored in the data array. The system selects the value for the optimized number according to a second procedure based on a slope of the performance metric. The system observes the performance metric associated with the selected optimized number, and stores, in the data array, the observed performance metric. | 2015-12-17 |
20150363292 | Risk Analysis of Codebase Using Static Analysis and Performance Data - An example system is configured to calculate performance statistics for a set of analysis tools; analyze a codebase using one or more analysis tools from the set of analysis tools; generate an analysis result for each analysis tool of the one or more analysis tools, the result describing one or more faults and one or more validations identified by the corresponding analysis tool; and estimate a risk of defects in the codebase based on the analysis result associated with each of the one or more analysis tools and the performance statistics associated with each of the one or more analysis tools. | 2015-12-17 |
20150363293 | EXECUTING DEBUG PROGRAM INSTRUCTIONS ON A TARGET APPARATUS PROCESSING PIPELINE - A target apparatus | 2015-12-17 |
20150363294 | Systems And Methods For Software Analysis - Systems, methods, and computer program products are provided for identifying software files, flaws in code, and program fragments by obtaining a software file, determining a plurality of artifacts, accessing a database which stores a plurality of reference artifacts for reference software files, comparing at least one of the artifacts to at least one of the reference artifacts stored in the database, and identifying the software file by identifying the reference software file having the reference artifacts that correspond to the plurality of artifacts. Certain embodiments can also automatically provide updated versions of files, patches to be applied, or repaired blocks of code to replace flawed blocks. Example embodiments can accept a wide variety of file types, including source code and binary files and can analyze source code or convert files to an intermediate representation (IR) and analyze the IR. | 2015-12-17 |
20150363295 | COMMAND COVERAGE ANALYZER - A method and apparatus of a novel command coverage analyzer is disclosed. Combinations of commands, options, arguments, and values of a product are extracted, customer environment and uses are considered, and a more comprehensive and accurate quality of software process and metric is provided. | 2015-12-17 |
20150363296 | FUNCTION TEST APPARATUS BASED ON UNIT TEST CASES REUSING AND FUNCTION TEST METHOD THEREOF - There is provided a function test apparatus based on unit test cases reusing and a function test method thereof. The function test apparatus related to the present disclosure is constructed with a Storage Portion, storing a unit test case for each function into a hierarchical constitution; a Selection Portion of unit test case, when a Test Object Function is provided, in order to abstract an internal constitution of a callee function activated by the Test Object Function, selectively reusing a unit test case of the callee function; a Generator of test case, generating at least one test case in order for all the unit test cases selected by the Selection Portion of test case to be performed; and a Performance Portion of test case, testing the Test Object Function by performing the test case. According to the configuration herein, a test for function may be conducted without analyzing the internal constitution of software function at an integral testing motion and a test of which a Test coverage is high may be conducted to the Test Object Function. Therefore, an advantage of high reliability for the test result is obtained. | 2015-12-17 |
20150363297 | PERFORMANCE TESTING OF SOFTWARE APPLICATIONS - Identifying performance issues in an application under test (AUT). The AUT executes on a system under test (SUT) in a test environment, and uses one or more context parameters of the SUT and/or the test environment. A rule engine identifies performance antipatterns in trace data generated by the AUT when executing a set of test suites, based on a set of performance antipattern definition rules, each performance antipattern associated with one or more context parameters. One or more performance test suites are identified that cause the AUT to use at least one of the one or more context parameters associated with the identified antipatterns. The list of identified performance test suites is ranked, based on respective priority values associated with each identified antipattern. | 2015-12-17 |
20150363298 | AUTOMATED TESTING OF WEBSITES BASED ON MODE - Examples of techniques for testing websites are described herein. In one example, a method for testing a website includes receiving, via a processor, a website address of the website to be tested. The method can include determining, via the processor, whether the website is in a staging mode or a production mode. The method can also include configuring, via the processor, a testing application to test the website according to the determined mode. | 2015-12-17 |
20150363299 | PERFORMANCE TESTING OF SOFTWARE APPLICATIONS - Identifying performance issues in an application under test (AUT). The AUT executes on a system under test (SUT) in a test environment, and uses one or more context parameters of the SUT and/or the test environment. A rule engine identifies performance antipatterns in trace data generated by the AUT when executing a set of test suites, based on a set of performance antipattern definition rules, each performance antipattern associated with one or more context parameters. One or more performance test suites are identified that cause the AUT to use at least one of the one or more context parameters associated with the identified antipatterns. The list of identified performance test suites is ranked, based on respective priority values associated with each identified antipattern. | 2015-12-17 |
20150363300 | GENERATING SOFTWARE TEST SCRIPT FROM VIDEO - Methods and apparatus are disclosed to generate software test script from video. Example methods disclosed herein include determining a user action in a frame of a video comprising recorded testing of software. The example method also includes identifying an action parameter corresponding to the user action. The example method also includes based on the action parameter, generating without user intervention a script to execute on the software. | 2015-12-17 |
20150363301 | TEST SCRIPT CREATION BASED ON ABSTRACT TEST USER CONTROLS - The life cycle of an application can be shortened by initiating the creation of a mock-up test script before the development of an application is complete. The concurrent creation of the mock-up test script and the application can reduce a time associated with the life cycle of an application. Mock-up test script creation is based on the user interface (UI) specification and a mock-up graphical user interface (GUI) without business logic. Test script creation can include associating a functional specification and a UI specification with a proposed application and creating a mock-up GUI for testing based on the UI specification. Test script creation can include developing an application based on the proposed application that includes a logic based on the functional specification and a GUI based on the UI specification and creating a mock-up test script based on the mock-up GUI and not based on the logic, the functional specification, and the GUI. | 2015-12-17 |
20150363302 | A/B TESTING FOR MOBILE APPLICATIONS - A machine may be configured to perform A/B testing on mobile applications. For example, the machine receives an identifier of a mobile device that stores a mobile application. The machine identifies a parameter of an element of a user interface displayed by the mobile application on the mobile device. The identifying of the parameter may be based on the identifier of the mobile device. The machine selects a parameter value that corresponds to the parameter. The selecting of the parameter value may be based on the identifier of the mobile device. The machine generates an instruction referencing the parameter value. The instruction may be executable by the mobile application to display the element of the user interface on the mobile device according to the parameter value. The machine transmits the instruction to the mobile device in response to receiving the identifier of the mobile device. | 2015-12-17 |
20150363303 | MOBILE AND REMOTE RUNTIME INTEGRATION - An application program may be analyzed to identify candidate classes or methods that may be executed using a remote computing node. Candidate classes or methods may be translocated to the remote computing node based on performance characteristics of the device on which the application program is running, the environment in which the device operates, and on the performance and availability of the remote computing node. An application program publisher may be assigned instances of virtual machines that may be dedicated to hosting translocated classes and methods. | 2015-12-17 |
20150363304 | SELF-LEARNING AND SELF-VALIDATING DECLARATIVE TESTING - A system and method for self-learning and self-validating declarative testing are provided. In example embodiments, a user experience module identifies a declarative test representing a user experience being tested. A test execution module simulates a client machine including a client machine environment and executes the declarative test using the simulated client machine and the user behavior data of the specific user to generate test results. A validation module validates the test results by invoking at least one of plurality of validators, including at least one client-side validator and at least one server-side validator. | 2015-12-17 |
20150363305 | METHOD FOR TEST CASE REDUCTION BASED ON PROGRAM BEHAVIOR SLICES - The present invention provides a method of test cases reduction based on program behavior slices. In the case that there is no need to scan all program paths, a test suite capable of covering all program behaviors is generated to relieve the state-space explosion problem confronted by program tests. In the present invention, during a static analysis stage, analyzing a control flow and an information flow of a program according to input program codes, extracting control dependence and data dependence of the program; calculating potential dependence of the program according to the control dependence and the data dependence of the program; on the basis of the control dependence, the data dependence and the potential dependence, constructing combination dependence of the program; during a dynamic execution stage, according to an execution path and the dependence relation, calculating program behavior slices covered by the path and program behavior slices uncovered by the path, and guiding symbolic execution to generate a path capable of covering new program slices according to the uncovered program behavior slices. Compared with the existing symbolic execution technique, the present invention can ensure the validity of the test suite, while at the same time reducing the number of the generated test cases remarkably. | 2015-12-17 |
20150363306 | METHODS AND SYSTEMS TO IDENTIFY AND REPRODUCE CONCURRENCY VIOLATIONS IN MULTI-THREADED PROGRAMS USING EXPRESSIONS - Methods and systems to identify threads responsible for causing a concurrency bug in a computer program having a plurality of concurrently executing threads are disclosed. An example method disclosed herein includes defining, with a processor, a data type. The data type including a first predicate, the first predicate being invoked using a first program instruction inserted in a first thread of the plurality of threads, a second predicate, the second predicate being invoked using a second program instruction inserted in a second thread of the plurality of threads, and an expression defining a relationship between the first predicate and the second predicate. The method further includes, in response to determining the relationship is satisfied during execution of the computer program, identifying the first thread and the second thread as responsible for the concurrency bug. | 2015-12-17 |
20150363307 | ADDRESS MAPPING FOR SOLID STATE DEVICES - Technologies are generally described for systems, devices and methods relating to swapping bits in memory addresses in solid state devices. In some examples, a bit swap module may receive a first memory address. The first memory address may include a first bit value at a first position of the first memory address and/or a second bit value at a second position of the first memory address. The bit swap module may swap the first bit value with the second bit value to produce a second memory address. The second memory address may be sent to a memory controller. In some examples, the first memory address may relate to a first package of memory and the second memory address may relate to a second package of memory. | 2015-12-17 |
20150363308 | METHOD FOR OPERATING CONTROLLER AND METHOD FOR OPERATING DEVICE INCLUDING THE SAME - A method of operating a controller includes receiving write data having chunks from a host, assigning each of finger prints to each of the chunks, counting the number of duplications of each of the finger prints, and changing a physical address assigned to each of first finger prints among the finger prints based on a count value of each of the finger prints based on a count value of each of the finger prints, and the physical address is assigned by a flash translation layer (FTL). | 2015-12-17 |
20150363309 | SYSTEM AND METHOD OF INCREASING RELIABILITY OF NON-VOLATILE MEMORY STORAGE - Various embodiments are described herein for a system and a method for increasing reliability of a secondary storage device used with a computing system where the secondary storage device contains a memory buffer, a controller, and non-volatile memory. The method may comprise initializing a test of the memory buffer; testing at least one memory block of the memory buffer; discontinuing use of a given memory block of the memory buffer if a defective memory location is detected for the given memory block; and storing test results for the memory buffer. | 2015-12-17 |
20150363310 | MEMORY HEAPS IN A MEMORY MODEL FOR A UNIFIED COMPUTING SYSTEM - A method and system for allocating memory to a memory operation executed by a processor in a computer arrangement having a first processor configured for unified operation with a second processor. The method includes receiving a memory operation from a processor and mapping the memory operation to one of a plurality of memory heaps. The mapping produces a mapping result. The method also includes providing the mapping result to the processor. | 2015-12-17 |
20150363311 | MEMORY MANAGEMENT METHOD - A method for managing main memory including DRAM and NVRAM in a computer depending on the operation state of the computer is provided. The method includes: (a) upon start of the computer, loading a program and the like into the DRAM, and loading predetermined read-only data and the like into the NVRAM; (b) in a state transition from a normal operation to a suspend state, moving data in the DRAM to the NVRAM; (c) in a state transition from the suspend state to the normal operation, reading data from the NVRAM for program execution; (d) in the case where a data write to the NVRAM occurs, stopping the data write, and moving data in a data area of the NVRAM subjected to the data write, to the DRAM; and (e) performing the data write to the DRAM to which the data has been moved. | 2015-12-17 |
20150363312 | ELECTRONIC SYSTEM WITH MEMORY CONTROL MECHANISM AND METHOD OF OPERATION THEREOF - An electronic system includes: a second memory module; a first memory module coupled to the second memory module; and a multicast controller for managing a cache on the first memory module for the second memory module. | 2015-12-17 |
20150363313 | SENSE OPERATION FLAGS IN A MEMORY DEVICE - Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page. | 2015-12-17 |
20150363314 | System and Method for Concurrently Checking Availability of Data in Extending Memories - A memory system for use in a system-in-package device (SiP) is disclosed. The memory system includes two cache memories. The first cache memory is on a first die of the SiP and the second cache memory is on a second die of the SiP. Both cache memories include tag random access memories (RAMs) corresponding to data stored in the corresponding cache memories. The second cache memory is of a different cache level from the first cache memories. Also, the first cache memory is on a first die of the SiP, and the second cache memory includes a first portion on the first die of the SiP, and a second portion on a second die of the SiP. Both cache memories can be checked concurrently for data availability by a single physical address. | 2015-12-17 |
20150363315 | METHOD FOR TEMPORARILY STORING DATA AND STORAGE DEVICE - A method for temporarily storing data and a storage device is provided. The method for temporarily storing data is applied to the storage device, and the storage device includes a source agent and a target agent. The method includes: sending, by the source agent, a data obtaining request to the target agent; receiving, by the source agent, target data that is corresponding to the data obtaining request and is returned by the target agent; determining, by the source agent, whether a snooping request that is for the target data and sent by the target agent is received after the data obtaining request is sent and before the target data is received, where the snooping request indicates that the target agent is simultaneously processing an obtaining request from another source agent for the target data; and if the snooping request is received, discarding, by the source agent, the target data | 2015-12-17 |
20150363316 | PRESERVING AN INVALID GLOBAL DOMAIN INDICATION WHEN INSTALLING A SHARED CACHE LINE IN A CACHE - A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared. | 2015-12-17 |
20150363317 | TECHNIQUES FOR PRESERVING AN INVALID GLOBAL DOMAIN INDICATION WHEN INSTALLING A SHARED CACHE LINE IN A CACHE - A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared. | 2015-12-17 |
20150363318 | CACHE WAY PREDICTION - In an example, a system and method are provided for predicting in which way a requested memory address is most likely to be held in a multi-way cache, based on the last way accessed by the specified address register if available. If not available, then the system may determine that no best prediction is available. In that case, each way is read, and the superfluous values are disregarded, or a cache fill is performed as necessary. In certain embodiments, only a portion of the least significant bits of an add operation are used for way prediction in base-plus-offset addressing modes. This enables the decision to be made before the full-width add is complete, so that the clock cycle length is not unnecessarily lengthened by the prediction operation. | 2015-12-17 |
20150363319 | FAST WARM-UP OF HOST FLASH CACHE AFTER NODE FAILOVER - Examples described herein include a system for storing data. The data storage system retrieves a first set of metadata associated with data stored on a first cache memory, and stores the first set of metadata on a primary storage device. The primary storage device is a backing store for the data stored on the first cache memory. The storage system selectively copies data form the primary storage device to a second cache memory based, at least in part, on the first set of metadata stored on the primary storage device. For some aspects, the storage system may copy the data from the primary storage device to the second cache memory upon determining that the first cache memory is in a failover state. | 2015-12-17 |
20150363320 | WRITE BACK CACHING OF BOOT DISK IN A UEFI ENVIRONMENT - Write back caching of Operating System (OS) boot data in a UEFI environment is disclosed. One embodiment is an apparatus that includes a non-volatile memory, a storage device, and a processor. The non-volatile memory caches boot data for an OS. The storage device stores the OS. The processor receives a write request for the storage device, and determines whether the write request modifies boot data accessed within a UEFI pre-OS boot environment. The processor directs the write request to the storage device responsive to determining that the write request modifies boot data accessed within the UEFI pre-OS boot environment, and directs the write request to the non-volatile memory responsive to determining that the write request does not modify boot data accessed within the UEFI pre-OS boot environment. | 2015-12-17 |
20150363321 | PARALLEL LOOKUP IN FIRST AND SECOND VALUE STORES - A data processing apparatus | 2015-12-17 |
20150363322 | SYSTEMS, METHODS, AND COMPUTER PROGRAMS FOR PROVIDING CLIENT-FILTERED CACHE INVALIDATION - A method and system includes generating a cache entry comprising cache line data for a plurality of cache clients and receiving a cache invalidate instruction from a first of the plurality of cache clients. In response to the cache invalidate instruction, the data valid/invalid state is changed for the first cache client to an invalid state without modifying the data valid/invalid state for the other of the plurality of cache clients from the valid state. A read instruction may be received from a second of the plurality of cache clients and in response to the read instruction, a value stored in the cache line data is returned to the second cache client while the data valid/invalid state for the first cache client is in the invalid state and the data valid/invalid state for the second cache client is in the valid state. | 2015-12-17 |
20150363323 | NON-VOLATILE MEMORY WRITE MECHANISM - A system includes a memory buffer to cache a non-volatile memory. The non-volatile memory stores a plurality of valid and obsolete variables in a plurality of valid and obsolete regions, respectively. The system further includes a journal region to track movement of valid variables and valid regions within the memory buffer utilizing alternating pairs of structure pointers to indicate at least portions of the plurality of valid and obsolete regions indicative of from where and to where the valid variables move during a write event. | 2015-12-17 |
20150363324 | SYSTEMS AND METHODS FOR A DE-DUPLICATION CACHE - A de-duplication is configured to cache data for access by a plurality of different storage clients, such as virtual machines. A virtual machine may comprise a virtual machine de-duplication module configured to identify data for admission into the de-duplication cache. Data admitted into the de-duplication cache may be accessible by two or more storage clients. Metadata pertaining to the contents of the de-duplication cache may be persisted and/or transferred with respective storage clients such that the storage clients may access the contents of the de-duplication cache after rebooting, being power cycled, and/or being transferred between hosts. | 2015-12-17 |
20150363325 | IDENTIFICATION OF LOW-ACTIVITY LARGE MEMORY PAGES - Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to mappings to small pages and accesses to these small pages are then tracked. For each selected large page, an activity level is determined based on the tracked accesses to the small pages included in the large page. By strategically selecting relatively low activity large pages for decomposition into small pages and subsequent memory reclamation while restoring the mappings to relatively high activity large pages, memory consumption is improved, while limiting performance impact attributable to using small pages. | 2015-12-17 |
20150363326 | IDENTIFICATION OF LOW-ACTIVITY LARGE MEMORY PAGES - Large pages that may impede memory performance in computer systems are identified. In operation, mappings to selected large pages are temporarily demoted to mappings to small pages and accesses to these small pages are then tracked. For each selected large page, an activity level is determined based on the tracked accesses to the small pages included in the large page. By strategically selecting relatively low activity large pages for decomposition into small pages and subsequent memory reclamation while restoring the mappings to relatively high activity large pages, memory consumption is improved, while limiting performance impact attributable to using small pages. | 2015-12-17 |
20150363327 | FLASH STORAGE DEVICES AND METHODS FOR ORGANIZING ADDRESS MAPPING TABLES IN FLASH STORAGE DEVICES - In some example embodiments, a method of organizing an address mapping table of a flash storage device based on Logical Block Address (LBA) size may comprise: identifying an extent of correlation between the LBA and flash page sizes, wherein the extent of correlation indicates greater or lesser extent; computing a total number of entries in each meta page of the table; and/or organizing the table with the total number of entries. In some example embodiments, a method of organizing an address mapping table of a flash storage device based on LBA size may comprise: determining flash page size of the flash storage device; determining the LBA size; and/or comparing the flash page and LBA sizes. When the flash page size is greater, the table may be organized based on flash page size. When the flash page size is less, the table may be organized based on LBA size. | 2015-12-17 |
20150363328 | METHODS AND APPARATUS FOR DATA PROCESSING - Data processing methods and apparatus for efficiently storing and retrieving data, e.g., blocks of data, to and from memory. The data processing including, e.g., techniques such as using linked lists and/or tables for tracking duplicate data blocks received for storage, the use of lossless data compression, and de-duplication based on comparing hash values, compressed data block sizes, and/or bit by bit comparisons of the block of data to be stored and previously stored blocks of data. For example, one embodiment of a method in accordance with the present invention includes generating a hash value from a block of data to be stored and a hash function; compressing the block of data to be stored to generate a compressed block of data, said compressed block of data being of a first size; comparing said generated hash value to hash values corresponding to previously stored blocks of data; and when said generated hash value matches a hash value of a previously stored block of data, determining if the block of data to be stored matches the previously stored block of data with the matching hash value. In some embodiments of the present invention, the aforementioned determining step includes comparing said first size to the size of said previously stored block of data with the matching hash value; and determining that said block of data to be stored does not match said previously stored block of data when said first size does not match the size of said stored block of data. | 2015-12-17 |
20150363329 | MEMORY ADDRESS TRANSLATION - In one example, a device includes at least one processor, a transceiver configured to send and receive data, and at least one memory device. The at least one memory device includes a range of physical memory addresses divided into a plurality of physical memory partitions that each includes a sub-range of the range of physical memory addresses and corresponds to a range of virtual memory addresses. Instructions encoded in the at least one memory device cause the at least one processor to receive a memory address request configured to request access to a requested physical memory address within the range of physical memory addresses, determine that the requested physical memory address is associated with one of the plurality of physical memory partitions, determine a virtual memory address corresponding to the requested physical memory address, and access the requested physical memory address via the determined virtual memory address. | 2015-12-17 |
20150363330 | Flash NAND device bad page replacement - Where one or more flash NAND devices are in an array where bit error recovery resolution is available, the controller can log what pages have had what degree of fails, and program a Replace Bad Page function to replace the bad page with a new page from another new die as needed. The Replace Bad Page function with logic blocks, content addressable memory and RAM, once programmed, provides the means to know when a bad page is being accessed and displaces this access with access to the new page, with no change in overall page access function or performance. | 2015-12-17 |
20150363331 | STORAGE CONTROL DEVICE AND METHOD OF CONTROLLING STORAGE CONTROL DEVICE - To improve response performance of a storage control device. A storage control device | 2015-12-17 |
20150363332 | HARDWARE PROTECTION OF INLINE CRYPTOGRAPHIC PROCESSOR - A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with it's own separate encryption capability, or no encryption at all. Data integrity is ensured by hardware protection from code attempting to access data across memory segment boundaries. Protection is also provided against dictionary attacks by monitoring multiple access attempts to the same memory location. | 2015-12-17 |
20150363333 | HIGH PERFORMANCE AUTONOMOUS HARDWARE ENGINE FOR INLINE CRYPTOGRAPHIC PROCESSING - A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with its own separate encryption capability, or no encryption at all. A Message Authentication Code is also employed to detect any memory corruption or unauthorized memory modification. | 2015-12-17 |
20150363334 | SPECULATIVE CRYPTOGRAPHIC PROCESSING FOR OUT OF ORDER DATA - A real time, on-the-fly data encryption system is shown operable to encrypt and decrypt the data flow between a secure processor and an unsecure external memory system. Multiple memory segments are supported, each with it's own separate encryption capability, or no encryption at all. Speculative decryption operations may be started when the memory used is capable of returning read data out of order. The full or partial results of the speculative operations are cached in order to allow matching the cryptographic operation to the read data when it arrives. | 2015-12-17 |
20150363335 | Memory Device, Memory System, and Operating Method of Memory System - A memory device, a memory system, and an operating method of the memory system is provided. The operating method includes operations of transmitting an authentication request to a memory device using a memory controller; converting the authentication request to a first address using the memory device; processing authentication data that corresponds to the first address and indicates a physical characteristic of the memory device and transmitting the authentication data as an authentication response to the authentication request to the memory controller using the memory device; and verifying whether the authentication response received from the memory device is an authentication response to the authentication request using the memory controller. | 2015-12-17 |
20150363336 | MEMORY DEVICE, MEMORY SYSTEM, AND METHOD OF OPERATING MEMORY SYSTEM - A method of operating a memory system including a first function block and a second function block includes generating a first authentication response indicating physical characteristics of the memory system, via the second function block, in response to a first authentication request received from the first function block; performing an error correction decoding on the first authentication response, via the first function block, by using first parity data corresponding to the first authentication request; and determining whether the second function block is authentic, depending on a result of the error correction decoding. | 2015-12-17 |
20150363337 | VERIFICATION OF INTELLECTUAL PROPERTY CORE TRUSTED STATE - Secure initialization of the state of an electronic circuit. A processor determines the trusted state of one or more architecture state registers of an intellectual property core. The processor clears entries in a memory of the intellectual property core. The processor verifies that state machines, included in execution logic of the intellectual property core, have not generated output. | 2015-12-17 |
20150363338 | METHOD OF OPERATING MEMORY CONTROLLER AND METHODS FOR DEVICES HAVING THE SAME - A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state. | 2015-12-17 |
20150363339 | Reversible Connector for Accessory Devices - Reversible connectors for accessory devices are described. In one or more implementations, a connector cable for an accessory of a host computing device is configured such that a head of the connector cable may be plugged into a corresponding port of the host in either orientation (straight or reverse). The host computing device is configured to sample signals associated with allocated pins of the connector to detect connection of the connector to an accessory port and to ascertain an orientation of the connector. A combination of high and low values of signals conveyed via these allocated pins upon insertion of the connector may be used by a controller of the host to distinguish between different types of devices and to resolve the orientation of the connector cable. A switching mechanism of the host computing device may then be configured to automatically route signals accordingly. | 2015-12-17 |
20150363340 | PROVIDING MULTIPLE SYNCHRONOUS SERIAL CONSOLE SESSIONS USING DATA BUFFERING - Embodiments are directed to providing synchronous communication between a baseboard management controller (BMC) and a serial console using data buffering, and to providing multiple synchronous serial console sessions using data buffering. In one scenario, a computer system polls a server console for server console data and receives server console data from the server console. The computer system buffers at least a portion of the received server console data in a data store, receives a request for the buffered server console data from a specified entity, and providing the requested buffered server console data to the specified entity. Optionally, the computer system may also receive encapsulated data from a chassis management application, unencapsulate the received encapsulated data, and send the unencapsulated data to the server console. | 2015-12-17 |
20150363341 | EXTERNAL STORAGE DEVICE - An external storage device includes a memory, a controller, a first interface, a second interface, a first switching module, and a second switching module. The controller is coupled to the memory. The first interface is used to connect to a first electronic device. The second interface used to connect to a second electronic device. The first switching module is coupled to the controller, the first interface, and the second interface. The second switching module is coupled to the controller, the first interface, the second interface, and the first switching module. When the first interface is electrically connected to a first electronic device and the second interface is electrically connected to the second electronic device, the first electronic device charges the controller and the second electronic device through the first switching module, and the first electronic device accesses the memory through the second switching module and the controller. | 2015-12-17 |
20150363342 | Storage Module and Method for Determining Ready/Busy Status of a Plurality of Memory Dies - A storage module and method are provided for determining ready/busy status of a plurality of memory dies. In one embodiment, a bus has a ready/busy line that is shared among the plurality of memory dies, and a time-division multiplex signal on the shared ready/busy line is used to communicate the ready/busy status of each of the memory dies. In another embodiment, each of the memory dies sends its ready/busy status to the storage controller using a different one of a plurality of data lines in the bus. In yet another embodiment, each of the memory dies sends a pulse across the ready/busy line with a different pulse width. To avoid collisions, each memory die waits a different number of clock cycles before attempting to send its pulse status after determining that the shared ready/busy line is in use. | 2015-12-17 |
20150363343 | AUTO-CONFIGURATION OF A PORT - Embodiments of the present invention provide automatic provisioning of a port in an information handling system, such as a router, switch, bridge, etc., according to the cable type that is inserted into the port. In embodiments, if a user has inserted a break-out cable into a port that is not configured for break-out mode, the information handling system quickly and transparently changes the port configuration to a break-out mode. Conversely, when a user inserts a non-break-out cable that cannot be fanned out into a quad-mode port, the information handling system configures that port to native mode (i.e., non-break-out mode). In embodiments, the user may override auto-configuration. In embodiments, one or more port configurations may be stored and applied to a port by a user. | 2015-12-17 |
20150363344 | Selectively Connecting a Port of an Electrical Device to Components in the Electrical Device - Techniques are presented herein to enable a port of an electrical device to be selectively connected to either a first component or a second component of the electrical device. The port is configured to physically interface with an external device. The first component and second component perform different functions. A signal directing circuit is coupled to the port, and is configured to selectively connect the port to one of the first and second components. | 2015-12-17 |
20150363345 | APPARATUSES AND METHODS OF INCREASING OFF-CHIP BANDWIDTH - Embodiments of the present invention include methods for increasing off-chip bandwidth. The method includes designing a circuit of switchable pins, replacing a portion of allocated pins of a processor with switchable pins, connecting the processor to a memory interface configured to switch the switchable pins between a power mode and a signal mode, providing a metric configured to identify which of the power mode and the signal mode is most beneficial during 1 millisecond intervals, and switching the switchable pins to signal mode during intervals where the signal mode provides more benefit than the power mode. | 2015-12-17 |
20150363346 | SATA INITIATOR ADDRESSING AND STORAGE DEVICE SLICING - Example embodiments relate to providing serial ATA (SATA) initiator addressing and storage device slicing. In example embodiments, an expander device configures an initiator serial attached SCSI (SAS) address to uniquely identify a SATA initiator, where the SATA initiator is associated with a target address of a SATA storage bridge. Further, the STP storage bridge of the expander device is configured to associate the initiator SAS address with a drive slice of an SATA storage device. At this stage, the expander device receives a SATA request from the SATA initiator, where the SATA request comprises a SATA command and a logical block addressing (LBA) address, and after inserting the initiator SAS address into the SATA request, sends an STP connection request to the target address. The expander device may then offset the LBA address based on the initiator SAS address to obtain an offset LBA address of the SATA storage device. | 2015-12-17 |
20150363347 | PORTABLE USB MASS STORAGE DEVICE - A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget. | 2015-12-17 |
20150363348 | AUTOMOBILE ADAPTOR SYSTEM, APPARATUS AND METHODOLOGY - An adapter for an electronic device usable in an automobile. The adapter includes a master dock with a port for a device-specific interface, and a device plug. The master dock interfaces with the automobile through an electronic communication connection, for example, USB. The master dock receives the device-specific interface to allow use of the adapter with various electronic devices. For example, device-specific interfaces may be provided for iPhones, Android phones, Windows phones, iPads, Nexus tablets, or virtually any other mobile electronic device. The device-specific interface receives the electronic device via a properly-positioned port, which connects the electronic device via the master dock to charging and/or data communication ports without use of a cable cord. Concomitantly, the automobile or vehicle has a variety of screens and/or consoles through which the user can view information from a smart phone, tablet or like device through said adaptor. Further, the windows of the vehicle, as well as the screens/consoles may incorporate therein or thereon touchscreen capability, whereby the user can interact, such as through the Internet or other network, to remote material and other users | 2015-12-17 |
20150363349 | LINK LAYER TO PHYSICAL LAYER (PHY) SERIAL INTERFACE - A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit. | 2015-12-17 |
20150363350 | HYBRID REPEATER FOR SUPPORTING BACKWARD COMPATIBILITY - Hybrid repeaters are described that are capable of transmitting data in accordance with different versions of a serial data protocol are described. The appropriate circuitry to be used to transmit incoming serial data is determined by monitoring sideband communication (e.g., a link training handshake) between the transmitter and the receiver. | 2015-12-17 |
20150363351 | DATA TRANSFER DEVICE AND DATA TRANSFER METHOD - A data transfer device performing data transfer at a high speed if a descriptor chain cannot be entirely transferred by a single activation. In a DMA control device, when a transfer activation signal is asserted, a descriptor information control part sequentially reads descriptor information from a descriptor information storage part. When the count of pieces of descriptor information that have been read becomes equal to a transferable frame count, a backward skip control part outputs a backward skip instruction. When the backward skip instruction is outputted, a descriptor information control part skips reading remaining descriptor information. | 2015-12-17 |
20150363352 | PULSE-LATCH BASED BUS DESIGN FOR INCREASED BANDWIDTH - A memory bus comprising a plurality of latches arranged sequentially between a source node and a destination node of a channel of the memory bus; and a pulse generator. The pulse generator is operable to generate a sequence of pulses, each sequential pulse to be simultaneously received by the plurality of latches. A pulse is generated for each edge of a clock signal. A first latch of the plurality of latches is operable to pass on a first data sample while a first pulse is received by the first latch of the plurality of latches. A second latch of the plurality of latches is operable to pass on a second data sample towards the first latch of the plurality of latches while the first pulse is simultaneously received by the first and second latches of the plurality of latches. | 2015-12-17 |
20150363353 | COMMUNICATION SYSTEM AND ELECTRONIC CIRCUIT - A communication system includes an I2C device, an SPI device, a selection circuit and an electronic circuit. The selection circuit selects the first data signal when the CS signal is not received, and generates a signal corresponding to the CS signal and transmit the CS signal to the SCL terminal as the stop signal and at the same time. The selection circuit selects the second data signal when the CS signal is received. The electronic circuit functions as a slave of the SPI communication in a case where the CLK signal has made a transition. The electronic circuit further functions as a slave of the I2C communication in a case where the CLK signal does not make a transition and signals indicating a condition under which the I2C communication is started are transmitted to the CS/SCL terminal and the data terminal. | 2015-12-17 |
20150363354 | Calculator - A calculator that comprises an inputting member, a calculating member and a displaying member, wherein the calculating member is provided for calculating the value of the expression by means of a processing unit and generating a calculated result, and the displaying member has a displaying area, in which the displaying member displays the expression and the corresponding calculated result by the processing unit, so as to provide convenience for the users. | 2015-12-17 |
20150363355 | FINE-GRAINED STREAM-POLICING MECHANISM FOR AUTOMOTIVE ETHERNET SWITCHES - A system and method for monitoring a plurality of data streams is disclosed. At a first processing stage, a first memory area is associated to an element of a plurality of data streams. Upon arrival of a frame associated with one of the plurality of data streams, a second memory area is associated to the arrived frame based on the element. In the second memory area, a data indicating an arrival of the arrived frame is recorded and on a successful recording, the frame is forwarded to a second processing stage. An independent process executes at a preselected time interval to erase contents of the first memory area. | 2015-12-17 |
20150363356 | Data Speculation for Array Processors - A method is disclosed of utilizing a plurality of Arithmetic Logic Units (ALUs) of an array processor. It is determined that a first quantity of the ALUs are scheduled to execute a function during a given processing cycle, with each ALU being scheduled to use a respective one of a plurality of selected input vectors as an input. It is also determined that a second quantity of the ALUs are not scheduled for use during the given processing cycle. A plurality of predicted future input vectors that differ from the plurality of selected input vectors are determined. The second quantity of ALUs are scheduled to execute the function during the given processing cycle using respective ones of the plurality of predicted future input vectors as inputs. After completion of the processing cycle, function outputs received from the first and second quantity of ALUs are cached. | 2015-12-17 |
20150363357 | MEMORY CONTROLLER AND SIMD PROCESSOR - Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an external section and a plurality of processor elements in an SIMD processor, so that one rectangular region corresponds to one processor element. In the SIMD processor, an address storage unit in a memory controller is capable of setting N number of addresses Ai (i=1 through N) in an external memory by utilizing a control processor. A parameter storage unit is capable of setting a first parameter OSV, a second parameter W, and a third parameter L by utilizing a control processor. A data transfer unit executes the transfer of data between an external memory, and the buffers in N number of processor elements contained in the applicable SIMD processor, based on the contents of the address storage unit and the parameter storage unit. | 2015-12-17 |
20150363358 | METHOD AND SYSTEM FOR CONTINUOUS OPTIMIZATION USING A BINARY SAMPLING DEVICE - A method and system are disclosed for continuous optimization. The method comprises obtaining an optimization problem involving continuous or semi-continuous variables in a digital computer; initiating a stochastic search process in the digital computer in order to solve the optimization problem; until a stopping criterion is met constructing in the digital computer at least one stochastically generated polynomial in binary variables representative of choices of candidate future state of the stochastic search process, providing the at least one polynomial in binary variables to a binary sampling device, sampling from domains of the at least one polynomial in binary variables using the binary sampling device to generate binary sample points, receiving the generated binary sample points in the digital computer and transiting to next state of the stochastic search process and providing a best known solution found as a solution of the optimization problem using the digital computer. | 2015-12-17 |
20150363359 | BUTTERFLY CHANNELIZER - A butterfly channelizer includes at least two stages. Each stage includes at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth. At least one clock is configured to generate a clock signal that drives the at least two stages. A first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number. | 2015-12-17 |
20150363360 | FAST FOURIER TRANSFORM DEVICE, FAST FOURIER TRANSFORM METHOD, AND RECORDING MEDIUM STORING FAST FOURIER TRANSFORM PROGRAM - [Problem] A fast Fourier transform method is provided that are able to input data to be processed or output processing results in no particular order. | 2015-12-17 |
20150363361 | Method for Kernel Correlation-Based Spectral Data Processing - Data points of input data are processed by first determining a Laplacian matrix for the data. A spectrum of the Laplacian matrix includes an attractive spectrum of positive eigenvalues, a repulsive spectrum of negative eigenvalues, and a neutral spectrum of zero eigenvalues. An operation for the processing is determined using the Laplacian matrix, using information about the attractive spectrum, the repulsive spectrum, and the neutral spectrum, wherein the information includes the spectra and properties derived from the Spectra. Then, the operation is performed to produce processed data. | 2015-12-17 |
20150363362 | METHOD, APPARATUS AND COMPUTER PROGRAM FOR DETERMINING AN INTERPOLATED COMPLEX VALUED SAMPLE - In a method for determining an interpolated complex valued sample, a radial component of the interpolated sample is determined using information on a radial component and information on of a phase component of a first complex valued sample and of a second complex valued sample. | 2015-12-17 |
20150363363 | GENERATING LANGUAGE SECTIONS FROM TABULAR DATA - A computer implemented method of generating a language section from tabular data in an electronic document may include identifying, in a first tabular portion of the electronic document, a set of categories used to organize tabular data. The method may include identifying a content characteristic for each category of the set of categories in the first tabular portion. And the method may include generating a first language section from at least two distinct categories of the set of categories, wherein a format of the first language section is based on the content characteristics for the at least two distinct categories. | 2015-12-17 |
20150363364 | METHOD AND APPARATUS FOR DOCUMENT PLANNING - Methods, apparatuses, and computer program products are described herein that are configured to be embodied as and/or performed by a document planner. In some example embodiments, a method is provided that comprises selecting a schema based on one or more messages available in a message store and using the selected schema and one or more messages available in the message store to generate a document plan. The schema of this embodiment may be defined by a specification containing one or more queries for selecting one or more messages, one or more messages, and/or one or more predefined phrases to instantiate a document plan. The method of this embodiment may also include applying an optimization specification to the document plan to generate an optimized document plan. | 2015-12-17 |
20150363365 | ACCESSIBILITY DETECTION OF CONTENT PROPERTIES THROUGH TACTILE INTERACTIONS - One or more tactile effects may be mapped to application user interface elements, formatting properties, and document structure and applied to a display comprising tactile capabilities (e.g., deformable screens, vibrations, static charges, heat, etc.). Formatting, structure, and user interface elements may be mapped to different screen variations that may be felt by a visually impaired user. A visually impaired user may be able to utilize his/her sense of touch to more easily comprehend formatting and structure of a document, as well as to have greater confidence to author professional and consistently formatted and structured documents. A tactile effect may be applied to a location of a displayed user interface element, formatting property, or document structure, or may be applied to a designated area of the display. | 2015-12-17 |
20150363366 | OPTIMIZED DOCUMENT VIEWS FOR MOBILE DEVICE INTERFACES - Portions of document contents are separated into individually controlled sections on a user interface of a smaller size client device display. A document viewed on a mobile device may include different content portions such as textual content, tables, slides and graphics. Due to a smaller user interface of the mobile device, some portions of the content may extend outside of the user interface and may not all be visible at the same time. The user may use gestures to scroll through and resize the document to view all of the contents. The system may separate each of the different content portions into individual sections and enable the user to control each section separately, such that the user may navigate, resize, and reposition each individual section without affecting the size and position of the remaining sections of the document for optimally viewing the document on the user interface. | 2015-12-17 |
20150363367 | DISPLAY PROCESSING DEVICE, DISPLAY PROCESSING METHOD, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a display processing device includes a reader and a display controller. The reader is configured to read content data that is to be displayed on a display. The display controller is configured to display, on the display, virtual content data in which one end of a display target area of the content data and the other end opposite to the one end of the display target area are connected, when a width of the display target area is larger than a width of the display. | 2015-12-17 |
20150363368 | Transforming HTML Forms into Mobile Native Forms - Techniques disclosed herein transform HTML forms into forms with graphical user interfaces (UIs) native to mobile devices. A user interface virtualization (UIV) agent divides an HTML form into rows based on row breaks. The UIV agent then identifies name-input pairs in the HTML form by applying a trained naïve Bayes classifier to determine name fields, and mapping the name fields to corresponding input fields. In addition, the UIV agent generates metadata which includes both information describing the rows in the form and the name-input information. Based on the metadata, a native form renderer running in the client device draws the form with native UI elements. In addition, the native form renderer forwards native UI events as HTML events. | 2015-12-17 |