49th week of 2010 patent applcation highlights part 29 |
Patent application number | Title | Published |
20100309699 | POWER FACTOR CORRECTION CIRCUIT - A power factor correction circuit includes a filter capacitor interposed between AC input terminals, a first inductor interposed between the first end of the filter capacitor and an input of a first rectifying bridge circuit, and a second inductor interposed between the second end of the filter capacitor and another input of the first rectifying bridge circuit. The power factor correction circuit further includes a second rectifying bridge circuit including inputs connected to AC input terminals, and outputs connected to a smoothing capacitor. A control circuit controls switching devices in the first rectifying bridge circuit. The power factor correction circuit can facilitate preventing an overcurrent from flowing through diodes and parasitic diodes in the switching devices, using a simple configuration. | 2010-12-09 |
20100309700 | POWER CONVERTER - An inverter circuit ( | 2010-12-09 |
20100309701 | SYNCHRONOUS RECTIFYING DRIVE CIRCUIT WITH ENERGY FEEDBACK FOR VOLTAGE DOUBLER RECTIFER - A current-driven synchronous rectifying drive circuit designed for a T-type voltage doubler rectifier with an energy feedback circuit including a clamp and energy feedback circuit, a high frequency transformer, a current transducer, an energy storage capacitor, an output capacitor, a first and a second synchronous rectifier, and a first drive circuit connected to the first synchronous rectifier and a second drive circuit connected to the second synchronous rectifier. | 2010-12-09 |
20100309702 | DC-TO-AC POWER INVERTER AND METHODS - Embodiments of the invention relate generally to semiconductors for power generation and conversion applications, and more particularly, to devices, integrated circuits, substrates, and methods to convert direct current (“DC”) voltage signals to alternating current (“AC”) voltage signals. In some embodiments, an inverter can include a modulator configured to convert a direct current signal into a first variable signal, and a transformation module configured to step up the first variable signal to form a second variable signal. The transformation module can be configured to generate a first portion of the second variable signal and a second portion of the second variable signal. Further, the inverter can include a waveform generator configured to synchronize the first portion and the second portion of the second variable signal at a frequency to generate an alternating current (“AC”) signal. | 2010-12-09 |
20100309703 | COMPACT AND ACCURATE ANALOG MEMORY FOR CMOS IMAGING PIXEL DETECTORS - The present invention relates to an analog memory circuit, i.e. a sample and hold circuit, wherein the source and the gate of the switching transistor is maintained at a same potential prior and after the sampling process using a transistor circuitry. The analog memory circuit comprises a memory capacitor ( | 2010-12-09 |
20100309704 | In-pakage microelectronic apparatus, and methods of using same - A mounting substrate for a processor includes a die side and a land side with a processor footprint configured on the die side. The processor footprint is coupled to at least one processor interconnect and a microelectronic die is embedded in the mounting substrate. The microelectronic die is coupled to the processor interconnect and communication between a processor to be installed on the processor footprint is in a rate between 10 Gb/s and 1 Tb/s. | 2010-12-09 |
20100309705 | Stacked memory devices - A stacked memory device may include a substrate, a plurality of memory groups sequentially stacked on the substrate, each memory group including at least one memory layer, a plurality of X-decoder layers, at least one of the plurality of X-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups, and a plurality of Y-decoder layers disposed alternately with the plurality of X-decoder layers, at least one of the plurality of Y-decoder layers being disposed between every alternate neighboring two of the plurality of memory groups. | 2010-12-09 |
20100309706 | Load reduced memory module and memory system including the same - A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate. | 2010-12-09 |
20100309707 | PCB CIRCUIT MODIFICATION FROM MULTIPLE TO INDIVIDUAL CHIP ENABLE SIGNALS - A semiconductor package is disclosed having a single CE signal during electrical test and a plurality of CE signals during normal operation thereafter. After electrical testing of the memory die during fabrication, the electrical traces carrying the single CE signal from the memory test pad matrix to each of the memory die may be severed. Severing the electrical traces from the memory test pad matrix electrically isolates the multiple electrical traces between the controller die and memory die, and allows separate and individual CE signals between the controller die and memory die during normal usage of the memory die. | 2010-12-09 |
20100309708 | SEMICONDUCTOR MEMORY - Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA | 2010-12-09 |
20100309709 | UNIT CELL OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE WITH THE SAME - Disclosed are a unit cell capable of improving a reliability by enhancing a data sensing margin in a read operation, and a nonvolatile memory device with the same. The unit cell of a nonvolatile memory device includes: an antifuse having a first terminal between an input terminal and an output terminal; and a first switching unit coupled between a second terminal of the antifuse and a ground voltage terminal. | 2010-12-09 |
20100309710 | Variable Impedance Circuit Controlled by a Ferroelectric Capacitor - A memory cell comprising a ferroelectric capacitor, a variable impedance element and a conductive load is disclosed. The ferroelectric capacitor, characterized by first and second polarization states, is connected between a control terminal and a first switch terminal. The variable impedance element has an impedance between the first and second switch terminals that is determined by a signal on a control terminal. The conductive load is connected between a first power terminal and the first switch terminal. The second switch terminal is connected to a second power terminal. When a potential difference is applied between the first and second power terminals, a potential on the first switch terminal varies in a manner determined by the state of polarization of the ferroelectric capacitor. | 2010-12-09 |
20100309711 | F-RAM Device with Current Mirror Sense Amp - A F-RAM memory device containing a current mirror sense amp. A F-RAM memory device containing a current mirror sense amp coupled to a negative voltage generator. A method of reading data from and restoring data back into F-RAM cells in a 2T2C F-RAM device containing a current mirror sense amp. A method of reading data from and restoring data back into F-RAM cells in a 1T1C F-RAM device. | 2010-12-09 |
20100309712 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization free layer, a first magnetization fixed layer, a second magnetization free layer and a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the second magnetization free layer. The first magnetization free layer has perpendicular magnetic anisotropy, and the first magnetization fixed layer and the second magnetization free layer has in-plane magnetic anisotropy. The first magnetization free layer has: first and second magnetization fixed regions whose magnetization directions are fixed; and a magnetization free region whose magnetization direction is reversible and connected to the first and second magnetization fixed regions. The magnetization free region and the second magnetization free layer are magnetically coupled to each other. In a plane parallel to each layer, center of the second magnetization free layer is displaced in a first direction from center of the magnetization free region. Whereas, the second magnetoresistance element has: a third magnetization free layer whose magnetization easy axis is parallel to a second direction; a second magnetization fixed layer whose magnetization direction is fixed in a third direction perpendicular to the second direction; and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the third magnetization free layer. The second magnetization fixed layer and the third magnetization free layer have in-plane magnetic anisotropy. | 2010-12-09 |
20100309713 | MAGNETIC RANDOM ACCESS MEMORY - An MRAM has: a memory cell including a first magnetoresistance element; and a reference cell including a second magnetoresistance element. The first magnetoresistance element has a first magnetization fixed layer, a first magnetization free layer, a first nonmagnetic layer sandwiched between the first magnetization fixed layer and the first magnetization free layer, a second magnetization fixed layer, a second magnetization free layer and a second nonmagnetic layer sandwiched between the second magnetization fixed layer and the second magnetization free layer. The first magnetization fixed layer and the first magnetization free layer have perpendicular magnetic anisotropy, and the second magnetization fixed layer and the second magnetization free layer have in-plane magnetic anisotropy. The first magnetization free layer and the second magnetization free layer are magnetically coupled to each other. Center of the second magnetization free layer is displaced in a first direction from center of the first magnetization free layer in a plane parallel to each layer. Whereas, the second magnetoresistance element has: a third magnetization free layer whose magnetization easy axis is parallel to a second direction; a third magnetization fixed layer whose magnetization direction is fixed in a third direction perpendicular to the second direction; and a third nonmagnetic layer sandwiched between the third magnetization fixed layer and the third magnetization free layer. The third magnetization fixed layer and the third magnetization free layer have in-plane magnetic anisotropy. | 2010-12-09 |
20100309714 | METHODS, STRUCTURES, AND DEVICES FOR REDUCING OPERATIONAL ENERGY IN PHASE CHANGE MEMORY - Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material. | 2010-12-09 |
20100309715 | STABLE CURRENT SUPPLY CIRCUIT IRRESPECTIVE OF PVT VARIATIONS AND SEMICONDUCTOR HAVING SAME - A current supply circuit comprises a reference voltage generator generating a reference voltage that varies with temperature, a current circuit generating a constant reference current irrespective of the temperature based on the reference voltage, and a current source generating a mirror current by mirroring a base current as a replica current of the reference current. | 2010-12-09 |
20100309716 | SUPPLY VOLTAGE GENERATING CIRCUIT AND SEMICONDUCTOR DEVICE HAVING SAME - A supply voltage generating circuit includes a first charge pump circuit that generates a first internal supply voltage, and second charge pump circuit that generates a second internal supply voltage. The absolute value of the second internal supply voltage is greater than that of the first internal supply voltage. The output terminal of the first charge pump circuit is connected to a secondary-side charging terminal of the second charge pump circuit. The secondary-side is an output-side of the corresponding charge pump circuit, and the charging terminal is an auxiliary charging terminal that supplies an auxiliary charge to a secondary-side output terminal of the corresponding charge pump circuit. The output terminal of the second charge pump circuit outputs a voltage value that is the result of adding a prescribed voltage value to the value of the first internal supply voltage applied to the charging terminal. | 2010-12-09 |
20100309717 | NON-VOLATILE MULTI-BIT MEMORY WITH PROGRAMMABLE CAPACITANCE - Non-volatile multi-bit memory with programmable capacitance is disclosed. Illustrative data memory units include a substrate including a source region and a drain region; and a gate stack structure over the substrate and between the source region and drain region. The gate stack structure includes a first solid electrolyte cell and a second solid electrolyte cell. The solid electrolyte cells having a capacitance that is controllable between at least two states. A gate contact layer is electrically coupled to a voltage source. The first solid electrolyte cell and the second solid electrolyte cell separate the gate contact layer from the substrate. | 2010-12-09 |
20100309718 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation. | 2010-12-09 |
20100309719 | Folding Data Stored in Binary Format Into Multi-State Format Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. | 2010-12-09 |
20100309720 | Structure and Method for Shuffling Data Within Non-Volatile Memory Devices - Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process. | 2010-12-09 |
20100309721 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a nonvolatile semiconductor memory device includes a memory cells, a bit line, a sense amplifier, a memory circuit and an arithmetic circuit. The memory cells store multiple values in one memory cell. The bit line connected with the memory cells. The sense amplifier supplies a write voltage to the bit line. The memory circuit stores one of write data that is to be written in the memory cell and the number of writes. The arithmetic circuit changes the write data stored in the memory circuit to the number of writes and updates the number of writes. The arithmetic circuit controls the write voltage supplied from the sense amplifier based on the write data, and sets the number of writes in accordance with the write data stored in the memory circuit upon confirmation that each memory cell has reached a predetermined threshold voltage. | 2010-12-09 |
20100309722 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. | 2010-12-09 |
20100309723 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REALIZING A CHIP WITH HIGH OPERATION RELIABILITY AND HIGH YIELD - A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder. | 2010-12-09 |
20100309724 | SEMICONDUCTOR MEMORY DEVICE USING ONLY SINGLE-CHANNEL TRANSISTOR TO APPLY VOLTAGE TO SELECTED WORD LINE - A semiconductor memory device has a memory cell array, a first transistor of a first conductivity type, a second transistor of a second conductivity type and a third transistor of the first conductivity type. A source or drain of the first transistor is connected to each of word lines. A drain of the second transistor is connected to a gate of the first transistor. A source of the third transistor is connected to the gate of the first transistor. The gates of the second transistor and the third transistor are not connected, a source of the second transistor is not connected to a drain of the third transistor, and the gate of the second transistor and the drain of the third transistor have different voltage levels corresponding to opposite logic levels each other. | 2010-12-09 |
20100309725 | PAGE BUFFER CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE PAGE BUFFER CIRCUIT, AND METHOD OF OPERATING THE NONVOLATILE MEMORY DEVICE - A page buffer circuit including a bit line selection unit configured to select the first or second bit line in response to a first control signal and couple the selected bit line to a sense node, or to selectively precharge or discharge the first and second bit lines to a first voltage level, a first latch unit configured to store program data and output the stored program data to the sense node, a second latch unit configured to store data of a low logic level in response to a reset signal and discharge a selected bit line from a precharge state to a second voltage level, and a voltage control element configured to raise a voltage level of the sense node or drop a voltage level of the sense node to a third voltage level in response to a second control signal. | 2010-12-09 |
20100309726 | REFERENCE VOLTAGE OPTIMIZATION FOR FLASH MEMORY - A system includes a voltage generator and a reference voltage setting module. The voltage generator is configured to generate K voltages to be applied to memory cells. The K voltages are used to determine a reference voltage used to read the memory cells, where K is an integer greater than 1. The reference voltage setting module is configured to selectively set the reference voltage to a value between two adjacent ones of the K voltages or one of the two adjacent ones of the K voltages. | 2010-12-09 |
20100309727 | METHOD OF OPERATING MEMORY DEVICE HAVING PAGE BUFFER - A method of verifying data in a memory device having a page buffer for performing a program operation, a verifying operation and a read operation, includes: storing data to be programmed in a multi level cell of a first latching circuit in the page buffer; storing reference data set for the verifying operation in a second latching circuit; programming the data stored in the first latching circuit to the multi level cell; and verifying the programming of the data through a first node or a second node in the second latching circuit in accordance with a verifying voltage. | 2010-12-09 |
20100309728 | MEMORY READ METHODS, APPARATUS, AND SYSTEMS - Some embodiments include first memory cells and a first line used to access the first memory cells, second memory cells and at least one second line used to access the second memory cells. The first and second memory cells have a number of threshold voltage values corresponding to a number of states. The states represent values of information stored in the memory cells. During a read operation to read the first memory cells, a first voltage may be applied to the first line and a second voltage may be applied to the second line. At least one of the first and second voltages may include a value based on a change of at least one of the threshold voltage values changing from a first value to a second value. The first and second values may correspond to a unique state selected from all of the states. Other embodiments including additional apparatus, systems, and methods are disclosed. | 2010-12-09 |
20100309729 | NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nonvolatile memory device and method of manufacturing the same are provided. In the nonvolatile memory device, a blocking insulation layer is provided between a trap insulation layer and a gate electrode. A fixed charge layer spaced apart from the gate electrode is provided in the blocking insulation layer. Accordingly, the reliability of the nonvolatile memory device is improved. | 2010-12-09 |
20100309730 | MEMORY ERASE METHODS AND DEVICES - Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge. | 2010-12-09 |
20100309731 | KEEPERLESS FULLY COMPLEMENTARY STATIC SELECTION CIRCUIT - Selection circuitry for use in register files, multiplexers, and so forth is disclosed. The selection circuitry includes a plurality of local bit lines coupled to global bit line circuitry. Groups of cells or data inputs are coupled to each of the local bit lines. When a cell or data input of a given group is selected, a group select signal is provided to the global bit line circuitry. The global bit line circuitry drives a global bit line responsive to the group select signal and the data driven on (or provided to) the local bit line associated with the selected cell/input, thus providing a data output. When no cell of a given group is selected, the group select signal is de-asserted, causing the respective global bit line to be held in a predetermined state. | 2010-12-09 |
20100309732 | DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group. | 2010-12-09 |
20100309733 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device is provided, which includes an input buffer provided with a first inverter that can electrically adjust circuit threshold values, a circuit: threshold value monitor provided with a second inverter having the same circuit configuration as the first inverter to detect the circuit threshold values of the first inverter when the input and output of the second inverter are short-circuited, respectively, a memory storing parameter values that correspond to the circuit threshold values detected by the circuit threshold value monitor, and a data-reader circuit reading the parameter values given to the first inverter from the memory. | 2010-12-09 |
20100309734 | METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND DATA PROCESSING DEVICE FOR MONITORING MEMORY CIRCUITS AND CORRESPONDING INTEGRATED CIRCUIT - An improved method monitors memory circuits, especially those used in integrated circuits. The method provides: writing random data in at least one monitor cell, which is implemented as a regular memory cell with an artificially deteriorated stability in order to provoke early fails when compared to fails in a regular memory cell; reading the random data out of the at least one monitor cell; comparing the output data of the read operation against an expected value to detect a value mismatch; and reporting the value mismatch to an error structure if the value mismatch is detected. | 2010-12-09 |
20100309735 | INTERNAL POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit. | 2010-12-09 |
20100309736 | SRAM WITH READ AND WRITE ASSIST - A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal. | 2010-12-09 |
20100309737 | SIGNAL ADJUSTING SYSTEM AND SIGNAL ADJUSTING METHOD - A signal adjusting system includes: a signal generating apparatus for transmitting a first driving signal and a second driving signal, a plurality of signal transmitting paths coupled to the signal generating apparatus, and a controlling apparatus coupled to the plurality of signal transmitting paths for receiving a first transmitted signal corresponding to the first driving signal and a second transmitted signal corresponding to the second driving signal, and detecting a phase difference between the first transmitted signal and the second transmitted signal to generate a detected result for the signal generating apparatus, wherein the signal generating apparatus adjusts a first driving ability of the first driving signal and a second driving ability of the second driving signal according to the detected result. | 2010-12-09 |
20100309738 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a bit line pair electrically connected to a memory cell and a bit line sense amplifier for detecting and amplifying voltage levels of the bit line pair. The semiconductor memory apparatus is configured to perform a test to determine the occurrence of leakage current by deactivating the bit line sense amplifier and applying a test voltage to the bit line pair when the semiconductor memory apparatus is in test mode. | 2010-12-09 |
20100309739 | SEMICONDUCTOR MEMORY APPARATUS AND PROBE TEST CONTROL CIRCUIT THEREFOR - Disclosed probe test control circuit includes: a bank active circuit configured to generate a bank active signal in response to a bank address and bank-by-bank test control signals; and a mat active circuit configured to generate a mat-by-mat sub-wordline selection signal and provide the mat-by-mat sub-wordline selection signal to a selected memory bank, in response to a row address signal, a row address enable signal and a mat-by-mat test control signal. | 2010-12-09 |
20100309740 | Low Power, Single-Ended Sensing in a Multi-Port SRAM Using Pre-Discharged Bit Lines - An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; releasing the bit line from being held at a zero voltage potential when the memory cell is being accessed; charging the bit line to a first voltage potential greater in value than the zero voltage potential during an access of the memory cell, wherein charging the bit line to a first voltage potential occurs for a first predetermined period of time after access to the memory cell has begun; and sensing the memory cell contents during an access of the memory cell, wherein sensing of the memory cell contents occurs for a second predetermined period of time after access to the memory cell has begun. | 2010-12-09 |
20100309741 | SEMICONDUCTOR DEVICE - The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL. | 2010-12-09 |
20100309742 | METHOD CONTROLLING DEEP POWER DOWN MODE IN MULTI-PORT SEMICONDUCTOR MEMORY - Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports. | 2010-12-09 |
20100309743 | POWER DETECTING CIRCUIT, PORTABLE DEVICE AND METHOD FOR PREVENTING DATA LOSS | 2010-12-09 |
20100309744 | SEMICONDUCTOR MEMORY DEVICE FOR GUARANTEEING RELIABILITY OF DATA TRANSMISSION AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device includes a system clock input unit configured to receive a system clock for synchronizing input times of an address signal and a command signal from a memory controller, a data clock input unit configured to receive first and second data clocks for synchronizing an input/output time of a data signal from the memory controller, wherein a phase of the second data clock is shifted according to a training information signal, and the second data clock having the shifted phase is inputted to the data clock input unit, and a phase detection unit configured to detect a logic level of the second data clock based on an edge of the first data clock, and generate the training information signal to transmit the generated signal to the memory controller according to the detected logic level. | 2010-12-09 |
20100309745 | KNEADING DEGREE ADJUSTING APPARATUS, EXTRUDER AND CONTINUOUS KNEADER - Provided is a kneading degree adjusting apparatus, which can have a wide adjusting range for a kneading degree even if a gate member and a cylindrical segment are not made so close as to invite a fear of metallic contacts. The kneading degree adjusting apparatus is disposed in a kneading treatment equipment, which includes a cylindrical segment formed at a predetermined portion and a kneading screw for kneading a material while feeding the same to the downstream side, thereby to adjust the kneading degree of the material. The kneading degree adjusting apparatus comprises a gate member having an opposed face confronting the outer circumference of the cylindrical segment and moved toward and away from the outer circumference of the cylindrical segment thereby to change the area of the material passage to be formed between the opposed face and the outer circumference of the cylindrical segment. The outer circumference and the opposed face are corrugated to form the passage into a bent shape. | 2010-12-09 |
20100309746 | Ultraclean Magnetic Mixer with Shear-Facilitating Blade Openings - A magnetically-coupled liquid mixer having a drive mount secured to and extending into a mixing vessel, a vessel-external first magnet array adjacent to the drive mount, a stub shaft extending into the vessel and having a first thrust bearing surface, a driven portion rotating on the stub shaft and having radially-mounted mixing blades a subset of which is characterized by each having an opening through which liquid flows during rotation, a second thrust bearing surface, and a second magnet array, the arrays being positioned with respect to one another such that the thrust bearing surfaces are spaced apart at least in the absence of above-threshold fluid dynamic thrust forces on the driven portion, the blade-opening feature introducing increased fluid shear into the liquid. | 2010-12-09 |
20100309747 | SYNCHRONOUS RECORDING SYSTEM AND SYNCHRONOUS RECORDING METHOD - A synchronous recording system is configured with a first seismograph and a second seismograph. The first seismograph includes a sensor, a GPS receiver, a data buffer, and a synchronous information transmission program that transmits synchronous information to the second seismograph, the information designating recording start time. The second seismograph includes a sensor, a GPS receiver, a data buffer, a recorder, a synchronous information reception program that receives the synchronous information, and a recording control program that starts, based on the synchronous information, recording in the recorder of oscillation data, which is recorded in the data buffer, from the designated recording start time. | 2010-12-09 |
20100309748 | Method and Apparatus for Determining Radial Shear Velocity Variation From Dipole Acoustic Logging - A radial shear velocity profile of an earth formation is obtained by using dipole and/or cross-dipole measurements. The non-uniqueness in the inversion is addressed by using a constraint based on the fact that high-frequency dipole shear waves are mostly sensitive to the near-borehole shear velocity. | 2010-12-09 |
20100309749 | METHODS AND SYSTEMS FOR MULTICOMPONENT TIME-LAPSE SEISMIC MEASUREMENT TO CALCULATE TIME STRAINS AND A SYSTEM FOR VERIFYING AND CALIBRATING A GEOMECHANICAL RESERVOIR SIMULATOR RESPONSE - A system, method, and computer program configured to provide an electronic method for seismic time-lapse characterization of an underground formation are provided. The method includes decomposing, with microprocessor executing a predefined set of instructions stored in a memory, baseline and monitor seismic survey data of a formation into a four dimensional Clifford Algebraic form; extracting, via the microprocessor, time delays from a matrix of decomposed sensor measurement vectors generated based on the four dimensional Clifford Algebra form; and determining, via the processor, time strains for the underground formation from differences in the extracted time delays from the matrix before displaying the determined time strains for the underground formation to a user via a monitor or a hard copy printed document. A procedure is also provided to calibrate and refine the static and dynamic models of an underground formation using the results from the seismic time-lapse characterization. | 2010-12-09 |
20100309750 | Sensor Assembly - An assembly for passive detection of features at known locations of a conduit. The assembly is a sensor assembly particularly well suited for detection of casing collars at known locations of cased wells, such as segmented hydrocarbon wells. Thus, the assembly is able to provide real time positioning information relative to any tool coupled thereto which is being advanced in the well pursuant to a well application. Given that the detection takes place in a passive manner via the combination of a magneto-responsive sensor and voltage responsive device, no separate dedicated power source or additional electronics are required. | 2010-12-09 |
20100309751 | SONAR SYSTEM AND PROCESS - A sonar system and method of use capable of discriminating a direct acoustic signal present at 60 dB or more above the acoustic echo signal. | 2010-12-09 |
20100309752 | Method and device of measuring location, and moving object - Disclosed is a moving object and a location measuring device and method thereof that may transmit an ultrasound signal to the moving object through a plurality of ultrasound transmitting units, and may estimate a location of the moving object at a current time based on distance information of distances between the moving object and the plurality of ultrasound transmitting units measured based on the transmitted ultrasound, inertia information, and location information of the moving object at a time prior to the current time. | 2010-12-09 |
20100309753 | FISH FINDER - This disclosure provides a fish finder, which includes a transmission module and a reception module, for outputting an ultrasonic wave underwater, receiving an echo, and outputting a reception signal corresponding to an intensity of the received echo, a control module for generating echo data corresponding to a depth based on the reception signal, a display module for displaying the echo data, and a user interface for receiving a user's operation. The control module causes the display module to display the echo data so that the echo data is displayed in two or more display screens. At least one display screen displays an area having a color different from a background color. A part of the echo data at a depth range corresponding to a height of the area is displayed in the other display screen so as to expand the echo data in a depth direction. The user interface specifies a position and a size of the area via the user's operation. | 2010-12-09 |
20100309754 | Alarm Clock With Nap Timer - An alarm clock includes a nap timer. At least one button may be used to add a predetermined time interval to a total nap time, while the clock is in its normal timekeeping mode. No further actions are necessary in order to set a nap time. An alarm will sound upon the elapsing of the set nap time. | 2010-12-09 |
20100309755 | WATCHBAND ATTACHING STRUCTURE AND WRISTWATCH WITH THE STRUCTURE - A watchband attaching structure includes paired projections provided on a case-side end part of a watchband and having coaxial first through-holes, and an intermediate part provided at a predetermined position on an outer circumference of a wristwatch case, placed between the projections, and having a second through-hole coaxial to the first holes. A diameter of the second hole is smaller than that of the first hole. Headed first and second screw members inserted into center holes of first and second tubular members are introduced into the first holes of the projections and the second hole of the intermediate part from both sides thereof. Male threads and female threads of the distal ends of the first and second members are connected to each other in the second hole while the heads thereof with the first and second tubular members are arranged in the first holes of the projections. | 2010-12-09 |
20100309756 | ROTATION SWITCH AND ELECTRONIC TIMEPIECE - A rotation switch includes an operating member that is operable to rotate, a magnet member that rotates integrally with the operating member, a magnetic sensor that is placed opposite to the magnet member, and a frame-shaped anti-magnetic shield plate that surrounds the periphery of the magnetic sensor. | 2010-12-09 |
20100309757 | Disc Access Apparatus and Disc Access Method - The directory information on a file system recorded on an optical disc is cached onto a hard disk as a directory table. When accessing a file on the optical disc, a processor references the directory table so as to obtain information related to a position, on the disc medium, where the file to be accessed is located, without accessing the directory information on the optical disc. A disc I/O controller moves a pickup unit to the location indicated by the positional information on the file to be accessed and reads the data on the file. The pickup unit is used to detect signals from the optical disc. | 2010-12-09 |
20100309758 | TRACKING SERVO METHOD OF OPTICAL VIDEO DISC PLAYER AND ITS SPECIAL DEVICE - A tracking servo method of an optical video disc player and its special device which accomplish angle adjustment in a simple, time-saving and effort-saving manner and improve the tracking servo capability of the optical video disc player. In the tracking servo method of an optical video disc player, a laser beam is split into a main beam and two sub beams, and tracking error signal generated from the two sub beams are subtracted from tracking error signal generated by the main beam; light spot of the main beam is circular in shape, and light spots of the two sub beams are elliptical in shape. The special device has an effective grating region ( | 2010-12-09 |
20100309759 | RECORDING AND REPRODUCING METHOD, RECORDING AND REPRODUCING DEVICE AND RECORD CARRIER - A recording and reproducing method for recording and/or reproducing information from a record carrier that comprises a plurality of recording layers layered in its film thickness direction and a guide layer having a plurality of tracks carrying tracking servo information, wherein a record mark is formed on each recording layer of the record carrier. The method comprises: a focusing step of converging a servo light beam onto the guide layer as well as selectively converging a main light beam group onto one of the recording layers through a common objective lens, wherein the main light beam group comprises a plurality of main light beams neighboring each other; a tracking step of performing a positioning control of the objective lens so that the servo light beam is tracking on one of the tracks; and a recording and/or reproducing step of performing recording and/or reproducing information with the main light beam group while performing the focusing step and the tracking step. When the servo light beam traces on one of the tracks neighboring each other, one trace group is composed of the main light beam group on the one of the recording layers, wherein, when the servo light beam traces on the other of the tracks neighboring each other, the other trace group is composed of the main light beam group on the one of the recording layers, wherein an interval between the one trace group and the other trace group is larger than an average trace pitch within the trace group. | 2010-12-09 |
20100309760 | RECORDING MEDIUM HAVING DATA STRUCTURE FOR MANAGING REPRODUCTION OF MULTIPLE AUDIO STREAMS RECORDED THEREON AND RECORDING AND REPRODUCING METHODS AND APPARATUSES - A recording medium having a data structure for managing reproduction of multiple audio streams is discussed. The recording medium according to an embodiment includes a data area storing at least multiple audio streams in at least one portion thereof, the multiple audio streams being multiplexed, each audio stream being a transport stream and stored as one or more packets, each packet having a packet identifier, and the packets of a same audio stream having a same packet identifier, and a management area including management information for managing reproduction of the multiple audio streams. | 2010-12-09 |
20100309761 | PRE-HEATING OF RECORDING MEDIA IN AN OPTICAL WRITING DEVICE - An optical writing device and methods and computer programs for writing data on an optically recordable medium are provided. One embodiment is a method for writing data on an optically recordable medium. One such method comprises: pre-heating a writing location on a recordable medium using a heat source to a temperature below a writing threshold temperature of the recordable medium; and writing on the writing location using a laser source by raising the temperature of the recording location above the writing threshold temperature. | 2010-12-09 |
20100309762 | OPTICAL DISC RECORDING APPARATUS AND METHOD, AND COMPUTER PROGRAM - An information recording apparatus ( | 2010-12-09 |
20100309763 | OPTICAL DISC RECORDING DEVICE, METHOD, AND COMPUTER PROGRAM - An information recording apparatus ( | 2010-12-09 |
20100309764 | MULTILAYERED OPTICAL DISK AND ITS RECORDING METHOD - To provide a recording method of a multilayered optical disk having three or more recording layers, for performing recording while securing sufficient test areas without reducing user data areas, and while suitably controlling the power of laser beam irradiated onto each of the layers. The method uses an optical disk which has at least a first recording layer and a second recording layer located on the side nearer to the light incident surface than the first recording layer, and which respectively has a first test area configured by a plurality of segments in the first recording layer and a second test area configured by a plurality of segments in the second recording layer. Further, the method is configured such that there is defined beforehand a predetermined radial distance L corresponding to relative precision of radial positions between the plurality of layers and the optical spot diameter, and that when an arbitrary segment in the second test area is test-recorded, a segment in the first test area, the radial distance of which from the recorded test area in the second test area is within the range of the predetermined radial distance L, is set as a segment in which the test recording is not performed. Thereby, even in the case where the radial positions of the test areas of the plurality of layers are substantially overlapped with each other, it is possible to precisely perform the learning of optical power. For this reason, it is possible to use and arrange the test areas of the plurality of layers without waste. Further, the learning of recording power can be performed without receiving the influence of the recorded state of the other layers, so that the accuracy of the learning of recording power can be improved. Thereby, it is possible to improve the quality of recording and the reliability of recorded data. | 2010-12-09 |
20100309765 | WRITE ONCE DISC ALLOWING MANAGEMENT OF DATA AREA, METHOD OF MANAGING THE DATA AREA, AND APPARATUS AND METHOD FOR REPRODUCING DATA FROM WRITE ONCE DISC - A write once disc allowing management of a data area, a method of managing the data area of the write once disc, an apparatus recording data on the write once disc, an apparatus and method of reproducing data from a write once disc. The write once disc, includes a lead-in zone, a data area, and a lead-out zone. The write once disc includes a predetermined area storing area allocation information which indicates whether at least one section of the data area is allocated for disc defect management. In the disc and method, area allocation information specifying a structure of the data area is recorded on the disc, thus allowing a recording/reproducing apparatus to recognize the data area structure. Therefore, allocating areas, such as a spare area, for disc defect management other than an area for storing user data, to the data area is possible. The allocation of the areas for disc defect management to the data area enables effective use of the write once disc. | 2010-12-09 |
20100309766 | TRACKING CONTROL DEVICE, TRACKING CONTROL METHOD, AND OPTICAL DISC APPARATUS - The invention provides a tracking control device, a tracking control method, and an optical disc apparatus that enable to stably perform the tracking control, and reduce an influence of stray light from the other layer on the tracking control. A sub push-pull signal correcting section corrects a sub push-pull signal to be generated from returning light of a sub beam in such a manner that a track crossing component of a main push-pull signal to be generated from returning light of a main beam, and a track crossing component of the sub push-pull signal to be generated from the returning light of the sub beam are canceled. A low pass filter reduces a high frequency component of the sub push-pull signal corrected by the sub push-pull signal correcting section. A subtractor subtracts a sub push-pull signal passing the low pass filter from the main push-pull signal to thereby generate a tracking error signal. | 2010-12-09 |
20100309767 | OPTICAL INFORMATION RECORDING METHOD, OPTICAL INFORMATION RECORDING DEVICE AND OPTICAL INFORMATION RECORDING MEDIUM - The present invention provides an optical information recording apparatus and method capable of effectively determining appropriate recording parameters in a short time with favorable efficiency, when recording information onto an optical disk having different information recording conditions and information recording characteristics. An information recording condition or an information recording characteristic of an optical disk | 2010-12-09 |
20100309768 | HOLOGRAM DISC READING AND WRITING APPARATUS AND HOLOGRAM DISC READING APPARATUS - A hologram disc reading and writing apparatus including a signal light source module, a beam splitter, a reference/reading light source, a reflector, and an optical reading head and a hologram disc reading apparatus are provided. A signal light beam emitted from the signal light source module is transmitted to a data region of a hologram disc through the beam splitter. The reference/reading light source, the signal light source module, and the optical reading head are disposed at the same side of the hologram disc. The reflector is disposed at the other side. A spherical wave light beam emitted from the reference/reading light source is transmitted through the data region and reflected by the reflector to form a phase conjugate light beam transmitted to and through the data region. The phase conjugate light beam is transformed to a data light beam transmitted to the optical reading head through the beam splitter. | 2010-12-09 |
20100309769 | OPTICAL PICKUP - In an optical pickup, a photo receiving portion for receiving returned light reflected by an optical disc is adhered and fixed to an optical base. The photo receiving portion has a photodetector and a plate on which the photodetector is loaded. The plate is fixed onto the optical base by adhesive such that the photo receiving portion is adhered and fixed to the optical base. The plate is in a substantially circular shape in plan view. | 2010-12-09 |
20100309770 | Optical head device and optical information recording/reproducing device - To provide an optical head device and an optical information recording/reproducing device for recording/reproducing a signal on/from an optical recording medium having two recording layers without generating the disturbance on the track error signal detected with differential push-pull method even if the interval between the target layer and the non-target layer changes. The light beam emitted from a semiconductor laser is divided into a zeroth order main beam and a positive and a negative first order diffracted light sub-beams by a diffractive optical element. The light beams are applied onto a disk by an objective lens. The reflected light beam of the main beam and reflected light beams of the sub-beams from the disk are received by a photodetector. From the output of the photodetector, a differential push-pull signal is calculated, and used as a track error signal. The sub-beams become Laguerre-Gauss beams by the diffractive optical element. | 2010-12-09 |
20100309771 | OPTICAL HEAD APPARATUS, OPTICAL DISK APPARATUS AND OPTICAL DISK - [Object] A recoding playback apparatus and an optical disk are provided that allows reduction of a low frequency noise at a time of playback of a super resolution optical disk including small record marks whose size is below the diffractive limitation, to enhance quality of a playback signal. | 2010-12-09 |
20100309772 | STORAGE MEDIUM, REPRODUCING METHOD, AND RECORDING METHOD - According to one embodiment, a write-once type information storage medium comprises an organic dye based recording material having sensitivity at a wavelength of 405 nm and at a recording wavelength in the range of 600 nm to 700 nm, wherein, when absorbance of a maximum absorption wavelength in the vicinity of 405 nm is defined as 1, the absorbance is 5% or more at any wavelength in the range of 600 nm to 700 nm. | 2010-12-09 |
20100309773 | INFORMATION RECORDING MEDIUM AND RECORDING/REPRODUCING DEVICE - An information recording medium according to the present invention includes a track on which a data sequence including a plurality of recording marks and a plurality of spaces provided between the plurality of recording marks is recordable; and a recording condition recording area in which a recording condition for recording the data sequence on the track is recordable. Where a recording mark which is included in the data sequence and is to be formed on the track based on the recording condition is a first recording mark, when a length of the first recording mark is longer than a prescribed length, the recording condition is classified using a combination of the length of the first recording mark and a length of a first space located adjacently previous or subsequent to the first recording mark, and when the length of the first recording mark is equal to or shorter than the prescribed length, the recording condition is classified using a combination of the length of the first recording mark, the length of the first space, and a length of a second space not located adjacent to the first space and located adjacent to the first recording mark. | 2010-12-09 |
20100309774 | METHOD AND APPARATUS FOR CROSS-TALK CANCELLATION - The present invention addresses the problem of a second (or higher) order representation of a transmit signal which is transmitted by a transceiver being mixed into the region of the frequency spectrum of interest to the transceiver receiver, such that it can not then be spectrally filtered out. At its most straightforward, in one embodiment of the invention this is achieved by providing a cross-talk cancellation unit which takes the transmit signal, and obtains the second (or higher) order representation thereof. This representation is then subtracted from the received signal before the signal is passed to the radio control receiver signal processing elements. However, in a more preferred arrangement a filter is also provided, to filter the second or higher order version of the transmit signal, prior to its being subtracted from the received signal. The filter basically takes out the effects of any other filtering or processing which has happened to the transmit signal in the receiver signal chain. This would be, for example, the filtering effects provided by the anti-aliasing filter in the receiver. | 2010-12-09 |
20100309775 | Transmission Using Nested OFDMA - A transmission of information within a wireless cellular network may include a first and second group of samples. A first group of samples is created comprising at least a first and a last subgroup, wherein the last subgroup is same as the first subgroup. A second group of samples created. A transformed set of samples produced by jointly transforming the created first and second group with a discrete Fourier transform (DFT). The transformed set of samples is expanded to produce an expanded set, and the expanded set is transformed with an inverse discrete Fourier transform (IDFT) to produce an OFDM symbol with a fractional payload. The first group of samples is a reference signal (RS), which is known to the receiver before the transmission occurs, while the second group of samples is information data. | 2010-12-09 |
20100309776 | Allocating Bandwidth in a Resilient Packet Ring Network by P Controller - Implementations and techniques for allocating bandwidth in a resilient packet ring network by a P-type controller are generally disclosed. | 2010-12-09 |
20100309777 | NODE APPARATUS, PROCESSING UNIT, AND CONTROL FRAME PROCESSING METHOD - A method for processing a control frame for controlling path protection switching between redundant paths including a working path and a protection path, which is executed at one of two node apparatuses coupled mutually via the redundant paths, the method comprising: at the time of switching of the redundant paths, stopping monitoring whether the control frame has been received via a previous working path which is the path used as the working path until the switching is completed; determining whether the other of the two node apparatuses has stopped transmitting the control frame via a new working path which is the path used as the working path after the switching is completed; and starting monitoring whether the control frame has been received via the new working path, when it is determined that the second apparatus has stopped transmitting the control frame via the new working path. | 2010-12-09 |
20100309778 | USE OF 1:1 PROTECTION STATE MACHINE FOR LOAD SHARING AND ALTERNATIVE PROTECTION SCHEMES - A system is provided for sharing a protection path between at least two protection groups in a network. The system includes at least one working path associated with each of the protection groups, and at least one working maintenance entity group (“WMEG”) monitoring the status of each of the working paths. Each WMEG notifies the protection group associated with the monitored working path of changes in the status of the monitored working path. At least one protection entity group (“PMEG”) monitors the status of the protection path and notifies each of the protection groups of changes in the status of the protection path. Each of the protection groups is switchable to the protection path in response to the receipt of notifications from the WMEG of changes to a non-operational status for the respective working paths associated with each of the protection groups. | 2010-12-09 |
20100309779 | Carrier sense multiple access (CSMA) for multiple user, multiple access, and/or MIMO wireless communications - Carrier sense multiple access (CSMA) for multiple user, multiple access, and/or MIMO wireless communications. In wireless communication systems that operate in supporting communications via one or more clusters, appropriate determination of when to begin making such transmissions on one or more clusters is made in accordance with intelligent carrier sense multiple access (CSMA) that may be performed in a number of different ways. In accordance with this, a cluster may be any combination composed of one or more channels among one or more bands. In supporting multi-cluster access, CSMA may be performed in selecting a primary cluster and performing backoff (e.g., countdown) thereon. After backoff is finished for the primary cluster, and the availability of one or more others clusters is checked, transmissions may be made using the available clusters. Alternatively, backoff may be made for each or multiple (a subset of) clusters or even individually for each respective cluster. | 2010-12-09 |
20100309780 | Allocating Bandwidth in a Resilient Packet Ring Network by PI Controller - Implementations and techniques for allocating bandwidth in a resilient packet ring network by a PI-type controller are generally disclosed. | 2010-12-09 |
20100309781 | SWITCHING BETWEEN MIMO AND RECEIVER BEAM FORMING IN A PEER-TO-PEER NETWORK - Aspects describe different multiple antenna techniques that can be utilized in a peer-to-peer network based on a network congestion level. A MIMO scheme where a transmitter sends to a receiver multiple spatial streams at substantially the same time in the same traffic segment can be utilized when network congestion level is low. A receiver beam forming scheme where transmitter sends a single stream in a traffic segment and receiver uses multiple receive antennas to maximize signal to noise ratio can be utilized when network congestion level is high. The connection pair (transmitter and receiver) occupy more control resources in the MIMO scheme than the receiver beam forming scheme. The decision related to which technique to utilize can be made at about the same time as a communication is initiated. Further, if network conditions change during a communication, the antenna technique that is utilized can be switched to a different technique during the communication exchange. | 2010-12-09 |
20100309782 | APPARATUS AND METHOD FOR MANAGING AN ACCESS MODE OF A NODE B IN A WIRELESS COMMUNICATION SYSTEM - An apparatus and a method for managing an access mode of an NB in a wireless communication system. In the method for changing the access mode of a second NB at a first NB or a CN, an access mode change of the second NB is determined. An access mode change request message is transmitted to the second NB, requesting the access mode change of the second NB. An access mode change response message including an access mode control result is received from the second NB. | 2010-12-09 |
20100309783 | Latency based Random Early Discard for Network Packets - Methods, systems, and apparatus used to determine whether to discard a network packet based upon the latency exhibited by an associated a network packet queue. Network devices can include a queue management module operable to identify a latency metric in network packet queues and determine whether the latency metric renders the network packet queue eligible for discarding packets based upon, for example, a latency policy. | 2010-12-09 |
20100309784 | Selection of an Edge Node in a Fixed Access Communication Network - A method and apparatus for selecting an edge node from a plurality of edge nodes in a fixed access communications network. A selection node receives from a host entity a request for a network service. The selection node then obtains, from at least one further network node, data relating to a plurality of edge nodes. On thebasis of the retrieved data, the selection node selects an edge node from the plurality of edge nodes, wherein the selected edge node provides a path between the host entity and the requested network service. The selection node then sends a response to the host entity, the response including information identifying the selected edge node. | 2010-12-09 |
20100309785 | ADMISSION CONTROL IN A TELECOMMUNICATION NETWORK - A method and system for performing admission control in a packet-based telecommunication network includes a backbone network coupled between at least two access networks. When a first user on a first access network wants to communicate with a second user located on a different access network, a request is made to a quality server whether network resources are available. The quality server separately monitors both access networks and the backbone network and determines whether network resources are available to satisfy the request. In one embodiment, a two-tier approach is used wherein a coordinator module interacts with an admission control subsystem including a plurality of subsystem modules. Each admission control subsystem module is responsible for monitoring a part of the network, such as, one access network or a backbone network. The coordinator module determines which subsystem modules are associated with the user request and interrogates such subsystem modules as to resource availability. | 2010-12-09 |
20100309786 | MANAGING A NETWORK FLOW USING APPLICATION CLASSIFICATION INFORMATION AND ACTIVE SIGNALING RELAY - Techniques for classifying and managing network flows associated with a network service using application classification information and active signaling relay are described. A network device, for example, includes a signaling interceptor and a network flow interface. The signaling interceptor monitors a communication between a customer device and an application server, and identifies a network flow associated with a network service provided to the customer device by the application server. The network flow interface applies a policy to the identified network flow. An active signaling relay module communicates with the application server using data injected within the signaling communications, and utilizes the injected data to further control the network flows and the delivery of the network service. | 2010-12-09 |
20100309787 | METHOD AND SYSTEM FOR SYMMETRIC TRANSMIT AND RECEIVE LATENCIES IN AN ENERGY EFFICIENT PHY - Aspects of a method and system for symmetric transmit and receive latencies in an energy efficient PHY are provided. In this regard, a delay introduced by a PHY of a network device for outbound traffic and a delay introduced by the PHY for inbound traffic may be controlled such that a transmit delay of the network device is equal, within a tolerance, to a receive latency of the network device. The delays may be controlled based on whether one or more energy efficiency features are enabled in the PHY. The delay introduced by the PHY for outbound traffic may be controlled based on an amount of buffered inbound traffic. The delay introduced by the PHY for inbound traffic may be controlled based on an amount of buffered outbound traffic. The delays may be controlled such that said receive latency and the transmit latency are approximately constant regardless of a mode of operation of the network device. | 2010-12-09 |
20100309788 | SYSTEMS AND METHODS TO PROVIDE FLOW CONTROL FOR MOBILE DEVICES - Systems, methods, and apparatuses are disclosed to facilitate wireless communications. User equipment (UE), such as a mobile device, identifies data congestion and transmits a recommended data rate modification wireless signal (e.g., a recommended reduced data rate) to the base station that is transmitting data to the UE. The base station may reduce the data rate of the down link (DL) to the reduced data rate. The UE may then receive data from the base station at the reduced data rate. Therefore, flow control may be implemented at the base station side (e.g., sometimes referred to as the Network (NW) side) based upon the reduced data rate modification determined and transmitted by the UE to the base station. In this way, the data rate transmission to the UE can be reduced to allow the UE to successfully process received data and successfully perform its functions. | 2010-12-09 |
20100309789 | ROUTING-BASED PROXIMITY FOR COMMUNICATION NETWORKS - A node in an overlay network requests a ranked list of other nodes in multiple areas of the overlay network that can provide a desired piece of content or service to the requesting node. A separate node such as a router generates the ranked list using a routing algorithm, returning the list to the requesting node so that the requesting node may acquire the desired content or service from the nearest node in the overlay network. | 2010-12-09 |
20100309790 | Femto base stations and methods for operating the same - Femto base stations and methods described herein suppress the need for an external GPS antenna and cable, while still providing a network service provider with the ability to obtain the desired GPS location coordinates and the user with the flexibility of placing the femto cell at the location of their choice within a home regardless of GPS signal strength. | 2010-12-09 |
20100309791 | EDGE-BASED LOSS-OF-SIGNAL DETECTION - Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data. | 2010-12-09 |
20100309792 | METHOD AND DEVICE FOR DATA RELAY TRANSMISSION IN WIRELESS RELAY NETWORK - A method and a device for data relay transmission in a wireless relay communication network are provided, in which, the relay station directly obtains corresponding egress CID related information based on input MAC PDUs, then generates output MAC PDUs including the egress CID related information, and at last, according to the egress CID related information, performs QoS scheduling for the output MAC PDUs, so as to output them in an sequence of QoS. The invention omits the steps of de-cascading, de-segmenting or de-capsulating the MAC PDUs in order to obtain MAC SDUs, and the steps of scheduling by category, cascading, segmenting, and encapsulating the MAC SDUs in order to re-generate the MAC PDUs in the prior art, and the invention simplifies the data processing procedure and achieves the goal of decreasing the relay latency. Preferably, before the relay station generates the output MAC PDUs based on the input MAC PDUs, it can also schedule the input MAC PDUs based on the ingress CID information therein, so as to further improve the QoS service performance. | 2010-12-09 |
20100309793 | METHOD OF ESTIMATING SIGNAL-TO-NOISE RATIO, METHOD OF ADJUSTING FEEDBACK INFORMATION TRANSMISSION, ADAPTIVE MODULATION AND CODING METHOD USING THE SAME, AND TRANSCEIVER THEREOF - A method of estimating a signal-to-noise ratio by considering user mobility, a method of adjusting feedback information transmission, an adaptive modulation and coding method using the same, and a transceiver thereof are disclosed. The present invention includes measuring a first channel parameter and a second channel parameter using first and second symbols sequentially received, respectively, estimating a channel quality considering a time delay between measurements of the first and second channel parameters using the first and second channel parameters, and transmitting information for the estimated channel quality if a variation of the first and second channel parameters is equal to or greater than a prescribed threshold. Accordingly, the present invention reduces performance degradation and feedback overhead caused by a time delay in channel quality estimation. | 2010-12-09 |
20100309794 | DPI MATRIX ALLOCATOR - A deep packet inspection (DPI) allocator for managing bandwidth in a communication channel, the DPI allocator comprising: a DPI application for inspecting data packets propagating to a destination via the channel that enter the allocator; and at least one service application for processing data packets that enter the allocator. | 2010-12-09 |
20100309795 | DYNAMICALLY RIGHT-SIZING PREFIXES FOR NETWORK AND APPLICATION PERFORMANCE - In one embodiment, performance parameters may be determined for each of a plurality of network address prefixes in a computer network. Based on the respective performance parameters, the prefixes may be resized through at least one of consolidation of adjacent prefixes and splitting of prefixes, and traffic may then be routed in the computer network based on the resized prefixes. | 2010-12-09 |
20100309796 | REDUCED-COMPLEXITY EQUALIZATION WITH SPHERE DECODING - Techniques for spherical decision-feedback sequence estimation are disclosed. A received signal is equalized by forming a trellis comprising a plurality of stages, each stage corresponding to a symbol time and comprising a plurality of nodes, each having a node state. A most likely received symbol sequence is identified by evaluating cumulative state metrics for the nodes according to MLSE or DFSE criteria. The trellis is formed by selecting a set of fan-out branches for each node by identifying, of all possible state transition branches from the node to successor nodes in the succeeding stage, those state transition branches that have a spherical branch metric less than a pre-determined metric limit, and determining the cumulative state metric for each node as a function of the cumulative state metrics for predecessor nodes in the preceding stage and the spherical branch metrics for fan-out branches connecting the predecessor nodes to the node. | 2010-12-09 |
20100309797 | Signal Measurements Based on Sync Signals - Methods and apparatus for determining a load estimate in a receiver in an orthogonal frequency division multiplex (OFDM) communication system include detecting at least one OFDM symbol of at least one predetermined synchronization signal; determining a signal strength measure based on the detected at least one synchronization symbol; detecting at least one OFDM symbol nearby to the OFDM symbol of the at least one predetermined synchronization signal; determining a total signal power measure based on the detected at least one nearby OFDM symbol; and determining the load estimate based on the signal strength measure and the total signal power measure. | 2010-12-09 |
20100309798 | Discontinuous Transmission and Reception - There is provided a method of determining a discontinuous reception and/or transmission cycle length, the method comprising determining information relevant to the cycle length from a high layer in a protocol stack; providing the information to a lower layer in the protocol stack; and in the lower layer of the protocol stack, determining the cycle length from the information. | 2010-12-09 |