49th week of 2013 patent applcation highlights part 76 |
Patent application number | Title | Published |
20130326179 | HOST MEMORY LOCKING IN VIRTUALIZED SYSTEMS WITH MEMORY OVERCOMMIT - A system and method for handling requests by virtual machines (VMs) to lock portions of main memory are disclosed. In accordance with one embodiment, a host operating system (OS) of a computer system receives a request by the guest OS of a VM to lock a portion of main memory of the computer system. The host OS determines whether locking the portion of main memory violates any of a set of constraints pertaining to main memory. The host OS locks the portion of main memory when locking does not violate any of the set of constraints. The locking prevents any page of the portion of main memory from being swapped out to a storage device. The host OS can still swap out pages of main memory that are not allocated to this VM and are not locked by any other VM. | 2013-12-05 |
20130326180 | MECHANISM FOR OPTIMIZED INTRA-DIE INTER-NODELET MESSAGING COMMUNICATION - Point-to-point intra-nodelet messaging support for nodelets on a single chip that obey MPI semantics may be provided. In one aspect, a local buffering mechanism is employed that obeys standard communication protocols for the network communications between the nodelets integrated in a single chip. Sending messages from one nodelet to another nodelet on the same chip may be performed not via the network, but by exchanging messages in the point-to-point messaging buckets between the nodelets. The messaging buckets need not be part of the memory system of the nodelets. Specialized hardware controllers may be used for moving data between the nodelets and each messaging bucket, and ensuring correct operation of the network protocol. | 2013-12-05 |
20130326181 | PROVIDING USAGE STATISTICS FOR VIRTUAL STORAGE - A method for obtaining a measurement of storage usage includes sending a request, by a processor, for the measurement of storage usage during execution of an application by the processor; counting blocks of storage to generate the measurement of storage usage by the application; and providing the measurement of storage usage to the application. | 2013-12-05 |
20130326182 | APPLICATION-CONTROLLED SUB-LUN LEVEL DATA MIGRATION - A source code-based specification is implemented for use as an interface between a storage controller and an owning application to migrate a specified size of data from physical storage behind the LUN to a new physical location. | 2013-12-05 |
20130326183 | APPLICATION-CONTROLLED SUB-LUN LEVEL DATA MIGRATION - A source code-based specification is implemented for use as an interface between a storage controller and an owning application to migrate a specified size of data from physical storage behind the LUN to a new physical location. | 2013-12-05 |
20130326184 | MEMORY APPARATUS - A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data. | 2013-12-05 |
20130326185 | MEMORY POWER TOKENS - Techniques are described for controlling availability of memory. As memory write operations are processed, the contents of memory targeted by the write operations are read and compared to the data to be written. The availability of the memory for subsequent write operations is controlled based on the outcomes of the comparing. How many concurrent write operations are being executed may vary according to the comparing. In one implementation, a pool of tokens is maintained based on the comparing. The tokens represent units of power. When write operations require more power, for example when they will alter the values of more cells in PCM memory, they draw (and eventually return) more tokens. The token pool can act as a memory-availability mechanism in that tokens must be obtained for a write operation to be executed. When and how many tokens are reserved or recycled can vary according to implementation. | 2013-12-05 |
20130326186 | Avoiding Physical Fragmentation in a Virtualized Storage Environment - A virtualized storage stack includes logical layers above the physical storage layer. Each logical layer allocates data blocks, and the data block allocation is propagated down to the physical storage layer. To facilitate contiguous storage, each layer of the virtualized storage stack maintains additional metadata associated with data blocks. For each data block, the metadata indicates whether the data block is free, provisioned and includes a tag that indicates when the data block was first written. Data blocks that were first written as part of the same write request share the same tag, and are mostly guaranteed to be physically co-located. Block allocations that reuse data blocks having the same tag are preferred. Such preference increases the likelihood of the blocks being contiguous in the physical storage as these blocks were allocated as part of the same first write. | 2013-12-05 |
20130326187 | STORAGE APPARATUS AND STORAGE AREA ALLOCATION METHOD - A storage system, method and program product, the system comprising: storage devices; and a controller configured to: provide virtual volumes to a host computer; manage logical units on the storage device and storage pools; allocate, in response to receiving a write request to a virtual volume, a storage region of the storage pools; and store data related to the write request in the storage region allocated, wherein the controller is further configured to: allocate first storage region in first storage pool to first virtual volume based on first size of the first storage region or the first virtual volume; allocate a second storage region in a second storage pool to a second virtual volume of the plurality of virtual volumes based on a second size of the second storage region or the second virtual volume. | 2013-12-05 |
20130326188 | INTER-CHIP MEMORY INTERFACE STRUCTURE - In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory. | 2013-12-05 |
20130326189 | EXTENSIBLE METHOD AND SYSTEM FOR STORAGE METADATA - According to an aspect of an embodiment, a system of using an extensible language to represent storage metadata includes a computer-readable storage medium and a processing device. The computer-readable storage medium may have stored thereon storage metadata. The processing device may be configured to write the storage metadata to the computer-readable storage medium in an extensible language format. The processing device may also be configured to manipulate the storage metadata in the extensible language format. The processing device may also be configured to transfer the storage metadata in the extensible language format. | 2013-12-05 |
20130326190 | COARSE-GRAINED RECONFIGURABLE PROCESSOR AND CODE DECOMPRESSION METHOD THEREOF - A coarse-grained reconfigurable processor having an improved code compression rate and a code decompression method thereof are provided to reduce a capacity of a configuration memory and reduce power consumption in a processor chip. The coarse-grained reconfigurable processor includes a configuration memory configured to store reconfiguration information including a header storing a compression mode indicator and a compressed code for each of a plurality of units and a body storing at least one uncompressed code, a decompressor configured to specify a code corresponding to each of the plurality of units among the at least one uncompressed code within the body based on the compression mode indicator and the compressed code within the header, and a reconfigurator including a plurality of PEs and configured to reconfigure data paths of the plurality of PEs based on the code corresponding to each unit. | 2013-12-05 |
20130326191 | SYSTEM AND METHOD FOR DISTRIBUTED COMPUTING - The invention refers to tightly coupled multiprocessor distributed computing systems. The proposed solution enables to develop distributed applications as usual monolithic applications with use of typical compilers and builders. These applications support complicated logic of interaction between elements executed in different nodes and, at that, have limited complexity of development. The invention determines requirements to a distributed application and a method of its execution, memory organization and system node interaction manner. | 2013-12-05 |
20130326192 | BROADCAST OPERATION ON MASK REGISTER - Embodiments of systems, apparatuses, and methods for performing a mask broadcast instruction in a computer processor are described. In some embodiments, the execution of a mask broadcast instruction causes a broadcast of a data element of the source operand to a destination register of the destination operand according to the broadcast size. | 2013-12-05 |
20130326193 | PROCESSOR RESOURCE AND EXECUTION PROTECTION METHODS AND APPARATUS - Embodiments include processing systems that determine, based on an instruction address range indicator stored in a first register, whether a next instruction fetch address corresponds to a location within a first memory region associated with a current privilege state or within a second memory region associated with a different privilege state. When the next instruction fetch address is not within the first memory region, the next instruction is allowed to be fetched only when a transition to the different privilege state is legal. In a further embodiment, when a data access address is generated for an instruction, a determination is made, based on a data address range indicator stored in a second register, whether access to a memory location corresponding to the data access address is allowed. The access is allowed when the current privilege state is a privilege state in which access to the memory location is allowed. | 2013-12-05 |
20130326194 | METHOD, APPARATUS AND INSTRUCTIONS FOR PARALLEL DATA CONVERSIONS - Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register. | 2013-12-05 |
20130326195 | PREVENTING EXECUTION OF PARITY-ERROR-INDUCED UNPREDICTABLE INSTRUCTIONS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA - Preventing execution of parity-error-induced unpredictable instructions, and related processor systems, methods, and computer-readable media are disclosed. In this regard, a method for processing instructions in a central processing unit (CPU) is provided. The method comprises decoding an instruction comprising a plurality of bits, and generating a parity error indicator indicating whether a parity error exists in the plurality of bits prior to execution of the instruction. If the parity error indicator indicates that the parity error exists in the plurality of bits, one or more of the plurality of bits are modified to indicate a no execution operation (NOP), without effecting a roll back of a program counter of the CPU and without re-decoding the instruction. In this manner, the possibility of the parity error causing an inadvertent execution of an unpredictable instruction is reduced. | 2013-12-05 |
20130326196 | SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING VECTOR PACKED UNARY DECODING USING MASKS - Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed unary value decoding using masks in response to a single vector packed unary decoding using masks instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described. | 2013-12-05 |
20130326197 | ISSUING INSTRUCTIONS TO EXECUTION PIPELINES BASED ON REGISTER-ASSOCIATED PREFERENCES, AND RELATED INSTRUCTION PROCESSING CIRCUITS, PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA - Issuing instructions to execution pipelines based on register-associated preferences and related instruction processing circuits, systems, methods, and computer-readable media are disclosed. In one embodiment, an instruction is detected in an instruction stream. Upon determining that the instruction specifies at least one source register, an execution pipeline preference(s) is determined based on at least one pipeline indicator associated with the at least one source register in a pipeline issuance table, and the instruction is issued to an execution pipeline based on the execution pipeline preference(s). Upon a determination that the instruction specifies at least one target register, at least one pipeline indicator associated with the at least one target register in the pipeline issuance table is updated based on the execution pipeline to which the instruction is issued. In this manner, optimal forwarding of instructions may be facilitated, thus improving processor performance. | 2013-12-05 |
20130326198 | LOAD-STORE DEPENDENCY PREDICTOR PC HASHING - Methods and processors for managing load-store dependencies in an out-of-order instruction pipeline. A load store dependency predictor includes a table for storing entries for load-store pairs that have been found to be dependent and execute out of order. Each entry in the table includes hashed values to identify load and store operations. When a load or store operation is detected, the PC and an architectural register number are used to create a hashed value that can be used to uniquely identify the operation. Then, the load store dependency predictor table is searched for any matching entries with the same hashed value. | 2013-12-05 |
20130326199 | METHOD AND APPARATUS FOR CONTROLLING A MXCSR - Disclosed is an apparatus and method generally related to controlling a multimedia extension control and status register (MXCSR). A processor core may include a floating point unit (FPU) to perform arithmetic functions; and a multimedia extension control register (MXCR) to provide control bits to the FPU. Further an optimizer may be used to select a speculative multimedia extension status register (SPEC_MXSR) from a plurality of SPEC_MXSRs to update a multimedia extension status register (MXSR) based upon an instruction. | 2013-12-05 |
20130326200 | INTEGRATED CIRCUIT DEVICES AND METHODS FOR SCHEDULING AND EXECUTING A RESTRICTED LOAD OPERATION - An integrated circuit device comprising at least one instruction processing module arranged to compare validation data with data stored within a target register upon receipt of a load validation instruction. Wherein, the instruction processing module is further arranged to proceed with execution of a next sequential instruction if the validation data matches the stored data within the target register, and to load the validation data into the target register if the validation data does not match the stored data within the target register. | 2013-12-05 |
20130326201 | PROCESSOR-BASED APPARATUS AND METHOD FOR PROCESSING BIT STREAMS - An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results. | 2013-12-05 |
20130326202 | LOAD TEST CAPACITY PLANNING - Disclosed herein are techniques for load test capacity planning. Resources consumed by instructions executing in a first computer apparatus are determined. A metric associated with a second computer apparatus is determined. A number of instances of the instructions that are able to execute concurrently in the second computer apparatus is determined. | 2013-12-05 |
20130326203 | MULTIPROCESSOR - A microprocessor has a plurality of debug modules, multiple sets of processor cores provided corresponding to the debug modules so that each set of the processor cores are debugged by the corresponding debug module, and a plurality of debug ring units provided corresponding to the debug modules, each debug ring unit generating a debug ring signal for instructing the corresponding processor cores to transit to a debug mode. The debug ring units are connected to generate a ring and sequentially transmit the debug ring signal, and when receiving the debug ring signal, each debug ring unit outputs, to the corresponding debug module, a debug transition signal for instructing the corresponding processor cores to transit to the debug mode. | 2013-12-05 |
20130326204 | Configuration-Preserving Preprocessor and Configuration-Preserving Parser - Methods, systems, and apparatuses, including computer programs encoded on computer readable media, for generating a plurality of tokens from one or more source files that include source code in a first programming language. The source code includes one or more static conditionals that include a conditional expression and branch code that is operative when the conditional expression is true. Various configurations are possible based upon the conditionals. A first static conditional includes one or more nested static conditionals within the branch code associated with the first static conditional. Each of the one or more nested static conditionals is hoisted to a beginning of the branch code associated with the first static conditional. Each innermost branch code does not contain a static conditional and each possible configuration is preserved. | 2013-12-05 |
20130326205 | DETERMINISTIC CLOCK CROSSING - Techniques and apparatuses for clock crossing. A reset circuit on a first die generates a forwarded FIFO reset signal synchronous to a reference clock that identifies a single edge. A clock generation circuit on the first die generates the reference clock signal. Control circuitry on the first die generates a forwarded signal, synchronous to the forwarded clock that identifies a forwarded clock edge with fixed timing relationship to the forwarded clock edge a transmit PLL locks to the single reference edge. A phase locked loop (PLL) on a second die is coupled to receive the reference clock signal, the PLL to generate a local clock signal. A circular FIFO with a write pointer advanced by the forwarded clock and a read pointer advanced by the local clock. | 2013-12-05 |
20130326206 | REINTIALIZATION OF A PROCESSING SYSTEM FROM VOLATILE MEMORY UPON RESUMING FROM A LOW-POWER STATE - Boot configuration information is stored to a volatile memory of a processing system during a low-power state. When resuming from the low-power state, a processor device accesses configuration information for a memory controller from a non-volatile memory and restores the memory controller using the configuration information so as to permit access to the volatile memory. The processor device then configures the initial contexts one or more processor cores using the core state information maintained by the volatile memory during the low-power state and accessed via the configured memory controller, and the one or more processor cores completes the boot process by executing resume boot code maintained by the volatile memory during the low-power state and accessed via the configured memory controller, rather than accessing boot code from a non-volatile memory. | 2013-12-05 |
20130326207 | IMPLEMENTING SECURITY FUNCTIONS USING ROM - Systems, methods, and other embodiments associated with implementing security functions in a read-only memory (ROM) are described. According to one embodiment, an device includes a read-only memory (ROM) that stores (i) a plurality of security functions and (ii) a mapping of locations of the plurality of security functions in the ROM. The device also includes a processing unit configured to, in response to a request by a process being executed by the processing unit, determine a location in the ROM of a security function using the mapping, and execute the security function for the process from the ROM. | 2013-12-05 |
20130326208 | Headset Computer (HSC) with Docking Station and Dual Personality - An example embodiment of the present invention includes a headset computing device (HSC) having a port for docking. When worn on a user's head, the HSC operates in a “headset” mode and behaves as a hands-free computing device. When docked with a docking station, the HSC operates in a “docked” mode and behaves as a conventional PC using a conventional PC monitor as a display output and keyboard and/or mouse input devices. Operating in the headset mode, the HSC can use automatic speech recognition and head-tracking features to recognize verbal and head-motion commands and presents to the user a specific set of hands-fee applications or application features. When in the docked mode, the headset computing device makes available a different set of applications or application features more suited to keyboard and mouse operation. A common data set stored in the headset memory supports both/all sets of applications. | 2013-12-05 |
20130326209 | Automatic Alert Mode Selection - Automatic Alert Mode Selection may put a device into vibrate, silent, or ringer mode, or take the device out of such modes. It may automatically adjust volume settings, as applicable. It may perform these functions based on a location, a calendar entry, or an event. One embodiment may comprise a software application that communicates with network data or location sensors, such as GPS, to collect location information. It may also sync with a user's calendar to retrieve data for appointments and events. Automatic Alert Mode Selection may also interact with a plurality of application programming interfaces (APIs). In one embodiment, Automatic Alert Mode Selection may be programmed to collect data at a predetermined time interval, and in yet another embodiment, the software's functionalities may be overridden by the user. | 2013-12-05 |
20130326210 | SECURE CLIENT-SIDE COMMUNICATION BETWEEN MULTIPLE DOMAINS - Methods and systems for secure client-side communication between multiple domains is provided. Such methods and systems can provide for decreased communication latency particularly effective for dynamic multi-domain and/or multi-tenant environments while allowing for granular security or specific security of messages and operations with regard to users, user sessions, groups, organizations, permissions sets, applications, or any other logical delineation. Such methods and systems may involve a variety of security components, for example, at least one set of instructions including a plurality of defined instruction to be utilized by users of the set of instructions to communicate, and cryptographic construct data in order to verify the data integrity and the authenticity of messages sent and received using the secure client-side communication between multiple domains. | 2013-12-05 |
20130326211 | METHOD AND SYSTEM FOR CONDITIONAL ACCESS TO A DIGITAL CONTENT, ASSOCIATED TERMINAL AND SUBSCRIBER DEVICE - The invention relates to a method and a system for conditional access making it possible to prevent the fraudulent use of a subscriber electronic device ( | 2013-12-05 |
20130326212 | HELPER APPLICATIONS FOR DATA TRANSFERS OVER SECURE DATA CONNECTIONS - Data rates in secure data communications may be improved by executing helper applications to assist a computer system in responding to requests for secure data. The computation-intensive calculations may be offloaded to helper applications executing on different central processor units (CPUs). When the helper applications execute on different CPUs, higher data rates are achievable because additional CPU time is available for handling the encryption and decryption processing. A main application receives the initial request for secure data connections and assigns tasks related to the connections to the helper applications. | 2013-12-05 |
20130326213 | METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF CONTEXT-AWARE COVER MESSAGE - One embodiment provides a system that facilitates secure communication between a sending device and a receiving device. During operation, the system first transmits an encrypted message to a secure message server, wherein the encrypted message is addressed to the receiving device. The system then generates a cover message which indicates that the encrypted message is available for the receiving device. The system then transmits a digest of the cover message to a cover message server and makes the cover message available for the receiving device, thereby allowing the receiving device to confirm with the cover message server whether the cover message indicates availability of the encrypted message for the receiving device, and allowing the receiving device to obtain the encrypted message from the secure message server. | 2013-12-05 |
20130326214 | APPARATUS AND METHODS FOR ACTIVATION OF COMMUNICATION DEVICES - A method that incorporates teachings of the subject disclosure may include, for example, storing, by a universal integrated circuit card (UICC) including at least one processor, a digital root certificate locking a communication device to a network provider, and disabling an activation of the communication device responsive to receiving an indication of a revocation of the stored digital root certificate from a certificate authority, wherein the indication of the revocation of the stored digital root certificate is associated with a revocation of permission for an identity authority to issue a security activation information to the communication device on behalf of the network provide. Other embodiments are disclosed. | 2013-12-05 |
20130326215 | ESTABLISHING TRUST WITHIN A CLOUD COMPUTING SYSTEM - A cloud computing system includes a cloud system managing unit, a plurality of sets of devices, where a set of devices includes one or more devices having a common aspect, and a plurality of authentication servers, where an authentication server is associated with one of the plurality of sets of devices based on the common aspect. The cloud computing system functions to establish trust between a corresponding one of the plurality of authentication servers and the one or more devices of one of the plurality of sets of devices, between the corresponding one of the plurality of authentication servers and the cloud system managing unit, and between the cloud system managing unit and the one or more devices. The cloud system managing unit configures the cloud computing system based on the trust between the cloud system managing unit and devices of the plurality of sets of devices. | 2013-12-05 |
20130326216 | METHODS AND ARRANGEMENTS TO LAUNCH TRUSTED, COEXISTING ENVIRONMENTS - Methods and arrangements to launch trusted, distinct, co-existing environments are disclosed. Embodiments may launch trusted, distinct, co-existing environments in pre-OS space with high assurance. A hardware-enforced isolation scheme may isolate the partitions to facilitate storage and execution of code and data. In many embodiments, the system may launch a partition manager to establish embedded and main partitions. Embedded partitions may not be visible to the main OS and may host critical operations. A main partition may host a general-purpose OS and user applications, and may manage resources that are not assigned to the embedded partitions. Trustworthiness in the launch of the embedded partition is established by comparing integrity metrics for the runtime environment against integrity measurements of a trusted runtime environment for the embedded partition, e.g., by sealing a cryptographic key with the integrity metrics in a trusted platform module. Other embodiments are described and claimed. | 2013-12-05 |
20130326217 | SELF-KEYED PROTECTION OF ANTICIPATORY CONTENT - Systems and methods are provided to facilitate anticipatory pushing of content to clients of a communications network in such a way that the content is unusable by the anticipatory clients until explicitly requested. Embodiments apply one or more self-keying techniques to a content dataset to generate an anticipatory dataset, such that the anticipatory dataset cannot be used to reconstruct the content dataset without a keying dataset that also can only be generated using the content dataset. The anticipatory dataset is pre-pushed to a client in anticipation of a future request for the content. If and when the client subsequently issues a request for the content dataset, the server intercepts the new copy of the content dataset received in response to the request, uses the content dataset to generate the keying dataset, and communicates the keying dataset to the client for local reconstruction of the content dataset by the client. | 2013-12-05 |
20130326218 | TECHNIQUES FOR SECURE MESSAGE OFFLOADING - Techniques for secure message offloading are presented. An intermediary is transparently situated between a user's local messaging client and an external and remote messaging client. The user authenticates to the local client for access and the intermediary authenticates the user for access to the remote client using different credentials unknown to the user. Messages sent from the local client are transparently encrypted by the intermediary before being passed to the remote client and messages received from the remote client are transparently decrypted before being delivered to the local client. | 2013-12-05 |
20130326219 | STORED PUBLIC KEY VALIDITY REGISTERS FOR CRYPTOGRAPHIC DEVICES AND SYSTEMS - Systems and techniques for performing cryptographic operations based on public key validity registers are described. A described system includes a controller and a memory structure to store one or more public keys. The memory structure includes one or more validity registers that respectively correspond to the one or more public keys. The controller has exclusive write access to the validity register. The controller can be configured to perform an authentication of a public key, write an authentication status value to the corresponding validity register based on a result of the authentication, and perform one or more cryptographic operations using the public key that are conditional on the validity register indicating an authenticated status for the public key. | 2013-12-05 |
20130326220 | RECIPIENT BLIND CRYPTOGRAPHIC ACCESS CONTROL FOR PUBLICLY HOSTED MESSAGE AND DATA STREAMS - Private message system, method, and apparatus are described. A private message that includes encrypted data and identifying information indicating a recipient client device authorized to read the private message is stored at a server computer. Since the client devices perform all encryption and decryption processing, the server computer stores the private message in a platform agnostic manner and without performing any encryption/decryption related processes. Although any number of recipient devices can receive the private message, only a recipient client device authorized in accordance with the identifying information can read the private message. | 2013-12-05 |
20130326221 | Confidential Message Exchange Using Benign, Context-Aware Cover Message Generation - Systems and methods are disclosed permitting a sender to send a secret and secure message to a recipient. An application on a sender device interfaces with known message generating tools to permit a user to generate a message. The local application encrypts the message (and optional attachments) based on public/private key pairing negotiated with the server given the recipient device id. The sender device transmits the cipher text to the server. The server generates a benign, text-based, context-appropriate message and delivers same to a recipient device by way of a known messaging service. The benign message provides a secret clue to the recipient that an encrypted message is available. Recipient may then access and decrypt the encrypted message, such as from the server in response to a successful challenge (e.g., password request). | 2013-12-05 |
20130326222 | INFORMATION PROCESSING APPARATUS AND METHOD, RECORDING MEDIUM AND PROGRAM - The present invention relates to an information processing apparatus allowing proper communication with a communication partner in accordance with a communication time of the communication partner. | 2013-12-05 |
20130326223 | METHODS AND SYSTEMS FOR INCREASING THE SECURITY OF PRIVATE KEYS - A method for increasing the security of private keys is provided that includes generating transaction data at a device operated by a user and processing the transaction data. Moreover, the method includes determining whether the user permits using a private key that is associated with the user and with a public-private key pair of the user. The private key is stored in a computer system different from the device. Furthermore, the method includes authenticating the user when the user permits using the private key, applying the private key to other data after successfully authenticating the user, and transmitting the other data to the device. The method also includes conducting a transaction with the transaction data. | 2013-12-05 |
20130326224 | System and Method for Message Verification in Broadcast and Multicast Networks - In a network device, a method for verified communication includes generating a network communication message using a selection of predetermined message elements having digital signatures generated with a private key. The network device generates a signature for the message by applying a homomorphic operation to the digital signatures of the selected predetermined message elements and to a one-time signature corresponding to a random number. The network device transmits the message in association with the signature for the message and the random number to at least one other network device. | 2013-12-05 |
20130326225 | LONG-TERM SIGNATURE TERMINAL, LONG-TERM SIGNATURE SERVER, LONG-TERM SIGNATURE TERMINAL PROGRAM, AND LONG-TERM SIGNATURE SERVER PROGRAM - A client terminal | 2013-12-05 |
20130326226 | INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING PROGRAM - A long-term signature registration system | 2013-12-05 |
20130326227 | AUTHENTICATION APPARATUS, AUTHENTICATION SYSTEM, AUTHENTICATION METHOD AND STORAGE MEDIUM - The first authentication unit of an authentication apparatus decides whether first authentication data exists in a received message, and performs, if it is decided that the first authentication data exists, authentication based on the first authentication data. The second authentication unit of the authentication apparatus decides whether second authentication data exists in the received message, and performs, if it is decided that the second authentication data exists, authentication based on the second authentication data. If the second authentication unit decides that no second authentication data exists in the received message, and the first authentication unit decides that authentication has succeeded, it is decided that authentication for the received message has succeeded. | 2013-12-05 |
20130326228 | Password Encryption Key - A password-encrypted key (PEK) is generated from a user-supplied password or other identifying data and then used to encrypt the user's password. The encrypted password is stored in a user record on a server. At login a would-be user's password is again used to make a key, which is then used to decrypt and compare the stored encrypted password with the would-be user's password to complete the login. The successful PEK is stored in a temporary session record and can be used to decrypt other sensitive user information previously encrypted and stored in the user record as well as to encrypt new information for storage in the user record. A public/private key system can also be used to maintain limited access for the host to certain information in the user record. | 2013-12-05 |
20130326229 | VERIFICATION APPARATUS, VERIFICATION PROGRAM, AND VERIFICATION METHOD - In a verification apparatus, a biometric information acquisition unit acquires a plurality of biometric information pieces from an object. A first verification unit calculates, as a verification score, the similarity between the biometric information piece and a verification information piece, and compares the calculated verification score with a first determination value to determine whether the biometric information piece matches the verification information piece. When the verification fails, a second verification unit performs verification on the plurality of biometric information pieces having a predetermined relationship, using the verification information piece and a second determination value which defines a less stringent criterion than the first determination value. The second verification unit compares the verification score with the second determination value, and determines that the match is confirmed when a plurality of biometric information pieces satisfy the criterion defined by the second determination value. | 2013-12-05 |
20130326230 | METHODS AND APPARATUS FOR DATA HASHING BASED ON NON-LINEAR OPERATIONS - A method and an apparatus that provides a hard problem based hashing mechanism to improve security of hash functions are described. The hashing mechanism can include a custom padding and/or a post processing to a hashed value strengthened via operations specifying a hard problem. In one embodiment, a new hash function may be provided or defined directly without introducing or relying on existing hash functions to embed security features based on this hard problem. The new hash functions can be used in usual constructions implying hash functions. For example, the standard HMAC construction could be applied on these hash functions, standard signature algorithms or authentication protocol, etc. | 2013-12-05 |
20130326231 | System and Method for Downloading Electronic Information to a Video Lottery - This invention relates to reprogramming of in-circuit programmable chips installed in video lottery terminals (VLTs) by downloading electronic information (software) to such chips. Encrypted electronic information is downloaded from a host device to a gaming terminal through a communications link. The terminal comprises a decryption component configured for decrypting the encrypted electronic information using at least two security keys, at least one said key being resident in the terminal and at least another said key being delivered to the terminal at the time of the downloading (the downloading facilitating a replacement of existing software in terminal with corresponding decrypted software obtained from decrypting the encrypted information). The encrypted information transmitted to the terminal comprises at least one next version key for later use by the decryption component in decrypting a next version of encrypted electronic information. The non-resident key may be provided to the terminal by means of an electronic plug-in security key or provided through a secure network. | 2013-12-05 |
20130326232 | DEVICE FOR CARRYING OUT A CRYPTOGRAPHIC METHOD, AND OPERATING METHOD FOR SAME - A device for carrying out a cryptographic method has an input interface for receiving input data, an output interface for outputting output data, and a cryptographic unit for carrying out the cryptographic method. A first functional unit is provided which is designed to convert at least a portion of the input data into transformed input data using a first deterministic method, and to supply the transformed input data to the cryptographic unit, and/or a second functional unit is provided which is designed to convert at least a portion of output data of the cryptographic unit into transformed output data using a second deterministic method, and to supply the transformed output data to the output interface. | 2013-12-05 |
20130326233 | LOCATING CRYPTOGRAPHIC KEYS STORED IN A CACHE - Example embodiments provide various techniques for locating cryptographic keys stored in a cache. The cryptographic keys are temporarily stored in the cache until retrieved for use in a cryptographic operation. The cryptographic key may be located or found through reference to its cryptographic key identifier. In an example, a particular cryptographic key may be needed for a cryptographic operation. The cache is first searched to locate this cryptographic key. To locate the cryptographic key, the cryptographic key identifier that is associated with this cryptographic key is provided. In turn, the cryptographic key identifier may be used as an address into the cache. The address identifies a location of the cryptographic key within the cache. The cryptographic key may then be retrieved from the cache at the identified address and then used in the cryptographic operation. | 2013-12-05 |
20130326234 | INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING PROGRAM - A long-term signature group has a package of long-term signature data and an information file. The package of long-term signature data is obtained by compressing original data and XAdES as long-term signature data of original data into a single file. In the information file, the hash value of the package of long-term signature data, the expiration date of ATS to be used in XAdES, a distribution point of expiration information, the serial number of ATS, and the like are recorded. Non-destruction of the package of long-term signature data can be confirmed by the hash value, the expiration date of ATS can be confirmed by the expiration date, and the expiration information can be obtained from the distribution point of the expiration information to confirm the validity of ATS. Therefore, the validity of the long-term signature is efficiently confirmed. | 2013-12-05 |
20130326235 | CRYPTOGRAPHIC METHOD - In a cryptographic method between a portable data carrier and a terminal device there are employed a public data-carrier key and a secret data-carrier key of the data carrier as well as a public terminal key and a secret terminal key of the terminal device. The data carrier employs as a public data-carrier key a static public key. As a secret data-carrier key the data carrier employs a secret key that is derived from a secret basic key associated with the public data-carrier key. Within the framework of the method, the terminal device checks an authentication parameter associated with the data carrier and different from the data-carrier keys. | 2013-12-05 |
20130326236 | Security of Program Executables and Microprocessors Based on Compiler-Architecture Interaction - A method, for use in a processor context, wherein instructions in a program executable are encoded with plural instruction set encodings. A method wherein a control instruction encoded with an instruction set encoding contains information about decoding of an instruction that is encoded with another instruction set encoding scheme. A method wherein instruction set encodings are randomly generated at compile time. A processor framework wherein an instruction is decoded during execution with the help of information provided by a previously decoded control instruction. | 2013-12-05 |
20130326237 | UNINTERRUPTABLE PC POWER UNIT FOR USE IN PERSONAL COMPUTER AND SERVERS - Uninterruptable PC Power Unit (UPCPU) for a personal computer (PC) replaces the power supply of a PC. The UPCPU comprises an internal battery to be used during AC power interruption. The UPCPU may be connected to external batteries installed in the PC's 5.25″ or 3.5″ drive bays. The UPCPU may supply 12V, uninterrupted power to power external devices such as a display or modem. The UPCPU is capable of safely saving work in progress and force shutdown or hibernation state of the PC. | 2013-12-05 |
20130326238 | SHARED ACCESS SYSTEM - A shared access system is for a plurality of shared access devices to share data and power, and one of the shared access devices includes an instruction unit, a connecting unit, a storage unit, a power unit and a processing unit. The instruction unit is for storing a plurality of application modes related to a plurality of multifunctional shared applications respectively; the connecting unit is for receiving and transmitting the data and transmitting the power; the storage unit has a storage space for storing the data; the power unit stores the power; and the processing unit is coupled to the instruction unit, the connecting unit, the storage unit and the power unit, and the processing unit determines sharing the data and the power according to the execution of one of the application modes. | 2013-12-05 |
20130326239 | POWER MANAGEMENT WITH THERMAL CREDITS - A power management system, in one embodiment, determines a thermal status (e.g. a temperature or a calculation of power consumption) of at least a portion of a data processing system, and based on that status, thermal credits are calculated and then used to determine a voltage dithering pattern and a voltage boost pattern. | 2013-12-05 |
20130326240 | HOST DEVICE WITH INSTALLABLE POWER SUPPLY - A host device with an installable power supply comprises: a casing which is a case with an installation space enclosed inside, and the installation space is partitioned into at least a power supply installation space and a plurality of uninterruptible power supply (UPS) installation spaces disposed adjacent to the power supply installation space; a power distribution board installed in the casing, and having an end extended to a junction of the power supply installation space and the UPS installation space, and the power distribution board further has a plurality of charging circuit boards; a power supply detachably coupled to the power distribution board; and a plurality of uninterruptible power supplies detachably coupled to the charging circuit board on the power distribution board. | 2013-12-05 |
20130326241 | POWER SUPPLY CIRCUIT TO SIMULATE BATTERY POWER - A power supply circuit includes a power output port, an operational amplifier, a voltage adjusting circuit, a feedback circuit, and a current controlling circuit. The power output port connects with an electronic device under test and provides a power supply which in all respects simulates the behavior of a battery being discharged as it supplies working power, the circuit also mimics the behavior of a battery in testing the battery-recharging abilities of the electronic device. | 2013-12-05 |
20130326242 | POWER SUPPLY APPARATUS FOR DATACENTER - A power supply apparatus for a datacenter includes a carrier to carry the datacenter on rails of a rail transport system, a number of pantographs each including a main body with first and second terminals and a contact plate connected to the first terminal of the main body, and a number of power supply systems. The contact plate of each pantograph is electrically in contact with a cable of the rail transport system. The power supply systems are coupled to the second terminals of the pantographs, and each of the power supply systems acquires power from the cable through the corresponding pantograph, and provides power for the datacenter. | 2013-12-05 |
20130326243 | SEMICONDUCTOR DEVICE HAVING IDENTIFICATION INFORMATION GENERATING FUNCTION AND IDENTIFICATION INFORMATION GENERATION METHOD FOR SEMICONDUCTOR DEVICE - A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state. | 2013-12-05 |
20130326244 | SEMICONDUCTOR DEVICE AND ALARM DEVICE - In the microcomputer in the alarm device, supply of power to a sensor portion or a CPU in a sensor is allowed or stopped by a power gate controlled by a power gate controller. In addition, a volatile memory portion and a nonvolatile memory portion are provided in the CPU, data of the volatile memory portion is stored in the nonvolatile memory portion before supply of power to the CPU is stopped, and the data of the nonvolatile memory portion is restored to the volatile memory portion after the supply of power to the CPU is resumed. Thus, during an interval between measurement periods, supply of power to the sensor portion and the CPU can be stopped, so that low power consumption can be achieved compared with the case where power is continuously supplied. | 2013-12-05 |
20130326245 | DYNAMIC ENERGY MANAGEMENT - A method of dynamic energy management that includes loading an energy budget configuration stream for an instruction of a thread, loading characterization data for the thread, computing energy management settings for the instruction based on the characterization data and the budget configuration stream, and driving control signals indicative of the computed energy management settings. | 2013-12-05 |
20130326246 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 2013-12-05 |
20130326247 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 2013-12-05 |
20130326248 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 2013-12-05 |
20130326249 | REGULATING POWER CONSUMPTION OF A MASS STORAGE SYSTEM - A technique includes receiving first work requests that are associated with a user workload. The technique includes using a machine to transform the first work requests into second work requests that are provided to components of a mass storage system to cause the components to perform work associated with a workload of the mass storage system; and regulating a power consumption of the mass storage system, including regulating a rate at which the second work requests are provided to the components of the mass storage system. | 2013-12-05 |
20130326250 | MANAGING POWER CONSUMPTION OF ELECTRONIC DEVICES RESPONSIVE TO USAGE FORECAST - A system and process that incorporates teachings of the subject disclosure may include, for example, transitioning a processor from a high-power consumption state to a low-power consumption state, wherefrom return to the high-power consumption state includes a boot process. Future demand for operation of the processor in the high-power consumption state is predicted, while the processor is in the low-power consumption state. The processor is transitioned from the low-power consumption state to the high-power consumption state in response to predicting future demand for operation of the processor in the high-power consumption state. Such transition of the processor from the low-power consumption state to the high-power consumption state sufficiently precedes actual demand for operation of the processor in the high-power consumption state so as to avoid perceptible user delay. Other embodiments are disclosed. | 2013-12-05 |
20130326251 | METHOD AND APPARATUS FOR RECOVERY FROM LOW POWER STATE - A method and apparatus for recovering from a low power state in a computing system is disclosed. In one embodiment of the method, the computing system enters the low power state from a standard power state after an activity detector indicates a user controlled peripheral device connected to the computer system has been inactive for a period of time. To enter the low power state, the method disconnects the user controlled peripheral device from a host controller, while continuing to supply power to the user controlled peripheral device and shutting off power to the host controller. The method returns the computer system to the standard power state when the activity detector indicates the user controlled peripheral device has become active. To return to the standard power state, power is restored to the host controller and the user controlled peripheral device is reconnected to the host controller. | 2013-12-05 |
20130326252 | COMPUTER READABLE MEDIUM AND COMPUTATION PROCESSING APPARATUS - According to an embodiment, there is provided with a non-transitory computer readable medium having instructions stored therein, which, when executed by a computer, causes the computer to execute steps including: calculating an access load on a memory area including a plurality of segment areas and determining, for each of the segment areas, one of a plurality of power states including a first power state and a second power state with its power consumption being lower than that of the first power state in accordance with the access load; and setting each of the segment areas to the power state determined therefor. | 2013-12-05 |
20130326253 | TOGGLING SLEEP-MODE OF A MOBILE DEVICE WITHOUT MECHANICAL OR ELECTROMAGNETIC TOGGLING BUTTONS - Techniques for toggling sleep modes. A gesture associated with the mobile device that is in a first mode is detected. The can be gesture indicative of a user toggling the sleep mode of the mobile device from a first mode. Responsive to the gesture, the first mode can be switched to a second mode. In the second mode at least one component of the mobile device is either powered-up or powered-down. | 2013-12-05 |
20130326254 | PROCEDURE FOR CHARGING A PORTABLE DEVICE USING A BATTERY-OPERATED COMPUTER - A method of charging a battery of a device using a battery of a computer powered by the battery, in which the procedure is implemented by a circuit independent of the computer's processors. The method includes supplying a power supply voltage, insufficient to charge a battery, to a computer port, as long as a device is detected as connected to the port, controlling the supply of a charging voltage to the port, while supplying charging voltage to the port, detecting an end of charging condition of a battery of the device, and controlling the cutting off of the charging voltage to the port if the end of charging condition is detected, where this condition is determined according to the intensity of a charging current and according to a quantity of electrical charge supplied to the port and/or of a charging period. | 2013-12-05 |
20130326255 | COMMUNICATION SYSTEM - A communication system includes a plurality of nodes performing communication via a common communication channel based on a communication protocol and including a first node or a second node. The first node transmits, to the communication channel, a wake-up frame as the communication frame for enabling the second node to transition from a sleep state to a normal state, determines whether or not the second node transitions to the normal state due to the wake-up frame, and generates an abnormal waveform pattern in the communication channel when determined that the second node does not transition to the normal state. The second node stores the identification information allocated to the second node, and enables the second node to transition from the sleep state to the normal state under on condition that the identification information included in the wake-up frame received from the communication channel is identical to the stored identification information. | 2013-12-05 |
20130326256 | GENERATING MONOTONICALLY INCREASING TOD VALUES IN A MULTIPROCESSOR SYSTEM - Generating monotonically increasing time-of-day values in a multiprocessor system is provided. Synchronization impulses are received by a processor of the multiprocessor system, and an execution of a read instruction of a time-of-day value within a processor of the processors is refused, if the execution of the read instruction of the time-of-day value is requested after a predefined time after a synchronization impulse of the synchronization impulses, and if a trigger signal, indicative of new data received by a related memory system, has been received after the predefined time, wherein the memory system is external to the processor. | 2013-12-05 |
20130326257 | MEMORY DEVICE, HOST DEVICE, AND SAMPLING CLOCK ADJUSTING METHOD - A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently. | 2013-12-05 |
20130326258 | Predicting Timing Violations - For predicting timing violations, a prediction module predicts a timing violation for a first instruction in a semiconductor device in response to use by the first instruction of a specified sensitized path. The prediction module further mitigates the predicted timing violation. | 2013-12-05 |
20130326259 | SYSTEM AND METHOD FOR MULTIPLE BACKPLANE TIME SYNCHRONIZATION - A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to generate a time command at a predetermined time interval. A backplane including a second controller is communicatively coupled to the first controller. The second controller may be operable to receive the time command from the first controller and calculate a skew for the time command based at least on a location of the backplane. The second controller may further be operable to adjust a time domain of the backplane based on the calculated skew for the time command to synchronize the backplane. | 2013-12-05 |
20130326260 | Automated Disaster Recovery System and Method - Methods and systems for recovering a host image of a client machine to a recovery machine comprise comparing a profile of a client machine of a first type to be recovered to a profile of a recovery machine of a second type different from the first type, to which the client machine is to be recovered, by a first processing device. The first and second profiles each comprise at least one property of the first type of client machine and the second type of recovery machine, respectively. At least one property of a host image of the client machine is conformed to at least one corresponding property of the recovery machine. The conformed host image is provided to the recovery machine, via a network. The recovery machine is configured with at least one conformed property of the host image by a second processing device of the recovery machine. | 2013-12-05 |
20130326261 | FAILOVER OF INTERRELATED SERVICES ON MULTIPLE DEVICES - A device may include a network interface for communicating with a failover device, a memory for instructions, and a processor for executing the instructions. The processor may execute the instructions to communicate with the failover device, via the network interface, to fail over the device to the failover device in a cluster by pushing a process on the device to the failover device when a first failover event occurs. The failover device is configured to fail over the device to the failover device by pulling the process on the device on the second device when a second failover event occurs. The device is in the cluster. | 2013-12-05 |
20130326262 | METHODS AND SYSTEMS FOR AUTOMATICALLY REROUTING LOGICAL CIRCUIT DATA FROM A LOGICAL CIRCUIT FAILURE TO A DEDICATED BACKUP CIRCUIT IN A DATA NETWORK - An example method of rerouting data involves rerouting a logical circuit from a first set of switches to a second set of switches to communicate data between network devices without breaking the logical circuit. The logical circuit comprises variable communication paths. The second set of switches is to form a route associated with the variable communication paths that is not predefined and that is dynamically defined at a time of automatic rerouting. The example method also involves rerouting the data from the logical circuit to a logical failover circuit in the data network when the logical circuit fails based on a committed information rate having been exceeded. The logical failover circuit comprises an alternative communication path to communicate the data. | 2013-12-05 |
20130326263 | DYNAMICALLY ALLOCATABLE MEMORY ERROR MITIGATION - Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error. | 2013-12-05 |
20130326264 | RESOLUTION OF A STORAGE ERROR IN A DISPERSED STORAGE NETWORK - A method begins by a dispersed storage (DS) processing module identifying an encoded data slice having an error, where a storage unit of a dispersed storage network (DSN) stores the encoded data slice. The method continues with the DS processing module sending a lock command to the storage unit. The method continues with the DS processing module determining resolution for the error of the encoded data slice, where the resolution includes one or more of: rebuilding the encoded data slice, issuing a set of delete requests to storage units of the DSN regarding a set of encoded data slices, issuing a set of undo write requests to the storage units of the DSN regarding the set of encoded data slices, and issuing a set of roll-back write requests to the storage units of the DSN regarding the set of encoded data slices. | 2013-12-05 |
20130326265 | SYSTEMS AND METHODS FOR DISASTER RECOVERY OF MULTI-TIER APPLICATIONS - A computer-implemented method for disaster recovery of multi-tier applications may include 1) identifying a multi-tier application that is provisioned with a plurality of production clusters at a production site, 2) identifying a disaster recovery site including a plurality of recovery clusters, 3) identifying, at the disaster recovery site, a failure of the multi-tier application at the production site, and 4) initiating, from the disaster recovery site, a migration of the multi-tier application from the production site to the disaster recovery site. Various other methods, systems, and computer-readable media are also disclosed. | 2013-12-05 |
20130326266 | Maximizing Use of Storage in a Data Replication Environment - Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device. | 2013-12-05 |
20130326267 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred. | 2013-12-05 |
20130326268 | REPAIR CONTROL CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME - A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses. | 2013-12-05 |
20130326269 | APPARATUS, SYSTEM AND METHOD FOR MANAGING SOLID-STATE RETIREMENT - A storage controller is configured to determine a reliability metric of a storage division of a solid-state storage medium based on one or more test read operations. The storage division may be retired based on the reliability metric and/or the age of the data on the storage division. A storage division comprising aged data may be marked for post-write reliability testing, which may comprise determining a post-write reliability metric in response to grooming and/or reprogramming the storage division. The storage controller may project the reliability metric of the storage division to the end of a predetermined data retention period. Portions of a storage divisions that exhibit poor reliability may be removed to improve the reliability of the storage division without taking the entire storage division out of service. | 2013-12-05 |
20130326270 | Maximizing Use of Storage in a Data Replication Environment - Mechanisms for controlling access to storage volumes on the secondary storage system is provided. A determination is made as to whether a first site computing device has sent a notification of a failure condition of a first site. In response to a determination that the notification of the failure condition of the first site has not been received, secondary workloads of a second site computing device are permitted to access storage volumes on the secondary storage system. In response to a determination that the notification of the failure condition of the first site has been received, a mode of operation of the second site is modified from a normal mode of operation to a failure mode of operation. In the failure mode of operation, the storage system controller of the second site blocks at least a portion of access requests from secondary workloads of the second site computing device. | 2013-12-05 |
20130326271 | HANDLING OF INITIALLY UNEXECUTABLE INSTRUCTIONS - According to example configurations, a monitor resource monitors hardware executing a software program. In response to detecting occurrence of a failure associated with an attempted execution of a given software instruction in the software program, the hardware generates a notification. The monitor resource receives the signal generated by the hardware. In response to receiving the signal, the monitor resource initiates computation of the data value associated with the given software instruction. For example, via a communication from the monitor resource to the hardware executing the software program, the monitor resource initiates computation of the value associated with the given instruction by directing the hardware to initiate execution of a specific routine. By way of example, the monitor resource can initiate a lazy computation based on execution of a fault handling function or subroutine to compute a value for the failed instruction. | 2013-12-05 |
20130326272 | STORAGE SYSTEM AND METHOD OF OPERATING THEREOF - Storage system(s) for storing data in physical storage in a recurring manner, method(s) of operating thereof, and corresponding computer program product(s). For example, a possible method can include: upon start of a storage recurrence, destaging dirty data which had been accommodated in the cache memory prior to the start of said storage recurrence thus giving rise to destaged data group, wherein destaging is provided with no overwriting of at least superseded data destaged before starting said storage recurrence whilst enabling retaining metadata indicative of location of said superseded data in the physical storage space; accommodating data obtained in said cache memory subsequent to the start of said storage recurrence whilst preventing said data from being destaged during said storage recurrence, thus giving rise to accommodated data group; and registering a point-in-time indicative of successful destaging of the destaged data group, thereby providing an order-preservation consistency indication corresponding to said recurrence. | 2013-12-05 |
20130326273 | VIRTUAL REPAIR OF DIGITAL MEDIA - Embodiments described herein are directed to a virtual repair of digital media using a virtual repair service. Digital media stored on a digital media device is read using a media player. A request is received by a virtual repair unit from the media player to perform a virtual repair of a segment of unreadable digital content of the digital media. The virtual repair unit retrieves a readable copy of the digital content corresponding to the segment of unreadable digital content identified in the request from a media repository using the virtual repair unit. The virtual repair unit transmits the readable copy of the digital content to the media player for insertion into a buffer of the media player. | 2013-12-05 |
20130326274 | METHOD FOR TRANSFERRING AND CONFIRMING TRANSFER OF PREDEFINED DATA TO A DEVICE UNDER TEST (DUT) DURING A TEST SEQUENCE - A method for testing a device under test (DUT) during a test sequence. In accordance with one embodiment, during a regular, pre-defined test sequence, data packets are transferred from a tester to a device under test (DUT) containing data related to at least one of an identification parameter of the DUT, an operational characteristic of the DUT and a request for data. Examples of such transferred data include address data for identifying the DUT (e.g., a unique media access control (MAC) address) and calibration data for controlling an operational characteristic of the DUT (e.g., signal power levels, signal frequencies or signal modulation characteristics). In accordance with another embodiment, the DUT retrieves and transmits data to the tester, either in response to the request for data or as a preprogrammed response to its synchronization with the tester. | 2013-12-05 |
20130326275 | HARDWARE PLATFORM VALIDATION - A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyses the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases. | 2013-12-05 |
20130326276 | METHOD AND APPARATUS FOR CORRELATING INPUT AND OUTPUT MESSAGES OF SYSTEM UNDER TEST - A method and apparatus for determining correlation between input and output messages in a system under test (SUT) is provided in the present invention. The SUT is provided with preset watch-points, and the running of the SUT is detected by triggering watch-points in a test platform at its run time. The method includes the steps of: upon detecting a message input operation, finding a variable that stores an input message, associating the variable with a tag of the input message, and adding a watch-point for the variable in the test platform; as well as, upon detecting network output operation, finding a variable that stores an output message of the SUT; and determining correlation between the output message and an input message according to a tag associated with the variable that stores the output message. | 2013-12-05 |
20130326277 | DATA LIFECYCLE MANAGEMENT - A method, system and computer program product for data lifecycle management is provided. A method for managing metrics from a monitored system comprises: identifying a fault from the monitored system; identifying from the monitored system, one or more metrics are that are directly related to the fault and one or more metrics that are indirectly related to the fault by virtue of being directly or indirectly related to the one or more directly related metrics; identifying a lifespan condition associated with the fault; adding or changing a lifespan for each of the directly and indirectly related metrics based on the identified lifespan condition; and removing metrics from the storage if their associated lifespans are over. | 2013-12-05 |
20130326278 | SERVER AND METHOD OF MANIPULATION IN RELATION TO SERVER SERIAL PORTS - A server in communication with a remote control device and a display device includes a super input/output (SIO) microchip, a basic input/output system (BIOS), and a baseboard management controller (BMC). The SIO microchip outputs debugging commands and IPMI commands. The BMC includes a setting module, receiving module, and a transmitting module. The setting module sets the BIOS to establish communication between the BMC and the SIO microchip. The receiving module receives the IPMI commands or the debugging commands to debug errors of firmware pre-stored in the BMC. The transmitting module outputs the errors of the firmware to the remote control device or the display device via the SIO microchip. | 2013-12-05 |