46th week of 2010 patent applcation highlights part 41 |
Patent application number | Title | Published |
20100291684 | MUTAGENESIS METHOD USING POLYETHYLENE GLYCOL MEDIATED INTRODUCTION OF MUTAGENIC NUCLEOBASES INTO PLANT PROTOPLASTS - Method for targeted alteration of a duplex acceptor DNA sequence in a plant cell protoplast, comprising combining the duplex acceptor DNA sequence with a donor mutagenic nucleobase, wherein the duplex acceptor DNA sequence contains a first DNA sequence and a second DNA sequence which is the complement of the first DNA sequence and wherein the donor mutagenic nucleobase comprises at least one mismatch with respect to the duplex acceptor DNA sequence to be altered, preferably with respect to the first DNA sequence, wherein the method further comprises a step of introducing the donor mutagenic nucleobase into the cell protoplasts using polyethylene glycol (PEG) mediated transformation and the use of PEG protoplast transformation for enhancing the rate of targeted mutagenesis. | 2010-11-18 |
20100291685 | METHODS FOR DETECTING DEFECTS IN INORGANIC-COATED POLYMER SURFACES - Lipophilic fluorescent substances can be used to detect surface defects in materials having hydrophilic (e.g., inorganic) coatings. Use of the described methods makes surface defects appear fluorescent, while the remaining surfaces are not labeled. The disclosed methods are inexpensive, rapid, and easy alternatives to existing approaches. | 2010-11-18 |
20100291686 | AUTOMATED PROTEIN ANALYZER - A dye binding method for protein analysis is disclosed. The method includes the steps of preparing an initial reference dye solution of unknown concentration from an initial reference dye concentrate and creating an electronic signal based upon the absorbance of the initial reference dye solution. Thereafter, an electronic signal is created based upon the absorbance of a dye filtrate solution prepared from the initial reference dye solution and an initial protein sample. The absorbance signals from the reference dye solution and the dye filtrate solution are sent to a processor that compares the respective absorbances and calculates the protein content of the protein sample based upon the difference between the absorbances. An electronic signal is created based upon the absorbance of a successive dye filtrate solution prepared from the reference dye solution and a successive protein sample, and the absorbance signal from the successive sample dye filtrate solution is sent to the processor to calculate the protein content of the successive sample based upon the difference between the absorbance of the initial reference dye solution and the absorbance of the successive dye filtrate solution. | 2010-11-18 |
20100291687 | AN ASSAY FOR SCREENING/RANKING ANTIOXIDANTS BASED ON THEIR EFFECTS ON MEMBRANE STEROL LATERAL ORGANIZATION - A method of screening an antioxidant for potency and/or toxicity in vitro, the method includes contacting the antioxidant with a model system comprising a sterol superlattice formation capable of generating a detectable signal, wherein the detectable signal changes in a parameter representative of an integrity of the sterol superlattice formation; and detecting and/or measuring disruption of the sterol superlattice formation, wherein the disruption is caused by oxidation of sterol upon contacting sterol with a prooxidant and the antioxidant and thereby screening the antioxidant for potency and/or toxicity. | 2010-11-18 |
20100291688 | COMPOSITIONS AND METHODS FOR SOLID PHASE EXTRACTION OF LIPIDS - A composition, method and device for the preparation of biological samples for subsequent instrumental analyses, such as GC, GC-MS, LC and LC-MS analysis, using a solid phase extraction (SPE) process is described. Through SPE process alone or an integrated combination of protein precipitation, filtration, and SPE using a hydrophobic zirconia-coated chromatographic media, interfering compounds, such as proteins, glycerides and phosphate-containing compounds, are eliminated from the biological, food, environmental and biotechnology samples, affording an enhanced analyte response during the instrumental analysis. | 2010-11-18 |
20100291689 | Lanthanide Complexes as Fluorescent Indicators for Neutral Sugars and Cancer Diagnosis - A group of water-soluble salophene-lanthanide complexes and other salophene-metal complexes are useful for purposes including: (i) detecting neutral carbohydrates at physiologically-relevant pH, (ii) the selective detection of gangliosides, and (iii) the selective detection of lysophosphatidic acid (LPA) in the presence of phosphatidic acid. The selective detection of LPA is useful in diagnosing ovarian and other cancers. | 2010-11-18 |
20100291690 | METHODS FOR DETECTING OR MONITORING CANCER USING LPC AS A MARKER - A method of detecting a cancer, such as ovarian cancer, in a test subject including (a) determining the amount of a lysophosphatidyl choline in a sample of a bodily fluid taken from the test subject, and (b) comparing the amount of the lysophosphatidyl choline in the sample of the bodily fluid taken from the test subject to a range of amounts of lysophosphatidyl choline found in samples of the bodily fluid taken from a group of normal subjects of the same species as the test subject and lacking the cancer, such as ovarian cancer, whereby a change in the amount of the lysophosphatidyl choline in the sample of the bodily fluid taken from the test subject indicates the presence of the cancer, such as ovarian cancer. | 2010-11-18 |
20100291691 | METHOD OF MEASURING GLYCATED HEMOGLOBIN CONCENTRATION AND CONCENTRATION MEASURING APPARATUS - When the concentration of glycated hemoglobin is measured, a plurality of wavelengths are selected as measurement wavelengths from the wavelength range of 400 to 450 nm. Preferably, by use of a liquid chromatography, at least the light of different peak wavelengths in the wavelength range of 415 to 430 nm are continuously or intermittently received to obtain a three dimensional chromatogram having as variables the wavelength, the elution time and the amount of detection. The concentration of glycated hemoglobin is calculated based on this three dimensional chromatogram. | 2010-11-18 |
20100291692 | METHOD FOR ANALYZING METAL SPECIMEN - A method for analyzing a metal specimen includes an electrolysis step of electrolyzing a metal specimen containing a reference element and a target element in an electrolytic solution, a sampling step of sampling a portion of the electrolytic solution, an analysis step of analyzing the sampled electrolytic solution, a concentration ratio-calculating step of calculating the concentration ratio of the target element to the reference element in the electrolytic solution on the basis of the analysis results, and a content-calculating step of calculating the content of the target element present in the form of a solid solution by multiplying the content of the reference element in the metal specimen by the obtained concentration ratio. | 2010-11-18 |
20100291693 | ORAL FLUID ASSAYS FOR THE DETECTION OF HEAVY METAL EXPOSURE - Methods for measuring the concentration of heavy metals such as aluminum, antimony, arsenic, barium, beryllium, cadmium, chromium, cobalt, copper, lead, manganese, molybdenum, nickel, selenium, silver, strontium, thallium, uranium, vanadium, zinc, or mixtures thereof in oral fluid are provided. The concentration of heavy metals in oral fluid can be accurately correlated with the concentration of heavy metal in the blood serum. The methods are useful for, among other things, diagnosis and monitoring of heavy metal exposure. | 2010-11-18 |
20100291694 | Crystal Structure of CRIg and C3B:CRIg Complex - The present invention concerns determination of the crystal structure of the macrophage specific receptor, CRIg (earlier referred to as STIgMA), and its complex with the C3b and C3c subunits of complement C3 (C3b:CRIg and C3c:CRIg complexes). The invention further concerns the use of the crystal structure of CRIg or the C3b:CRIg complex to screen for and identify molecules structurally and/or functionally related to CRIg, including CRIg agonists and antagonists. | 2010-11-18 |
20100291695 | DETECTION OF NUCLEIC ACID SEQUENCE MODIFICATION - The invention relates to a non-PCR based method for the detection of a nucleotide modification in a nucleic acid sample comprising contacting a solution comprising nucleic acid sample with a nucleic acid probe in a temperature-controlled and UV illuminated container and measuring the UV absorption of the nucleic acid sample/nucleic acid probe complex. | 2010-11-18 |
20100291696 | Process For Detecting Nucleic Acids - A process for detecting nucleic acids, having the following steps: providing at least one nanoparticle that is functionalised for the nucleic acid to be detected by means of at least one oligonucleotide that is bound to it and that is able to hybridize with at least one segment of a nucleic acid to be detected; bringing the functionalised nanoparticle into contact with a sample in which the nucleic acid is to be detected; and measuring a property that provides information about the degree of hybridization of the at least one oligonucleotide with the nucleic acid to be detected. In addition, the process includes the step of exciting the nanoparticles to generate heat, for example by means of a photothermal effect. The invention is suitable, in particular, for high-throughput DNA analysis. | 2010-11-18 |
20100291697 | Coated Colloidal Materials - Coated colloidal materials, methods for making coated colloidal materials, and methods of using coated colloidal materials are disclosed. The method yields coated colloidal materials where the optical characteristics of the core is not adversely affected. The coated colloidal materials can be self-assembled into films, layers, or structures and used in the detection of analytes through detection assays. | 2010-11-18 |
20100291698 | DETECTION OF NITRO- AND NITRATE-CONTAINING COMPOUNDS - A method of the invention is a method of detecting nitramines and nitrate esters believed to be present on a sampling substrate. In the method, a sampling substrate is exposed to a first reagent that is formulated to react with nitramine- and nitrate ester-type explosives to release nitrite. The sampling substrate is then exposed to a second reagent that contains an acid to react with the nitrite and a diaminoaromatic present in either the first or second reagent, to form a triazole that will luminesce. Another method of the invention combines this process for nitramine- and nitrate ester-based explosives detection with a technique to detect nitroaromatic-based explosives using luminescent polymers, for a three-step process for the detection of explosives in these three classes. | 2010-11-18 |
20100291699 | COMPOSITIONS AND METHODS FOR SIMULTANEOUS DETECTION OF VOLATILE SULFUR COMPOUNDS AND POLYAMINES - Disclosed are compositions and methods useful for the rapid and facile simultaneous detection of malodorous bacterial metabolites in samples of expired breath and other fluids. The invention enables estimation, by simple visual inspection and comparison against standards, of the concentration of polyamines and volatile sulfur compounds in the micromolar to millimolar range. | 2010-11-18 |
20100291700 | Analysis of membrane component interactions - Devices and methods for detecting interaction between components associated with lipid membranes and analytes are described herein. In certain methods, a surface of a compartment of a device is coated with a material that attaches to lipid membrane from a sample. An analyte is introduced and interaction is detected, for example, by back scattering interferometry. In another method, a surface is passivated with a material that does not bind a lipid membrane. A sample is introduced that contains a membrane comprising a component for testing and an analyte. Interaction is detected. In a third method, a channel is filled with a first liquid that does not comprise a lipid membrane. A bolus of a second liquid that comprises a membrane comprising a component for testing and an analyte is introduced under laminar flow conditions so that a leading edge of the second liquid does not completely displace the first liquid in a sensing area that is interrogated by optical methods, for example, a laser. Interaction between the analyte and the component is detected. | 2010-11-18 |
20100291701 | CYANIDE AND RELATED SPECIES DETECTION WITH METAL SURFACES - An assay method and kit for detecting a chemical. The method and kit utilize a metal surface capable of surface enhanced Raman Scattering. The metal surface may be provided in the form of one or more nanoparticles, to increase the surface enhanced Raman Scattering capability of the metal surface. The nanoparticles may be treated with one or more additives to further enhance or maintain the surface enhanced Raman Scattering capability of the nanoparticles. | 2010-11-18 |
20100291702 | Functionalized Fluorescent Nanocrystal Compositions and Methods for Their Preparation - The present invention provides for functionalized fluorescent nanocrystal compositions and methods for making these compositions. The compositions are fluorescent nanocrystals coated with at least one material. The coating material has chemical compounds or ligands with functional groups or moieties with conjugated electrons and moieties for imparting solubility to coated fluorescent nanocrystals in aqueous solutions. The coating material provides for functionalized fluorescent nanocrystal compositions which are water soluble, chemically stable, and emit light with a high quantum yield and/or luminescence efficiency when excited with light. The coating material may also have chemical compounds or ligands with moieties for bonding to target molecules and cells as well as moieties for cross-linking the coating. In the presence of reagents suitable for reacting to form capping layers, the compounds in the coating may form a capping layer on the fluorescent nanocrystal with the coating compounds operably bonded to the capping layer. | 2010-11-18 |
20100291703 | BIOSENSOR - A biosensor applicable to an environment suitable for biosensing is provided, which is a solid-state element for performing detections in an aqueous environment. The biosensor at least includes a biosensing layer, a light-emitting diode and a photodiode. The biosensing layer causes changes in the light-emitting property thereof after absorbing, adsorbing and/or bonding with a biological substance released during in vivo signal transduction in an organism, and the rays of light generated by excitation of the light-emitting diode causes the biosensing layer to emit fluorescence. After the fluorescence is absorbed by the photodiode, it can be converted into an interpretable photocurrent signal. Afterwards, the meaning of the in vivo signal transduction can be understood by interpretation of the photocurrent signal. | 2010-11-18 |
20100291704 | Method of Inorganic Analysis by Mass Spectrometry - A method of inorganic analysis by mass spectrometry comprises treating a surface with a chelating reagent so that inorganic elements can be made volatile and desorbed directly from the surface, exposing the volume over the surface or a swab wiping the surface to a flow of metastable atoms and molecules at atmospheric pressure to ionize volatile compounds, and passing the ionized volatile compounds to a mass spectrometer or the like. | 2010-11-18 |
20100291705 | ANTIGEN EXPOSING MICELLE AND UNORDERED AGGREGATE - An antigen exposing micelle or unordered aggregate comprising at least one carrier, at least one epitope and at least one anchoring molecule, wherein said anchoring molecule comprises at least one anchoring part, intended to anchor the antigen exposing micelle to a surface. | 2010-11-18 |
20100291706 | DYE CONJUGATES AND METHODS OF USE - The present invention relates to cyanine compounds, compositions comprising them, articles of manufacture, and methods of making and using them. The cyanines usefully comprise one or more carboxyl groups or derivatives thereof that are indirectly attached to an aryl ring on an alkylaryl cyanine substituent. Also provided are conjugates of the disclosed cyanines and one or more other substances. Solvates, solutions, and derivatized forms of the cyanines are also provided. The cyanines find use in a variety of bioassays, both in direct single-label applications and in energy transfer formats. Methods utilizing the disclosed cyanines for analyzing a sample for a target are provided. Also disclosed are detection complexes comprising the disclosed cyanines, as well as compositions and articles comprising the cyanines in an excited state, for example formed by direct excitation or by energy transfer. The cyanines may be used as alternatives to other known optically active species in a variety of settings. Other embodiments are described further herein. | 2010-11-18 |
20100291707 | Multiplexed Scanometric Assay for Target Molecules - The present invention is directed to compositions and methods of use of a functionalized nanoparticle having a catalytic metal deposit. | 2010-11-18 |
20100291708 | METHODS TO DIAGNOSE A REQUIRED REGULATION OF TROPHOBLAST INVASION - Methods are provided for the diagnosis and treatment of patients with increased risk of preeclampsia. The methods involve measuring levels of TGF-β | 2010-11-18 |
20100291709 | HUMAN NT-PRO B-TYPE NATRIURETIC PEPTIDE ASSAY HAVING REDUCED CROSS-REACTIVITY WITH OTHER PEPTIDE FORMS - The present disclosure relates to assays for detecting and/or quantifying the amount of human NT-pro B-type natriuretic peptide or human NT-pro B-type natriuretic peptide fragment in a test sample. | 2010-11-18 |
20100291710 | BIOSENSOR SYSTEM FOR EXTERNAL ACTUATION OF MAGNETIC PARTICLES IN A BIOSENSOR CARTRIDGE - The invention provides for a biosensor system ( | 2010-11-18 |
20100291711 | INTEGRATED SENSOR MICROSYSTEM AND METHOD FOR DETECTING BIOMOLECULES IN LIQUID - An integrated microsystem for detecting biomolecules is made up of a micropump for delivering a sample, a microsensor for detecting the presence of a target biomolecule in the sample, a microheater for maintaining the temperature of operation, a microcontroller for regulating the sample delivery and a signal processor for analyzing the sensor signal. A single wall carbon nanotube based biological sensor can be used as the microsensor. The single wall carbon nanotube based sensor can either have a chance in conductance based on the presence and/or quantity of the target biomolecule or quantify the mass uptake of the sensor matrix. | 2010-11-18 |
20100291712 | MANIPULATION OF MAGNETIC MICROPARTICLES IN A HIGH PRESSURE LIQUID SYSTEM AND EXTRACTION PROCESS - The invention concerns a device and a method for the manipulation of a liquid sample material in which magnetic microparticles are suspended whereby the microparticles have a functionalized surface and an analyte is bound to the surface. The sample material is introduced into a device with a liquid system through an injection device ( | 2010-11-18 |
20100291713 | METHOD OF FORMING HIGHLY CONFORMAL AMORPHOUS CARBON LAYER - A method of forming a conformal amorphous hydrogenated carbon layer on an irregular surface of a semiconductor substrate includes: vaporizing a hydrocarbon-containing precursor; introducing the vaporized precursor and an argon gas into a CVD reaction chamber inside which the semiconductor substrate is placed; depositing a conformal amorphous hydrogenated carbon layer on the irregular surface of the semiconductor substrate by plasma CVD; and controlling the deposition of the conformal ratio of the depositing conformal amorphous hydrogenated carbon layer. The controlling includes (a) adjusting a step coverage of the conformal amorphous hydrogenated carbon layer to about 30% or higher as a function of substrate temperature, and (b) adjusting a conformal ratio of the conformal amorphous hydrogenated carbon layer to about 0.9 to about 1.1 as a function of RF power and/or argon gas flow rate, | 2010-11-18 |
20100291714 | METHOD AND SYSTEM FOR THE IN-SITU DETERMINATION OF THE MATERIAL COMPOSITION OF OPTICALLY THIN LAYERS - A system and method for in situ determination of a material composition of optically thin layers deposited from a vapor phase onto a substrate includes irradiating the substrate with incoherent light of at least three different wavelengths, optically detecting in a spatially resolved manner a reflection intensity of a diffuse or a direct light scattering emanating from a deposited layer outside of a total reflection, concurrently providing numerical values of the detected reflection intensity to an optical layer model based on general line transmission theory, ascertaining values for the optical layer parameters of the deposited layer from the optical layer model for the at least three different wavelengths by numerically adapting the optical layer model to a time characteristic of the detected reflection intensities, and quantitatively determining a material composition of the deposited layer from the ascertained values by comparing the ascertained values to standard values. | 2010-11-18 |
20100291715 | MOUNTED STRUCTURE, LIQUID DROPLET EJECTION HEAD, LIQUID DROPLET EJECTION APPARATUS AND MANUFACTURING METHOD - A liquid droplet ejection head includes: a first substrate having a pressurizing chamber with a nozzle aperture that ejects liquid droplets, and a first surface on which is formed a first wiring electrically connected to the drive element; a second substrate disposed on the first surface of the first substrate and covering the driven element, the second substrate having a second surface and a side surface, the second surface facing in a same direction as the first surface of the first substrate and on which is formed a second wiring, the side surface on which is formed a third wiring that combines the first wiring and the second wiring; a semiconductor element disposed on the second surface of the second substrate, and which drives the driven element; and plating that electrically connects the first wiring, the second wiring, the third wiring, and a connection terminal of the semiconductor element. | 2010-11-18 |
20100291716 | ORGANIC ELECTROLUMINESCENCE DEVICE AND METHOD OF MANUFACTURING THE SAME - An EL device with low manufacturing costs and improved yield due to simplified structure and use of an organic light emitting transistor and a method of manufacturing the same are disclosed. The EL device includes: a first organic light emitting transistor including a first source electrode; a first drain electrode opposing the first source electrode; a first intermediate layer including at least an emission layer formed between the first source electrode and the first drain electrode; and a first gate electrode which is insulated from the first source electrode, the first drain electrode, and the first intermediate layer and surrounds the first intermediate layer; and a second organic light emitting transistor including a second source electrode; a second drain electrode opposing the second source electrode; a second intermediate layer including at least an emission layer formed between the second source electrode and the second drain electrode; and a second gate electrode which is insulated from the second source electrode, the second drain electrode, and the second intermediate layer, surrounds the second intermediate layer, and is connected to the first drain electrode. | 2010-11-18 |
20100291717 | OPTIMIZED PROCESS FOR FABRICATING LIGHT-EMITTING DEVICES USING ARTIFICIAL MATERIALS - The present invention relates to a process for fabricating light-emitting devices. More particularly, the aim of the invention is to allow the fabrication of light emitters with improved efficiency by using artificial materials, enabling antireflection or high-reflectivity treatments to be carried out. | 2010-11-18 |
20100291718 | METHOD OF FABRICATING SEMICONDUCTOR LASER - A substrate product is formed, and the substrate product includes a first region, a second region, a protrusion structure, and first and second scribe marks. The first region includes sections arranged in first and second axes to form an array, and the second region is provided adjacent to the array. The protrusion structure is provided in the second region; the first and second scribe marks are provided in the second region; the first and second scribe marks extend along first and second reference lines, respectively; and the first and second reference lines define boundary of the sections. After sandwiching the substrate product between films, a first cleavage of the substrate product is performed along the first scribe mark to form a first laser bar and another substrate product, and a second cleavage of the other substrate product is performed along the second scribe mark to form a second laser bar and still another substrate product. Each section includes a laser stripe extending in the direction of the first axis, the substrate product includes a semiconductor substrate and a semiconductor laminate for the semiconductor laser provided on the semiconductor substrate. The protrusion structure is provided on the first reference line. | 2010-11-18 |
20100291719 | METHOD FOR MANUFACTURING NITRIDE BASED SINGLE CRYSTAL SUBSTRATE AND METHOD FOR MANUFACTURING NITRIDE BASED SEMICONDUCTOR DEVICE - A method for manufacturing a nitride based single crystal substrate and a method for manufacturing a nitride based semiconductor device. The method for manufacturing the nitride based single crystal substrate includes forming a nitride based single crystal layer on a preliminary substrate; forming a polymer support layer by applying a setting adhesive material having flowability on the upper surface of the nitride based single crystal layer and hardening the applied adhesive material; and separating the nitride based single crystal layer from the preliminary substrate by irradiating a laser beam onto the lower surface of the preliminary substrate. The method for manufacturing the nitride based single crystal substrate is applied to the manufacture of a nitride based semiconductor device having a vertical structure. | 2010-11-18 |
20100291720 | Method of fabricating organic light emitting diode display - A method of fabricating an organic light emitting diode display device includes: sequentially forming a thin film transistor (TFT) array, a first electrode, a bank pattern, a spacer, and a first relevant layer on an acceptor substrate; sequentially forming a metal pattern and an organic light emission material layer on a doner substrate; aligning and attaching the acceptor substrate and the doner substrate, and forming the light emission layer by transferring the organic light emission material onto the acceptor substrate by applying power to the metal pattern; and sequentially forming the second relevant layer and the second electrode on the light emission layer-formed acceptor substrate. | 2010-11-18 |
20100291721 | PROCESSES FOR FORMING ELECTRONIC DEVICES INCLUDING SPACED-APART RADIATION REGIONS - Processes for forming an electronic device include forming a first radiation region, a second radiation region spaced apart from the first radiation region, and an insulating region. The insulating region can have a first side and a second side opposite the first side. The first radiation region can lie immediately adjacent to the first side, and the second radiation region can lie immediately adjacent to the second side. Within the insulating region, no other radiation region may lie between the first and second radiation regions, and the insulating region can include an insulating layer that includes a plurality of openings. A process for forming the electronic device can include patterning an insulating layer. | 2010-11-18 |
20100291722 | ETCHANT AND METHOD OF MANUFACTURING AN ARRAY SUBSTRATE USING THE SAME - An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH | 2010-11-18 |
20100291723 | METHOD OF MANUFACTURING AN ORGANIC ELECTRONIC OR OPTOELECTRONIC DEVICE - A method of manufacturing an organic electronic or optoelectronic device, the method comprising the steps of: (a) providing a substrate having a plurality of banks formed thereon with alternating well formations formed therebetween, the surface of said banks having imprint formations formed thereon of a dimension conferring a selected wetting property to the surface of said banks that is different from the surface of said wells; and (b) depositing an organic solution into said well formations, wherein the wetting property of said banks causes any organic solution deposited thereon to be at least partially repelled. | 2010-11-18 |
20100291724 | METHOD OF PRODUCING HIGH PERFORMANCE PHOTOVOLTAIC AND THERMOELECTRIC NANOSTRUCTURED BULK AND THIN FILMS - Embodiments of the invention provide methods of forming photovoltaic or thermoelectric materials, including photovoltaic or thermoelectric films. In one embodiment, the invention provides a method of forming a photovoltaic material, the method comprising: depositing an inorganic capped nanoparticle solution onto a substrate; and heating the substrate. | 2010-11-18 |
20100291725 | Method of forming a flexible nanostructured material for photovoltaic panels - An efficient and low-cost method is intended for forming a flexible nanostructured material suitable for use as an active element of a photovoltaic panel. The method consists of evaporating a colloidal solution, which contains nanoparticles of various sizes and/or masses, from a flat surface of a rotating body on which the solution forms a thin and easily vaporizable layer, and simultaneously releasing the nanoparticles from the solution for their free flight through a gaseous medium toward the flexible substrate. As a result, the particles of different sizes and/or types of material are deposited onto the flexible substrate in a predetermined sequence that corresponds to the magnitude of resistance experienced by the nanoparticles during their free flight. In this method, the final, flexible nanostructured material is formed as a multilayer nanostructured film in which the nanoparticles of larger size and greater density are deposited onto the flexible substrate first and thus are located under the nanoparticles of smaller size and smaller density. | 2010-11-18 |
20100291726 | Method of Fabricating a Radiation Detector - The present invention relates to a method of fabricating a radiation detector comprising a photosensitive sensor assembly ( | 2010-11-18 |
20100291727 | ROLL-TO-ROLL PROCESSING METHOD AND TOOLS FOR ELECTROLESS DEPOSITION OF THIN LAYERS - A deposition method and a system are provided to deposit a CdS buffer layer on a surface of a solar cell absorber layer of a flexible workpiece from a process solution including all chemical components of the CdS buffer layer material. CdS is deposited from the deposition solution while the flexible workpiece is elastically shaped by a series of shaping rollers to retain the process solution on the solar cell absorber layer and while the flexible workpiece is heated by contacting to a heated liquid that the shaping rollers are fully or partially immersed. The flexible workpiece is elastically shaped by pulling a back surface of the flexible workpiece into surface cavity of the shaping rollers using magnetic force. | 2010-11-18 |
20100291728 | MANUFACTURING METHOD OF THE SOLAR CELL - A method of manufacturing a solar cell, which can improve productivity by improving a surface texturing process for effectively capturing incident light during a process for manufacturing the solar cell, is provided. The method includes cleaning a substrate, texturing a surface of the substrate, doping and diffusing impurities into the substrate, coating an anti-reflection layer on the substrate, formed metal electrodes on the substrate, and cutting off corner electrodes among the metal electrodes. The texturing of the surface of the substrate includes printing a mask having a predetermined pattern on the substrate through an imprint process, etching the substrate, and removing the mask. | 2010-11-18 |
20100291729 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - A method of manufacturing a photoelectric conversion device having a semiconductor substrate, comprises a first step of forming an insulating film on the semiconductor substrate, a second step of forming first holes in the insulating film, a third step of forming, in the insulating film, second holes shallower than the first holes, a fourth step of forming electrically conductive portions by embedding an electrically conductive material in the first holes, and forming planarization assisting portions by embedding the electrically conductive material in the second holes, and a fifth step of polishing the electrically conductive portions, the insulating film, and the planarization assisting portions until the planarization assisting portions are removed, thereby planarizing upper surfaces of the electrically conductive portions and the insulating film. | 2010-11-18 |
20100291730 | BACKSIDE ILLUMINATED IMAGING DEVICE, SEMICONDUCTOR SUBSTRATE, IMAGING APPARATUS AND METHOD FOR MANUFACTURING BACKSIDE ILLUMINATED IMAGING DEVICE - A backside illuminated imaging device performs imaging by illuminating light from a back side of a p substrate to generate electric charges in the substrate based on the light and reading out the electric charges from a front side of the substrate. The device includes n layers located in the substrate and on an identical plane near a front side surface of the substrate and accumulating the electric charges; n+ layers between the respective n layers and the front side of the substrate, the n+ layers having an exposed surface exposed on the front side surface of the substrate and functioning as overflow drains for discharging unnecessary electric charges accumulated in the n layers; p+ layers between the respective n+ layers and the n layers and functioning as overflow barriers of the overflow drains; and an electrode connected to the exposed surface of each of the n+ layers. | 2010-11-18 |
20100291731 | METHOD OF FIELD-CONTROLLED DIFFUSION AND DEVICES FORMED THEREBY - A technique for creating high quality Schottky barrier devices in doped (e.g., Li | 2010-11-18 |
20100291732 | Manufacturing method for electronic devices - A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting the first metallic bond part and the second metallic bond part. | 2010-11-18 |
20100291733 | SEMICONDUCTOR PACKAGE WITH IMPROVED SIZE, RELIABILITY, WARPAGE PREVENTION, AND HEAT DISSIPATION AND METHOD FOR MANUFACTURING THE SAME - The semiconductor package includes a semiconductor package module with circuit patterns formed on an insulation substrate, at least two semiconductor chips electrically connected to each of the circuit patterns using bumps, and an insulation member filled in any open space in the semiconductor module. A cover plate is formed on the upper portion of the semiconductor package module, and a penetration electrode penetrates the semiconductor package. The penetration electrode is electrically connected to the circuit patterns. The described semiconductor package improves upon important characteristics such as size, reliability, warpage prevention, and heat dissipation. | 2010-11-18 |
20100291734 | Semiconductor Device with an Improved Solder Joint - A semiconductor device with an improved solder joint system is described. The solder system includes two copper contact pads connected by a body of solder and the solder is an alloy including tin, silver, and at least one metal from the transition groups IIIA, IVA, VA, VIA, VIIA, and VIIIA of the Periodic Table of the Elements. The solder joint system also includes, between the pads and the solder, layers of intermetallic compounds, which include grains of copper and tin compounds and copper, silver, and tin compounds. The compounds contain the transition metals. The inclusion of the transition metals in the compound grains reduce the compound grains size and prevent grain size increases after the solder joint undergoes repeated solid/liquid/solid cycles. | 2010-11-18 |
20100291735 | STACKABLE SEMICONDUCTOR CHIP LAYER COMPRISING PREFABRICATED TRENCH INTERCONNECT VIAS - A stackable layer and stacked multilayer module are disclosed. Individual integrated circuit die are tested and processed at the wafer level to create vertical area interconnect vias for the routing of electrical signals from the active surface of the die to the inactive surface. Vias are formed at predefined locations on each die on the wafer at the reticle level using a series of semiconductor processing steps. The wafer is passivated and the vias are filled with a conductive material. The bond pads on the die are exposed and a metallization reroute from the user-selected bond pads and vias is applied. The wafer is then segmented to form thin, stackable layers that can be stacked and vertically electrically interconnected using the conductive vias, forming high-density electronic modules which may, in turn, be further stacked and interconnected to form larger more complex stacks. | 2010-11-18 |
20100291736 | STACKING MULTIPLE DEVICES USING SINGLE-PIECE INTERCONNECTING ELEMENT - An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads. | 2010-11-18 |
20100291737 | Method of manufacturing semiconductor package - A method of manufacturing a semiconductor package that includes: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs. | 2010-11-18 |
20100291738 | Patterned Die Attach and Packaging Method Using the Same - A semiconductor die is attached to a packaging substrate by a patterned layer of conductive metal that includes voids. The voids provide a space into which the metal may expand when heated in order to avoid placing mechanical stress on the bonds caused by mismatches in the thermal coefficients of thermal expansion of the die, the conductive metal bond layer and the substrate. An additional coating of conductive metal may be flowed over the bond lines to reinforce the bonds. | 2010-11-18 |
20100291739 | DICING DIE BONDING FILM AND DICING METHOD - The present invention relates to a dicing die bonding film, which is able to maintain good workability and reliability in any semiconductor packaging process, such as adhesive property, gap filling property and pick-up property, while controlling burr incidence in a dicing process and thus contamination of die, and a dicing method. Specifically, the present invention is characterized by optimizing tensile characteristics of the dicing die bonding film, or carrying out the dicing on the parts of the die bonding film in the dicing process and separating it through an expanding process. Therefore, the present invention may regulate physical properties of films so as to have the maximized adhesive property, pick-up property and gap filling property without any specific restriction, while controlling burr incidence in the dicing process and contamination of die. As a result, workability and reliability in a packaging process may be excellently maintained. | 2010-11-18 |
20100291740 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the semiconductor layer, and a gate electrode arranged so as to oppose the channel region via the gate insulating film. At least a portion of the semiconductor layer includes a catalyst element capable of promoting crystallization, and the semiconductor layer further includes a gettering region that includes the catalyst element at a higher concentration than in the channel region or the source region and the drain region. The thickness of the gate insulating film on the gettering region is smaller than that on the source region and the drain region, or the gate insulating film is not disposed on the gettering region. | 2010-11-18 |
20100291741 | Method of fabricating array substrate - A method of fabricating an array substrate includes sequentially forming a first metal layer, a first inorganic insulating layer and an intrinsic amorphous silicon layer on a substrate, the first metal layer including a first metallic material layer and a second metallic material layer; crystallizing the intrinsic amorphous silicon; forming a gate electrode, a gate line, a gate insulating layer and an active layer; forming an interlayer insulating layer including first and second contact holes respectively exposing both sides of the active layer; forming first and second ohmic contact patterns respectively contacting the both sides of the active layers, a source electrode, a drain electrode, and a data line connecting the source electrode; forming a passivation layer on the source electrode, the drain electrode; and forming a pixel electrode on the passivation layer and contacting the drain electrode. | 2010-11-18 |
20100291742 | REVERSE CONSTRUCTION MEMORY CELL - A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate. | 2010-11-18 |
20100291743 | Semiconductor device and method of forming the same - A method of forming a semiconductor device includes the following processes. A first pillar and a second pillar are formed on a semiconductor substrate. A semiconductor film is formed which includes first and second portions. The first portion is disposed over a side surface of the first pillar. The second portion is disposed over a side surface of the second pillar. The first and second portions are different from each other in at least one of impurity conductivity type and impurity concentration. A part of the semiconductor film is removed by etching back. The first and second portions are etched at first and second etching rates that are different from each other. | 2010-11-18 |
20100291744 | HIGH DENSITY TRENCH MOSFET WITH SINGLE MASK PRE-DEFINED GATE AND CONTACT TRENCHES - Trench gate MOSFET devices may be formed using a single mask to define gate trenches and body contact trenches. A hard mask is formed on a surface of a semiconductor substrate. A trench mask is applied on the hard mask to predefine a body contact trench and a gate trench. These predefined trenches are simultaneously etched into the substrate to a first predetermined depth. A gate trench mask is next applied on top of the hard mask. The gate trench mask covers the body contact trenches and has openings at the gate trenches. The gate trench, but not the body contact trench, is etched to a second predetermined depth. Conductive material of a first kind may fill the gate trench to form a gate. Conductive material of a second kind may fill the body contact trench to form a body contact. | 2010-11-18 |
20100291745 | METHOD FOR MANUFACTURING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - Bit line diffusion layers are formed in an upper part of a semiconductor substrate with a bit line contact region being interposed between the bit line diffusion layers. A conductive film is formed over the semiconductor substrate, the bit line diffusion layers, and first gate insulating films. Then, control gate electrodes are formed from the conductive film. Thereafter, at least the first gate insulating film in the bit line contact region is removed, and a connection diffusion layer is formed in the bit line contact region so as to connect the bit line diffusion layers located on both sides of the bit line contact region. When forming the control gate electrodes, the conductive film is left so as to extend over the bit line contact region and over the bit line diffusion layers located on both sides of the bit line contact region. | 2010-11-18 |
20100291746 | Shared contact structure, semiconductor device and method of fabricating the semiconductor device - A shared contact structure, semiconductor device and method of fabricating the semiconductor device, in which the shared contact structure may include a gate electrode disposed on an active region of a substrate and including facing first and second sidewalls. The first sidewall may be covered with an insulating spacer. The source/drain regions may be formed within the active region adjacent the first sidewall, and provided on the opposite side of the second sidewall. A corner protection pattern may be formed adjacent the source/drain regions and the insulating spacer, and covered by an inter-layer dielectric. A shared contact plug may be formed through the inter-layer dielectric, to be in contact with the gate electrode, corner protection pattern and source/drain regions. | 2010-11-18 |
20100291747 | Phase Change Memory Device and Manufacturing Method - A phase change memory device comprises a photolithographically formed phase change memory cell having first and second electrodes and a phase change element positioned between and electrically coupling the opposed contact elements of the electrodes to one another. The phase change element has a width, a length and a thickness. The length, the thickness and the width are less than a minimum photolithographic feature size of the process used to form the phase change memory cell. The size of the photoresist masks used in forming the memory cell may be reduced so that the length and the width of the phase change element are each less than the minimum photolithographic feature size. | 2010-11-18 |
20100291748 | METHOD FOR MAKING PMC TYPE MEMORY CELLS - A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte. | 2010-11-18 |
20100291749 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing a semiconductor wafer, the method comprising: providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks. | 2010-11-18 |
20100291750 | METHOD OF FABRICATING FLASH MEMORY DEVICE - A semiconductor device includes a semiconductor substrate having a cell region and a peripheral region. A cell array is defined within the cell region, the cell array having first, second, third, and fourth sides. A first decoder is defined within the peripheral region and provided adjacent to the first side of the cell array. A first isolation structure is formed at a first boundary region provided between the first side of the cell array and the peripheral region. A first active region is formed at a second boundary region that is provided between the second side of the cell array and the peripheral region. The first isolation structure has a first portion that has a first depth and a second portion that has a second depth. | 2010-11-18 |
20100291751 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void. | 2010-11-18 |
20100291752 | METHOD FOR MANUFACTURING SOI SUBSTRATE AND SOI SUBSTRATE - A method is demonstrated to form an SOI substrate having a silicon layer with reduced surface roughness in a high yield. The method includes the step of bonding a base substrate such as a glass substrate and a bond substrate such as a single crystal semiconductor substrate to each other, where a region in which bonding of the base substrate with the bond substrate cannot be performed is provided at the interface therebetween. Specifically, the method is exemplified by the combination of: irradiating the bond substrate with accelerated ions; forming an insulating layer over the bond substrate; forming a region in which bonding cannot be performed in part of the surface of the bond substrate; bonding the bond substrate and the base substrate to each other with the insulating layer therebetween; and separating the bond substrate from the base substrate, leaving a semiconductor layer over the base substrate. | 2010-11-18 |
20100291753 | SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE - A single crystal semiconductor layer is formed over a substrate having an insulating surface by the following steps: forming an ion doped layer at a given depth from a surface of a single crystal semiconductor substrate; performing plasma treatment to the surface of the single crystal semiconductor substrate; forming an insulating layer on the single crystal semiconductor substrate to which the plasma treatment is performed; bonding the single crystal semiconductor substrate to the substrate having the insulating surface with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate using the ion doped layer as a separation surface. As a result, a semiconductor substrate in which a defect in an interface between the single crystal semiconductor layer and the insulating layer is reduced can be provided. | 2010-11-18 |
20100291754 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor substrate is irradiated with accelerated hydrogen ions, thereby forming a damaged region including a large amount of hydrogen. After a single crystal semiconductor substrate and a supporting substrate are bonded to each other, the semiconductor substrate is heated, so that the single crystal semiconductor substrate is separated in the damaged region. A single crystal semiconductor layer which is separated from the single crystal semiconductor substrate is irradiated with a laser beam. The single crystal semiconductor layer is melted by laser beam irradiation, whereby the single crystal semiconductor layer is recrystallized to recover its crystallinity and to planarized a surface of the single crystal semiconductor layer. After the laser beam irradiation, the single crystal semiconductor layer is heated at a temperature at which the single crystal semiconductor layer is not melted, so that the lifetime of the single crystal semiconductor layer is improved. | 2010-11-18 |
20100291755 | MANUFACTURING METHOD OF SOI SUBSTRATE - An SOI substrate is manufactured by a method in which a first insulating film is formed over a first substrate over which a plurality of first single crystal semiconductor films is formed; the first insulating film is planarized; heat treatment is performed on a single crystal semiconductor substrate attached to the first insulating film; a second single crystal semiconductor film is formed; a third single crystal semiconductor film is formed using the first single crystal semiconductor films and the second single crystal semiconductor films as seed layers; a fragile layer is formed by introducing ions into the third single crystal semiconductor film; a second insulating film is formed over the third single crystal semiconductor film; heat treatment is performed on a second substrate superposed on the second insulating film; and a part of the third single crystal semiconductor film is fixed to the second substrate. | 2010-11-18 |
20100291756 | METHOD FOR THE PRODUCTION OF A SEMICONDUCTOR STRUCTURE - Semiconductor structures are produced by providing a 3C—SiC semiconductor layer containing a monocrystalline 3C—SiC layer by implantation of carbon in silicon on a first silicon substrate and applying an epitaxial layer of nitride compound semiconductor suitable for the generation of optoelectronic components onto the 3C—SiC semiconductor layer structure, wherein the epitaxial layer of nitride semiconductor is transferred onto a second substrate by bonding the nitride layer onto the second substrate surface and mechanically or chemically removing silicon and layers containing SiC, the second substrate being a metal with a reflectivity ≧80% or being substantially transparent. | 2010-11-18 |
20100291757 | METHOD OF FORMING, MODIFYING, OR REPAIRING A SEMICONDUCTOR DEVICE USING FIELD-CONTROLLED DIFFUSION - A technique for altering or repairing the operating state of a semiconductor device comprises field-controlled diffusion of mobile dopant atoms within the metal oxide crystal lattice. When heated (e.g., above 550 K) in the presence of an electric field (e.g., bias to ground of +/−50 V) the dopant atoms are caused to collect to form an ohmic contact, leaving a depletion region. Metal-semiconductor junction devices such as diodes, photo-diodes, photo-detectors, MESFETs, etc. may thereby be fabricated, repaired or modified. | 2010-11-18 |
20100291758 | Thin-Film Devices Formed From Solid Particles - Methods and devices are provided for forming thin-films from solid group IIIA-based particles. In one embodiment of the present invention, a method is described comprising of providing a first material comprising an alloy of a) a group IIIA-based material and b) at least one other material. The material may be included in an amount sufficient so that no liquid phase of the alloy is present within the first material in a temperature range between room temperature and a deposition or pre-deposition temperature higher than room temperature, wherein the group IIIA-based material is otherwise liquid in that temperature range. The other material may be a group IA material. A precursor material may be formulated comprising a) particles of the first material and b) particles containing at least one element from the group consisting of: group IB, IIIA, VIA element, alloys containing any of the foregoing elements, or combinations thereof. The temperature range described above may be between about 20° C. and about 200° C. It should be understood that the alloy may have a higher melting temperature than a melting temperature of the IIIA-based material in elemental form. | 2010-11-18 |
20100291759 | COMPLEXES OF CARBON NANOTUBES AND FULLERENES WITH MOLECULAR-CLIPS AND USE THEREOF - Separation of carbon nanotubes or fullerenes according to diameter through non-covalent pi-pi interaction with molecular clips is provided. Molecular clips are prepared by Diels-Alder reaction of polyacenes with a variety of dienophiles. The pi-pi complexes of carbon nanotubes with molecular clips are also used for selective placement of carbon nanotubes and fullerenes on substrates. | 2010-11-18 |
20100291760 | Method and system for spatially selective crystallization of amorphous silicon - The manufacturing methodology to produce polycrystalline silicon in time and cost efficient manner uses a spatially selective crystallization approach to greatly reduce the amount of energy delivered to the work surface. The amorphous silicon film is subjected to laser radiation substantially exclusively at localized areas where TFTs are to be formed. The source of radiation is a copper vapor laser which produces a highly stable radiation in a visible spectrum with an energy sufficient to convert amorphous silicon into polysilicon in 1-3 shots. The optic system delivers the homogenized, conditioned and focused laser beam to the area of interest in a controlled manner. Single or multi-laser beam arrangements, as well as different shapes and sizes of laser beam spots are contemplated. | 2010-11-18 |
20100291761 | Method For Producing A Wafer Comprising A Silicon Single Crystal Substrate Having A Front And A Back Side And A Layer of SiGe Deposited On The Front Side - A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order:
| 2010-11-18 |
20100291762 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process. | 2010-11-18 |
20100291763 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - Oxidation of a metal film disposed under a high permittivity insulation film can be suppressed, and the productivity of a film-forming process can be improved. In a method of manufacturing a semiconductor device, a first high permittivity insulation film is formed on a substrate by alternately repeating a process of supplying a source into a processing chamber in which the substrate is accommodated and exhausting the source and a process of supplying a first oxidizing source into the processing chamber and exhausting the first oxidizing source; and a second high permittivity insulation film is formed on the first high permittivity insulation film by alternately repeating a process of supplying the source into the processing chamber and exhausting the source and a process of supplying a second oxidizing source different from the first oxidizing source into the processing chamber and exhausting the second oxidizing source. | 2010-11-18 |
20100291764 | Methods Of Removing Noble Metal-Containing Nanoparticles, Methods Of Forming NAND String Gates, And Methods Of Forming Integrated Circuitry - Some embodiments include methods of removing noble metal-containing particles from over a substrate. The substrate is exposed to a composition that reduces adhesion between the noble metal-containing particles and the substrate, and simultaneously the substrate is spun to sweep at least some of the noble metal-containing particles off from the substrate. Some embodiments include methods in which tunnel dielectric material is formed across a semiconductor wafer. Metallic nanoparticles are formed across the tunnel dielectric material. A stack of two or more different materials is formed over the metallic nanoparticles. A portion of the stack is covered with a protective mask while another portion of the stack is left unprotected. The unprotected portion of the stack is removed to expose some of the metallic nanoparticles. The semiconductor wafer to is subjected to etchant suitable to undercut at least some of the exposed metallic nanoparticles, and simultaneously the semiconductor wafer is spun. | 2010-11-18 |
20100291765 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - An aspect of the present disclosure, there is provided a method for fabricating a semiconductor device, including, forming a gate insulating film on a semiconductor substrate, forming a metal film on the gate insulating film, depositing a metal-silicon compound film on the metal film without exposing the semiconductor substrate into atmosphere after forming the metal film, forming a silicon film on the metal-silicon compound film, and etching the metal film, the metal-silicon compound film, and the silicon film. | 2010-11-18 |
20100291766 | Transistor Constructions and Processing Methods - A transistor construction includes a first floating gate having a first conductive or semiconductive surface and a second floating gate having a second conductive or semiconductive surface. A dielectric region is circumferentially surrounded by the first surface. The region is configured to reduce capacitive coupling between the first and second surfaces. Another transistor construction includes a floating gate having a cavity extending completely through the floating gate from a first surface of the floating gate to an opposing second surface of the floating gate. The floating gate otherwise encloses the cavity, which is filled with at least one dielectric. A method includes closing an upper portion of an opening in insulator material with a gate material during the deposition before filling a lower portion with the gate material. The depositing and closing provide an enclosed cavity within the lower portion of the opening. | 2010-11-18 |
20100291767 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In MOSFET having SBD as a protection element, a TiW (alloy having tungsten as a main component) film is used as an aluminum-diffusion barrier metal film below an aluminum source electrode in order to secure properties of SBD. The present inventors have found that a tungsten-based barrier metal film is in the form of columnar grains having a lower barrier property than that of a titanium-based barrier metal film such as TiN so that aluminum spikes are generated relatively easily in a silicon substrate. In the present invention, when a tungsten-based barrier metal film is formed by sputtering as a barrier metal layer between an aluminum-based metal layer and a silicon-based semiconductor layer therebelow, the lower layer is formed by ionization sputtering while applying a bias to the wafer side and the upper layer is formed by sputtering without applying a bias to the wafer side. | 2010-11-18 |
20100291768 | Method for Fabricating a Semiconductor Device - An exposure mask for recess gate includes a transparent substrate and a recess gate pattern. The recess gate pattern is disposed over the transparent substrate. The recess gate pattern includes a first portion having a first line width and a second portion having a second line width smaller than the first line width. In the second portion, elements of the recess gate pattern are separated. | 2010-11-18 |
20100291769 | ALTERNATIVE METHODS FOR FABRICATION OF SUBSTRATES AND HETEROSTRUCTURES MADE OF SILICON COMPOUNDS AND ALLOYS - The present invention relates to alternative methods for the production of crystalline silicon compounds and/or alloys such as silicon carbide layers and substrates. In one embodiment, a method of the present invention comprises heating a porous silicon deposition surface of a porous silicon substrate to a temperature operable for epitaxial deposition of at least one atom or molecule, contacting the porous silicon deposition surface with a reactive gas mixture comprising at least one chemical species comprising a group IV element and at least one silicon chemical species, and depositing a silicon-group IV element layer on the porous silicon deposition surface. In another embodiment, the chemical species comprising a group IV element can be replaced with a transition metal species to form a silicon silicide layer. | 2010-11-18 |
20100291770 | METHOD OF FORMING OPENINGS IN A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE FABRICATED BY THE METHOD - A method of forming openings to a layer of a semiconductor device comprises forming a dielectric layer over the layer of the semiconductor device, and forming a mask over the dielectric layer. The mask comprises a plurality of mask openings arranged in a regular pattern extending over the dielectric layer and the plurality of mask openings include a plurality of first mask openings and a plurality of second mask openings, each of the plurality of first mask openings being greater in size than each of the plurality of second mask openings. The method further comprises reducing the size of the plurality of second mask openings such that each of the second mask openings is substantially closed and removing portions of the dielectric layer through the plurality of first mask openings to provide openings extending through the dielectric layer to the layer. | 2010-11-18 |
20100291771 | Methods Of Forming Patterns On Substrates - Methods of forming a pattern on a substrate include forming carbon-comprising material over a base material, and spaced first features over the carbon-comprising material. Etching is conducted only partially into the carbon-comprising material and spaced second features are formed within the carbon-comprising material which comprise the partially etched carbon-comprising material. Spacers can be formed along sidewalls of the spaced second features. The carbon-comprising material can be etched through to the base material using the spacers as a mask. Spaced third features can be formed which comprise the anisotropically etched spacers and the carbon-comprising material. | 2010-11-18 |
20100291772 | Semiconductor Manufacturing Method - The present invention discloses a semiconductor manufacturing method. The method for activating a p-type impurity doped in a semiconductor element in a chamber comprises that a vacuum pressure is exerted to the chamber first, and the semiconductor element is heated to a preset temperature and the heating is persisted for a preset period to activate the p-type impurity doped in the semiconductor element. | 2010-11-18 |
20100291773 | ELECTRICAL CONNECTOR DEFINING PLURALITY OF DISCRETE INTERCONNECTING SECTORS FOR RESPECTIVELY RECEIVING INDIVIDUAL IC PACKAGE THEREON - An electrical connector for receiving more than one IC packages ( | 2010-11-18 |
20100291774 | ELECTRICAL SOCKET HAVING CONTACT TERMINALS ARRANGED IN FAN-OUT PITCH ARRANGEMENT - An LGA socket used for connecting a chip module and a print circuit board includes an insulative housing and a number of terminals received in the housing. The housing has a top surface and a bottom surface opposite to each other. Each of the terminals includes an upper arm extending beyond the top surface of the housing and a lower arm extending beyond the bottom surface of the housing. The upper arms and the lower arms of the terminals extend from the base portion with different lengths so as to form different pitches at top and bottom surfaces of the housing. | 2010-11-18 |
20100291775 | ELECTRICAL CONNECTOR AND ASSEMBLY THEREOF - An electrical connector assembly includes an electrical connector, an IC seated on connector and a PCB. The electrical connector includes an insulative housing and a number of electrical contacts each having a retaining portion secured to the housing, a main portion connecting with the retaining portion and a contact portion. The contact portion has a pair of first contacting sections electrical connected with the PCB and a pair of second contacting sections contacting with the IC, and the first and second contacting sections of the electrical contact are disposed in passageways on the PCB. | 2010-11-18 |
20100291776 | Board-To-Board Connector Assembly - A board-to-board connector assembly includes a receptacle connector having a plurality of first terminals, and a plug connector having a plurality of second terminals. Each of the first terminals has an elastic arm oppositely defining two first contact portions, and a first contact arm spaced away from the elastic arm. Each of the second terminals has a second contact arm defining two opposite contact means, and a third contact arm defining a second contact portion towards the second contact arm. When the plug connector is mated with the receptacle connector, the elastic arm of the first terminal is disposed between the second and third contact arms of the corresponding second terminal to make the two first contact portions electrically contact one of the two contact means and the second contact portion respectively, and the first contact arm electrically abuts against the other contact means. | 2010-11-18 |
20100291777 | ELELCTRICAL CONNECTOR ASSEMBLY WITH NOTCH FOR RECEIVING MATING COMPONENT - An electrical connector assembly mounted on a printed circuit board (PCB) includes an insulating housing. The insulating housing includes a base with opposite front and rear end regions and a plurality of side walls upwardly extending from the base. The base cooperates with the side walls to commonly define a first receiving room. A notch defined in the front region of the base forms a second receiving room under the first receiving room. Said second receiving room is smaller than the first receiving room in both the front-to-back direction and a transverse direction perpendicular to said front-to-back direction. No portions of said contacts are located in the second receiving room so as to allow an optoelectronic module including a first portion and a second portion to be snugly received in the first receiving room and the second receiving room respectively, the second portion is attached to the first portion and supported on a top surface of the PCB. | 2010-11-18 |
20100291778 | DETECTION OF IMPROPERLY SEATED ELECTRONIC COMPONENT - A system comprises a circuit board, a pair of electrically-conductive board contacts mounted on the circuit board, and a connector assembly coupled to the board and adapted to receive an electrical component. The connector assembly has a pair of deflectable arms. Each deflectable arm comprises a conductive arm contact. Inserting the electrical component into the connector causes the deflectable arms to be deflected from a resting position and away from said electrical component thereby preventing the board contacts from electrically contacting the arm contacts. When the electrical component is fully seated in the connector, the deflectable arms revert back to the resting positioning thereby causing the arm contacts to electrically contact the board contacts. | 2010-11-18 |
20100291779 | ELECTRICAL PLUG DEVICE WITH FOLDING BLADES - An electrical plug device includes a housing, support members coupled to the housing and electrically conductive members, each supported by one of the support members. The support members are able to rotate about respective axes so that the electrically conductive members can move between a closed position with the electrically conductive members folded into a trough in the housing and an open position with the electrically conductive members extended out of the housing. An elastic member is coupled to the housing to engage one or more of the support members when the electrically conductive members are in the open position or the closed position. Rotation of the support members from the open or closed positions is inhibited by the engagement of the elastic member and the one or more support members. | 2010-11-18 |
20100291780 | PORTABLE ELECTRONIC DEVICES - A portable electronic device includes a connector case and defines a cavity communicating to the air. A guiding portion is formed in the cavity. The connector case includes at least one interface and an engaging portion. The engaging portion is slidablly attached to the guiding portion. The at least one interface is exposed when the connector case slides out from the cavity. | 2010-11-18 |
20100291781 | FIXTURE - A fixture includes a base seat, a resist mechanism, a drive mechanism and an adjust mechanism. The resist mechanism is fixed to the base seat and includes a connector. The drive mechanism is fixed to the base seat. The adjust mechanism is fixed to the base seat and includes a connecting board. The connecting board has a power module attached thereto. The adjust mechanism can adjust the power module relative to the connector. The drive mechanism can drive the connector to move towards the power module. | 2010-11-18 |
20100291782 | GROMMET FOR ELECTRICAL CONNECTOR AND METHOD OF MANUFACTURING THE SAME - A grommet for an electrical connector that comprises a main insulative body that defines a longitudinal axis and at least one inner bore extending through the main insulative body along the longitudinal axis and adapted to receive a wire. The inner bore is defined by a funnel shaped entry area, a contact receiving area opposite the entry area, and an extended longitudinal sealing web that is disposed between the entry area and the contact receiving area. The extended longitudinal sealing web being configured to provide a large surface area for continuous sealing contact with the wire. | 2010-11-18 |
20100291783 | ELECTRONIC DEVICE HAVING USB INTERFACE CAPABLE OF EXTRACTION PROOF - An electronic device, which has a USB interface capable of extraction proof, includes a main body and a USB metallic plug. One side of the main body has a USB metallic plug, on a face of which at least one fastening component is arranged. When the fastening component is buckled into the groove of a USB connector of an electronic product, it can prevent the electronic from being stolen by a thief. | 2010-11-18 |