46th week of 2013 patent applcation highlights part 22 |
Patent application number | Title | Published |
20130300403 | GEAR ABSOLUTE POSITION SENSOR FOR MANUAL TRANSMISSIONS - The present invention provides a gear absolute position sensor assembly (GAPS) that senses the current absolute, position of the shift lever of a manual transmission. The sensor assembly provides data to an associated electronic controller such as an engine control module (ECM) regarding the current position of the shift lever, such as an engaged gear. The sensor assembly preferably comprises at least one Hall effect or other type of magnetic field (proximity) sensors in combination with an application specific integrated circuit (ASIC) which is supplied with data from the sensors, decodes the output of the sensors and provides an output identifying a specific engaged gear or neutral for use by vehicle or engine management electronics. The sensors are mounted proximate the shift linkage at a location where they can sense both rotation and translation. | 2013-11-14 |
20130300404 | CURRENT SENSOR - A first magnetic sensor and a second magnetic sensor are disposed so that the main sensitivity axis direction of the first magnetic sensor is oriented in the direction of an induction magnetic field from a current flowing through a current line, the main sensitivity axis direction of the second magnetic sensor is oriented in a direction opposite to the direction of an induction magnetic field from the current flowing therethrough, the individual main sensitivity axis directions of the first and second magnetic sensors are oriented in a same direction, and the individual sub-sensitivity axis directions of the first and second magnetic sensors are oriented in the same directions as or directions opposite to the directions of the sub-sensitivity axis components of the induction magnetic fields to which the first and second magnetic sensors are individually subjected from a current flowing through an adjacent current line adjacent to the current line. | 2013-11-14 |
20130300405 | QUENCHING DEPTH MEASUREMENT METHOD AND QUENCHING DEPTH MEASUREMENT APPARATUS - A quenching depth measuring method is used for measuring the quenching depth in a workpiece and includes the steps of: magnetizing the workpiece by disposing, in the vicinity of the workpiece, a magnetizer equipped with an exciting coil; detecting, through a detection coil, an induced magnetic field generated by the magnetization; measuring the induced magnetic field as the output voltage of the detection coil; and specifying the thickness of the quenched hardened layer of the workpiece on the basis of known electromagnetic characteristic information of an unquenched material and a fully-quenched material and an output voltage value measured by the detection coil, the unquenched material being made of the same material as the constituent material of the workpiece and being a material on which a quenching process is not performed, the fully-quenched material being a material on which the quenching process is performed. | 2013-11-14 |
20130300406 | METHODS AND APPARATUS FOR MAGNETIC SENSOR HAVING INTEGRATED COIL - Methods and apparatus for a magnetic field sensor including a die, a coil proximate the die to generate a magnetic field, and a magnetic field sensing element having to detect changes in the magnetic field generated by the coil in response to a ferromagnetic target. | 2013-11-14 |
20130300407 | Current Sensor - A current sensor includes a conductive element, and at least two magnetic field sensors arranged on the conductive element and configured to sense a magnetic field generated by a current through the conductive element, wherein the at least two magnetic field sensors are arranged on opposite sides of a line perpendicular to a current flow direction in the conductive element. The current sensor further includes an insulating layer arranged between the conductive element and the magnetic field sensors, and at least two conductor traces provided on the insulating layer, wherein one end of the conductor traces connects to a respective magnetic field sensor, and the other end of the conductor traces providing a terminal for outputting the sensor signals. The conductor traces are arranged such that they do not extend entirely around the conductive element. | 2013-11-14 |
20130300408 | MAGNETOMETER WITH ANGLED SET/RESET COIL - A magnetometer with a set/reset coil having portions that cross portions of sensing strips at an angle in order to create a magnetic field in the sensing strip that is at an angle with respect to the easy axis of magnetization of the sensing strip. Each sensing strip may have a portion having a magnetic field created therein that is different from a magnetic field created in another portion of the same sensing strip. As a result, a lower set/reset coil current is needed to initialize the magnetometer. | 2013-11-14 |
20130300409 | Single-Package Bridge-Type Magnetic Field Sensor - A magnetoresistive sensor bridge utilizing magnetic tunnel junctions is disclosed. The magnetoresistive sensor bridge is composed of one or more magnetic tunnel junction sensor chips to provide a half-bridge or full bridge sensor in a standard semiconductor package. The sensor chips may be arranged such that the pinned layers of the different chips are mutually anti-parallel to each other in order to form a push-pull bridge structure. The sensor chips are then interconnected using wire bonding. The chips can be wire-bonded to various standard semiconductor leadframes and packaged in inexpensive standard semiconductor packages. The bridge design may be push-pull or referenced. In the referenced case, the on-chip reference resistors may be implemented without magnetic shielding. | 2013-11-14 |
20130300410 | Method for fast spin-echo MRT imaging - The invention relates to a method for fast autocalibrated spin-echo MRT imaging by means of independently coded echo groups, wherein one of the two echo groups is used for recording a reference data set or a training data set, while the other echo group is recorded in subsampled manner. | 2013-11-14 |
20130300411 | TRIANGLE COIL ARRANGEMENT - An array arrangement can be provided, that, for example, can include a plurality of triangular antenna arrangements, which can be configured to transmit or receive a magnetic resonance signal(s). A processing arrangement can be configured to generate information associated with a magnetic resonance image based on the magnetic resonance signal(s). A shield arrangement can be configured to shield the triangular antenna arrangements. | 2013-11-14 |
20130300412 | ARRANGEMENT FOR MULTIPLE FREQUENCY, MULTIPLE PORTAL NQR DETECTION - Nuclear quadrupole resonance measurement using two or more wire loop(s) within a space to define a portal, and driving the wire loop(s) with a baseband digital transmitter generating a chirped or stepped signal, to create a corresponding varying electromagnetic field within the portal. Coherent emissions reflected thereby are detected through a directional coupler feeding the transceiver. The detected coherent emissions are processed with a matched filter to determine presence of a target object within the portal. | 2013-11-14 |
20130300413 | METHOD AND APPARATUS FOR GENERATING MAGNETIC RESONANCE IMAGE - A method of generating a magnetic resonance image includes: generating composite data by using a plurality of data sets acquired from a plurality of coils, based on coil characteristics of the plurality of coils; generating first interpolation data by interpolating the composite data; generating a plurality of filtered data sets by filtering the first interpolation data with respect to a plurality of frequency bands; and generating the magnetic resonance image by using the plurality of filtered data sets. | 2013-11-14 |
20130300414 | Local SAR Reduction In Multi-Slice pTx via SAR-Hopping Between Excitations - Described here are a system and method for designing radio frequency (“RF”) pulses for parallel transmission (“pTx”) applications, and particularly pTx applications in multislice magnetic resonance imaging (“MRI”). The concept of “SAR hopping” is implemented by framing the concept between slice-selective excitations as a constrained optimization problem that attempts designing multiple pulses simultaneously subject to an overall local SAR constraint. This results in the set of RF waveforms that yield the best excitation profiles for all pulses while ensuring that the local SAR of the average of all pulses is below the regulatory limit imposed by the FDA. Pulses are designed simultaneously while constraining local SAR, global SAR, and peak power, and average power explicitly. | 2013-11-14 |
20130300415 | MULTI-CHANNEL TRANSMIT MR IMAGING - The invention relates to a multi-channel (e.g. quadrature) MRI transmit system in which RF power amplifiers having different power capabilities are used in different transmit channels. This results in reduced system costs, due to the avoidance of an unused excess of RF power capability when the power demand for obtaining a homogeneous B1-field (RF shimming) is asymmetric and the asymmetry is qualitatively the same for different imaging applications. The multi-channel transmit unit may also comprise a commutator which enables to selectively connect each RF power amplifier to each drive port of transmit coil arrangement (e.g. a birdcage coil). | 2013-11-14 |
20130300416 | INTERLEAVED SPIN-LOCKING IMAGING - A magnetic resonance (MR) system | 2013-11-14 |
20130300417 | SYSTEMS AND METHODS FOR NOISE CONTROL IN A MEDICAL IMAGING SYSTEM - A noise abatement system includes a processor configured to measure noise in an imaging system and generate a switch mode power supply (SMPS) input signal based on the measured noise and an adjustable switched mode power supply configured to receive the SMPS input signal and adjust a switching frequency of the switched mode power supply, based on the SMPS signal, to operate at a frequency that generates harmonics that are outside of an imaging bandwidth of the imaging system. A system and calibration method are also described herein. | 2013-11-14 |
20130300418 | MR Antenna With Compensation for Variable Distance to Shield - A whole-body coil for a magnetic resonance tomography device includes one or more compensation capacitors between a high-frequency antenna and an RF shield. The one or more compensation capacitors each have variable capacitance caused by a variation in a distance of the RF shield to the high-frequency antenna. | 2013-11-14 |
20130300419 | Methods, Systems and Apparatuses for Sensing and Measuring the Electric Field within the Earth - Methods, systems, and apparatuses for measuring an electric potential in the earth, which includes a first sensor are disclosed. The first sensor includes a sensing plate for placement in an environment in close proximity to the earth. The sensing plate has an operative capacitive coupling with the earth and measures the earth's electric potential. The sensor also includes a barrier providing electrochemical segregation between the sensing plate and the earth and an amplifier having at least one stage for receiving and amplifying a first signal carrying the potential measured by the sensing plate. The sensor also includes a first connection carrying the first signal from the sensing plate to the amplifier; and a reference voltage for application to the first stage of the amplifier, the reference voltage providing a reference against which the potential measured by the sensing plate is compared. Other embodiments are described and claimed. | 2013-11-14 |
20130300420 | Acquisition System and Method for Towed Electromagnetic Sensor Cable and Source - An electromagnetic survey acquisition system includes a sensor cable and a source cable, each deployable in a body of water, and a recording system. The sensor cable includes an electromagnetic sensor thereon. The source cable includes an electromagnetic antenna thereon. The recording system includes a source current generator, a current sensor, and an acquisition controller. The source current generator powers the source cable to emit an electromagnetic field from the antenna. The current sensor is coupled to the source current generator. The acquisition controller interrogates the electromagnetic sensor and the current sensor at selected times in a synchronized fashion. | 2013-11-14 |
20130300421 | SYSTEM FOR DETECTING UNDERWATER GEOLOGICAL FORMATIONS IN PARTICULAR FOR THE LOCALIZATION OF HYDROCARBON FORMULATIONS - The present invention relates to a system ( | 2013-11-14 |
20130300422 | METHOD FOR OPERATING A MAGNETIC SWITCHING ELEMENT - In a method for operating a magnetic switching element, at least one connection of at least one sensor device is connected to at least one connection of a coil of the magnetic switching element, and at least one measuring state is established in which the at least one connection of the coil is largely at least temporarily decoupled from a ground, a voltage source, and/or a current source activating the coil, and at least one auxiliary voltage and/or at least one auxiliary current is/are applied to the at least one connection of the coil in the measuring state, and at least one sensor signal is ascertained from at least one electrical potential, at least one potential difference, and/or at least one current flowing at the connections of the coil. | 2013-11-14 |
20130300423 | MEASURING DEVICE FOR CHECKING AN ELECTIRCAL CIRCUIT BREAKER - Measuring device for checking an electrical circuit breaker includes a current generating unit designed to generate a measurement current for a continuity measurement of a switching contact of the circuit breaker. The measuring device furthermore includes a measuring unit for registering a measurement signal at the circuit breaker, an energy supply unit for supplying a control drive of the circuit breaker with electrical energy, and a control unit, which has a timer. The control unit is able output to the control drive, via the control output, a signal for opening or closing the circuit breaker, and to determine a time-based switching behaviour of the circuit breaker in dependence on the measurement signal. Further, the control unit is designed, in the case of the circuit breaker being closed, to determine the resistance of the switching contact in dependence on the measurement current and the measurement signal. | 2013-11-14 |
20130300424 | MEASUREMENT OF A RESISTANCE OF A SWITCHING CONTACT OF AN ELECTRICAL CIRCUIT BREAKER - The present invention relates to a measuring device ( | 2013-11-14 |
20130300425 | ELECTRIC STORAGE DEVICE MANAGEMENT SYSTEM, ELECTRIC STORAGE DEVICE PACK, AND METHOD OF ESTIMATING STATE OF CHARGE - An electric storage device management system includes a voltage sensor, a memory, and a controller. The voltage sensor detects a voltage across an electric storage device having a correlation between an open circuit voltage (OCV) and a state of charge (SOC) including a slight change region and a sharp change region. The memory stores information on correlation between OCV and SOC in the sharp change region. The controller is configured to: determine an OCV based on a voltage detected by the voltage sensor; determine whether the defined OCV is within the sharp change region; determine an SOC corresponding to the defined OCV based on the stored information stored if the defined OCV is within the sharp change region; determine the determined SOC as an estimated SOC; and prohibit the determining of the SOC as an estimated SOC if the defined OCV is out of the sharp change region. | 2013-11-14 |
20130300426 | BATTERY SYSTEM WITH CELL VOLTAGE DETECTING UNITS - A battery system with at least one module includes a plurality of battery cells. A cell voltage detecting circuit is associated with each battery cell of the plurality of battery cells. The cell voltage detecting circuits of the at least one module are connected to a multiplexer. An output of the multiplexer is connected to a communication bus via an analog-digital converter. The communication bus is connected to an evaluating unit. The multiplexer is additionally connected to at least one auxiliary voltage source that is known to the evaluating unit. In a method for monitoring a battery system with at least one module including a plurality of battery cells, a voltage of each of the battery cells is detected and fed to an evaluating unit via a cell voltage detecting unit. An output signal of the cell voltage detecting unit is tested for plausibility. | 2013-11-14 |
20130300427 | ELECTROSTATIC DISCHARGE TEST METHOD AND TEST SYSTEM - An ESD test method for testing an object is disclosed. The object is activated and controlled to separate from a horizontal plane by a pre-determined distance. A first discharge voltage is provided to an external metal portion of the object. A first error is determined to have or have not occurred during the operation of the object each time after the first discharge voltage is provided to the external metal portion. The object is processed to eliminate the first error and then the first discharge voltage is provided to the external metal portion when the first error occurs during the operation of the object. The first error is induced by a hardware structure of the object. The object is moved to contact with the horizontal plane and a specific action is executed when the first error has not occurred during the operation of the object. | 2013-11-14 |
20130300428 | Determination of a Stray Capacitance of an AC Current Generator - For the purpose of determining a stray capacitance of an AC current generator a differential current is measured as a current sum over a plurality of lines carrying a current of the AC current generator, an electric signal which depends on generator voltages present at the AC current generator with respect to earth potential and which is in phase with a leakage current component of the differential current is generated. The electric signal is scaled by multiplying it by a scaling factor; and the scaled electric signal is subtracted from the differential current to obtain a remainder. The scaling factor is repeatedly updated such that the effective value of the remainder reaches a minimum at the present value of the scaling factor. | 2013-11-14 |
20130300429 | Diagnostic Receptacle For Electric Vehicle Supply Equipment - Systems, methods, apparatuses, and computer-readable media provide electric supply equipment | 2013-11-14 |
20130300430 | ISOLATION MONITOR - An isolation monitor is disclosed in which a switchable bias voltage is imposed on a chassis ground. An isolation voltage is measured when a bias voltage is applied. When there are no electrical faults, the isolation voltage swings up and down to known values. When a fault occurs, the isolation voltage will not to swing to the known values, and thus the isolation resistance can be measured and alarm generated if the isolation resistance falls below a threshold value. | 2013-11-14 |
20130300431 | SENSOR TAPE FOR SECURITY DETECTION AND METHOD OF FABRICATION - A sensor in the form of an elongated flexible tape has a plurality of signal paths made from electrical wire or optical fiber which extend between one end and another end of the tape. The electrical wires or optical fibers are disposed in spaced relation across the width and along the length of the tape, and are terminated in connectors at the endpoints of the tape. One connector includes a multiplexer to which an input signal is applied for propagation along the signal paths, The other connector includes an AND gate which provides an output signal which changes in the event of a break in any one or more of the signal paths, thereby indicating an alarm condition. The connectors may be integrated into a signal detector to interface with communication links. The tape is a material that is non-conductive and in which the wires or optical fibers may be woven, disposed or embedded in some manner. | 2013-11-14 |
20130300432 | METHOD FOR TESTING MASK ARTICLES - A method for testing a mask article includes the steps of electrically connecting the mask article to an electrical sensor, applying a bias voltage to a plurality of testing sites of the mask article with a conductor, measuring at least one current distribution of the testing sites with the electrical sensor, and determining the quality of the mask article by taking the at least one current distribution into consideration. | 2013-11-14 |
20130300433 | METHOD FOR TESTING MASK ARTICLES - A method for testing a mask article includes steps of electrically connecting the mask article to an electrical sensor, applying a bias voltage to a plurality of testing sites of the mask article with a conductor, measuring at least one current distribution of the testing sites with the electrical sensor, and determining the quality of the mask article by taking the at least one current distribution into consideration. | 2013-11-14 |
20130300434 | METHOD FOR TESTING MASK ARTICLES - A method for testing a mask article includes steps of electrically connecting the mask article to an electrical sensor, applying a bias voltage to a plurality of testing sites of the mask article with a conductor, measuring at least one current distribution of the testing sites with the electrical sensor, and determining the quality of the mask article by taking the at least one current distribution into consideration. | 2013-11-14 |
20130300435 | Integrated Electric Field Sensor - An electric field sensor includes one or more sensing electrodes connected to an integrated amplifier that bootstraps all parasitic capacitances at the sensor input to provide for a very high input impedance without the need for neutralization or other adjustments and calibration. The integrated amplifier for the electric field sensor further includes low-noise ESD/biasing structures to stabilize the DC-potential of the sensor with a minimum amount of added noise, leakage and parasitic capacitance. | 2013-11-14 |
20130300436 | Stud Detector - A stud detector has a voltage source, a first device, and a second device. The first device serves to generate a voltage that is galvanically decoupled from the voltage source. The second device serves for the potential-free transmission of a control signal. | 2013-11-14 |
20130300437 | METHOD OF MEASURING A PHYSICAL PARAMETER AND ELECTRONIC INTERFACE CIRCUIT FOR A CAPACITIVE SENSOR FOR IMPLEMENTING THE SAME - A physical parameter is measured via an electronic circuit connected to a two capacitor sensor. The circuit includes an amplifier connected to the common capacitor electrode, a logic unit for digital processing amplifier data and supplying a digital measuring signal, a digital-analogue converter for supplying a measuring voltage based on the digital measuring signal, a switching unit for alternately supplying the measuring voltage to the first and second fixed capacitor electrodes, and a regulated voltage for negative biasing or a low voltage for positive biasing from a voltage supply source. A first phase consists in biasing the first fixed electrode with the measuring voltage from first binary word and reference voltage, and the second fixed electrode with low voltage, and a second phase consists in biasing the second fixed electrode with measuring voltage from second binary word, which is reverse of the first binary word, and the reference voltage. | 2013-11-14 |
20130300438 | Self-Capacitance Detection Using Trans-Conductance Reference - In one embodiment, a method includes modifying a voltage at a capacitance of a touch sensor to a first voltage level. The method also includes modifying the voltage at the capacitance to a second voltage level, resulting in a first current. The method also includes modifying a voltage at an integration capacitor to a charging-voltage level based on the first current. The method also includes determining whether a touch input to the touch sensor has occurred based on the charging-voltage level. | 2013-11-14 |
20130300439 | SYSTEM AND METHOD OF SENSING ACTUATION AND RELEASE VOLTAGES OF AN INTERFEROMETRIC MODULATOR - A method for sensing the actuation and/or release voltages of a electromechanical system or a microelectromechanical device include applying a test pulse to the device and sensing its state. In one embodiment, the device is part of a system comprising an array of interferometric modulators suitable for a display. The method can be used to compensate for temperature dependent changes in display pixel characteristics. | 2013-11-14 |
20130300440 | CAPACITIVE TOUCH SENSOR AND FABRICATION METHOD THEREOF AND CAPACITIVE TOUCH PANEL - A capacitive touch sensor includes multiple first-axis traces, multiple second-axis traces, an insulation layer and multiple metal traces. Each first-axis trace includes multiple first touch-sensing pads and first connecting lines connected therebetween. Each second-axis trace includes multiple second touch-sensing pads and second connecting lines connected therebetween. At least one of the first connecting line and the second connecting line is a metal printing line. | 2013-11-14 |
20130300441 | SUBSTANCE DETECTION SENSOR - A substance detection sensor includes an insulating layer; two electrodes spaced in opposed relation to each other on the insulating layer; and conductive layers formed between the two electrodes on the insulating layer so as to electrically connect the two electrodes, and of which a swelling ratio varies depending on the type and/or amount of a specific gas. The conductive layers are formed by dividing into plural layers between the two electrodes. | 2013-11-14 |
20130300442 | Chip Socket - The present document relates to chip sockets which for testing integrated circuit chips. A chip socket carries an integrated circuit chip comprising a plate for mounting onto a front side of a PCB, a plurality of electrical PCB connectors in a first area on a backside of the plate, wherein the plurality of electrical PCB connectors is adapted for electrically connecting the chip socket to a corresponding plurality of connectors on the PCB and a corresponding plurality of chip connectors on a front side of the plate, wherein the plurality of chip connectors is electrically connected to the plurality of electrical PCB connectors respectively; wherein the plurality of chip connectors connect the chip socket to a corresponding plurality of connectors of the integrated circuit chip, wherein the plate comprises a recess at its backside. | 2013-11-14 |
20130300443 | MODULATED TEST MESSAGING FROM DEDICATED TEST CIRCUITRY TO POWER TERMINAL - The present disclosure describes a novel method and apparatus for using a device's power and ground terminals as a test and/or debug interface for the device. According to the present disclosure, messages are modulated over DC voltages applied to the power terminals of a device to input test/debug messages to the device and output test/debug messages from the device. The present disclosure advantageously allows a device to be tested and/or debugged without the device having any shared or dedicated test or debug interface terminals. | 2013-11-14 |
20130300444 | BURN IN BOARD, SYSTEM, AND METHOD - Systems, methods, and apparatuses are provided for facilitating the use of a burn in board comprising integrated circuits. An apparatus may comprise a burn in board and a plurality of integrated circuits connected to the burn in board. Each integrated circuit may be configured to at least connect to a plurality of components to be subjected to a burn in process at room temperature; receive at least one signal for testing the plurality of components during the burn in process; and transmit the at least one signal to each of the plurality of components. Corresponding systems and methods are also provided. | 2013-11-14 |
20130300445 | VARIABLE SPACING FOUR-POINT PROBE PIN DEVICE AND METHOD - A continuous variable spacing probe pin device, including first and second probe pins. The first and second probe pins are configured to measure a property of a conductive layer. In a first configuration, the first and second probe pins include respective first portions arranged to contact the conductive layer to measure the property. In a second configuration, the first and second probe pins include respective second portions arranged to contact the conductive layer to measure the property. A first area for each respective first portion is different from a second area for each respective second portion. | 2013-11-14 |
20130300446 | CHUCKS FOR SUPPORTING SOLAR CELL IN HOT SPOT TESTING - In an embodiment, a chuck to support a solar cell in hot spot testing is provided. This embodiment of the chuck comprises a base portion and a support portion disposed above the base portion. The support portion is configured to support the solar cell above the base portion and to define a cavity between a bottom surface of the solar cell and the base portion that thermally separates a portion of the bottom surface of the solar cell from the base portion. | 2013-11-14 |
20130300447 | MANUFACTURING METHOD FOR ELECTRONIC COMPONENT, INSPECTION METHOD FOR ELECTRONIC COMPONENT, SHEET SUBSTRATE, ELECTRONIC COMPONENT, AND ELECTRONIC APPARATUS - A manufacturing method for an electronic component includes arranging, across boundaries of a first substrate region, wires for electrically connecting a piezoelectric resonator element arranged in the first substrate region and a lid arranged in a second substrate regions to a sheet substrate, performing, after arranging the piezoelectric resonator element and the lid in the substrate regions, input and output of a signal to and from the piezoelectric resonator element via the lid connected to the wires, and dividing the sheet substrate in each of the boundaries. | 2013-11-14 |
20130300448 | TESTING METHOD AND TESTING DEVICE FOR PHOTOELECTRIC CONVERSION DIE - A testing device includes a laser source, a current testing device, and a processor. The processor includes a user interface, a control unit, a calculation unit, and a data generation unit. The user interface receives user inputs to determine control parameters. The control unit controls the laser source to emit a laser beam on a photoelectric conversion die according to the control parameters. | 2013-11-14 |
20130300449 | Solar Power Generation System, Abnormality Detection Method, and Abnormality Detection System - In order to provide a system which detects and classifies abnormality in a solar battery even during power generation, an output voltage and an output current of the solar battery during power generation are detected, and a solar battery characteristic equation and a threshold value for detecting an abnormal state are calculated using the detected voltage value and current value and the measurement data of an external environment measurement unit. The kind of abnormal state of the solar battery is classified using the calculation result of the characteristic equation and the threshold value. | 2013-11-14 |
20130300450 | TEST DEVICE AND TEST SYSTEM OF SEMICONDUCTOR DEVICE AND TEST METHOD FOR TESTING SEMICONDUCTOR DEVICE - A test device of a semiconductor device for testing a semiconductor device including a plurality of interface pads includes a plurality of coupling units, each configured to be coupled to a corresponding one of the plurality of interface pads, a channel configured to be coupled to the plurality of coupling units, a voltage generating unit configured to generate a test voltage applied to the channel, and a current measuring unit configured to measure a current that flows on the channel in response to the test voltage. | 2013-11-14 |
20130300451 | EVALUATING TRANSISTORS WITH E-BEAM INSPECTION - A test structure of a semiconductor wafer includes a series of electrical units connected electrically in series output-to-input in an open loop configuration. The series of electrical units is configured to have alternating output voltages, such that each electrical unit is configured to output a voltage opposite an output voltage of a preceding electrical unit. Each electrical unit is configured to have an output voltage that alternates when an input voltage applied to a first electrical unit in the series of electrical units alternates. | 2013-11-14 |
20130300452 | INSTRUMENT FOR MEASURING LED LIGHT SOURCE - A LED light source measuring instrument includes a shell portion and a test portion. The shell portion supports the test portion. The test portion includes a carrier plate for carrying a LED light source, and provides automatic electrical connections to a bottom surface of an SMT LED light source. The test portion further includes a flexible tube and a vacuum pump, at least one air hole set in the test portion, the flexible tube connecting with the air hole and the vacuum pump, the vacuum provided by the vacuum pump holding the LED light source firmly to the under test zone of the carrier plate. | 2013-11-14 |
20130300453 | FUEL DISPENSER INPUT DEVICE TAMPER DETECTION ARRANGEMENT - A system for detecting unauthorized removal or tampering. The system comprises a printed circuit board having tamper-response electronics and a flexible circuit assembly defining a connector portion, a switch portion, and a cable extending between the connector portion and the switch portion. The flexible circuit assembly is coupled with the printed circuit board at the connector portion. The flexible circuit assembly comprises a plurality of layers each comprising a flexible dielectric substrate and a switch disposed in the switch portion. The switch is in electrical communication with the tamper-response electronics of the printed circuit board via a conductive path. The flexible circuit assembly also comprises a tamper-responsive conductor circuit enclosing the conductive path. The tamper-responsive conductor circuit is in electrical communication with the tamper-response electronics of the printed circuit board. | 2013-11-14 |
20130300454 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT WITH MICRO CIRCUITS AND POST PROCESSING - A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. Additionally, post processing may be performed on GDS layers to provide a realistic fill of the empty space so as to resemble structural elements found in a functional circuit. | 2013-11-14 |
20130300455 | MULTIPLE SIGNAL FORMAT OUTPUT DRIVER WITH CONFIGURABLE INTERNAL LOAD - A multiple signal format output driver is configurable to provide a current-mode logic (CML) output signal in response to a CML value of one or more first values of the control signal. The output driver is configurable to provide a low-power, low-voltage positive emitter-coupled logic (low-power LVPECL) output signal in response to a low-power LVPECL value of the one or more first values of the control signal. The output driver is configurable to provide a low-voltage differential signaling (LVDS) output signal in response to an LVDS value of the one or more first values of the control signal. The output driver may be configurable to provide a LVPECL output signal in response to a second value of the control signal. The output driver may be configurable to provide a high-speed current steering logic (HCSL) output in response to a third value of the control signal. | 2013-11-14 |
20130300456 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR DEVICE - Provided is a semiconductor chip for a programmable logic device which can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. Further, a semiconductor device using the semiconductor chip is provided. The semiconductor chip can hold configuration data even when supply of a power supply potential is interrupted and can operate with low power. The semiconductor chip includes a transistor and a pad connected to the transistor. The transistor is formed using a material which allows a sufficient reduction in off-state current of the transistor; for example, an oxide semiconductor material that is a wide bandgap semiconductor. | 2013-11-14 |
20130300457 | NON-BINARY DECODER ARCHITECTURE AND CONTROL SIGNAL LOGIC FOR REDUCED CIRCUIT COMPLEXITY - A decoder for sequentially enabling outputs in response to clock signal inputs is described including X number of logic stages corresponding to X number of outputs of the decoder. Each of the logic stages has a plurality of inputs, wherein each logic stage includes fewer than log | 2013-11-14 |
20130300458 | Clock Signal Synchronization Circuit - A circuit for detecting a time skew, including: at least two comparators; a first set of paths respectively connecting a first source of a first signal to said comparators; and a second set of paths respectively connecting a second source of a second signal to said comparators, each comparator detecting a possible skew between said first and second signals. | 2013-11-14 |
20130300459 | KEY PRESS DETECTING CIRCUIT AND METHOD FOR DETECTING THE STATUS OF MULTIPLE KEYS THROUGH A SINGLE PIN - A key press detecting circuit and method detect the status of multiple keys through a single pin. In an embodiment, a constant current is provided to apply to a key module through a single pin, to generate a voltage at the single pin that is related to the equivalent resistance of the key module observed from the single pin, and the voltage of the single pin is compared with a set of reference values to identify the status of the plurality of keys. In another embodiment, a variable current is provided to apply to a key module through a single pin in such a way that the variable current is adjusted to maintain a constant voltage at the single pin, and the variable current is compared with a set of reference values to identify the status of the plurality of keys. | 2013-11-14 |
20130300460 | METHOD AND SYSTEM FOR SIGNAL SYNTHESIS - The invention describes methods and systems for digital synthesis of electric signals. According to the invention, one or more bit-patterns are provided, each indicative of a rectangular waveform having a characteristic frequency. Further to determining a selected signal frequency to be synthesized, a selected bit-pattern associated therewith is obtained. Bits of the selected bit-pattern are cyclically serialized to generate a substantially rectangular waveform signal comprising the characteristic frequency. Then, the signal is filtered to suppress spurious frequencies outside a certain unfiltered frequency band which corresponds to the selected bit-pattern to thereby obtain a filtered signal with prominent frequency component corresponding to the selected signal frequency. | 2013-11-14 |
20130300461 | POWER SWITCH DRIVING CIRCUITS AND SWITCHING MODE POWER SUPPLY CIRCUITS THEREOF - In one embodiment, a power switch driving circuit can include: (i) a first circuit configured receiving a control signal, and controlling a first transistor gate, where a first transistor source is coupled to a power supply, and a first transistor drain is coupled to a driving signal configured to control a power switch; (ii) a second circuit configured to receive the control signal, and to control a second transistor gate, where a second transistor source is coupled to ground, and a second transistor drain is coupled to the driving signal; and (iii) a driving enhancement circuit having a third transistor and a first inverter that is configured to invert an output of the first circuit to control a third transistor gate, where a third transistor source is coupled to the driving signal, and a third transistor drain is coupled to the power supply. | 2013-11-14 |
20130300462 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - To reduce power consumption, a semiconductor device includes a power source circuit for generating a power source potential, and a power supply control switch for controlling supply of the power source potential from the power source circuit to a back gate of a transistor, and the power supply control switch includes a control transistor for controlling conduction between the power source circuit and the back gate of the transistor by being turned on or off in accordance with a pulse signal that is input into a control terminal of the control transistor. The power source potential is intermittently supplied from the power source circuit to the back gate of the transistor, using the power supply control switch. | 2013-11-14 |
20130300463 | Method and Apparatus for Monitoring Timing of Critical Paths - An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyser circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values. | 2013-11-14 |
20130300464 | METHOD OF CONTROLLING A SWITCHED MODE POWER SUPPLY AND CONTROLLER THEREFOR - A controller for an SMPS is disclosed. The controller applies a frequency jitter to the SMPS to reduce Electromagnetic Interference (EMI) and/or audible noise. A second input variable is multiplied by a correlated jitter signal, in order to compensate the output power for the frequency jitter. A corresponding method is also disclosed. Since the jitter compensation occurs within the controller, the method is particularly suitable for controllers operating under different control modes for different output powers (or other output criteria). The multiplicative compensation is applicable across a wide range of converter types. | 2013-11-14 |
20130300465 | SYSTEMS AND METHODS OF SIGNAL SYNCHRONIZATION FOR DRIVING LIGHT EMITTING DIODES - System and method for signal synchronization. The system includes a first selection component, a first signal generator, a second signal generator and a first gate drive component. The first selection component is configured to receive a first mode signal and generate a first selection signal based on at least information associated with the first mode signal. The first signal generator is configured to, if the first selection signal satisfies one or more first conditions, receive a first input signal and generate at least a first clock signal based on at least information associated with the first input signal. Furthermore, the first gate drive component is configured to, if the first selection signal satisfies the one or more first conditions, receive at least the first clock signal and output a first drive signal to a first switch. | 2013-11-14 |
20130300466 | SYSTEM AND METHOD FOR SYNCHRONIZING A LOCAL CLOCK WITH A REMOTE CLOCK - A system for synchronizing a first clock and a second clock includes a receiver associated with the first clock, configured to receive a remote pulse from the second clock. The remote pulse has a pulse repetition frequency and spectral characteristics that are known to the local clock. The system also includes a local pulse emitter configured to create a local pulse at the first clock, and optics configured to align the local pulse and the remote pulse. The system further includes an interferometer configured to create an interference pattern between the local pulse and the remote pulse. A controller is provided that is configured to calculate a time delay between the first clock and the second clock based on the interference pattern between the local pulse and the remote pulse. | 2013-11-14 |
20130300467 | HIGHER-ORDER PHASE NOISE MODULATOR TO REDUCE SPURS AND QUANTIZATION NOISE - A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function. | 2013-11-14 |
20130300468 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor device including an integrator circuit, in which electric discharge from a capacitor can be reduced to shorten time required for charging the capacitor in the case where supply of power supply voltage is stopped and restarted, and a method for driving the semiconductor device are provided. One embodiment has a structure in which a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit. Further, in one embodiment of the present invention, a transistor with small off-state current is electrically connected in series to a capacitor in an integrator circuit; the transistor is on in a period during which power supply voltage is supplied; and the transistor is off in a period during which supply of the power supply voltage is stopped. | 2013-11-14 |
20130300469 | INPUT JITTER FILTER FOR A PHASE-LOCKED LOOP (PLL) - An input jitter filter for a phase-locked loop and methods of use are provided. The method includes generating a masking zone around falling edges of a feedback signal. The method also includes determining that one or more outputs of a phase detector fall within the masking zone. The method further includes ignoring input clock noise when the one or more outputs of the phase detector fall within the masking zone. | 2013-11-14 |
20130300470 | Low Jitter Clock Generator for Multiple Lanes High Speed Data Transmitter - The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input. | 2013-11-14 |
20130300471 | PHASE-LOCKED LOOP CIRCUIT - A phase-locked loop (PLL) circuit is provided. The PLL circuit includes a phase frequency detector (PFD), a first charge pump (CP), a second CP, a first loop component set, a second loop component set, a voltage control oscillator (VCO) and a frequency divider. The first CP and the second CP are coupled to the PFD. The first loop component set is coupled between the first CP and the VCO. The second loop component set is coupled between the second CP and the VCO. The frequency divider is coupled between the PFD and the VCO. The first loop component set generates an offset current to adjust the working range of the first CP and the second CP. The second loop component set generates an offset current and a DC adjustment voltage to control the control voltage outputted to the VCO. | 2013-11-14 |
20130300472 | METHOD FOR SYNCHRONIZING SAMPLING TO SINUSOIDAL INPUTS - A method for synchronizing input sampling to desired phase angles of sinusoidal signals including determining a delay time period for converging a next sample point to a next desired phase angle based on a phase error value. | 2013-11-14 |
20130300473 | PHASE-LOCKED LOOP (PLL) FAIL-OVER CIRCUIT TECHNIQUE AND METHOD TO MITIGATE EFFECTS OF SINGLE-EVENT TRANSIENTS - A PLL fail-over circuit technique and method to mitigate the effects of single-event transients comprises providing a pair of substantially identical phase-locked loops and producing a respective delayed clock signal from each. The outputs of the phase-locked loops are monitored for errors comprising high frequency transients or differences in clock signal outputs from a reference frequency. A clock out signal is output representative of the first delayed clock signal if an error is detected in the second phase-locked loop and the second delayed clock signal is output if an error is detected in the first phase-locked loop. | 2013-11-14 |
20130300474 | DELAY-LOCKED LOOP AND METHOD FOR A DELAY-LOCKED LOOP GENERATING AN APPLICATION CLOCK - A delay-locked loop includes a first delay unit, a second delay unit, a third delay unit, a phase detector, and a controller. The first delay unit generates a first delay clock according to a clock and a first delay time. The second delay unit generates a second delay clock according to the first delay clock and a second delay time. The third delay unit generates a third delay clock according to the second delay clock and a third delay time. The phase detector generates a phase detection signal according to the clock and the second delay clock. The controller generates and outputs a phase control signal according to the phase detection signal. The second delay unit and the third delay unit adjust the second delay time and the third delay time respectively according to the phase control signal. | 2013-11-14 |
20130300475 | LOW POWER, JITTER AND LATENCY CLOCKING WITH COMMON REFERENCE CLOCK SIGNALS FOR ON-PACKAGE INPUT/OUTPUT INTERFACES - Low power, jitter and latency clocking with common reference clock signals for on-package input/output interfaces. A filter phase locked loop circuit in a master device on a first die provides a clock signal having a frequency of 2F. A local phase locked loop circuit in the master device on the first die is coupled with the filter phase locked loop to provide a clock signal to functional components of the master device through a local clock divider circuit to provide a clock signal of F to the functional components. A remote phase locked loop circuit in a slave device on a second die is coupled with the filter phase locked loop to provide a clock signal to one or more functional components of the slave device through a local clock divider circuit to provide a clock signal of F to the functional components. | 2013-11-14 |
20130300476 | LOW NOISE AND LOW POWER VOLTAGE CONTROLLED OSCILLATORS - LC tank and ring-based VCOs are disclosed that each include a differential pair of transistors for steering a tail current generated by a current source responsive to a bias voltage. A biasing circuit generates the bias voltage such that a transconductance for the transistors in the differential pairs is inversely proportional to a resistance. | 2013-11-14 |
20130300477 | SEMICONDUCTOR DEVICE - A semiconductor device includes a controlled oscillator and a control unit. The controlled oscillator includes a resonance circuit, an amplification unit, and a current adjustment unit. The resonance circuit includes one or a plurality of inductors and a first capacitive unit having a variable capacitance value. The amplification unit is connected to the resonance circuit, and outputs a local oscillation signal having an oscillation frequency corresponding to a resonance frequency of the resonance circuit. The current adjustment unit adjusts a value of a drive current to be supplied to the amplification unit. The control unit controls the capacitance value of the first capacitive unit and the current adjustment unit. When the control unit instructs the current adjustment unit to change the value of the drive current to be supplied to the amplification unit, the control unit also changes the capacitance value of the first capacitive unit. | 2013-11-14 |
20130300478 | Method and Associated Apparatus for Clock-Data Edge Alignment - An edge alignment apparatus includes: a signal source, for generating a first and a second square wave signals; a phase delay circuit, for receiving the first and the second square wave signals to generate a delayed first and a delayed second square wave signals; a data circuit, for generating a third square wave signal according to the delayed second square wave signal; and a phase calibrating circuit, for receiving the third square wave signal and the delayed first squared wave signal to generate at least one phase tuning signal to the phase delay circuit for tuning a phase difference between the delayed first and the delayed second square wave signals, such that a signal edge of the third square wave signal aligns with that of the first square wave signal. The first, second and third square wave signals have a same frequency. | 2013-11-14 |
20130300479 | METHOD AND DEVICE FOR GENERATING SHORT PULSES - There is described a method and corresponding pulse generating device, for generating an output pulse signal having an output pulse duration. The method comprises: receiving at an input port an input pulse signal comprising an input pulse duration; duplicating the input pulse signal into a first digital pulse signal and a second digital pulse signal each comprising the input pulse duration; delaying at least one of the first and the second digital pulse signals by a time delay to obtain respectively a first and a second delayed digital pulse signal, a time delay difference between the first and the second delayed digital pulse signals being substantially equal to the output pulse duration; logically combining the first and the second delayed digital pulse signals to generate the output pulse signal with the output pulse duration smaller than the input pulse duration; and outputting the output pulse signal at an output port. | 2013-11-14 |
20130300480 | DATA OUTPUT CIRCUIT AND DATA OUTPUT METHOD THEREOF - A data output circuit and a data output method thereof are provided. The data output circuit includes a delay locked loop, a duty ratio correction block, and an output unit. The delay locked loop corrects a duty ratio of a first internal clock. The delay locked loop includes a correction enable signal output unit configured to output a correction enable signal when the operation of correcting the duty ratio of the first internal clock is completed. The duty ratio correction block corrects the duty ratio of the first internal clock by using a duty ratio detection signal in response to the correction enable signal, and outputs the corrected first internal clock as an output clock. The output unit detects a duty ratio of the output clock, generates the duty ratio detection signal to the duty ratio correction block, and outputs a data strobe signal in response to the output clock. | 2013-11-14 |
20130300481 | EDGE SELECTION TECHNIQUES FOR CORRECTING CLOCK DUTY CYCLE - Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit. | 2013-11-14 |
20130300482 | PARTIAL RESPONSE RECEIVER AND RELATED METHOD - A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sampled bit to represent the input signal. A first storage circuit coupled to an output of the first multiplexer circuit stores the first sampled bit in response to a first clock signal. A second multiplexer circuit selects one of the sampled signals as a second sampled bit to represent the input signal based on the first sampled bit. A second storage circuit stores a sampled bit selected from the sampled signals in response to a second clock signal. A time period between the second storage circuit storing a sampled bit and the first storage circuit storing the first sampled bit is substantially greater than a unit interval in the input signal. | 2013-11-14 |
20130300483 | METHODS AND DEVICES RELATING TO TIME-VARIABLE SIGNAL PROCESSING - Time-Mode Signal Processing (TMSP) offers a means for offsetting some of the challenges for analog circuit designs when exploiting CMOS circuit processes designed for digital applications. It would therefore be beneficial to provide a digital method for the storage, addition and subtraction of Time-Mode variables as these offer significant benefit to providing TMSP techniques and expanding their exploitation within devices, systems, and applications. Whilst driven by CMOS process challenges the TM circuits outlined may exploit essentially any digital circuit technology since they are based upon delay. The inventors present an approach to TM variables wherein a switched delay unit is exploited and adopted such that the instantaneous phase difference between two rising signal edges can be latched and used to perform various arithmetic operations. Beneficially, the technique allows analog sampled-data signal processing to be implemented within digital circuitry. | 2013-11-14 |
20130300484 | OFFSET-COMPENSATED ACTIVE LOAD AND METHOD - In accordance with an embodiment, an offset-compensated active load includes a pair of transistors having control electrodes connected to their drain electrodes through coupling devices. The control electrodes of the transistors are connected to each other through a plurality of charge storage elements. In accordance with another embodiment, an offset current is generated in response to coupling input terminals of an input stage together. The offset current flows towards an active load which generates an offset voltage in response to the offset current. The offset voltage is stored in the plurality of charge storage devices of the offset-compensated active load. | 2013-11-14 |
20130300485 | APPARATUS AND METHOD FOR HIGH VOLTAGE SWITCHES - Apparatus and method for coupling high voltages for a semiconductor device via high voltage switches are disclosed. A high voltage switch includes a switch and a level shifter. The switch is defined between a voltage source and a voltage output. An enable line is coupled to a first transistor of the switch. The level shifter includes an input and an output. A characterization line is coupled to the input of the level shifter and the output of the level shifter is coupled to a second transistor of the switch. The level shifter further includes a power rail that is coupled to the switch between the first transistor and the second transistor. | 2013-11-14 |
20130300486 | REDUCED DELAY LEVEL SHIFTER - A circuit comprising a first input transistor having a drain, a source and a gate. A first diode connected transistor having a drain, a source and a gate, wherein the gate of the first diode connected transistor is coupled to the drain of the first diode connected transistor, and the drain of the first input transistor is coupled to the drain of the first diode connected transistor. A first load transistor having a drain, a source and a gate, wherein the drain of the first load transistor is coupled to the drain of the first diode connected transistor and the source of the first load transistor is coupled to the source of the first diode connected transistor. | 2013-11-14 |
20130300487 | SEMICONDUCTOR SWITCH - A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor. | 2013-11-14 |
20130300488 | Passive Offset and Overshoot Cancellation for Sampled-Data Circuits - A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase. | 2013-11-14 |
20130300489 | ADAPTABLE MIXER AND LOCAL OSCILLATOR DEVICES AND METHODS - An adaptable mixer device is operable in a first mode and a second mode and includes a first set of mixer units operable in the first mode and a second set of mixer units operable in the second mode. The second set of mixer units includes at least one mixer unit that is common to both the first set of mixer units and the second set of mixer units. The second set of mixer units also includes a plurality of mixer units that are not in the first set of mixer units. Similarly, the first set of mixer units including a plurality of mixer units that are not in the second set of mixer units. | 2013-11-14 |
20130300490 | RETURN-TYPE CURRENT-REUSE MIXER - A return-type current-reuse mixer having a transconductance/amplification stage, a mixing stage, and a high-pass and a low-pass filter network. The transconductance/amplification stage has a current-reuse CMOS topology wherein an input frequency signal is converted into a frequency current, low-frequency components are removed from the frequency current by the high-pass filter network, the frequency current is fed into the mixing stage, modulation occurs in the mixing stage, and then an intermediate-frequency signal is generated and output. Once high-frequency components are removed from the intermediate-frequency signal by the low-pass filter network, the intermediate-frequency signal is sent again for input into the transconductance/amplification stage, then amplified in the transconductance/amplification stage and output. The mixer transconductance/amplification stage employs a current-reuse technique. The input frequency and the output intermediate-frequency signal share a common transconductance/amplification stage. The mixer reduces power consumption, simplifies the circuit topology, and provides high conversion gain. | 2013-11-14 |
20130300491 | Subsea Power Switching Device and Methods of Operating the Same - It is described a switching device comprising a semiconductor switching unit; a contactor electrically coupled in series with the semiconductor switching unit; and a controller being configured for activating an electrically isolating state of the switching device and/or activating an electrically conducting state of the switching device based on a command signal or based on a comparison of a measured value and predetermined activation condition. | 2013-11-14 |
20130300492 | SWITCHING POWER CAPABLE OF AVOIDING COUPLING EFFECTS - A switching power capable of avoiding coupling effects is provided. The switching power comprises a driving loop. The driving loop comprises the substrate end and the gate end of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a controlling gate, and the controlling gate is connected to the gate end of the power MOSFET and the substrate end of the power MOSFET is connected to the controlling gate. The switching power provided by the present can avoid the coupling effect of the driving loop and the power stage loop at the common source pin, thereby reducing the switching power losses and improving the efficiency of the switching power. | 2013-11-14 |
20130300493 | ANALOG SWITCHING CIRCUIT, ASSOCIATED CONTROL CIRCUIT AND METHOD - The present invention discloses an analog switching circuit having a first terminal receiving an input signal, a second terminal providing an output signal and a control terminal receiving a switching control signal. The analog switching circuit has a first logic circuit providing a first control signal and a second control signal based on the switching control signal; an NMOS and a PMOS coupled between the first terminal and the second terminal, and controlled by the first control signal and the second control signal respectively; a first control circuit controls the backgate voltage of the NMOS based on the input signal and the switching control signal; and a second control circuit controls the backgate voltage of the PMOS based on the input signal and the switching control signal. | 2013-11-14 |
20130300494 | OUTPUT CIRCUIT - An output circuit includes a current source and a first MOS transistor coupled in series between a power supply terminal and an output terminal. The first MOS transistor includes a backgate coupled to a drain of the second MOS transistor. The second MOS transistor includes a source coupled to a source of a third MOS transistor. The second MOS transistor includes a source coupled to backgates of the second and third MOS transistors. The backgates of the second and third MOS transistors are in a floating condition. | 2013-11-14 |
20130300495 | CHARGE PUMP CIRCUIT AND METHOD FOR GENERATING A SUPPLY VOLTAGE - A charge pump circuit ( | 2013-11-14 |
20130300496 | INTERNAL VOLTAGE GENERATING CIRCUIT - An internal voltage generating circuit may include a first pull up resistor activated by a first range signal and connected between a pull up voltage terminal and a pull up common node; a second pull up resistor activated by a second range signal and connected between the pull up voltage terminal and the pull up common node; a first pull down resistor activated by the first range signal and connected between a pull down voltage terminal and a pull down common node; a second pull down resistor activated by the second range signal and connected between the pull down voltage terminal and the pull down common node; a resistor string including a plurality of series resistors connected between the pull up common node and the pull down common node; and a voltage selection circuit select voltage in response to voltage selection information. | 2013-11-14 |
20130300497 | RECONFIGURABLE INTEGRATED CIRCUIT - A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals. | 2013-11-14 |
20130300498 | METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR LOW POWER MULTIMODE INTERCONNECT FOR LOSSY AND TIGHTLY COUPLED MULTI-CHANNEL - Methods, systems, and computer readable media for low power multimode interconnect for lossy and tightly coupled multi-channel are disclosed. According to one aspect, a system for low power multimode interconnect includes a receiver for receiving a plurality of input signals that have been encoded by a multimode encoding equation to have voltage levels according to the multimode encoding equation and for decoding the received signals according to a multimode decoding equation to produce binary data as output, wherein the receiver includes a set of frequency-compensated amplifiers for emphasizing high-frequency components of the received input signals and a set of latches for receiving amplified signals from the frequency-compensated amplifiers and for decoding the amplified signals according to the multimode decoding equation to produce binary data as output. | 2013-11-14 |
20130300499 | PROGRAMMABLE WIDE-BAND RADIO FREQUENCY FEED NETWORK - The programmable wide-band radio frequency feed network is a wideband multi-port microwave/RF feed network that can operate with multiple communication bands covering a wide frequency range. In addition, the feed network is programmable via a digital controller and has two degrees of freedom, viz., amplitude and phase variations. The feed network provides amplification as well as attenuation to the amplitude of the incoming signals. The feed network is designed using discrete microwave components, and fabricated on a multilayer printed circuit board (PCB) with a small footprint. The digitally controlled feed network is ideal for any antenna array application within the covered frequency range, and can be re-programmed for various wireless communication standards. | 2013-11-14 |
20130300500 | METHOD AND APPARATUS FOR FILTER-LESS CLASS D AUDIO AMPLIFIER EMI REDUCTION - An audio system includes a speaker and a class D amplifier with a class-D PWM (pulse width modulation) modulator configured for generating first and second PWM signals, each with three differential output levels. The class-D amplifier also has a differential output driver configured for driving a first and a second output signals onto a first and a second output terminals in response to the first and the second PWM signals, wherein each of the first and the second output signals has three differential output levels. An inverse common-mode signal generator is coupled to first and second output signals for providing an inverse common-mode signal. The audio system also includes one or more output terminals for providing the inverse common mode signal, and further includes a wire or a trace on a PCB (printed circuit board) inverse common mode signal. | 2013-11-14 |
20130300501 | BANDWIDTH EXTENSION OF AN AMPLIFIER - An amplifier may include a gain stage configured to convert an input voltage signal to a current signal and to amplify the input voltage signal according to a gain. The amplifier may also include a buffer stage coupled to the gain stage at an internal node. The buffer stage may be configured to convert the current signal to an output voltage signal and to buffer the current signal from the gain stage so that a frequency bandwidth of the amplifier may be approximately maintained when the gain of the gain stage is increased. | 2013-11-14 |
20130300502 | VARIABLE-GAIN LOW NOISE AMPLIFIER - The present disclosure relates to variable-gain low noise amplifiers and RF receivers. An exemplary method for processing a RF signal provides a low noise amplifier with main and auxiliary amplifier modules. When a selection indicates the low noise amplifier operating in a high-gain mode, the main and auxiliary amplifier modules are coupled in parallel. When the selection indicates the low noise amplifier operating in a low-gain mode, the main and auxiliary amplifier modules are cross coupled. When a selection indicates the low noise amplifier operating in a moderate-gain mode, the auxiliary amplifier modules are disconnected from the main amplifier module. | 2013-11-14 |