46th week of 2008 patent applcation highlights part 58 |
Patent application number | Title | Published |
20080282050 | Methods and arrangements for controlling memory operations - In one embodiment, a method for operating a memory management system concurrently with a processing pipeline is disclosed. The memory management system can fetch and effectively load registers to reduce stalling of the pipeline because the disclosed system provides improved data retrieval as compared to traditional systems. The method can include storing a memory request limit parameter, receiving a memory retrieval request from a multi-processor system to retrieve contents of a memory location and to place the contents in a predetermined location. The method can also include determining a number of pending memory retrieval requests, and then processing a new retrieval request if the number of pending memory retrieval requests is at or below the memory request limit parameter. | 2008-11-13 |
20080282051 | Methods and arrangements for controlling results of memory retrival requests - In one embodiment, a method for operating a memory management system concurrently with a processing pipeline is disclosed. The method can include requesting data from a memory retrieval system utilizing a retrieval request, where the memory retrieval system can provide memory contents to a processing pipeline. In addition, an instruction can be processed by the processing pipeline, possibly a conditional instruction, that/which makes the retrieval request obsolete. The instruction can be associated with the identifier such that retrieve data from the memory can be associated with an instruction. The method can determine if the retrieval request is obsolete based on the results of processing of the instruction and the loading of the retrieved data into the pipeline can be forgone in response to determining that the retrieval request is obsolete. | 2008-11-13 |
20080282052 | Operating Media Devices in Pre-Os Environment - According to one embodiment, a method for initializing a plurality of media devices in communication with a computing device; mapping information corresponding to each initialized media device to a plurality of memory locations of the computing device; and operating the initialized media devices based on the mapped information corresponding to each operated media device while the computing device is in a pre-OS environment. According to another embodiment a system comprising a plurality of media devices in communication with a computing device and adapted for initialization by the computing device; and a memory mapping logic adapted to map information corresponding to the initialized media devices to a plurality of memory locations in a system memory of the computing device, wherein the computing device is adapted to operate the initialized media devices based on the mapped information corresponding to each operated media device while the computing device is in a pre-OS environment. | 2008-11-13 |
20080282053 | METHOD FOR CONVERTING MEMORY ADDRESSES OF DIFFERENT PROGRAMMABLE LOGIC CONTROLLERS CONNECTED TO HUMAN-MACHINE INTERFACE - A method converts the memory addresses of different programmable logic controllers (PLC) connected to human-machine interface (HMI). The PLCs of different specifications are associated with different memory addresses. The memory address data corresponding to PLCs with various specifications is first established in HMI. A mapping condition is checked for the memory type and memory size for the PLC with different specification. A mapping relationship is established when the mapping condition is satisfied and data is automatically sent to the memory area of the new PLC. | 2008-11-13 |
20080282054 | SEMICONDUCTOR DEVICE HAVING MEMORY ACCESS MECHANISM WITH ADDRESS-TRANSLATING FUNCTION - A pseudo-physical address is used for accessing a memory from a CPU (Central Processing Unit). One of function blocks that is needed for the current application program is selected based on the pseudo-physical address, and the pseudo-physical address is translated to a real physical address by the selected function block. There are provided parallel lines of memory access functions extending from the CPU, whereby it is possible to perform an optimal memory access transaction for each application program, and it is possible to improve the memory access performance without lowering the operation frequency and without increasing the number of cycles required for a memory access. | 2008-11-13 |
20080282055 | Virtual Translation Lookaside Buffer - A virtual page number lookup request is received at a virtual Translation Lookaside Buffer (TLB), wherein the virtual TLB includes an instruction TLB and a data TLB. A lookup of the virtual page number in the virtual TLB is performed. A physical page number corresponding to the virtual page number in the virtual TLB is returned. | 2008-11-13 |
20080282056 | Hardware memory management unit simulation - Various technologies and techniques are disclosed for concurrently performing address translation data lookups for use by an emulator. On a first thread, a first lookup is performed for address translation data for use by an emulator. On a second thread, a second lookup for the address translation data is concurrently and speculatively performed. The address translation data from a successful lookup from either the first lookup or the second lookup is used to map a simulated physical address to a virtual address of the emulator. For example, the first thread can perform a translation lookaside buffer lookup while the second thread concurrently and speculatively performs a page table entry lookup for the address translation data. | 2008-11-13 |
20080282057 | Database Heap Management System With Variable Page Size and Fixed Instruction Set Address Resolution - A heap management system for a database uses “sets” of pages to store database information. As memory for each successive set of pages is allocated, more memory is allocated for storing rows in each page of the set. Similarly, the maximum number of rows of information storable in each page of each set is greater for each successive set of pages. The number of computer instructions needed to resolve (or calculate) the memory address for a particular row is fixed. Given a target row number, (and the number of rows in the first page, and the width of the column or column group), only a fixed number of computer instructions need to be executed to resolve the starting memory address for the target row. In addition, information of the same type (i.e., one or more columns of a table) may be stored in different pages, and these pages may be located in discontiguous memory segments. This allows space for new rows to be allocated, without requiring all pre-existing rows to be moved to a different memory segment. | 2008-11-13 |
20080282058 | Message queuing system for parallel integrated circuit architecture and related method of operation - An integrated circuit comprises an external memory, a plurality of parallel connected Vector Processing Engines (VPEs), and an External Memory Unit (EMU) providing a data transfer path between the VPEs and the external memory. Each VPE contains a plurality of data processing units and a message queuing system adapted to transfer messages between the data processing units and other components of the integrated circuit. | 2008-11-13 |
20080282059 | METHOD AND APPARATUS FOR DETERMINING MEMBERSHIP IN A SET OF ITEMS IN A COMPUTER SYSTEM - A method and apparatus for maintaining membership in a set of items to be used in a predetermined manner in a computer system. A representation of each member of the set is mapped into a number of components of a primary and secondary vector when a member is added to the set. Periodically, the primary vector is changed to the secondary vector and the secondary vector to the primary vector. When members of the set are deleted, the components of the secondary vector are changed to indicate deletion of these members after the primary vector is changed to the secondary vector. Finally, membership in the set is determined by examining the components in the primary vector, and the members in the set of items are then used in a predetermined manner in the computer system. More specifically, in a sample embodiment of the present invention, membership in the set would determine if data is to be stored or removed from cache memory in a computer system. This invention, for example, provides a low cost and high performance mechanism to phase out aging membership information in a prefeteching mechanism for caching data or instructions in a computer system. | 2008-11-13 |
20080282060 | ACTIVE MEMORY COMMAND ENGINE AND METHOD - A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also generated by the command engine, and the ACU command include instruction memory addresses corresponding to an address in an array control unit where processing array instructions are stored. | 2008-11-13 |
20080282061 | Array Type Operation Device - An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction. | 2008-11-13 |
20080282062 | Method and apparatus for loading data and instructions into a computer - A computer array ( | 2008-11-13 |
20080282063 | METHODS AND APPARATUS FOR LATENCY CONTROL IN A MULTIPROCESSOR SYSTEM - Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated with at least one of the sub-processors, and each being operable to alter a delay of data transfer at least one of into and out of its associated sub-processor in order to alter one or more latencies associated with the paths on the ring bus between pairs of the sub-processors. | 2008-11-13 |
20080282064 | System and Method for Speculative Thread Assist in a Heterogeneous Processing Environment - A system and method for speculative assistance to a thread in a heterogeneous processing environment is provided. A first set of instructions is identified in a source code representation (e.g., a source code file) that is suitable for speculative execution. The identified set of instructions are analyzed to determine the processing requirements. Based on the analysis, a processor type is identified that will be used to execute the identified first set of instructions based. The processor type is selected from more than one processor types that are included in the heterogeneous processing environment. The heterogeneous processing environment includes more than one heterogeneous processing cores in a single silicon substrate. The various processing cores can utilize different instruction set architectures (ISAs). An object code representation is then generated for the identified first set of instructions with the object code representation being adapted to execute on the determined type of processor. | 2008-11-13 |
20080282065 | Image forming apparatus and control method for the same - An image forming apparatus includes a job-history managing unit that creates and manages a job history, registers a job history, as a job history instance, containing an operation code that instructs a series of job operations to be executed and also containing an operating condition of the job operation, and that registers a macro instance which can be interpreted by other image forming apparatuses and is encoded to an executable shared code. The image forming apparatus also includes an interpreter unit that reads the job history instance, encodes the operation code to the shared code, and registers the shared code as the macro instance. | 2008-11-13 |
20080282066 | Compact instruction set encoding - The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is operable to determine three four-bit operand elements from the remaining eleven bits of the input, the three operand elements each having one of twelve possible binary values. The operand decoding logic is operable to decode an encoded group of the eleven bits to determine a first part of each of the three operand elements, and to read verbatim a verbatim group of the eleven bits to determine a second part of each of the three operand elements. | 2008-11-13 |
20080282067 | Issue policy control within a multi-threaded in-order superscalar processor - A multi-threaded in-order superscalar processor | 2008-11-13 |
20080282068 | HOST COMMAND EXECUTION ACCELERATION METHOD AND SYSTEM - The present invention sets forth an interface method and system for host acceleration between an electronic device and a host PC. The system comprises an acceleration unit for rapidly classifying a type of an host command then issuing a flag signal to a microprocessor. The microprocessor then executes corresponding actions according to the flag signal and the host command without parsing the host command for accelerating the data communication between the device and a host PC. | 2008-11-13 |
20080282069 | METHOD AND SYSTEM FOR DESIGNING A FLEXIBLE HARDWARE STATE MACHINE - Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor. | 2008-11-13 |
20080282070 | SIMD ARITHMETIC DEVICE CAPABLE OF HIGH-SPEED COMPUTING - A general-purpose register file including a plurality of general-purpose registers stores parallel arithmetic data. A plurality of pattern registers store a plurality of items of pattern data indicating the rearrangement of data in bytes, in half words, in words, or in a combination of these units. A data select circuit selects one of the items of pattern data stored in the plurality of pattern registers according to specifying data included in an instruction. A rearranging circuit rearranges parallel arithmetic data according to the item of pattern data selected by the data select circuit. | 2008-11-13 |
20080282071 | Microprocessor and register saving method - A microprocessor which realizes fast register saving and restoring which are involved in subroutine calls, and is capable of reducing the scale of a program. A register file is provided with at least one register for storing data to be used for computational processing. A saving memory stores therein data saved from the registers. A saving control unit saves data from a writing destination register to the saving memory when an instruction to write to the register is executed in a subroutine. Then the saving control unit restores data saved in the saving memory back to the original registers when an instruction to return from the subroutine is executed. | 2008-11-13 |
20080282072 | Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table - A computer system is disclosed which includes a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received. | 2008-11-13 |
20080282073 | Comparing text strings - A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null terminated string may be detected. The shorter strings may be handled differently than longer strings. | 2008-11-13 |
20080282074 | METHOD OF OPTIMIZING PERFORMANCE OF MULTI-CORE CHIPS AND CORRESPONDING CIRCUIT AND COMPUTER PROGRAM PRODUCT - A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a V | 2008-11-13 |
20080282075 | Controlling circuit for communication port - A controlling circuit for a communication port having a ring indicator (RI) pin is provided. The controlling circuit includes a first selection circuit and a second selection circuit. The first selection circuit is controlled by a basic input/output system (BIOS) for determining whether an RI signal is transmitted to the RI pin. The second selection circuit is controlled by the BIOS for determining whether a first voltage or a second voltage is transmitted to the RI pin. | 2008-11-13 |
20080282076 | INFORMATION PROCESSING DEVICE - Abstract An information processing device, including: a processing unit; a peripheral circuit module; and a boot address register, wherein the information processing device comprises a first operation mode and a second operation mode having an operating current which is lower than that of said first operation mode, wherein the boot address register holds an address of an instruction to be executed by said processing unit first when the boot address register returns from said second operation mode to said first operation mode, wherein the address is output from said boot address to the processing unit when said information processing device shifts from said second operation mode to said first operation mode. | 2008-11-13 |
20080282077 | APPARATUS, METHOD AND PROGRAM PRODUCT FOR INITIATING COMPUTER SYSTEM OPERATION - A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS. | 2008-11-13 |
20080282078 | GATEWAY DEVICE, CONTROLLING METHOD OF THE SAME, AND PROGRAM RECORD MEDIUM STORING CONTROLLING METHOD - A method of controlling a gateway device includes the steps of converting a plain text mail received from a client device to an encrypted mail; transmitting the encrypted mail to a mail transmission server; and notifying a transmission error to the client device when the transmission error occurs between the gateway device and the mail transmission server is provided. | 2008-11-13 |
20080282079 | System and method for ad-hoc processing of cryptographically-encoded data - The present disclosure provides a system and method for ad-hoc processing of cryptographically-encoded data. In one embodiment, a recipient receives a cryptographically-encoded email and proceeds to contact a processing server to decrypt said cryptographically-encoded email. The recipient may interact with the server either by copying-and-pasting the content of the cryptographically-encoded email to a web interface provided by the processing server or by forwarding it to the processing server using his existing email software. In the case of the forward, the processing server sends yet another email back to the recipient containing a URL to a web interface for continuing to interact with the processing server in order to decrypt the cryptographically-encoded email. Through its web interface, the processing server guides the recipient through the steps required to view a decrypted version of the cryptographically-encoded email. | 2008-11-13 |
20080282080 | Method and apparatus for adapting a communication network according to information provided by a trusted client - Hosts connecting to the network implement an adaptive networks client that monitors other applications on the host and provides information to an adaptive networks server to provide information about traffic being generated by the host. The client may also capture information about the user, host, access type, and other information of interest. The information provided by the adaptive network client may allow the network to adapt to the user, the device, the application, and the protocol being used. Users and applications can be authenticated and trusted. From a network standpoint, having a trusted client associated with the host allows the same benefits as deep packet inspection, regardless of whether the traffic is encrypted, and without requiring the network elements to actually perform deep packet inspection. The administrator may also centrally apply policy to control which applications are allowed to run on the hosts. | 2008-11-13 |
20080282081 | MUTUALLY AUTHENTICATED SECURE CHANNEL - A system and methods for establishing a mutually authenticated secure channel between a client device and remote device through a remote access gateway server. The remote access gateway server forwards secure connection requests and acknowledgements between the client and the remote device such that the remote access gateway does not possess any or all session keys necessary to decrypt communication between the client device and remote device. | 2008-11-13 |
20080282082 | NETWORK COMMUNICATION DEVICE - A disclosed network communication device corresponds to IP communications and is capable of performing IPsec communication. The network communication device includes a setting unit configured to obtain and set an operation mode specified by an administrator user; a detecting unit configured to detect a communication error caused by an incorrect portion in an IPsec setting; and a changing unit configured to change the IPsec setting, based on the operation mode set by the setting unit, to correct the incorrect portion or to cancel the IPsec communication, in the event that the communication error is detected. | 2008-11-13 |
20080282083 | METHOD AND SYSTEM FOR CONTROLLED MEDIA SHARING IN A NETWORK - A method for controlling media sharing among a plurality of nodes in a network. The present method is comprised of availing to the network an instance of media content for sharing among the plurality of nodes by a source node communicatively coupled to the network. The present method further includes decrypting the instance of media content from an encryption local to the source node. The present method further includes encrypting the instance of media content into an intermediate encryption. The present method further includes transferring the instance of media content to a node while the instance of media content is in the intermediate encryption. The node is associated with the network. The decrypting and the encrypting and the transferring are in response to receiving a request for the instance of media content from the node. | 2008-11-13 |
20080282084 | METHODS AND APPARATUS FOR SECURE OPERATING SYSTEM DISTRIBUTION IN A MULTIPROCESSOR SYSTEM - Methods and apparatus provide for: decrypting a first of a plurality of operating systems (OSs) within a first processor of a multiprocessing system using a private key thereof, the plurality of OSs having been encrypted by a trusted third party, other than a manufacturer of the multiprocessing system, using respective public keys, each paired with the private key; executing an authentication program using the first processor to verify that the first OS is valid; and executing the first OS on the first processor. | 2008-11-13 |
20080282085 | Method to Search for Affinities Between Subjects and Relative Apparatus - A method to search for affinities between subjects comprises the passages of effecting a step of registering a user with a certification authority ( | 2008-11-13 |
20080282086 | Method and Apparatus for Protecting Information and Privacy - A system for protecting software against piracy while protecting a user's privacy enables enhancements to the protection software in a user device and extended protections against piracy. The protection system allows the user device to postpone validation of purchased tags stored in a tag table for installed software and to re-establish ownership of a tag table to recover from invalidation of a tag table identifier value resulting from revelation of a tag table identifier value. Continued use of the tag table is provided by the use of credits associated with a tag table. A protection center is protected against denial of service attacks by making calls to the protection center cost time or money to the attackers. | 2008-11-13 |
20080282087 | System debug and trace system and method, and applications thereof - An embedded system or system on chip (SoC) includes a secure JTAG system and method to provide secure on-chip control, capture, and export of on chip information in an embedded environment to a probe. In one embodiment, the system comprises encryption logic associated with a JTAG subsystem and decryption logic in the probe for encrypted JTAG read traffic. Inverted encryption/decryption logic provides bi-directional encryption and decryption of JTAG traffic. Encrypted information includes both authentication of valid probe/target interface and encryption of debug data. | 2008-11-13 |
20080282088 | AUTHENTICATED NONVOLATILE MEMORY SIGNING OPERATIONS - A wireless device includes a nonvolatile memory that handles the task of securely performing integrity checks that do not expose the authentication private key externally. The system security architecture installs and associates private keys with the nonvolatile memory to create a secure execution environment resistant to virus attack. The nonvolatile memory provides integrity checks of nonvolatile memory data and generates signatures for data provided by the memory. | 2008-11-13 |
20080282089 | Signature Generation Apparatus and Signature Verification Apparatus - A signature generation apparatus and a signature verification apparatus which can prevent the occurrence of norm zero vector forgery attack. The signature generation apparatus ( | 2008-11-13 |
20080282090 | Virtual Property System for Globally-Significant Objects - Virtual property system for globally-significant objects across autonomous computing environments. Objects with global persistence and identity are instantiated by a plurality of their real-world claim-holders through authentication of a computer-readable object specification and owner identity. Owner may then claim benefit of the object across autonomous computing environments such as virtual worlds by authenticating his identity. Ownership transfer is accomplished through the current owner authenticating an ownership transfer document. When used in conjunction with the owner-proxy method, object transfer may occur without the distribution of ownership revocation lists. | 2008-11-13 |
20080282091 | Systems and Methods of Securing Resources Through Passwords - Disclosed is a method of authorizing access to an item that maintains a lockout count and blocks access to the item if the lockout count exceeds a predetermined value. One feature is that the invention “variably” increments the lockout count if the presented password fails to exactly match the stored password. In this process the invention increments the lockout count different amounts depending upon how closely the presented password matches the stored password. The invention also provides a methodology that allocates a plurality of the same passwords to a plurality of users who share the same userid. The invention allows continuous operation of the item being accessed by providing that each of the passwords has a different expiration date. Also, when dealing with situations where a plurality of users who share the same userid also share the same password, the invention maps information associated with the users to the password in a data file and periodically updates the data file. | 2008-11-13 |
20080282092 | Card reading apparatus with integrated identification function - A card reading apparatus integrating identification function is provided, including a USB interface, a memory card interface, an ATA/ATAPI interface, a USB OTG controller, an identification interface module, an encrypted identification processor, and at least an identification device. The USB interface, the memory card interface, and the ATA/ATAPI interface are connected respectively to a USB interface media device, a flash memory card, and a data storage device, such as hard disk or CD-RW. The USB OTG controller is connected to the USB interface, the memory card interface, and the ATA/ATAPI interface so that the USB interface media device, the flash memory card, and the data storage device can exchange data under the control of the USB OTG controller. The identification interface module is connected to the USB OTG controller, the encrypted identification processor is connected to the identification interface module, and the identification device is connected to the encrypted identification processor. Therefore, the identification device can use fingerprint, other biological identification data or magnetic card to transmit the identification data to the encrypted identification processor. The results from the encrypted identification processor are used to enable and disable the USB OTG controller so that the stored data can be protected by encrypted identification function. | 2008-11-13 |
20080282093 | METHODS AND APPARATUS FOR SECURE PROGRAMMING AND STORAGE OF DATA USING A MULTIPROCESSOR IN A TRUSTED MODE - Methods and apparatus provide for: entering a secure mode in which a given processor may initiate a transfer of information into or out of said processor, but no external device may initiate a transfer of information into or out of said processor; and programming at least one trusted data storage location using a direct memory access (DMA) command to be one of read-only, write-only, readable and writeable, limited access, and reset, where said at least one trusted data storage location is located external to said processor. | 2008-11-13 |
20080282094 | Optical storage media and the corresponding cryptography for data encryption thereof - Based on the demand of developing a data encryption technique for the optical storage media, the present invention discloses a cryptography for data encryption based on a design of specific hardware conditions, so as to achieve the security requirements for the encrypted digital data stored in the optical storage media and the design requirements for the security issues on the optical storage media for software vendors in the current market. | 2008-11-13 |
20080282095 | METHOD FOR TRANSFERRING AND/OR PROVIDING PERSONAL ELECTRONIC DATA OF A DATA OWNER - In a method to transfer and/or to provide personal electronic data of an owner, in particular health-related electronic data of a patient, the personal electronic data are transferred and/or provided in a form stored on a data medium, at least partially encrypted, together with at least one decryptor for at least partial decryption, as well as at least one mechanism to present and/or to access and/or to enable the presentation of and/or the access to at least one part of the personal electronic data. | 2008-11-13 |
20080282096 | SYSTEM AND METHOD FOR ORDER-PRESERVING ENCRYPTION FOR NUMERIC DATA - A system, method, and computer program product to automatically eliminate the distribution information available for reconstruction from a disguised dataset. The invention flattens input numerical values into a substantially uniformly distributed dataset, then maps the uniformly distributed dataset into equivalent data in a target distribution. The invention allows the incremental encryption of new values in an encrypted database while leaving existing encrypted values unchanged. The flattening comprises (1) partitioning, (2) mapping, and (3) saving auxiliary information about the data processing, which is encrypted and not updated. The partitioning is MDL based, and includes a growth phase for dividing a space into fine partitions and a prune phase for merging some partitions together. | 2008-11-13 |
20080282097 | METHOD FOR INDICATING A POWER SWITCH OF A COMPUTER AND DEVICE THEREOF - A device for indicating the power switch of a computer is disclosed in the invention, which is applied in portable computers and indicates the position of a power switch of a portable computer when the computer is in shutdown status. The portable computer comprises at least a monitor and a main system, wherein an indicating device is also disposed in the portable computer; the indicating device includes a detecting unit, an illuminating element, and a controller. The detecting unit detects whether the monitor and the main system have been unclosed and separated from each other; if the detection result is “true”, a trigger signal is exported. The illuminating element is disposed in the proximity of the power switch on the portable computer. The controller accepts the trigger signal and adjusts the illumination of the illuminating element. | 2008-11-13 |
20080282098 | Semiconductor memory device and error correction method therof - A semiconductor memory device comprising: a memory array having a data area and a check code area; refresh control means which controls a refresh operation in a data holding state; operation means which executes an encoding operation for generating the check code using a bit string in the data area, and executes a decoding operation for performing the error detection/correction of the data using the check code; encode control means for controlling an encode process in which in a change to the data holding state, a first and second code are written in the check code area; and decode control means for controlling a decode process in which at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively. | 2008-11-13 |
20080282099 | INFORMATION PROCESSING APPARATUS AND POWER SAVING CONTROL METHOD - According to one embodiment, an information processing apparatus includes a sound controller which reproduces a sound signal, and a sound driver which controls a drive of the sound controller. The sound driver includes a volume full-mute determination unit which determines whether or not the apparatus is set in a volume full-mute state of making zero sound output volume, and a control unit which determines whether or not the apparatus is set in a volume full-mute state by using the volume full-mute determination unit when a sound signal reproduce request is made while the sound controller has transferred to a power saving mode, and maintains the sound controller in a power saving mode when the apparatus is set in a volume full-mute state. | 2008-11-13 |
20080282100 | INTEGRATED CIRCUIT WITH POWER CONTROL AND POWER CONTROL METHOD THEREOF - Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal. | 2008-11-13 |
20080282101 | Optimum power management of system on chip based on tiered states of operation - Optimum power management of system on chip based on tiered states of operation is disclosed. In one embodiment, a system on chip includes a hardware module including one or more of a microcontroller, a microprocessor, a DSP core, a memory, a timing source, a peripheral, and an external interface to have a real time counter module of the peripheral isolated from a rest of the hardware module using a plurality of voltage level shifting cells and/or a plurality of voltage island cells. Also, the system on chip includes a software module associated with the real time counter module to generate one or more control signals to one or more devices external to the system on chip during a sleep mode of the system on chip. | 2008-11-13 |
20080282102 | Maintaining Optimum Voltage Supply To Match Performance Of An Integrated Circuit - Power supply voltage to an integrated circuit (IC) or a portion of an IC is maintained at an optimum level matching the IC performance. Voltage ranges and delay measures for corresponding operating frequencies are stored in tables in a voltage control block. When a new frequency of operation is desired, the voltage control block measures delay performance of the IC, and sets the supply voltage to a value specified in a corresponding entry in a table. The voltage control block then continues to measure delay performance, and dynamically adjusts the power supply voltage to an optimum value thereby minimizing power consumption. | 2008-11-13 |
20080282103 | Lightweight time change detection - A timer service uses a single timer function to perform timing services for both relative and absolute timers. The first timers from a sorted array of absolute timers and relative timers are used in a function that will return when the earliest absolute timer expires or will timeout when the earliest relative timer expires. The timer function may be interrupted when a new timer is added to one of the arrays. The function will operate in a predictable and consistent manner, even when a system clock is adjusted. | 2008-11-13 |
20080282104 | Self Healing Software - The systems and methods describe a self healing framework (SHF) that can monitor errors in a computing system and can resolve the errors and/or suggest methods for resolving the errors to a user based on a heuristic approach. In addition, the SHF can analyze errors that occurred in the past and can predict such occurrences in the future to help users take proactive actions against possible errors. | 2008-11-13 |
20080282105 | DATA INTEGRITY VALIDATION IN STORAGE SYSTEMS - Data validation systems and methods are provided. Data is recorded in N data chunks on one or more storage mediums. A first validation chunk independently associated with said N data chunks comprises first validation information for verifying accuracy of data recorded in said N data chunks. The first validation chunk is associated with a first validation appendix comprising second validation information, wherein the first validation appendix is stored on a first storage medium independent of said one or more storage mediums. | 2008-11-13 |
20080282106 | DATA STORAGE WITH INCREMENTAL REDUNDANCY - A method for operating a memory includes encoding input data with an Error Correction Code (ECC) to produce input encoded data including first and second sections, such that the ECC is decodable based on the first section at a first redundancy, and based on both the first and the second sections at a second redundancy that is higher than the first redundancy. | 2008-11-13 |
20080282107 | Method and Apparatus for Repairing Memory - Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit. | 2008-11-13 |
20080282108 | PROGRAM SYNTHESIS AND DEBUGGING USING MACHINE LEARNING TECHNIQUES - One embodiment is directed to synthesizing code fragments in a software routine using known inputs and corresponding expected outputs. A computer system provides a software routine with known inputs and corresponding expected outputs, infers software routine instructions based on the known inputs and corresponding expected outputs, and synthesizes a correctly functioning code fragment based on the inferred instructions. Another embodiment is directed to automatically resolving semantic errors in a software routine. A computer system provides the software routine with known inputs and corresponding expected outputs for portions of a program fragment where an error has been localized. The computer system learns a correctly functioning program fragment from pairs of input-output descriptions of the program fragment, determines the program statements that can transform given input states into given output states after execution of those program statements, and alters portions of the software routine with the learned program fragments. | 2008-11-13 |
20080282109 | Debugging system and debugging method - A debugging system includes an emulator connected via a communication line for two-way communication and a target device to be debugged by the emulator. The emulator includes a serial signal transmitting unit to transmit a control signal as serial data to the target device and an A/D converter to convert an analog signal into a digital signal and to output the digital signal, the analog signal is input from the target device via the communication line. The target device includes a trace circuit, a serial signal receiving unit to receive the serial data and a D/A converter to convert, in response to the control signal received, trace information into an analog signal, and to output the analog signal, the trace information is output by the trace circuit. | 2008-11-13 |
20080282110 | SCAN CLOCK ARCHITECTURE SUPPORTING SLOW SPEED SCAN, AT SPEED SCAN, AND LOGIC BIST - Herein described are at least a method and a system to perform scan testing of an integrated circuit chip using one or more internal and external clock sources. In a representative embodiment, the method comprises receiving at least one external clock signal and three control signals generated by an off-chip clock source, generating at least one internal clock signal from an on-chip clock source, and using the at least one external clock signal and the at least one internal clock signal by a logic circuitry to generate one or more scan test clocks to perform scan testing of one or more corresponding clock domains. In a representative embodiment, the system comprises at least one on-chip clock source and first and second circuitries for generating a scan test clock for a clock domain. | 2008-11-13 |
20080282111 | Worker thread corruption detection and remediation - A thread has a corruption detection mechanism that compares a beginning state of a function with an ending state to determine any inconsistencies. Based on the type of inconsistency, a remedial action may be taken, such as ignoring the inconsistency, cleaning up the inconsistency, and terminating the thread with an exception. The analysis may also include analyzing various states after function execution to find problems such as incomplete transactions. Such a thread may be useful in an operating system as well as a multi-threaded application environment. | 2008-11-13 |
20080282112 | Method and apparatus for testing request-response service using live connection traffic - The subject matter herein provides for a method and apparatus for comparison of network systems using live traffic in real-time. The inventive technique presents real-world workload in real-time with no external impact (i.e. no impact on the system under test), and it enables comparison against a production system for correctness verification. A preferred embodiment of the invention is a testing tool for the pseudo-live testing of CDN content staging servers, According to the invention, traffic between clients and the live production CDN servers is monitored by a simulator device, which then replicates this workload onto a system under test (SUT). The simulator detects divergences between the outputs from the SUT and live production servers, allowing detection of erroneous behavior. To the extent possible, the SUT is completely isolated from the outside world so that errors or crashes by this system do not affect either the CDN customers or the end users. Thus, the SUT does not interact with end users (i.e., their web browsers). Consequently, the simulator serves as a proxy for the clients. By basing its behavior off the packet stream sent between client and the live production system, the simulator can simulate most of the oddities of real-world client behavior, including malformed packets, timeouts, dropped traffic and reset connections, among others. | 2008-11-13 |
20080282113 | Failure information management method and apparatus, failure detection method and apparatus, electronic apparatus, information processing apparatus and computer-readable storage medium - A failure information management method manages failure information related to a replaceable part of an electronic apparatus, by generating an error log, and storing the error log in a non-volatile memory of the replacement recommended part itself. The error log is generated by recording first generation information in a representative log information part and detailed log information part in a non-overwritable manner with respect to a first failure of a replacement recommended part, and by recording second generation information in the representative log information part and the detailed log information part in an overwritable manner with respect to second and subsequent failures of the replacement recommended part. | 2008-11-13 |
20080282114 | METHOD TO ENHANCE MICRO-C4 RELIABILITY BY REDUCING THE IMPACT OF HOT SPOT PULSING - A system for reducing an impact of hot spot, pulsing of a semiconductor device including: first generating means for generating a plurality of local op-codes; a sequencer for augmenting customer op-codes with the plurality of local op-codes; selecting means for selecting one or more of the randomly arriving customer op-codes awaiting execution; monitoring means for tracking which of the one or more randomly arriving customer op-codes have been selected; separating means for separating the plurality of local op-codes from the one or more customer op-codes; storing means for storing one or more data related to the processing of the plurality of local op-codes and the customer op-codes; and second generating means for generating an output for a customer corresponding to that customer op-code while gainfully employing an output generated by local op-codes for system health monitoring purpose. | 2008-11-13 |
20080282115 | CLIENT-SERVER TEXT MESSAGING MONITORING FOR REMOTE COMPUTER MANAGEMENT - Implementation of a client-server text messaging (CSTM) monitor installed on a computer system that is configured to monitor a client-server text messaging (CSTM) server for commands posted thereto, and a management program installed on the computer system which is responsive to the commands. The CSTM monitor is lightweight and allows multiple computer systems to monitor a CSTM server and execute posted commands. Managed computer systems are more efficient because the management program does not run continuously. The commands are text-based and, therefore, require very little network bandwidth between a management system and the managed computer system. The invention allows a centralized computer management system to monitor managed computer systems and implement corrective measures without overburdening the systems or network bandwidth. | 2008-11-13 |
20080282116 | Transient Fault Detection by Integrating an SRMT Code and a Non SRMT Code in a Single Application - Disclosed is a method for running a first code generated by a Software-based Redundant Multi-Threading (SRMT) compiler along with a second code generated by a normal compiler at runtime, the first code including a first function and a second function, the second code including a third function. The method comprises running the first function in a leading thread and a tailing thread ( | 2008-11-13 |
20080282117 | METHODS, APPARATUS, AND SYSTEMS FOR INTEGRATED MANAGEMENT, GRAPHICS AND I/O CONTROL OF SERVER SYSTEMS - In one embodiment of the invention, a server system is disclosed for data processing having a printed circuit board with one or more processors to process data; a network interface controller coupled to the one or more processors; and a monolithic integrated circuit (IC) coupled to the one or more processors and the network interface controller. The network interface controller couples the server system to a network for remote client access to the server system. The monolithic integrated circuit couples a remote computer system to the server system via the network. The remote computer system includes a remote storage device, a remote display, a remote keyboard, and a remote mouse to allow remote control and management of the server system. | 2008-11-13 |
20080282118 | Highly Reliable Distributed System - The highly reliable distributed system is composed of a communication protocol processing unit which comprises a mailbox for storing a communication message, and executes communication protocol processing between data of an application program and a network controller using the network controller performing network communication of the message in the mailbox; an error detection coding unit; an error detection decoding unit which reconverts data converted from communication data by the error detection coding unit to the original data, and detects that the content of the data is damaged if it is damaged; and a data comparing unit for checking whether or not two kinds of data agree with each other. | 2008-11-13 |
20080282119 | MEMORY DEVICE AND BUILT IN SELF-TEST METHOD OF THE SAME - A memory device including, a nonvolatile memory which stores a step item, a parameter start address, and a parameter which has an address corresponding to the parameter start address and defines the step item, and a controller which performs, on the nonvolatile memory, a test step corresponding to the step item defined by the parameter, the controller being formed in the same chip as the nonvolatile memory. | 2008-11-13 |
20080282120 | Memory structure, repair system and method for testing the same - A memory structure is provided. The memory structure includes a memory array, an error correct code (ECC) unit, and a comparator. The memory array includes at least one memory cell being written and storing at least one original data. The ECC unit is for reading at least one tested data from the at least one memory cell, correcting the at least one tested data when there is an error occurred in the at least one tested data and outputting at least one ECC data accordingly. The comparator is for determining whether the at least one original data is substantially the same as the at least one ECC data or not and outputting an output signal indicating whether the at least one memory cell passes or fails. | 2008-11-13 |
20080282121 | Integrated Circuit and Test Method - An integrated circuit test controller and method defining a number N of failure events, applying the test to an integrated circuit under test by applying a predetermined sequence of input and output operations according to a test algorithm. Output data is compared to expected data, and a failure signal is generated when the output data does not correspond to the expected data. If a failure signal is generated, failure data related to the failure event is stored in a failure data register set. If the number N of failure events has been reached or if there are no more tests left, the content of the data failure register set is read out through a parallel failure data output port. | 2008-11-13 |
20080282122 | SINGLE SCAN CLOCK IN A MULTI-CLOCK DOMAIN - Herein described are at least a method and a system to perform scan testing of an integrated circuit chip. The integrated circuit chip is scan tested using only a single scan clock. The single scan clock is provided through a single pin on the integrated circuit chip. In a representative embodiment, the method comprises inputting a single scan clock, first shifting data into one or more flip-flops of one or more scan chains by clocking the data into one or more scan in (SI) inputs of the one or more flip-flops using the single scan clock, selectively clocking flip-flops of a clock domain, and second shifting data from said one or more flip-flops of said one or more scan chains. In a representative embodiment, the system comprises one or more clock domains and one or more clock domain scan test modules. | 2008-11-13 |
20080282123 | System and Method of Multi-Frequency Integrated Circuit Testing - A system and method of multi-frequency integrated circuit testing with a method for testing a clocked logic type integrated circuit including creating exerciser code on the integrated circuit when the integrated circuit is operating at a first frequency, switching the integrated circuit to operating at a second frequency greater than the first frequency, and running the exerciser code on the integrated circuit when the integrated circuit is operating at the second frequency. | 2008-11-13 |
20080282124 | Predictive run testing - A test object can be selectively included in a test run based on predicting the behavior of the test object. In one embodiment, the present invention includes predicting how likely the test object is to produce a failure in a test run and deciding whether to include the test object in the test run based on the predicted likelihood. This likelihood of producing a failure may be based on any number of circumstances. For example, these circumstances may include the history of prior failures and/or the length of time since the test object was last included in a test run. | 2008-11-13 |
20080282125 | Method and Apparatus for Combined Packet Retransmission and Soft Decoding of Combined Packets in a Wireless Communication Network - In a wireless communication network using point-to-point or point-to-multipoint communications, this disclosure teaches the use of combined packets for retransmission and corresponding soft value processing at a receiver, wherein combined packets are formed as the logical combination of two or more previously transmitted packets and allow the receiver to use a single combined packet to correct one or more failed packets. For example, with the combined packet retransmission and corresponding soft value receiver processing as taught herein, a given receiver can use a given combined packet to correct bit errors in all (failed) packets comprising the combined packet as long as the bit errors in a failed packet do not overlap (or align) with bit errors in the other failed packets comprising the combined packet. | 2008-11-13 |
20080282126 | ACKNOWLEDGMENTS OF NEGATIVE ACKNOWLEDGMENTS BY RELAY STATIONS AND MOBILE STATIONS - Various example embodiments are discloses. According to one example embodiment, a method may include sending a packet to both a relay station and a destination station in a wireless network, receiving a relay station acknowledgment (ACK) or negative acknowledgment (NACK) from the relay station during an ACK/NACK frame, and receiving a destination station ACK or NACK from the destination station during the ACK/NACK frame. The relay station ACK or NACK may either acknowledge or negatively acknowledge successful receipt of the packet by the relay station. The destination station ACK or NACK may either acknowledge or negatively acknowledge successful receipt of the packet by the destination station. | 2008-11-13 |
20080282127 | HYBRID AUTOMATIC REPEAT REQUEST SYSTEM AND METHOD - A data communication method for puncturing of parity bits defining all parity data for a minimum code rate generated by an encoder is disclosed. The method initializes an accumulator associated with the parity bits to an initial value, and for each parity bit increments the accumulator by a increment value and determines if the accumulator has overflowed. If the accumulator overflows, at least one of the parity bits is selected for transmission. | 2008-11-13 |
20080282128 | Method of Error Correction Code on Solid State Disk to Gain Data Security and Higher Performance - An electronic data storage device having a Reed Solomon (RS) decoder including a syndrome calculator block responsive to information including data and overhead and operative to generate a syndrome, in accordance with an embodiment of the present invention. The electronic data storage device further includes a root finder block coupled to receive said syndrome and operative to generate at least two roots, said RS decoder for processing said two roots to generate at least one error address identifying a location in said data wherein said error lies; and an erasure syndrome calculator block responsive to said information and operative to generate an erasure syndrome, said RS decoder responsive to said information identifying a disk crash, said RS decoder for processing said erasure syndrome to generate an erasure error to recover the data in said disk crash. | 2008-11-13 |
20080282129 | Operational parameter adaptable LDPC (Low Density Parity Check) decoder - Operational parameter adaptable LDPC (Low Density Parity Check) decoder. A novel means is presented by which LDPC coded signal can be decoded, and any one or more operational parameters can be adjusted during the decoding processing. For example, the original information extracted from a received LDPC coded signal (e.g., log likelihood ratios (LLRs)), can be modified during (or before) the iterative decoding processing performed in accordance with decoding an LDPC coded signal. Such modification of an operational parameter can include any one or combination of scaling, compression (and expansion/decompression), adding an offset to or subtracting an offset from, scaling, rounding, and/or some other modification of an operational parameter. The bit (or variable) edge messages and/or the check edge messages can also undergo modification during decoding processing. In addition, the operational parameter modification can be selective, in that, different modification can be performed to different parameters and/or during different decoding iterations. | 2008-11-13 |
20080282130 | DIGITAL BROADCASTING SYSTEM AND METHOD OF PROCESSING DATA - A digital broadcasting system and a data processing method are disclosed. Herein, additional encoding is performed on mobile service data, which are then transmitted, thereby providing robustness in the processed mobile service data, so that the mobile service data can respond more strongly against fast and frequent channel changes. The data processing method of a digital broadcast transmitting system includes the steps of forming a RS frame by grouping a plurality of mobile service data bytes that is being inputted, and performing error correction encoding in RS frame units, forming a super frame by grouping a plurality of the error correction encoded RS frame, performing row permutation in super frame units, and dividing the super frame back to RS frames, and dividing the RS frame into a plurality of data groups. | 2008-11-13 |
20080282131 | ERROR DETECTION CODE GENERATING METHOD AND ERROR DETECTION CODE GENERATOR - In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver. | 2008-11-13 |
20080282132 | Error Correcting Code | 2008-11-13 |
20080282133 | COOPERATIVE CONCATENATED CODING FOR WIRELESS SYSTEMS - Cooperative concatenated coding techniques are provided for wireless communications between at least two users and a base station. A network system employing cooperative concatenated coding includes cooperating user devices each configured to encode and transmit at least a portion of a joint message. The joint message includes at least a portion of a first message from a first cooperating user device and at least a portion of a second message from a second cooperating user device. An embodiment includes encoding a first message from a first cooperating user, receiving a second message from a second cooperating user and decoding the second message. The methodology also includes re-encoding at least a portion of the decoded message with at least a portion of the first message to form a combined message, and then transmitting at least a portion of the combined message. | 2008-11-13 |
20080282134 | Methods and Apparatus for Detection of Performance Conditions in Processing System - Techniques are disclosed for detection of performance conditions in processing systems. For example, a method of detecting a performance condition in at least one particular processing device of a processing system having a plurality of processing devices includes the following steps. Data is input to a data structure associated with the particular processing device, over a given time period. The input data may be a buffer or a bucket. The input data represents data associated with the execution of at least one function performed by the particular processing device. The given time period includes the time period between consecutive heartbeat signals transmitted by the particular processing device. At least a portion of the input data is removed from the data structure associated with the particular processing device, near the end of the given time period. The removed input data is compared to an expected function execution level. An alarm signal is generated, when warranted, based on the comparison of the removed input data to the expected function execution level such that a performance condition in the particular processing device is determinable. | 2008-11-13 |
20080282135 | PARITY GENERATOR, PRIORITY ENCODER, AND INFORMATION PROCESSOR - In order to generate a parity of output data from a priority encoder without increasing processing time or making the circuitry complex, the present invention a first level generator having a plurality of first component circuits arranged in parallel, into each of which one of a plurality of sets of a specific number of bits of the binary data in sequence from the most significant bit is input and each of which generates and outputs a first signal for parity generation of bit data of the specific number of bits and a second signal representing whether or not the entire bit data of the specific number of bits is “0s” or “1s”; and a second level generator generating the parity of the binary data based on the first signal and the second signal from each of said first component circuits of said first level generator. | 2008-11-13 |
20080282136 | Parity generation circuit, counter circuit, and counting method - A circuit outputs, upon receipt of data and a parity of the data, count information on the number of bits in the data represented as a base-n number (n: a natural number equal to or larger than 2) and the parity of the count information. The circuit includes a determining unit and an inverting unit. The determining unit determines that the number of bits in the data represented as a base-n number is a specific value. The inverting unit outputs, as the parity of the count information, any one of a value of the parity of the data and an inverted value of the parity depending on a result of determination by the determining unit. | 2008-11-13 |
20080282137 | ERROR DETECTION CODE GENERATING METHOD AND ERROR DETECTION CODE GENERATOR - In a mobile communication system, an error detection code or a quality frame indicator (e.g., CRC) is generated using selectively frame information, and at least one of a WCA identifier of another terminal, and a corresponding terminal identifier. And the terminal identifier can be implicitly transmitted to the receiver. | 2008-11-13 |
20080282138 | METHODS AND SYSTEMS FOR MULTIMEDIA OBJECT ASSOCIATION TO DIGITAL PAPER SPATIAL DIAGRAMS - Methods and systems for multimedia object association to digital paper spatial diagrams are disclosed herein. A method for multimedia object association to digital paper spatial diagrams includes the steps of (1) capturing a media object to be imported into a spatial information system; (2) linking the captured media object to a digital paper document containing a spatial diagram, using a input device configured to select a linking action area located in a first area of the digital paper document and configured to select a location for the captured multimedia data object on a second area of the digital paper document; (3) transferring the media object and the data from the input device to a spatial information system; and (4) combining the media object and the data of the input device to create an updated digital paper document containing the media object. | 2008-11-13 |
20080282139 | Tree view for reusable data markup language - Methods and systems provide a “tree view” for a markup language referred to as Reusable Data Markup Language (“RDML”). Generally, a tree view comprises the components necessary for automatically manipulating and displaying a graphical display of numerical data contained in RDML markup documents. RDML is a markup language, such as the Hypertext Markup Language (“HTML”) or the Extensible Markup Language (“XML”). Generally, RDML facilitates the browsing and manipulation of numbers, as opposed to text as in HTML, and does so by requiring attributes describing the meaning of the numbers to be attached to the numbers. Upon receiving RDML markup documents, the tree view transforms, formats, manipulates and displays data stored in the markup documents using the attributes describing the meaning of the data. The tree view uses the attributes of the numbers to, for example, facilitate the simultaneous display of different series of numbers of different types on a single display. It automatically displays the relationship between series of numbers while displaying appropriate labels, titles, number precision, etc. A tree view may be a component of a data viewer used to retrieve, manipulate, and view documents in the RDML format. | 2008-11-13 |
20080282140 | EMBEDDED WEBSITE BANNER SYSTEM AND METHOD - A system and method for providing a website involve a novel way of porting a full website through an ad banner. A user viewing a website including the ad banner interacts with the ad banner. The ad banner then expands and the ported website is viewed in the expanded ad banner as covering over the first website. The user's perception does not include the experience of being redirected to another website. The method and system for providing this website are described herein. | 2008-11-13 |
20080282141 | System for creating a reusable list, saving it in a clipboard, and accessing a current document version by selecting a hyperlink on the list - A computer system that allows a user to select one or more of the documents that are listed in a summary view of documents and creates a list of the selected documents. Advantageously, for each selected document, the list includes document summary data pertaining to the selected document and a hyperlink to the selected document. | 2008-11-13 |
20080282142 | Rendering a User Interface - There is provided a user interface which is defined by a plurality of actors and the attributes) that are associated with the actors. A renderer is used to render the user interface in accordance with the attributes of the actors. Changes in actor attributes, for example in response to a keypress, cause the user interface to be updated. | 2008-11-13 |
20080282143 | Document Processing Device and Document Processing Method - A document processing apparatus that allows a structured document to be appropriately processed is provided. | 2008-11-13 |
20080282144 | Structured Document Bounding Language - Using a bounding language to control or restrict the changes that can be made to contents of a structured document (e.g., a document encoded in the Extensible Markup Language, or “XML”), and also the bounding language and documents encoded according to the bounding language. A Document Type Definition (“DTD”) is defined as a “bounding DTD”, and one or more structured documents containing editing restrictions are defined according to this DTD. A processing component uses a structured document containing editing restrictions as input, and programmatically determines which fields of another structured document can be edited, which fields should be hidden, and so forth. By restricting the parts of the file that can be edited, users who need to do the editing are shielded from irrelevant details, and can carry out their task with less risk of making errors (and without needing to understand the details of the structured document markup language). | 2008-11-13 |
20080282145 | METHOD AND SYSTEM FOR EFFECTIVE SCHEMA GENERATION VIA PROGRAMMATIC ANALYSIS - A method to generate an effective schema of an electronic document for optimizing the processing thereof may include performing a programmatic analysis to determine all required portions of the electronic document. The method may also include generating a parser or deserializer to build an optimized document model; and specializing a document processing program against the optimized document model. | 2008-11-13 |
20080282146 | TEXT DISPLAY DEVICE - Presented is a device for aiding in reading comprehension which includes a display unit with a first position and a second position. The most recently read text is typically displayed on the right hand side of the display unit and the recently read text is displayed on the left hand page. | 2008-11-13 |
20080282147 | Constraint and rule-based page layout - Technologies are described herein for laying out content. Constraints and rules are defined for one or more content objects. The constraints are utilized to lay out content objects on a canvas. Content is received for one of the content objects. The constraints and rules for the content object are utilized in an attempt to fit the content to the selected content object. If the content cannot be fit to the selected content object, the rules are utilized to modify the constraints for the other content objects and the layout for the canvas is regenerated. If the available content cannot be fit to the content objects on a page without overflowing, one or more additional pages are added to the canvas. Once the additional pages have been added, the content objects are laid out and content is fitted to the content objects across all of the pages. | 2008-11-13 |
20080282148 | PROCESSING METHOD FOR INCREASING SPEED OF OPENING A WORD PROCESSING DOCUMENT - A processing method for increasing speed of opening a word processing document includes: reading a data content of a word processing document; reading typeset information of a page stored in the word processing document and obtaining paragraph information and object information of the page; according to the paragraph information and object information of the page, loading the data content of the page, generating and displaying the typeset content. The processing method performs reading of the typeset information of a document and the conventional data contents at the same time. | 2008-11-13 |
20080282149 | Automated Paragraph Layout - Methods and apparatus for calculating paragraph layout. A method begins with a first node in a paragraph and calculates an optimal line break scheme for paragraph layout that ended in the node. For every subsequent node in the paragraph, the method calculates an optimal line break scheme for paragraph layout that ends respectively in every subsequent node. Each optimal line break scheme is calculated by minimizing the total of a penalty value of a current line and all preceding penalties of all preceding lines. The preceding penalties of all preceding lines are defined by a previously calculated optimal line break scheme. | 2008-11-13 |