45th week of 2012 patent applcation highlights part 18 |
Patent application number | Title | Published |
20120280666 | METHOD AND APPARATUS FOR A CONTROL CIRCUIT RESPONSIVE TO AN IMPEDANCE COUPLED TO A CONTROL CIRCUIT TERMINAL - A method, in a power supply controller, of responding to an increase in current through a terminal of the power supply controller, is disclosed. The method includes regulating the terminal to a first voltage level and sensing a magnitude of a first current through the terminal while the controller is regulating the terminal to the first voltage level. The method also includes providing an initial response by the power supply controller in response to the magnitude of the first current exceeding a first threshold current level and then regulating the terminal to a second voltage level after the magnitude of the first current exceeds the first threshold current level. The magnitude of a second current through the terminal is sensed while the controller is regulating the terminal to the second voltage level and the controller determines a final response based on the magnitude of the second current. | 2012-11-08 |
20120280667 | Flexible load current dependent feedback compensation for linear regulators utilizing ultra-low bypass capacitances - The present document relates to low-dropout (LDO) regulators having low output capacitance. The regulator comprises a differential amplification stage configured to amplify a differential voltage between a reference voltage and a measure of the output voltage, thereby yielding a drive current at an output of the amplification stage; a subsequent output amplification stage configured to provide the regulated output voltage and a output current at an output of the output amplification stage, based on a drive voltage at an input of the output amplification stage; and a first output current feedback loop configured to sense the output current; and feed back a first coupling current derived from the sensed output current to a first intermediate point between the output of the differential amplification stage and the input of the output amplification stage; wherein the drive voltage is dependent on the drive current and the first coupling current. | 2012-11-08 |
20120280668 | POWER SUPPLY CONTROL APPARATUS - A power supply control apparatus includes an output transistor coupled between a first power supply line and an output terminal, the output terminal being configured to be coupled with a load, a discharge transistor coupled between a gate of the output transistor and the output terminal, and rendered conductive when the output transistor is brought into a non-conduction state, a negative voltage control unit coupled between the first power supply line and the gate of the output transistor, and bringing the output transistor into a conduction state when the counter electromotive voltage applied to the output terminal from the load exceeds a predetermined value, a diode having a cathode coupled with the first power supply line, and an anode, a third resistor provided between the anode of the diode and a second power supply line, and a compensation transistor coupled between the second power supply line and the output terminal. | 2012-11-08 |
20120280669 | DYNAMIC CONTROL OF FREQUENCY COMPENSATION FOR IMPROVED OVER-VOLTAGE PROTECTION IN A SWITCHING REGULATOR - An error amplifier includes a difference amplifier providing an error signal representing a difference in voltage between a feedback signal and a reference signal. The error amplifier further includes a compensation circuit limiting the rate of change of the error signal. The compensation circuit includes a switch that when activated effectively removes a circuit portion from the compensation circuit. A switch signal indicates for the switch to be activated when the feedback signal exceeds the reference signal by a predefined amount. | 2012-11-08 |
20120280670 | OFF-LINE CONVERTER WITH DIGITAL CONTROL - A power converter includes an input and an output. A regulation circuit is coupled between the power converter input and the power converter output. The regulation circuit is coupled to receive a feedback signal representative of the power converter output. The feedback signal has a first feedback state that represents a level at the power converter output that is above a threshold level and a second feedback state that represents a level at the power converter output that is below the threshold level. An oscillator is included in the regulation circuit that provides an oscillation signal that cycles between two states. The regulation circuit is coupled to be responsive to the oscillation signal and to a change between the first and second feedback states to enable or disable a flow of energy from the power converter input to the power converter output. | 2012-11-08 |
20120280671 | On-time Control Module and On-time Control Method - The present invention discloses an on-time control module for compensating a switching frequency in a switching regulator. The on-time control module includes an average voltage generating circuit, for generating an average voltage related to a duty according to an input voltage and the duty, and an on-time controller, for generating a control signal of an on-time related to the duty according to the input voltage and the duty voltage. | 2012-11-08 |
20120280672 | POWER SUPPLY CIRCUIT FOR UNIVERSAL SERIAL BUS PORT - A power supply circuit for Universal Serial Bus (USB) ports includes a first USB port and a current amplifier circuit electrically connected to the first USB port. The first power converter receives a first voltage and outputs a first current. The second power converter receives the first voltage and outputs a second current. The first power converter and the second power converter are electrically connected together. The first current is output to the first USB port together with the second current. | 2012-11-08 |
20120280673 | VOLTAGE CONTROL APPARATUS, METHOD, AND PROGRAM - The voltage control apparatus ( | 2012-11-08 |
20120280674 | SNUBBER CIRCUIT - A snubber circuit comprises a first energy storage device and circuitry coupled to the first energy storage device to facilitate capturing, by the first energy storage device, energy of a switching circuit. The snubber circuit also comprises a second energy storage device coupled to the first energy storage device to store the captured energy. The circuitry additionally facilitates resetting of the first energy storage device. | 2012-11-08 |
20120280675 | Calibration Assembly for Aide in Detection of Analytes with Electromagnetic Read-Write Heads - Described are embodiments to ensure that the equipment utilized to detect antigens is reliable and accurate. Accordingly, one embodiment of the invention includes a calibration assembly having nanoparticles, with known magnetic properties, spaced apart at known y-axis locations along the calibration assembly. In one embodiment, the calibration assembly may be used to calibrate a matched filter of the write and read circuitry. Because the calibration assembly comprises nanoparticles with known magnetic properties the read response of the read circuitry to a particular nanoparticle may be stored in the matched filter as an ideal signal for that nanoparticle. The ideal signal stored in the matched filter may then be utilized for reliably and accurately detecting antigens. Still further, the ideal signal stored within the matched filter of the write and read circuitry may be utilized in a correlation test of a calibration assembly to ensure that the calibration assembly is within a manufacturer's or user's acceptable standards for calibration of their write and read assemblies. | 2012-11-08 |
20120280676 | POSITION DETECTING DEVICE - A position detecting device affixed to a handle bar, wherein the positional displacement between a section to be detected and a detecting section is minimized to reduce the degradation of the detection accuracy. A position detecting device | 2012-11-08 |
20120280677 | MAGNETIC POSITION DETECTING DEVICE - A magnetic position detecting device ( | 2012-11-08 |
20120280678 | STATOR AND RESOLVER - Coils are formed into a coil group for a single phase by serially connecting a plurality of coils so that the resulting magnetic flux distribution is a sine wave distribution. The coil group for a single phase is constituted by a plurality of coil sets, formed from two coils that are wound around two adjacent magnetic pole teeth, connected in series. Each coil set includes coils of the two magnetic pole teeth constituting that coil set wound in opposite directions to each other looking from the inside of the stator. An electrical wire extending from an end winding of each coil is turned back so as to run in a direction opposite to an electrical wire connection to a start winding of that coil, and is connected to either a start winding of the next coil or a connection terminal. | 2012-11-08 |
20120280679 | Shaft Angle Measurement - A magnetic angle sensor system for determining a shaft angle for one or more pivoting or rotating shaft means. The or each of said shaft means is provided with means adapted to generate a magnetic field, such that means can be energised in turn to induce a magnetic field in a detector. In a first step the sensor arrangement measures the background field in the absence of any current in the wire or solenoid, such that the angle of the shaft means can be determined from the magnetic field in the solenoid and the background field. The invention concerns the use of an evoked response field whether alternating or steady whereby the angle is determined by the difference in field when the evoking magnetic stimulus is present from when it is absent. | 2012-11-08 |
20120280680 | HALL INTEGRATED CIRCUIT PACKAGE - A Hall integrated circuit package includes a Hall integrated circuit and a field line guiding module. The Hall integrated circuit and the field line guiding module are assembled together with a connecting pin of the Hall integrated circuit exposed to outside. Magnetic field causing by carrying current of a cable passing through the field line guiding portion will be detected by the Hall integrated circuit more accurately so that current measurement based on the detection of magnetic field will be more sensitive and precise. | 2012-11-08 |
20120280681 | Magnetic Field Sensor Having A Control Node To Receive A Control Signal To Adjust A Threshold - An integrated magnetic field sensor includes a magnetic field sensing element configured to generate a magnetic field sensing element output signal in response to a magnetic field. The integrated magnetic field sensor also includes a threshold control node configured to receive a control signal from outside of the integrated magnetic field sensor, wherein the integrated magnetic field sensor is configured to provide an adjustable threshold signal in response to the control signal. The integrated magnetic field sensor also includes a comparator having a first input node coupled to receive a first signal representative of the magnetic field sensing element output signal, a second input node coupled to receive a second signal representative of the adjustable threshold signal, and an output node at which is generated an output signal responsive to the first and second signals. | 2012-11-08 |
20120280682 | Systems for Characterizing Resonance Behavior of Magnetostrictive Resonators - Illustrative embodiments of systems for characterizing resonance behavior of magnetostrictive resonators are disclosed. In one illustrative embodiment, an apparatus may comprise a first channel including one or more driving coils and one or more magnetostrictive resonators, the first channel having a first impedance; a second channel having a second impedance, the second impedance differing from the first impedance by an impedance attributable to the one or more magnetostrictive resonators; a signal source configured to apply an input signal to both the first and second channels; and a signal receiver configured to generate a combined output signal in response to output signals measured from both the first and second channels. | 2012-11-08 |
20120280683 | SYSTEM AND METHOD FOR MAGNETIC RESONANCE RADIO-FREQUENCY FIELD MAPPING - A system and method for radio-frequency (RF) field mapping are provided. One method includes encoding a B | 2012-11-08 |
20120280684 | APPARATUS AND METHOD FOR RECONSTRUCTING 3D IMAGE BY USING MAGNETIC RESONANCE IMAGING - An apparatus for reconstructing 3D images by using magnetic resonance imaging (MRI) includes an image acquiring unit configured to acquire a plurality of MR images about a region of interest of an object at different angles, respectively; and an image reconstructing unit configured to reconstruct the 3D image by using the plurality of MR images, wherein the plurality of MR images include information of a slice direction about the region of interest, which is changed depending on the different angles. According to the invention, since the 3D image is reconstructed by using the MR images acquired at different angles, the 3D image may have a better SNR than the method for;reconstructing 3D images of the related an. | 2012-11-08 |
20120280685 | Linear Phase Microstrip Radio Frequency Transmit Coils - Systems, devices and methods provide an RF coil which produces a field having linear phase variation across an imaging volume. In one embodiment, a coil comprises multiple microstrip elements configured to have an increased effective electrical length. This increase in electrical length allows for a larger linear phase shifts over the length of the microstrip element which in turn increases linear phase variation capabilities. This may be accomplished by increasing the effective dielectric properties of the microstrip element. Increasing the effective dielectric may be accomplished by utilizing distributed capacitors along the length of a microstrip element (e.g. lumped element capacitors), by altering the materials used to fabricate the microstrip element, etc. Additionally, increasing the effective dielectric may be accomplished using a combination of these means. Embodiments may further enable linear phase variation along the imaging volume at high frequencies, such as frequencies utilized for 3 T and above MRI devices. | 2012-11-08 |
20120280686 | MEASURING BIOLOGICAL TISSUE PARAMETERS USING DIFFUSION MAGNETIC RESONANCE IMAGING - Methods, devices and systems are disclosed for measuring biological tissue parameters using restriction spectrum magnetic resonance imaging. In one aspect, a method of characterizing a biological structure includes determining individual diffusion signals from magnetic resonance imaging (MRI) data in a set of MRI images that include diffusion weighting conditions (e.g., diffusion gradient directions, diffusion gradient strengths, sensitivity factors (b-values), or diffusion times), combining the individual diffusion signals to determine a processed diffusion signal corresponding to at least one location within one or more voxels of the MRI data, calculating one or more parameters from the processed diffusion signal by using the diffusion weighting conditions, and using the one or more parameters to identify a characteristic of the biological structure, in which the one or more parameters include values over a range of one or more diffusion length scales based on at least one of diffusion distance or diffusion rate. | 2012-11-08 |
20120280687 | MAGNETIC RESONANCE DEVICE - A magnetic resonance device includes a measuring chamber, a high-frequency shield at least partially enclosing the measuring chamber and an antenna arrangement that includes a plurality of antenna elements disposed around the measuring chamber. The antenna elements have at least one component that is active in the manner of an antenna and extends, as viewed from the high-frequency shield, towards an interior of the measuring chamber. | 2012-11-08 |
20120280688 | Magnetic Resonance (MR) Radio Frequency (RF) Coil and/or High Resolution Nuclear Magnetic Resonance - An MR coil including an MR RF receive coil comprising graphene. | 2012-11-08 |
20120280689 | RETAINING CLIP FOR PLUGGABLE ELECTRONICS COMPONENTS - A local coil for a magnetic resonance tomography system includes a mainboard, at least one plug-in module that is connectable to the mainboard, and a clip engaging with the plug-in module and the mainboard. The clip is arranged at least partially at a side of the mainboard. | 2012-11-08 |
20120280690 | Method for Subsurface Electromagnetic Surveying Using Two or More Simultaneously Actuated Electromagnetic Sources - A method for electromagnetic exploration includes imparting a first electromagnetic signal into subsurface formations and imparting a second electromagnetic signal into the formations substantially contemporaneously with imparting the first electromagnetic signal. The first and second electromagnetic signals are substantially uncorrelated with each other. A combined electromagnetic response of the formations to the first and second imparted electromagnetic signals is detected. A response of the formations to each of the first and the second imparted signals is determined from the detected response. | 2012-11-08 |
20120280691 | DETECTING AN ABNORMALITY OF A SWITCH IN A HIGH VOLTAGE ELECTRICAL SUBSTATION - There is provided a method for determining an abnormality during operation of a high voltage disconnect switch, the method comprising: determining a current position of an arm of the high voltage disconnect switch operatively connected to a motor, the motor being operated for driving the arm of the high voltage disconnect switch; determining a torque of the motor corresponding to the current position of the arm; comparing the torque of the motor to a torque threshold for the current position of the arm; and outputting an abnormality signal based on the comparison. | 2012-11-08 |
20120280692 | APPARATUS AND METHOD FOR MANAGING BATTERY PACK - The present invention discloses an apparatus and method for managing a battery pack, which can rapidly and accurately diagnose the coupling state of a bus bar to battery modules in the battery pack. In accordance with the present invention, provided is an apparatus for managing a battery pack having a plurality of battery modules and a bus bar coupled between the battery modules to electrically connect the battery modules, the apparatus comprising a coupling detection unit for detecting the coupling state of the bus bar to the battery modules; and a controlling unit for determining whether the coupling state of the bus bar has a defect on the basis of the coupling state detected by the coupling detection unit. | 2012-11-08 |
20120280693 | BATTERY CELL IMPEDANCE MEASUREMENT METHOD AND APPARATUS - A circuit arrangement for determining impedance of a battery cell is provided. A first circuit is configured to generate sine and cosine waveforms having N sample values per period. A second circuit is coupled to an output of the first circuit and is configured to input a current into the cell in response to the sample values of the cosine waveform. The current has an amplitude proportional to the sample values of the cosine waveform. A third circuit is coupled to the cell and configured to sample voltage levels across the cell resulting from the current being input into the cell. A fourth circuit is coupled to an output of the third circuit and is configured to separate each voltage level sampled by the third circuit into real and imaginary components. | 2012-11-08 |
20120280694 | BATTERY SYSTEM - A battery system is disclosed. In one embodiment, the system includes i) a plurality of battery modules each of which is configured to store power, wherein each battery module is electrically connected to at least one other battery module and ii) a plurality of management units configured to monitor states of the battery modules. Each management unit is electrically connected to at least one other management unit and one or more of the battery modules. Each management unit may include: at least one measuring unit configured to perform the monitoring and a receiving unit configured to i) receive measurement data including the monitoring results from the measuring unit via a first communication protocol and ii) receive measurement data from another receiving unit included in another management unit via a second communication protocol different from the first communication protocol. | 2012-11-08 |
20120280695 | VOLTAGE DETECTION APPARATUS - A voltage detection apparatus includes first to third circuit boards are provided on first to third battery packs of a battery system respectively. The first circuit board includes a first voltage detection portion detecting a voltage of the first battery pack, a control portion controlling the first voltage detection portion, and a first insulation device which connecting the first voltage detection portion with the control portion. The second circuit board includes a second voltage detection portion detecting a voltage of the second battery pack, and a second insulation device connecting the second voltage detection portion with the control portion. The third circuit board includes a third voltage detection portion connected in series with the second voltage detection portion and detecting a voltage of the third battery pack. The control portion controls the second and third voltage detection portions. | 2012-11-08 |
20120280696 | TEST CHIP AND CHIP TEST SYSTEM USING THE SAME - A chip test system including a chip under test, a test chip, and a test equipment is provided. The chip under test receives a test input data and provides a test output data according to the test input data. The test chip performs at least one of a skew test, a jitter test, and a setup/hold time test on the chip under test by using the test input data and determines whether a test result falls within a predetennined range. The test equipment provides the test input data and inputs the test input data into the chip under test through the test chip. | 2012-11-08 |
20120280697 | VEHICULAR INSULATION RESISTANCE DETECTION APPARATUS - The vehicular insulation resistance detection apparatus includes a cyclic signal generating unit that generates a cyclic signal, a first resistor that has one end to which the cyclic signal is applied, a first capacitor that has one end connected to the other end of the first resistor and the other end connected to a high-voltage circuit, a second capacitor that has one end connected to the other end of the first resistor, a second resistor that has one end connected to the other end of the second capacitor and the other end connected to a low-voltage ground that is a circuit ground of a low-voltage circuit, a series circuit that includes a diode and a third resistor connected in series, and is connected in parallel with the second capacitor, this diode having a forward direction coincident with a direction from the other end of the second capacitor to the one end of the second capacitor, a voltage detection unit that detects a voltage between the low-voltage ground and the other end of the second capacitor as a detection signal, and an insulation resistance detection unit that detects a resistance value of an insulation resistance based on an amplitude of the detection signal. | 2012-11-08 |
20120280698 | CAPACITANCE-TYPE PROXIMITY SENSOR DEVICE AND ELECTRONIC APPARATUS USING THE SAME - A capacitance-type proximity sensor device includes internal electrodes that are arranged such that capacitance is formed therebetween, external electrodes that are arranged in the outer circumference of the internal electrodes, a driving circuit that outputs a driving voltage, a detecting circuit that detects an output signal, a multiplexer that connects an electrode serving as a driving electrode to the driving circuit, connects an electrode serving as a detecting electrode to the detecting circuit, and connects an electrode serving as a shielding electrode to the ground, and a CPU that calculates the position of an object to be detected. When the object to be detected is detected, the multiplexer changes the internal electrodes and the external electrodes to the detecting electrodes, the driving electrodes, and the shielding electrodes. | 2012-11-08 |
20120280699 | PARTIAL DISCHARGE ANALYSIS COUPLING DEVICE - A partial discharge analysis (PDA) coupling device is provided. In one embodiment, a device includes: a connector electrically connecting a first coupling capacitor and a second coupling capacitor; a first conductive rod for electrically connecting the first coupling capacitor to a high voltage input; a second conductive rod for electrically connecting the second coupling capacitor to ground; a current transformer substantially surrounding a portion of the second conductive rod, the current transformer configured to generate a pulse signal; and a reference signal generator adjacent to the current transformer configured to generate a reference signal in phase with the pulse signal. | 2012-11-08 |
20120280700 | CIRCUIT AND METHOD FOR SENSING A DIFFERENTIAL CAPACITANCE - A circuit for sensing a differential capacitance includes a charge-storing circuit to generate a first output voltage and a second output voltage related to capacitances at two terminals of the differential capacitance, respectively, an operational amplifier to amplify the difference between the first and second output voltages to generate a sensing value, a first sampling capacitor having one terminal connected to the negative input terminal and the other terminal receiving the first or second output voltage, and a second sampling capacitor having one terminal connected to the negative input terminal and the other terminal switched to the output terminal of the operational amplifier. The second sampling capacitor stores a non-ideal error value to offset the non-ideal effect of the operational amplifier imparted on the sensing value. | 2012-11-08 |
20120280701 | MICROORGANISM NUMBER MEASUREMENT DEVICE - A microorganism number-measuring apparatus includes: measurement container including measurement liquid; rotary driver; bacteria-collection signal generator; measurement signal generator; output amplifier for amplifying outputs of signal generators and; I/V amplifier; impedance measuring unit for measuring impedance of liquid; microorganism number-computing unit for computing the number of microorganisms present in liquid; solution conductivity-computing unit for computing conductivity of liquid; and warm-up section for warming up at least one of I/V amplifier and output amplifier. Warm-up section computes a warm-up signal based on the conductivity computed by conductivity-computing unit. Warm-up section computes the warm-up signal having a current the same in magnitude as that flowing through measurement electrode by using the measured solution conductivity, and applies the signal to at least one of I/V amplifier and output amplifier. | 2012-11-08 |
20120280702 | TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES - A testing head for a test equipment of electronic devices of the type includes a plurality of contact probes inserted into guide holes which are realized in at least an upper guide and a lower guide separated one another by an air zone. Each of such contact probes include at least a probe body having a substantially rectangular section and a projecting arm from the probe body which ends with a probe tip for contacting one of a plurality of contact pads of a device to be tested. The projecting arm projects outside the probe body so as to have a lug with respect to both faces of the probe body which converge in an edge in order to define a probe tip offset and external with respect to the probe body. | 2012-11-08 |
20120280703 | TESTING HEAD FOR A TEST EQUIPMENT OF ELECTRONIC DEVICES - A testing head for a test equipment of electronic devices comprises a plurality of contact probes inserted into guiding holes made in at least one upper guide and in a lower guide, separate from one another by an air zone, the contact probes comprising at least one enlarged portion suitable for preventing the escape of such probes from the guiding holes. Conveniently, the enlarged portions of the contact probes adjacent according to a direction of distribution of contact pads of an integrated device to be tested have respective larger sides orthogonal to one another. | 2012-11-08 |
20120280704 | SYSTEM FOR TESTING AN INTEGRATED CIRCUIT OF A DEVICE AND ITS METHOD OF USE - A cartridge, including a cartridge frame, formations on the cartridge frame for mounting the cartridge frame in a fixed position to an apparatus frame, a contactor support structure, a contactor interface on the contactor support structure, a plurality of terminals, held by the contactor support structure, for contacting contacts on a device, and a plurality of conductors, held by the contactor support structure, connecting the interface to the terminals. | 2012-11-08 |
20120280705 | TEST HEAD, TEST BOARD AND TEST APPARATUS - A test board can be inserted to a test head and removed from the test head while the connecting section for mounting thereon devices under test is mounted on the upper portion of the test head. A test head for retaining therein at least one test board for testing devices under test, includes: a casing provided with, on one side surface thereof, an opening through which the at least one test board is inserted and removed, the casing retaining therein the at least one test board with an upper side thereof oriented towards an upper surface of the casing; and a mounting member that guides a lower side of the at least one test board through the opening to a pre-set position, imposes an upward force to the lower side of the at least one test board, thereby mounting the at least one test board to the casing. | 2012-11-08 |
20120280706 | CLEANING SHEET, CLEANING MEMBER, CLEANING METHOD, AND CONTINUITY TEST APPARATUS - Provided is a cleaning unit for removing foreign matter adhering to a probe needle of a probe card for a continuity test, the cleaning unit being capable of effectively removing the foreign matter adhering to the probe needle without abrading the probe needle. A cleaning sheet of the present invention is a cleaning sheet, including a cleaning layer for removing foreign matter adhering to a probe needle of a probe card for a continuity test, in which the cleaning layer has an arithmetic average roughness Ra in conformity with JIS-B-0601 of 100 nm or less. | 2012-11-08 |
20120280707 | BOARD MOUNTING APPARATUS, TEST HEAD, AND ELECTRONIC DEVICE TEST APPARATUS - A board mounting apparatus includes: a guide mechanism which guides a pin electronic card along a horizontal direction to an inside of a test head; and an insert mechanism which moves a pin electronic card guided into the test head along a vertical direction so that the pin electronic card is electrically connected through connectors to a back board. | 2012-11-08 |
20120280708 | INTEGRATED CIRCUIT CHIP AND TESTING METHOD THEREOF - An integrated circuit chip is provided. The integrated circuit chip includes a pad, a first resistor, a second resistor, a first switch, a second switch and a controller. The first resistor and the first switch are serially connected between the pad and a first reference voltage terminal. The second resistor and the second switch are serially connected between the pad and a second reference voltage terminal. The controller selectively turns on and off the first and second switches according to an error determining mechanism. The error determining mechanism determines whether an error condition associated with the pad is present. | 2012-11-08 |
20120280709 | Compressor Protection And Grid Fault Detection Device - A compressor monitoring system includes current and voltage monitors, current and voltage averaging modules, a control module, and a switch. The current monitor measures a current drawn by a motor of a compressor. The current averaging module generates first and second average current values based on the current measured by the current monitor. The voltage monitor measures a utility power voltage. The voltage averaging module generates first and second average voltage values based on the voltage measured by the voltage monitor. The control module selectively generates a fault signal when a first ratio is greater than a first predetermined threshold and a second ratio is less than a second predetermined threshold. The first ratio is based on the first and second average current values. The second ratio is based on the first and second average voltage values. The switch deactivates the motor when the fault signal is generated. | 2012-11-08 |
20120280710 | REUSE OF CONSTANTS BETWEEN ARITHMETIC LOGIC UNITS AND LOOK-UP-TABLES - A combinatorial processing element used in a reconfigurable logic device having a plurality of processing elements interconnected by way of a routing network. The combinatorial processing element includes an arithmetic logic unit, having at least one input, a multiplexer tree, having a data input and a memory device. The processing element is arranged such that the memory can be connected to the data input of the multiplexer tree and/or the at least one input of the arithmetic logic unit. | 2012-11-08 |
20120280711 | FPGA RAM BLOCKS OPTIMIZED FOR USE AS REGISTER FILES - A random access memory circuit adapted for use in a field programmable gate array integrated circuit device is disclosed. The FPGA has a programmable array with logic modules and routing interconnects programmably coupleable to the logic modules and the RAM circuit. The RAM circuit has three ports: a first readable port, a second readable port, and a writeable port. The read ports may be programmably synchronous or asynchronous and have a programmably bypassable output pipeline register. The RAM circuit is especially well adapted for implementing register files. A novel interconnect method is also described. | 2012-11-08 |
20120280712 | SCALABLE NON-BLOCKING SWITCHING NETWORK FOR PROGRAMMABLE LOGIC - A L-level permutable switching network (L-PSN) having switches and multiple levels of conductors that are used to connect a first plurality of conductors to other multiple sets of conductors within respective interconnect resources constraints. The L-PSN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The L-PSN is used to connect a first set of conductors, through the L-PSN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The L-PSN is scalable for large sized sets of conductors and can be used in tandem or hierarchically to enable programmable interconnections among large sized circuits. | 2012-11-08 |
20120280713 | NONVOLATILE LATCH CIRCUIT AND NONVOLATILE FLIP-FLOP CIRCUIT - A nonvolatile latch circuit of the invention includes a variable resistance element which is formed by interposing an oxide layer between electrodes, and changes to a low resistance state by applying a voltage to cause current flow in the direction from the first to the second electrode, and changes to a high resistance state by applying a voltage to cause current flow in the reverse direction, wherein a first terminal of a transistor, a first terminal of other transistor, an output terminal of an inverter circuit, and an output terminal of other inverter circuit are respectively connected to one electrode, the other electrode, a second terminal of the transistor, and a second terminal of the other transistor, and a current flowing through the variable resistance element when changed to a low resistance state is smaller in absolute value than a current therethrough when changed to a high resistance state. | 2012-11-08 |
20120280714 | CLOCK SYNCHRONIZATION - In an example embodiment, a method for synchronizing clocks between a plurality of clocked devices where one of the plurality of clocked devices is not directly synchronized with another of the plurality of clocked devices. Clock offset and a clock drift between a first clock associated with a first device and a second clock associated with a second is directly determined based on signals exchanged between the first and second devices. Clock offset and clock drift between the second clock and a third clock associated with a third device is directly determined based on signals exchanged between the second and third devices. A clock offset and clock drift between the first clock and third clock is determined based on a difference between the clock offset and drift between the first and second clocks and the clock offset and drift between the second and third clocks. | 2012-11-08 |
20120280715 | LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE - The logic circuit includes an input terminal, an output terminal, a main logic circuit portion that is electrically connected to the input terminal and the output terminal, and a switching element electrically connected to the input terminal and the main logic circuit portion. Further, a first terminal of the switching element is electrically connected to the input terminal, a second terminal of the switching element is electrically connected to a gate of at least one transistor included in the main logic circuit portion, and the switching element is a transistor in which a leakage current in an off state per micrometer of channel width is lower than or equal to 1×10 | 2012-11-08 |
20120280716 | Fractional-Rate Phase Frequency Detector - A phase frequency detector detects the difference between the edges of a fractional-rate recovered clock signal and the edges within a serial data bit stream, where the edges within the serial data bit stream correspond with the edges of a full-rate clock signal that was used to clock the serial data bit stream. | 2012-11-08 |
20120280717 | Method For Arc Detection And Devices Thereof - A method for arc detection includes detecting a changing rate of a signal indicative of light strength, detecting the amplitude of the signal, and indicating an occurrence of an arc if the changing rate of the signal exceeds a first predetermined threshold and the amplitude of the signal exceeds a second predetermined threshold. An arc detecting device, an arc detecting system, and an arc protecting apparatus thereof are provided. The arc detecting system includes a light collector ( | 2012-11-08 |
20120280718 | SMART EDGE DETECTOR - This description relates to an edge detector including a pulse generator configured to generate a first pulse when a first clock and a second clock are at a same logic level and generate a second pulse when the first clock and the second clock are at different logic levels. The edge detector further includes a first RC circuit configured to charge the first pulse and a second RC circuit configured to charge the second pulse. The edge detector further includes a circuitry that, based on a width of the first pulse or of the second pulse, is configured to provide a select signal to select an edge of the second clock for triggering. | 2012-11-08 |
20120280719 | Apparatus and Method for Selectively Enabling and Disabling a Squelch Circuit Across AHCI and SATA Power States - An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode. | 2012-11-08 |
20120280720 | INTRA-PAIR SKEW CANCELLATION TECHNIQUE FOR DIFFERENTIAL SIGNALING - A method for deskewing a differential signal is provided. A common-mode voltage of a differential signal and an average for the common-mode voltage of the differential signal are measured. A difference between first and second portions of the differential signal is determined, and deskew information is derived from the common-mode voltage and the average. The deskew information can then be combined with the difference to deskew the differential signal. | 2012-11-08 |
20120280721 | SQUELCH DETECTION CIRCUIT - A squelch detection circuit for high-speed serial communication includes: an input level shifter configured to receive signals inputted through signal lines and shift the received signals to a predetermined potential level; a comparator configured to receive signals outputted from the input level shifter, and compares the received signals to determine whether data signals are noise or signal components; and a reset signal generator configured to receive the signals outputted from the input level shifter, convert the received signals into a single signal, and then generate a reset signal for an elastic buffer. The squelch detection circuit may detect a squelch state and provide a reset value for an elastic buffer in a USB 2.0 interface, and may reduce power consumption as much as possible in a suspend mode. | 2012-11-08 |
20120280722 | TRACK AND HOLD CIRCUIT - A track and hold circuit that includes a switch device and a capacitive hold device. The track and hold circuit includes a track-voltage generating device adapted to generate a control voltage based on a signal on an input terminal of the switch device and supply the control voltage to the switch device during track phases of the track and hold circuit. The control voltage provides a channel charge, which is the same for each track phase, in the switch device. | 2012-11-08 |
20120280723 | Driver with Impedance Control - An integrated circuit (IC) may be configured to communicate signals to an external device (e.g., a memory) via a driver. The driver may include a plurality of driver circuits arranged in parallel with respect to each other. Each driver circuit in turn may include a plurality of driver sub-circuits. Based, for example, on the load presented by the external device and/or operating conditions of the IC, a control circuit may provide signals that enable individual ones of driver circuits to result in a selected driver strength. The control circuit may also provide impedance control signals that enable or disable individual sub-circuits within one or more driver circuit, to thereby control the output impedance of each such driver circuit. | 2012-11-08 |
20120280724 | APPARATUS AND METHODS OF REDUCING PRE-EMPHASIS VOLTAGE JITTER - One embodiment relates to a method of driving a transmission signal with pre-emphasis having minimal voltage jitter. A digital data signal is received, and a pre-emphasis signal is generated. The pre-emphasis signal may be a phase shifted and scaled version of the digital data signal. An output signal is generated by adding the pre-emphasis signal to the digital data signal within a driver switch circuit while low-pass filtering is applied to current sources of the driver switch circuit. Other embodiments, aspects, and features are also disclosed. | 2012-11-08 |
20120280725 | DRIVER CIRCUIT, DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT, AND ELECTRONIC APPLIANCE INCLUDING THE DISPLAY DEVICE - An object of the present invention is to provide a driver circuit including a normally-on thin film transistor, which driver circuit ensures a small malfunction and highly reliable operation. The driver circuit includes a static shift register including an inverter circuit having a first transistor and a second transistor, and a switch including a third transistor. The first to third transistors each include a semiconductor layer of an oxide semiconductor and are depletion-mode transistors. An amplitude voltage of clock signals for driving the third transistor is higher than a power supply voltage for driving the inverter circuit. | 2012-11-08 |
20120280726 | CONTROL CIRCUIT ARRANGEMENT FOR PULSE-WIDTH MODULATED DC/DC CONVERTERS AND METHOD FOR CONTROLLING A PULSE-WIDTH MODULATED CONVERTER - A control circuit arrangement for pulse-width modulated DC/DC converters includes a phase generator for a complementary driver which provides respective gate signals to a first and second driver transistor in response to a control signal. A clock control circuit receives a clock signal and a pulse-width modulated signal and provides the control signal in response to a signal edge of the pulse-width modulated signal and the clock signal applied thereto. A mode selection input terminal receives a mode selection signal to select a first mode or a second mode of operation. The phase generator provides in the first mode each of the gate signals the control signal and the respective other gate signal. In the second mode of operation, it provides each gate signal in response to the control signal. | 2012-11-08 |
20120280727 | POWER-ON RESET CIRCUIT - A power on reset circuit is capable of changing logic level of reset signal at different threshold voltages. | 2012-11-08 |
20120280728 | POWER SEMICONDUCTOR DEVICE HAVING PLURALITY OF SWITCHING ELEMENTS CONNECTED IN PARALLEL - A power semiconductor device includes first and second power semiconductor elements connected in parallel to each other and a drive control unit. The drive control unit turns on or off each of the first and second power semiconductor elements in response to an ON instruction and an OFF instruction repeatedly received from outside. Specifically, the drive control unit can switch between a case where the first and second power semiconductor elements are simultaneously turned on and a case where one of the first and second power semiconductor elements is turned on first and thereafter the other thereof is turned on, in response to the ON instruction. The drive control unit turns off one of the first and second power semiconductor elements first and thereafter turns off the other thereof, in response to the OFF instruction. | 2012-11-08 |
20120280729 | ADAPTIVE DIGITAL PHASE LOCKED LOOP - In some embodiments, a digital PLL (DPLL) is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error. | 2012-11-08 |
20120280730 | APPARATUS AND METHODS FOR ADJUSTING VOLTAGE CONTROLLED OSCILLATOR GAIN - Apparatus and methods for adjusting a gain of an electronic oscillator, such as a voltage-controlled oscillator (VCO), are disclosed. In one aspect, an apparatus for compensating for VCO gain variations includes a charge pump controller. The charge pump controller can be configured to select a VCO gain model based on a comparison of a VCO gain indicator and a threshold value stored in a memory, obtain VCO gain model parameters from the memory corresponding to the selected VCO gain model, and compute a charge pump current control value using the VCO gain model parameters. The charge pump current control value can be used to compensate for VCO gain variations. | 2012-11-08 |
20120280731 | PHASE-LOCKED-LOOP CIRCUIT INCLUDING DIGITALLY-CONTROLLED OSCILLATOR - A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal. | 2012-11-08 |
20120280732 | APPARATUS, SYSTEM, AND METHOD FOR VOLTAGE SWING AND DUTY CYCLE ADJUSTMENT - Described herein are an apparatus, system, and method for compensating voltage swing and duty cycle of a signal on an input-output (I/O) pad of a processor by adjusting the voltage swing and duty cycle of the signal. The apparatus comprises a driver to transmit a signal on an I/O pad, the signal on the I/O pad having a voltage swing and a duty cycle; and an adjustment unit, coupled to the driver, to receive the signal from the I/O pad transmitted by the driver and to generate voltage swing and duty cycle control signals for adjusting the voltage swing and duty cycle of the signal on the I/O pad respectively. Described herein is also an analog-to-digital (A2D) converter for measuring and/or calibrating various signal attributes including current, voltage, and time. | 2012-11-08 |
20120280733 | Adjusting circuit of duty cycle and its method - An adjusting circuit of duty cycle includes an edge detecting circuit, a flip-flop connected to the edge detecting circuit, a feedback control circuit connected to the flip-flop and a charge pump circuit connected to the feedback control circuit. The edge detecting circuit detects an edge of an inputted clock signal. The flip-flop sets an outputting terminal thereof at a first level according to a clock signal outputted by the edge detecting circuit. The charge pump circuit controls a duration of the first level outputted the outputting terminal of the flip-flop by charging and discharging a capacitor. The flip-flop sets the outputting terminal thereof at a second level contrary to the first level according to a clock signal outputted by the feedback control circuit. An adjusting method of duty cycle is also disclosed. The adjusting circuit of duty cycle has a simple structure, a stable performance and a fast speed. | 2012-11-08 |
20120280734 | METHOD AND APPARATUS FOR PULSE WIDTH MODULATION - An integrated control circuit according to aspects of the present invention includes an oscillator, a capacitor, and a logic gate. The oscillator generates a periodic timing signal that cycles between a first logic state for a first time duration and a second logic state for a second time duration. The capacitor receives a charge current in response to the periodic timing signal transitioning to the first logic state, where a voltage on the capacitor increases for the first time duration to an initial value. The logic gate generates a periodic output signal having a duty ratio that is responsive to a time that it takes the capacitor to discharge from the initial value to a reference voltage. A period of the periodic output signal is the period of the periodic timing signal. | 2012-11-08 |
20120280735 | APPARATUS AND METHOD TO HOLD PLL OUTPUT FREQUENCY WHEN INPUT CLOCK IS LOST - A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock. | 2012-11-08 |
20120280736 | CIRCUIT AND METHOD FOR REDUCING THE PROPAGATION OF SINGLE EVENT TRANSIENT EFFECTS - Circuits and a corresponding method are used to eliminate or greatly reduce SET induced glitch propagation in a radiation hardened integrated circuit. A clock distribution circuit and an integrated circuit portioning can be radiation hardened using one or two latch circuits interspersed through the integrated circuit, each having two or four latch stages. | 2012-11-08 |
20120280737 | SIGNAL DELAY CIRCUIT, CLOCK TRANSFER CONTROL CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE SAME - A signal delay circuit including a clock transfer control circuit configured to transmit or block a clock signal, and a pulse signal generation circuit configured to delay a first pulse signal in response to the transmitted clock signal to generate a second pulse signal which has a longer active period than the first pulse signal. | 2012-11-08 |
20120280738 | VARIABLE ATTENUATOR HAVING STACKED TRANSISTORS - In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator. | 2012-11-08 |
20120280739 | SYSTEM AND METHOD FOR LEVEL-SHIFTING VOLTAGE SIGNALS USING A DYNAMIC LEVEL-SHIFTING ARCHITECTURE - A system and method to level-shift multiple signals from a first voltage domain to a second voltage domain with minimized silicon area. A level-shifting system may be organized by implementing a static level-shifter coupled to a plurality of dynamic level-shifters. The static level-shifter may provide a voltage control signal for each of the dynamic level-shifters. Each of the dynamic level-shifters may level-shift an individual input signal from a first voltage domain to a second voltage domain. | 2012-11-08 |
20120280740 | OUTPUT BUFFER CIRCUIT AND INPUT/OUTPUT BUFFER CIRCUIT - An output buffer circuit includes first and second output circuits, and those output terminals are coupled to each other. The first output circuit outputs a first signal having a voltage level of a first high potential power supply or a low potential power supply and includes a first output transistor at a high potential side. The second output circuit outputs a second signal having a voltage level of a second high potential power supply, which is lower than the first high potential power supply, or the low potential power supply and includes a second output transistor at a high potential side. A control circuit sets the gate and back gate of at least one of the first and second output transistor to the voltage level of the second high potential power supply when the first high potential power supply is deactivated and the second high potential power supply is activated. | 2012-11-08 |
20120280741 | SEMICONDUCTOR DEVICE - A technique which reduces the influence of external noise such as crosstalk noise in a semiconductor device to prevent a circuit from malfunctioning. A true signal wire and a bar signal wire which are susceptible to noise and part of an input signal line to a level shifter circuit, and shield wires for shielding these signal wires are laid on an I/O cell. Such I/O cells are placed side by side to complete a true signal wire connection and a bar signal wire connection. These wires are arranged in a way to pass over a plurality of I/O cells and are parallel to each other or multilayered. | 2012-11-08 |
20120280742 | 670 GHZ SCHOTTKY DIODE BASED SUBHARMONIC MIXER WITH CPW CIRCUITS AND 70 GHZ IF - A coplanar waveguide (CPW) based subharmonic mixer working at 670 GHz using GaAs Schottky diodes. One example of the mixer has a LO input, an RF input and an IF output. Another possible mixer has a LO input, and IF input and an RF output. Each input or output is connected to a coplanar waveguide with a matching network. A pair of antiparallel diodes provides a signal at twice the LO frequency, which is then mixed with a second signal to provide signals having sum and difference frequencies. The output signal of interest is received after passing through a bandpass filter tuned to the frequency range of interest. | 2012-11-08 |
20120280743 | SIGNAL PROCESSING ARRANGEMENT AND SIGNAL PROCESSING METHOD, PARTICULARLY FOR ELECTRONIC CIRCUITS - A signal processing arrangement including a signal processing stage that divides an input signal (Vin) applied to a signal input (In) of the signal processing stage into at least two subsignals (Vin_a, Vin_b) as a function of a signal amplitude (A) of the input signal (Vin), wherein the signal processing stage is designed for parallel signal processing of the subsignals (Vin_a, Vin_b), and a reconstruction stage connected to the signal processing stage and provides an output signal (Vout) by weighting and combining the at least two processed subsignals (Vin_a, Vin_b). | 2012-11-08 |
20120280744 | CHARGE PUMP CIRCUIT - A charge pump circuit includes a charge generation circuit, a tracking circuit, a replica circuit, and a main charge pump. The main charge pump generates a charge current and a discharge current to a subsequent loop filter according to a UP signal and a DOWN signal. The replica circuit generates a first voltage in response to the current values of the first current source and the second current source of the main charge pump. The tracking circuit adjusts the current values of the first current source and the second current source of the main charge pump according to the first voltage and a second voltage, wherein the second voltage is in response to a voltage of an output node of the main charge pump. | 2012-11-08 |
20120280745 | MULTI-LAYER SWITCHING IN CHARGE-DOMAIN OR SAMPLING IF FILTERS - A signal filter system which uses two groups of switches to couple tap current cells with integrating cells. The first group of switches couples tap current cells with at least one shared connection or bus while the other group of switches couples the shared connection or bus with the integrating cells. Multiple shared connections can be used and the tap current cells can be divided into groups with each group sharing at least one shared connection that is dedicated to that group. The system also allows for more than one tap current cell to simultaneously be coupled to a single integrating cell. | 2012-11-08 |
20120280746 | DC-DC CONVERTER SEMICONDUCTOR DIE STRUCTURE - A direct current (DC)-DC converter having a DC-DC converter semiconductor die and an alpha flying capacitive element is disclosed. The DC-DC converter semiconductor die includes a first series alpha switching element, a second series alpha switching element, a first alpha flying capacitor connection node, which is about over the second series alpha switching element, and a second alpha flying capacitor connection node, which is about over the first series alpha switching element. The alpha flying capacitive element is electrically coupled between the first alpha flying capacitor connection node and the second alpha flying capacitor connection node. By locating the first alpha flying capacitor connection node and the second alpha flying capacitor connection node about over the second series alpha switching element and the first series alpha switching element, respectively, lengths of transient current paths may be minimized, thereby reducing noise and potential interference. | 2012-11-08 |
20120280747 | FEEDBACK BASED BUCK TIMING OF A DIRECT CURRENT (DC)-DC CONVERTER - At least a first shunt switching element and switching control circuitry of a first switching power supply are disclosed. At least the first shunt switching element is coupled between a ground and an output inductance node of the first switching power supply. The first switching power supply provides a buck output signal from the output inductance node. The switching control circuitry selects one of an ON state and an OFF state of the first shunt switching element. When the buck output signal is above a first threshold, the switching control circuitry is inhibited from selecting the ON state. The first switching power supply provides a first switching power supply output signal based on the buck output signal. By using feedback based on the buck output signal, the switching control circuitry may refine the timing of switching between series switching elements and shunt switching elements to increase efficiency. | 2012-11-08 |
20120280748 | MULTI-PORT AMPLIFICATION DEVICE THAT SELF-COMPENSATES IN THE PRESENCE OF TRAFFIC - A system for multi-distributed amplification of a communication signal including at least one plurality N of input pathways connected to an input Butler matrix which delivers as output N distributed signals, a plurality N of tube amplifiers which receive as input said distributed signals and produce as output N amplified and phase-shifted signals each of a complex gain Gi and an output Butler matrix which receives as input said amplified signals and produces as output N output signals, wherein the phase error and amplitude error are self-compensated in the presence of traffic. | 2012-11-08 |
20120280749 | SYSTEMS AND METHODS FOR MITIGATING SPECTRAL REGROWTH FROM NON-LINEAR SYSTEMS - Various embodiments are directed to a non-linear amplifier system comprising a reference output generator, an adaptive filter, a amplitude distortion (AM-AM) compensator, a phase distortion (AM-PM) compensator, an adaptive spectrum controller and a non-linear system. The reference output generator may receive an input signal and generating a reference output. The adaptive filter may generate a modified input signal based on the input signal and the reference output. The AM-AM compensator may act on the modified input signal to compensate for AM-AM distortion. The phase distortion (AM-PM) compensator may act on the modified input signal to compensate for AM-PM distortion. The adaptive spectrum controller may provide parameters to the adaptive filter to minimize the power spectral density (PSD) of an output of the non-linear amplifier system in a stop-band and maximize the PSD of the output of the non-linear amplifier system in a pass-band. | 2012-11-08 |
20120280750 | CIRCUIT ARRANGEMENT FOR A REDUNDANT POWER SUPPLY FOR A POWER AMPLIFIER - The switching arrangement is used for the redundant power supply for a power amplifier, especially a high-frequency power amplifier. The power amplifier in this context provides several output-stage components and several power-supply units. The power-supply units are connected together at their load-end connections and supply the output-stage components jointly with energy. If a power-supply unit fails, at least two output-stage components are actively switched off, so that the power amplifier can continue to operate although with reduced output power. | 2012-11-08 |
20120280751 | Noise Rejecting High-Side Power Switch - An apparatus includes a pass element comprising an input, an output and a control input. The pass element, with a first signal on the control input, passes a voltage from the input to the output and, with a second signal on the control input, blocks the voltage on the input from passing to the output. A differential amplifier includes a non-inverting input coupled to the input, an inverting input coupled to the output, an amplifier output coupled to the control input and a bias current connection. The differential amplifier, with a bias current supplied, supplies the first signal along with a closed feedback loop from the output and supplies the second signal in absence of the bias current. A current source is coupled to the bias current connection and an enable input. The current source supplies the bias current and, in absence of an enable signal, disables the bias current. | 2012-11-08 |
20120280752 | EMBEDDED RF PA TEMPERATURE COMPENSATING BIAS TRANSISTOR - A radio frequency (RF) power amplifier (PA) amplifying transistor of an RF PA stage and an RF PA temperature compensating bias transistor of the RF PA stage are disclosed. The RF PA amplifying transistor includes a first array of amplifying transistor elements and a second array of amplifying transistor elements. The RF PA temperature compensating bias transistor provides temperature compensation of bias of the RF PA amplifying transistor. Further, the RF PA temperature compensating bias transistor is located between the first array and the second array. As such, the RF PA temperature compensating bias transistor is thermally coupled to the first array and the second array. The RF PA stage receives and amplifies an RF stage input signal to provide an RF stage output signal using the RF PA amplifying transistor. | 2012-11-08 |
20120280753 | SYSTEM AND METHOD FOR ADJUSTING GAIN FREQUENCY RESPONSE OF RF POWER AMPLIFIER - A radio frequency (RF) amplifier is disclosed including an active device adapted to amplify an input signal in accordance with a gain frequency response to generate an output signal, and a dissipative circuit adapted to modify the gain frequency response by dissipating the input or output signal more so at a first frequency range than at a second frequency range. The dissipative circuit may include a resistive element, and an open circuit adapted to operate as an open at a specified frequency to substantially minimize the dissipation of the input or output signal through the resistive element at the specified frequency. The open circuit may include an open-ended transmission line having an electrical length of a half wavelength or multiple thereof at the specified frequency. Alternatively, the open circuit may include a short-ended transmission line having an electrical length of a quarter wavelength or odd multiple thereof at the specified frequency. | 2012-11-08 |
20120280754 | POWER AMPLIFIER WITH CO-EXISTENCE FILTER - A power amplifier architecture and front end circuits utilizing the same that connect a transceiver to an antenna are disclosed. The transceiver is configured for a specific operating frequency. An input matching segment is connected to an input port, and an output matching segment is connected to an output port. An amplifier segment includes at least one transistor with a first terminal connected to the input matching segment, a second terminal connected to the output matching segment, and a third terminal connected to a filter with a range of rejection frequencies. The filter is connected in close proximity to a first inductive interconnection tying a junction connected to the third terminal to a ground. A compensator is also connected to the input matching segment and the output matching segment to minimize instability of the filter. | 2012-11-08 |
20120280755 | FLIP-CHIP POWER AMPLIFIER AND IMPEDANCE MATCHING NETWORK - Embodiments of circuits, apparatuses, and systems for a flip-chip power amplifier and impedance matching network are disclosed. Other embodiments may be described and claimed. | 2012-11-08 |
20120280756 | MATRIX STRUCTURE OSCILLATOR - An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance | 2012-11-08 |
20120280757 | SEMICONDUCTOR INTEGRATED CIRCUIT AND ABNORMAL OSCILLATION DETECTION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor device includes a first oscillator that generates a first clock signal, a second oscillator that generates a second clock signal in response to the first clock signal, a third oscillator that generates a third clock signal, a counter that counts a signal corresponding to the first clock signal or a signal corresponding to the second clock signal during a predetermined period that is set based on the third clock signal to generate an overflow signal indicating that a count value of the signal corresponding to the first clock signal or the signal corresponding to the second clock signal exceeds a predetermined value, and an abnormality notice unit that receives the overflow signal to generate an abnormal signal indicating that an abnormal oscillation occurs in at least one of the first to third clock signals. | 2012-11-08 |
20120280758 | Bulk acoustic wave resonator and method of manufacturing thereof - The invention concerns a novel bulk acoustic wave (BAW) resonator design and method of manufacturing thereof The bulk acoustic wave resonator comprises a resonator portion, which is provided with at least one void having the form of a trench which forms a continuous closed path on the resonator portion. By manufacturing the void in the same processing step as the outer dimensions of the resonator portion, the effect of processing variations on the resonant frequency of the resonator can be reduced. By means of the invention, the accuracy of BAW resonators can be increased. | 2012-11-08 |
20120280759 | OSCILLATOR - There are disposed a sealing member, a pair of electrode pads to electrically couple a piezoelectric resonator, a plurality of connection pads to electrically couple an integrated circuit element and the piezoelectric resonator, and wiring patterns to establish electrical continuity between the pair of electrode pads and the plurality of connection pads, and the piezoelectric resonator and the integrated circuit element are disposed side by side in plan view. An output wiring pattern establishes electrical continuity between one of the connection pads and an alternating current output terminal of an oscillation circuit, and a power source wiring pattern establishes electrical continuity between one of the connection pads and a direct current power source terminal of the oscillation circuit. The electrode pads are disposed closer to the power source wiring pattern than the output wiring pattern. | 2012-11-08 |
20120280760 | APPARATUS AND METHODS RELATED TO FERRITE BASED CIRCULATORS - Apparatus and methods related to ferrite based circulators are disclosed. A ferrite disk used in a circulator can be configured to reduce intermodulation distortion when routing radio-frequency signals having closely spaced frequencies. Such a reduction in intermodulation distortion can be achieved by adjusting magnetization at the edge portion of the ferrite disk. By way of an example, a ferrite disk with a reduced saturation magnetization (4 PiMs) edge portion can reduce intermodulation distortion. Example configurations with such a reduced 4 PiMs edge portions are disclosed. | 2012-11-08 |
20120280761 | Impedance matching component - The present disclosure discloses an impedance matching component disposed between a first medium and a second medium, which is formed by stacking a plurality of homogeneous metamaterial sheet layers in a direction perpendicular to surfaces thereof. Each of the metamaterial sheet layers comprises a substrate and a plurality of man-made microstructures attached thereon. A first and last metamaterial sheet layers have impedances identical to those of the first and second media respectively. The man-made microstructures attached on the first metamaterial sheet layer have a first pattern, the man-made microstructures attached on the last metamaterial sheet layer have a second pattern, and the man-made microstructures attached on intermediate ones of the metamaterial sheet layers have patterns that are combinations of the first and second patterns, with the first pattern becoming smaller continuously and the second pattern becoming larger continuously in the stacking direction of the metamaterial sheet layers. | 2012-11-08 |
20120280762 | HIGH ISOLATION WAVEGUIDE SWITCH - Embodiments of the invention are directed to a high isolation waveguide switch that can either be manually or mechanically operated. Operation proceeds by loosening a fastener, which draws a rotor portion of the switch away from a stator portion; rotating the rotor by 90 degrees; and tightening the fastener, pushing the rotor into contact with the stator and completing connections to the waveguide ports. Gaskets may provide EMI shielding and ensure port-to-port isolation. | 2012-11-08 |
20120280763 | Processing Signals by Couplers Embedded in an Integrated Circuit Package - Methods and systems for processing signals via directional couplers embedded in a package are disclosed and may include generating via a directional coupler, one or more output RF signals that may be proportional to a received RF signal. The directional coupler may be integrated in a multi-layer package. The generated RE signal may be processed by an integrated circuit electrically coupled to the multi-layer package. The directional coupler may include quarter wavelength transmission lines, which may include microstrip or coplanar structures. The directional coupler may be electrically coupled to one or more variable capacitances in the integrated circuit. The variable capacitance may include CMOS devices in the integrated circuit. The directional coupler may include discrete devices, which may be surface mount devices coupled to the multi-layer package or may be devices integrated in the integrated circuit. The integrated circuit may be flip-chip bonded to the multi-layer package. | 2012-11-08 |
20120280764 | FERRITE PHASE SHIFTER AND AUTOMATIC MATCHING APPARATUS - In a ferrite phase shifter, a temperature rise at ferrites can be suppressed to maintain the characteristics of the frites even when used at high power. Thus, the phase shifter can stably demonstrate high performance. The ferrite phase shifter includes a rectangular waveguide, substantially sheet-like ferrites disposed to face each other with respective mounting surfaces kept in tight contact with inner walls of wide surfaces of the rectangular waveguide facing each other, and a coil which is wound around the periphery of the rectangular waveguide in a position substantially corresponding to the position of the ferrites and through which a current is passed. | 2012-11-08 |
20120280765 | Low AC resistance conductor designs - Described herein are improved configurations for providing a stranded printed circuit board trace comprising, a plurality of conductor layers, a plurality of individual conductor traces on each of the said conductor layers, and a plurality of vias for connecting individual conductor traces on different said conductor layers, the vias located on the outside edges of the stranded trace. The individual conductor traces of each layer may be routed from vias on one side of the stranded printed circuit board trace to vias on the other side in a substantially diagonal direction with respect to the axis of the stranded printed circuit board trace. In embodiments, the stranded printed circuit board trace configuration may be applied to a wireless power transfer system. | 2012-11-08 |