44th week of 2010 patent applcation highlights part 42 |
Patent application number | Title | Published |
20100279445 | TRANSFLECTIVE TYPE DIODE SUBSTRATE AND A METHOD FOR FABRICATION THE SAME - A transflective diode substrate for a liquid crystal display device, includes: a reflective zone including a diode having a scan electrode, an insulating pattern on the scan electrode and a pixel electrode over the scan electrode, organic patterns around the diode, and a reflection electrode over the organic patterns; and a transmissive zone adjacent to the reflective zone; wherein the pixel electrode is formed in the reflective zone and the transmissive zone. | 2010-11-04 |
20100279446 | OPTICAL PHASE CONJUGATION LASER DIODE - A phase-conjugating resonator that includes a semiconductor laser diode apparatus that comprises a phase-conjugating array of retro-reflecting hexagon apertured hexahedral shaped corner-cube prisms, an electrically and/or optically pumped gain-region, a distributed bragg reflecting mirror-stack, a gaussian mode providing hemispherical shaped laser-emission-output metalized mirror. Wherein, optical phase conjugation is used to neutralize the phase perturbating contribution of spontaneous-emission, acoustic phonons, quantum-noise, gain-saturation, diffraction, and other intracavity aberrations and distortions that typically destabilize any stimulated-emission made to undergo amplifying oscillation within the inventions phase-conjugating resonator. Resulting in stablized high-power laser-emission-output into a single low-order fundamental transverse cavity mode and reversal of intra-cavity chirp that provides for high-speed internal modulation capable of transmitting data at around 20-Gigabits/ps. | 2010-11-04 |
20100279447 | DBR LASER WITH IMPROVED THERMAL TUNING EFFICIENCY - A distributed Bragg reflector (DBR) includes a base substrate and a gain medium formed on the base substrate. A waveguide positioned above the base substrate in optical communication with the gain medium and defines a gap extending between the base substrate and the waveguide along a substantial portion of the length thereof. The waveguide having a grating formed therein. A heating element is in thermal contact with the waveguide and electrically coupled to a controller electrically configured to adjust optical properties of the waveguide by controlling power supplied to the heating element. | 2010-11-04 |
20100279448 | Method of manufacturing vertical light emitting device - Provided is a method of manufacturing a vertical light emitting device. The method of manufacturing the vertical light emitting device may include forming an emissive layer including a n-type semiconductor layer, an active layer, and a p-type semiconductor layer on a substrate, forming a first trench dividing the emissive layer into light emitting device units in which the emissive layer remains on the lower part of the first trench to a desired, or alternatively, a predetermined thickness, forming a passivation layer on the emissive layer, forming a p-type electrode on the p-type semiconductor layer of the emissive layer, forming a metal supporting layer on the passivation layer and the p-type electrode, removing the substrate, removing a remaining portion of the emissive layer when the surface of the emissive layer is exposed by removing the substrate, forming a n-type electrode on the n-type semiconductor layer of the emissive layer, and cutting the metal supporting layer to divide the emissive layer into the light emitting device units. | 2010-11-04 |
20100279449 | DISPLAY DEVICE PROVIDED WITH SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INSTALLED WITH DISPLAY DEVICE PROVIDED WITH SEMICONDUCTOR ELEMENT - According to one feature of the invention, a region of an insulating film surface at least overlapped with a part of a gate electrode or wiring is coated with an organic agent; a fluid in which conductive fine particles are dispersed in an organic solvent is discharged by a droplet discharging method in the insulating film surface ranging from a region where the organic agent is coated and left to a region where the organic agent is not coated. The organic agent is coated to improve wettability of the fluid in the insulating film surface, and one of each ends of the source electrode and the drain electrode adjacent to each other by interposing the curve therebetween is formed by being curved in a concave and the other end is formed by being curved in a convex. | 2010-11-04 |
20100279450 | Active Device Array Substrate and Method for Fabricating the Same - An active device array substrate and its fabricating method are provided. According to the subject invention, the elements of an array substrate such as the thin film transistors, gate lines, gate pads, data lines, data pads and storage electrodes, are provided by forming a patterned first metal layer, an insulating layer, a patterned semiconductor layer and a patterned metal multilayer. Furthermore, the subject invention uses the means of selectively etching certain layers. Using the aforesaid means, the array substrate of the subject invention has some layers with under-cut structures, and thus, the number of the time-consuming and complicated mask etching process involved in the production of an array substrate can be reduced. The subject invention provides a relatively simple and time-saving method for producing an array substrate. | 2010-11-04 |
20100279451 | DIRECT CONTACT HEAT CONTROL OF MICRO STRUCTURES - A method of providing thermal tuning of microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is disclosed. A heater is provided integrated with the MEMS for controllably heating the MEMS to control performance characteristics thereof. | 2010-11-04 |
20100279452 | IMAGE SENSOR CHIP PACKAGE METHOD - In an image sensor chip package method, a transparent substrate having an upper surface, a lower surface, and through holes is provided. The through holes pass through the transparent substrate. Conductive posts are formed in the through holes. A sealing ring is formed on the lower surface of the transparent substrate. A chip having an active surface, an image sensitive area, and die pads is provided. The image sensitive area and the die pads are located on the active surface. Conductive bumps are formed and respectively disposed on the die pads for respectively connecting the conductive posts. At the time the active surface of the chip is turned to face toward the lower surface of the transparent substrate. The chip is assembled to the transparent substrate and electrically connected with the conductive posts via the die pads. The sealing ring surrounds the image sensitive area and the die pads. | 2010-11-04 |
20100279453 | Method for making an anti-reflection film of a solar cell - A method is disclosed for making an anti-reflection film of a solar cell. The method includes the step of providing a laminate. The laminate includes a ceramic substrate, a titanium-based compound film, a p | 2010-11-04 |
20100279454 | Method of Manufacturing a Solar Cell - A method of manufacturing a solar cell. The method includes the steps of providing a substrate, applying a first dopant to a first surface, applying a second dopant to a second surface, covering the doped first surface with a hard mask, applying a third dopant to the substrate side, removing the hard mask, applying a pattern of first electrical contacts to the doping pattern, and applying a pattern of second electrical contacts to the doped second surface, the pattern of second electrical contacts and the doping pattern being straight-lined opposed. | 2010-11-04 |
20100279455 | Methods, facilities and simulations for a solar power plant - In an embodiment, the present invention discloses methods and simulations for constructing a solar power plant meeting a criterion of either a desired power selling price or a capital investment. The present methods can provide design considerations for a solar power plant that is affordable and cost effective. For example, the present methods focus on a desired power selling price, to ensure the solar power plant provides competitive power as compared to existing oil, coal or nuclear based power plants. Alternatively, the present methods can focus on a desired capital investment for building a solar power plant. The construction plan and the solar technology are selected to achieve this price or investment consideration. | 2010-11-04 |
20100279456 | Compound solar and manufacturing method thereof - On a surface of a GaAs substrate, layers to be a top cell are formed by epitaxial growth. On the top cell, layers to be a bottom cell are formed. Thereafter, on a surface of the bottom cell, a back surface electrode is formed. Thereafter, a glass plate is adhered to the back surface electrode by wax. Then, the GaAs substrate supported by the glass plate is dipped in an alkali solution, whereby the GaAs substrate is removed. Thereafter, a surface electrode is formed on the top cell. Finally the glass plate is separated from the back surface electrode. In this manner, a compound solar battery that improves efficiency of conversion to electric energy can be obtained. | 2010-11-04 |
20100279457 | METHOD FOR MANUFACTURING A SEMICONDUCTOR LIGHT-RECEIVING DEVICE - Disclosed is a method for manufacturing a semiconductor light-receiving device having high reproducibility and reliability. Specifically disclosed is a semiconductor light-receiving device | 2010-11-04 |
20100279458 | PROCESS FOR MAKING PARTIALLY TRANSPARENT PHOTOVOLTAIC MODULES - A process for making a partially transparent photovoltaic cell or a partially transparent photovoltaic module comprising series-connected or parallel-connected photovoltaic cells comprises the step of forming a patterned back electrode(s) by screen printing, jet printing, roll-to-roll processing or depositing through a shadow mask with openings. The pattern of the back electrode is determined at the same time when the back electrode is disposed, such that the complexity and cost of the process can be reduced. | 2010-11-04 |
20100279459 | METHOD FOR REDUCING CONTACT RESISTANCE OF CMOS IMAGE SENSOR - A method for performing a CMOS Image Sensor (CIS) silicide process is provided to reduce pixel contact resistance. In one embodiment, the method comprises forming a Resist Protect Oxide (RPO) layer on the CIS, forming a Contact Etch Stop Layer (CESL), forming an Inter-Layer Dielectric (ILD) layer, performing contact lithography/etching, performing Physical Vapor Deposition (PVD) at a pixel contact hole area, annealing for silicide formation at pixel contact hole area, performing contact filling, and defining the first metal layer. The Resist Protect Oxide (RPO) layer can be formed without using a photo mask of Cell Resist Protect Oxide (CIRPO) photolithography for pixel array and/or without silicide process at pixel array. The method can include implanting N+ or P+ for pixel contact plugs at the pixel contact hole area. The contact filling can comprise depositing contact glue plugs and performing Chemical Mechanical Polishing (CMP). | 2010-11-04 |
20100279460 | ORGANIC THIN FILM TRANSISTOR - To provide an organic thin film transistor including a pair of electrodes for allowing a current to flow through an organic semiconductor layer made of an organic semiconductor material, and a third electrode, wherein the organic semiconductor material is composed mainly of an arylamine polymer having a weight-average molecular weight (Mw) of 20,000 or more. | 2010-11-04 |
20100279461 | Method of Fabricating Zinc Oxide Film Having Matching Crystal Orientation to Silicon Substrate - A zinc oxide (ZnO) film is fabricated. Metal-organic chemical vapor deposition (MOCVD) is used to obtain the film with few defects, high integrity and low cost through an easy procedure. The ZnO film above a silicon substrate has a matching crystal orientation to the substrate. Thus, the ZnO film is fit for ultraviolet light-emitting diodes (UV LED), solar cells and related laser devices. | 2010-11-04 |
20100279462 | FIELD EFFECT TRANSISTOR USING AMORPHOUS OXIDE FILM AS CHANNEL LAYER, MANUFACTURING METHOD OF FIELD EFFECT TRANSISTOR USING AMORPHOUS OXIDE FILM AS CHANNEL LAYER, AND MANUFACTURING METHOD OF AMORPHOUS OXIDE FILM - An amorphous oxide containing hydrogen (or deuterium) is applied to a channel layer of a transistor. Accordingly, a thin film transistor having superior TFT properties can be realized, the superior TFT properties including a small hysteresis, normally OFF operation, a high ON/OFF ratio, a high saturated current, and the like. Furthermore, as a method for manufacturing a channel layer made of an amorphous oxide, film formation is performed in an atmosphere containing a hydrogen gas and an oxygen gas, so that the carrier concentration of the amorphous oxide can be controlled. | 2010-11-04 |
20100279463 | METHOD OF FORMING STACKED-DIE PACKAGES - A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer. | 2010-11-04 |
20100279464 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage. | 2010-11-04 |
20100279465 | SEMICONDUCTOR MANUFACTURING METHOD OF DIE PICK-UP FROM WAFER - A manufacturing method of a semiconductor device comprising the steps of: affixing a die attach film and a dicing film to a back surface of a semiconductor wafer: thereafter dicing the semiconductor wafer and the die attach film to divide the semiconductor wafer into a plurality of semiconductor chips: thereafter pulling the dicing film from the center toward the outer periphery of the dicing film with a first tensile force to cut the die attach film chip by chip; and thereafter picking up the semiconductor chips together with the die attach film while pulling the dicing film from the center toward the outer periphery of the dicing film with a second tensile force smaller than the first tensile force. | 2010-11-04 |
20100279466 | APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, PACKAGED SEMICONDUCTOR COMPONENTS, METHODS OF MANUFACTURING APPARATUS FOR PACKAGING SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR COMPONENTS - Packaged semiconductor components, apparatus for packaging semiconductor devices, methods of packaging semiconductor devices, and methods of manufacturing apparatus for packaging semiconductor devices. One embodiment of an apparatus for packaging semiconductor devices comprises a first board having a front side, a backside, arrays of die contacts, arrays of first backside terminals electrically coupled to the die contacts, arrays of second backside terminals, and a plurality of individual package areas that have an array of the die contacts, an array of the first backside terminals, and an array of the second backside terminals. The apparatus further includes a second board having a first side laminated to the front side of the first board, a second side, openings through the second board aligned with individual package areas that define die cavities, and arrays of front contacts at the second side electrically coupled to the second backside terminals by interconnects extending through the first board and the second board. | 2010-11-04 |
20100279467 | METHODOLOGY FOR PROCESSING A PANEL DURING SEMICONDUCTOR DEVICE FABRICATION | 2010-11-04 |
20100279468 | LAMINATED FILM AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The present invention provides a laminated film which includes a pressure-sensitive adhesive sheet including a pressure-sensitive adhesive layer, and a die-adhering layer laminated on the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet, the laminated film being for use in a production step of a semiconductor device, in which the pressure-sensitive adhesive layer of the pressure-sensitive adhesive sheet contains a water-supporting body, and the pressure-sensitive adhesive layer has a gel fraction of 90% by weight or more. | 2010-11-04 |
20100279469 | Low-Voiding Die Attach Film, Semiconductor Package, and Processes for Making and Using Same - This invention is a low-voiding adhesive film prepared from a composition. The composition comprises a toughening polymer, a curable resin, a curing agent for the curable resin, a void reduction compound, and a curing agent for the void reduction compound. The void reduction compound has at least two Si—O moieties contiguous with each other and at least one reactive functionality. Additional embodiments of this invention are described, including a process for producing the low-voiding die attach film, a method for reducing voids in a semiconductor package using the film of this invention, and a semiconductor package assembled with the film of this invention. | 2010-11-04 |
20100279470 | PACKAGE WITH MULTIPLE DIES - A semiconductor die package is disclosed. It includes a leadframe structure comprising a first die attach pad and a second die attach pad. A plurality of leads extend from the first and second die attach pads. The plurality of leads includes at least a first control lead and a second control lead. A first semiconductor die including a first device is mounted on the first die attach pad, and a second semiconductor die has a second device is mounted on the second die attach pad. A housing is provided in the semiconductor die package and protects the first and second dies. The housing may have an exterior surface and at least partially covers the first semiconductor die and the second semiconductor die. The first control lead and the second control lead are at opposite sides of the semiconductor die package. | 2010-11-04 |
20100279471 | UNDERFILL DISPENSING SYSTEM FOR INTEGRATED CIRCUITS - A system for dispensing an underfill material between an integrated circuit (IC) chip and a substrate includes a platform at which the underfill material is supplied. The IC chip and the substrate are mounted at the periphery of the platform. The platform rotates and facilitates the movement of the underfill material toward the IC chip and the substrate. The system further includes a Bernoulli tube that is located proximate to the IC chip and the substrate. The Bernoulli tube generates a low pressure in the proximity of the IC packages. The low pressure facilitates the dispensing of the underfill material between the IC chip and the substrate. | 2010-11-04 |
20100279472 | MANUFACTURING METHOD OF NON-VOLATILE MEMORY - In a manufacturing method of a non-volatile memory, a substrate is provided, and strip-shaped isolation structures are formed in the substrate. A first memory array including memory cell columns is formed on the substrate. Each memory cell column includes memory cells connected in series with one another, a source/drain region disposed in the substrate outside the memory cells, select transistors disposed between the source/drain region and the memory cells, control gate lines extending across the memory cell columns and in a second direction, and first select gate lines respectively connecting the select transistors in the second direction in series. First contacts are formed on the substrate at a side of the first memory array and arranged along the second direction. Each first contact connects the source/drain regions in every two adjacent active regions. | 2010-11-04 |
20100279473 | THIN FILM TRANSISTOR SUBSTRATE AND FABRICATING METHOD THEREOF - A thin film transistor substrate and a fabricating method that includes an opening hole that separates a gate shorting line connected to a gate shorting bar used upon a lighting-inspecting of a gate line into an odd and an even gate shorting line is provided. | 2010-11-04 |
20100279474 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A formation of a gate electrode provided over an oxide semiconductor layer of a thin film transistor is performed together with a patterning of the oxide semiconductor layer. | 2010-11-04 |
20100279475 | THIN FILM TRANSISTOR, DISPLAY DEVICE HAVING THIN FILM TRANSISTOR, AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor. | 2010-11-04 |
20100279476 | Manufacturing Method for Field-Effect Transistor - To provide a manufacturing method for a field-effect transistor, such as a thin-film transistor, enabling reductions in the number patterning steps and the number of photomasks and improvements in the throughput and the yield. In the method, an oxide film is formed by processing the surface of a crystalline semiconductor with ozone water or hydrogen peroxide water. Using the oxide film thus formed as an etch stop, a gate electrode, a source electrode, and a drain electrode of the field-effect transistor are simultaneously formed from a same starting film in one patterning step by use of one photomask. After forming the gate electrode, the source electrode, and the drain electrode, heating is performed thereon at 800° C. or higher for a predetermined time. Thereby, the contact resistances between the source electrode and the crystalline semiconductor and between the drain electrode and the crystalline semiconductor are reduced, whereby improving the electrical conductivity. | 2010-11-04 |
20100279477 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A highly responsive semiconductor device in which the subthreshold swing (S value) is small and reduction in on-current is suppressed is manufactured. A semiconductor layer in which a thickness of a source region or a drain region is larger than that of a channel formation region is formed. A semiconductor layer having a concave-convex shape which is included in the semiconductor device is formed by the steps of forming a first semiconductor layer over a substrate; forming a first insulating layer and a conductive layer over the first semiconductor layer; forming a second insulating layer over a side surface of the conductive layer; forming a second semiconductor layer over the first insulating layer, the conductive layer and the second insulating layer; etching the second semiconductor layer using a resist formed partially as a mask; and performing heat treatment to the first semiconductor layer and the second semiconductor layer. | 2010-11-04 |
20100279478 | TRENCH MOSFET HAVING TRENCH CONTACTS INTEGRATED WITH TRENCH SCHOTTKY RECTIFIERS HAVING PLANAR CONTACTS - An integrated configuration comprising trench MOSFET having trench contacts and trench Schottky rectifier having planar contacts is disclosed. The trench contacts for trench MOSFET provide a lower specific on-resistance. Besides, for trench gate connection, planar gate contact is employed in the present invention to avoid shortage issue between gate and drain in shallow trench gate. Besides, W plugs filled into both trench contacts and planar contacts enhance the metal step coverage capability. | 2010-11-04 |
20100279479 | Formation Of Raised Source/Drain On A Strained Thin Film Implanted With Cold And/Or Molecular Carbon - A method is disclosed for enhancing tensile stress in the channel region of a semiconductor structure. The method includes performing one or more cold-carbon or molecular carbon ion implantation steps to implant carbon ions within the semiconductor structure to create strain layers on either side of a channel region. Raised source/drain regions are then formed above the strain layers, and subsequent ion implantation steps are used to dope the raised source/drain region. A millisecond anneal step activates the strain layers and the raised source/drain regions. The strain layers enhances carrier mobility within a channel region of the semiconductor structure, while the raised source/drain regions minimize reduction in strain in the strain layer caused by subsequent implantation of dopant ions in the raised source/drain regions. | 2010-11-04 |
20100279480 | METHOD OF MAKING SMALL GEOMETRY FEATURES - A method of forming a small geometry feature. The method includes forming a source layer on a top surface of a substrate; forming a mandrel on a top surface of the source layer, the mandrel having a sidewall; sputtering material from the source layer onto the sidewall of the mandrel to form a sidewall layer on the sidewall of the mandrel; and removing the mandrel. Also methods to forming wires and field effect transistors of integrated circuits. | 2010-11-04 |
20100279481 | CONTROL OF DOPANT DIFFUSION FROM BURIED LAYERS IN BIPOLAR INTEGRATED CIRCUITS - An integrated circuit and method of fabricating the integrated circuit is disclosed. The integrated circuit includes vertical bipolar transistors ( | 2010-11-04 |
20100279482 | Semiconductor Device and Method of Manufacturing the Same - In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size. | 2010-11-04 |
20100279483 | LATERAL PASSIVE DEVICE HAVING DUAL ANNULAR ELECTRODES - A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed. | 2010-11-04 |
20100279484 | Method of making multi-layer structure for metal-insulator-metal capacitor - The present invention discloses a method of making a multi-layer structure for metal-insulator-metal capacitors, in which, a bottom electrode plate layer is formed on a substrate, wherein a Ti/TiN layer serving as a top anti-reflection coating (top ARC) of the bottom electrode plate layer including a titanium layer and a titanium nitride layer formed on the titanium layer is formed using a first and a second physical vapor deposition (PVD) processes at a temperature ranging from 25 to 400° C., and then a first capacitor dielectric layer, a middle electrode plate layer, a second capacitor dielectric layer, and a top electrode plate layer are formed on the bottom electrode plate layer in an order from bottom to top. | 2010-11-04 |
20100279485 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. A first contact plug is formed in a first insulating film. A barrier film is formed on the first insulating film. A second insulating film is formed on the barrier film. A support film is formed on the second insulating film. A first electrode is formed so as to penetrate the support film and the second insulating film. The first electrode is electrically connected to the first contact plug. A portion of the support film is removed. A remaining portion of the support film mechanically supports the first electrode. The second insulating film is removed by a wet etching to expose an outside surface of the first electrode while the barrier film prevents the first insulating film from being etched. At least one of the barrier film and the support film is formed by using high density plasma chemical vapor deposition. | 2010-11-04 |
20100279486 | NONVOLATILE MEMORY HAVING CONDUCTIVE FILM BETWEEN ADJACENT MEMORY CELLS - A floating gate MOS transistor having a conductive floating gate electrode insulated from a semiconductor material having a main surface by a gate dielectric layer. At least one isolation region formed lateral to the gate electrode. An evacuation is formed in the isolation region and beneath the main surface of the semiconductor material layer. A conductive material fills the evacuation. A conductive control gate electrode is formed above the floating gate electrode. The floating gate electrode is laterally aligned to at least one isolation region. | 2010-11-04 |
20100279487 | METHOD FOR TRANSFERRING A LAYER FROM A DONOR SUBSTRATE ONTO A HANDLE SUBSTRATE - The invention relates to a method for transferring a layer from a donor substrate onto a handle substrate wherein, after detachment, the remainder of the donor substrate is reused. To get rid of undesired protruding edge regions which are due to the chamfered geometry of the substrates, the invention proposes to carry out an additional etching process before detachment occurs. | 2010-11-04 |
20100279488 | Method for Preparing SOI Substrate Having Backside Sandblasted - Provided is a method of preparing an SOI substrate having a backside roughened which the SOI substrate has a reduced number of defects in a silicon layer at the front surface in spite of sandblasting having been applied to the backside of the SOI substrate. Specifically provided is the method comprising the steps of: etching 10 nm or more of a surface of a silicon film of an SOI substrate; sandblasting a backside of the SOI substrate with protective tape attached to the etched surface of the silicon film, the back side being the other side of the SOI substrate from the etched surface; removing the protective tape after the sandblasting; and polishing and cleaning a silicon film surface from which the protective tape has been removed. | 2010-11-04 |
20100279489 | Semiconductor bond pad patterns and method of formation - In a semiconductor wafer, the polyimide film underneath a power metal structure is partially etched to create corresponding surface depressions of the conformal top power metal. The depressions at the surface of power metal are visible under optical microscopy. Arrangement of the depressions in a pattern facilitates the alignment of probe needles, set-up of automated wire bonding and microscopic inspection for precise alignment of wire bonds. | 2010-11-04 |
20100279490 | METHODS AND APPARATUS FOR LASER SCRIBING WAFERS - A method for singulating dies from a wafer includes laser scribing a continuous line on each side of the die, and laser ablating an area adjacent the laser scribed continuous line on each side of the die. The laser ablations in the area adjacent the laser scribed continuous line on each side of the die being spaced from one another. The method also includes sawing the laser abated area adjacent the continuous line. A method for singulating dies from a wafer includes laser scribing a first continuous line, laser scribing a second continuous line spaced apart from the first continuous line, and laser scribing a third continuous line. The third continuous line positioned between the first continuous line and the second continuous line. The third continuous line overlaps the second continuous line and the third continuous line. | 2010-11-04 |
20100279491 | DIE ATTACH FILM-PROVIDED DICING TAPE AND PRODUCTION PROCESS OF SEMICONDUCTOR DEVICE - The present invention provides a die attach film-provided dicing tape, which includes a dicing tape, a supporting tape and a die attach film laminated in this order, wherein the supporting tape is a tape having a self-rolling peelability, and a process for producing a semiconductor device by using the die attach film-provided dicing tape. | 2010-11-04 |
20100279492 | Method of Fabricating Upgraded Metallurgical Grade Silicon by External Gettering Procedure - Upgraded metallurgical grade silicon (UMG-Si) is fabricated by a ‘green’ (environmental protected) external gettering procedure. Impurities concentration of the fabricated UMG-Si is reduced for 100 times than its source material. The UMG-Si obtained has a purity ratio reaching 4N to 6N. Thus, substrates made of the UMG-Si can be used in solar cells and related photoelectrical applications. | 2010-11-04 |
20100279493 | DOPING OF SEMICONDUCTOR LAYER FOR IMPROVED EFFICIENCY OF SEMICONDUCTOR STRUCTURES - A system and method for intentional doping, including variable doping, within a semiconductor structure for improved efficiency is described. One embodiment includes a method for forming a semiconductor structure, the method comprising forming a first semiconductor layer, wherein the first semiconductor layer comprises a first semiconductor material, and forming a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer comprises a second semiconductor material, wherein the second semiconductor material is an oppositely-typed semiconductor material from the first semiconductor material, and wherein the second semiconductor layer comprises a first region adjacent to the first semiconductor layer, wherein the first region comprises second semiconductor material, and a second region adjacent to the first region, wherein the second region comprises intentionally doped second semiconductor material to increase a built-in potential of the semiconductor structure. | 2010-11-04 |
20100279494 | Method For Releasing a Thin-Film Substrate - The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate is formed on top of the porous silicon layer. The middle porous silicon layer is then selectively etched to separate the TFSS and semiconductor template. The disclosed advanced etching chemistries and etching methods achieve selective etching with minimal damage to the TFSS and template. | 2010-11-04 |
20100279495 | METHOD OF FORMING p-TYPE GALLIUM NITRIDE BASED SEMICONDUCTOR, METHOD OF FORMING NITRIDE SEMICONDUCTOR DEVICE, AND METHOD OF FORMING EPITAXIAL WAFER - A method of forming a p-type gallium nitride based semiconductor without activation annealing is provided, and the method can provide a gallium nitride based semiconductor doped with a p-type dopant. A GaN semiconductor region | 2010-11-04 |
20100279496 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region. | 2010-11-04 |
20100279497 | Method for Manufacturing Semiconductor Device with a Recessed Channel - A semiconductor device having a recessed channel and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate formed with an isolation layer defining an active region including a channel region and a junction region, a recessed trench including a top trench formed within the channel region of the semiconductor substrate and a bottom trench formed from a bottom surface of the top trench with a width narrower than the top trench, and a gate stack overlapping the recessed trench and extending across the active region. | 2010-11-04 |
20100279498 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MAKING THE SAME - A method for forming a semiconductor structure is provided. The method includes providing a substrate; forming a dielectric layer on the substrate; forming a conductor pattern on a main surface of the dielectric layer, the conductor pattern having a top surface and sidewalls; and performing a selective atomic layer deposition (ALD) process to selectively deposit a conformal metal layer onto the top surface and sidewalls of the conductor pattern, but without depositing onto the main surface of the dielectric layer substantially. | 2010-11-04 |
20100279499 | METHOD FOR MANUFACTURING A MEMORY - A method for manufacturing a memory includes first providing a substrate with a horizontally adjacent control gate region and floating gate region which includes a sacrificial layer and sacrificial sidewalls, removing the sacrificial layer and sacrificial sidewalls to expose the substrate, forming dielectric sidewalls adjacent to the control gate region, forming a floating gate dielectric layer on the exposed substrate and forming a floating gate layer adjacent to the dielectric sidewalls and on the floating gate dielectric layer. | 2010-11-04 |
20100279500 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device having increased reliability includes a fuse region and a monitoring region. Fuses are located on an insulation film in the fuse region and are exposed through fuse windows. A monitoring pattern is located on the insulation film in the monitoring region. The monitoring pattern includes sub-patterns that are exposed through a monitoring window. | 2010-11-04 |
20100279501 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - After a plurality of pads ( | 2010-11-04 |
20100279502 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING A THIN FILM PROBE SHEET FOR USING THE SAME - A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested. | 2010-11-04 |
20100279503 | Method for Producing an Electrically Conductive Connection - A method for producing an electrically conductive connection between a first surface of a semiconductor substrate and a second surface of the semiconductor substrate includes producing a hole, forming an electrically conductive layer that includes tungsten, removing the electrically conductive layer from the first surface of the semiconductor substrate, filling the hole with copper and thinning the semiconductor substrate. The hole is produced from the first surface of the semiconductor substrate into the semiconductor substrate. The electrically conductive layer is removed from the first surface of the semiconductor substrate, wherein the electrically conductive layer remains at least with reduced thickness in the hole. The semiconductor substrate is thinned starting from a surface, which is an opposite surface of the first surface of the semiconductor substrate, to obtain the second surface of the semiconductor substrate with the hole being uncovered at the second surface of the semiconductor substrate. | 2010-11-04 |
20100279504 | INTEGRATED CIRCUIT PACKAGE SYSTEM INCLUDING HONEYCOMB MOLDING - A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts. | 2010-11-04 |
20100279505 | METHOD FOR FABRICATING PATTERNS ON A WAFER THROUGH AN EXPOSURE PROCESS - A method for forming patterns on a wafer includes forming a fence having a sloped face in an edge portion of the wafer. The sloped face is direct to an inside of the wafer. A first photoresist layer is formed which extends to cover the fence on the wafer. First photoresist patterns are formed by performing a first exposure and development on the first photoresist layer. An etch process is performed using the first photoresist patterns and the fence as an etch mask. The fence is formed by selectively exposing a negative resist using a light shielding blade, and at this time, the first photoresist layer is formed including a positive resist. | 2010-11-04 |
20100279506 | Polishing silicon carbide - The invention provides a method of chemically-mechanically polishing a substrate comprising at least one layer of single crystal silicon carbide. The method utilizes a chemical-mechanical polishing composition comprising a liquid carrier, an abrasive, a catalyst comprising a transition metal composition, and an oxidizing agent. | 2010-11-04 |
20100279507 | Method for chemical mechanical polishing a substrate - A method for chemical mechanical polishing of a substrate, comprising: providing a substrate, wherein the substrate comprises silicon dioxide; providing a chemical mechanical polishing composition, wherein the chemical mechanical polishing composition comprises: water, an abrasive; a diquaternary cation according to formula (I); and optionally a quaternary alkylammonium compound; providing a chemical mechanical polishing pad; creating dynamic contact at an interface between the chemical mechanical polishing pad and the substrate; and dispensing the chemical mechanical polishing composition onto the chemical mechanical polishing pad at or near the interface between the chemical mechanical polishing pad and the substrate; wherein the chemical mechanical polishing composition has a pH of 2 to 6; wherein the chemical mechanical polishing composition exhibits a silicon dioxide removal rate of at least 1,500 Å/min. | 2010-11-04 |
20100279508 | METHOD FOR REDUCING AMINE BASED CONTAMINANTS - Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing. | 2010-11-04 |
20100279509 | Silicon-based hardmask composition and process of producing semiconductor integrated circuit device using the same - A silicon-based hardmask composition, including an organosilane polymer represented by Formula 1: | 2010-11-04 |
20100279510 | ETCHING METHOD AND RECORDING MEDIUM - An etching method by which a fluorine-added carbon film formed on a substrate is etched by plasma includes a first step of etching the fluorine-added carbon film with plasma of an oxygen-containing processing gas, and a second step of etching the fluorine-added carbon film with plasma of a fluorine-containing processing gas. | 2010-11-04 |
20100279511 | Wafer Through Silicon Via Forming Method And Equipment Therefor - Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads. | 2010-11-04 |
20100279512 | PLASMA PROCESSING APPARATUS AND METHOD FOR PLASMA-PROCESSING SEMICONDUCTOR SUBSTRATE - A plasma processing apparatus includes an antenna unit for generating plasma by using microwaves as a plasma source in such a way that a first region having a relatively high electron temperature of plasma, and a second region having a lower electron temperature of plasma than the first region are formed in a chamber, a first arranging means for arranging a semiconductor substrate W in the first region, a second arranging means for arranging the semiconductor substrate in the second region, and a plasma generation stopping means for stopping the generation of plasma of a plasma generating means, while the semiconductor substrate is arranged in the second region. | 2010-11-04 |
20100279513 | Systems and Methods for Nanowire Growth and Manufacturing - The present invention is directed to compositions of matter, systems, and methods to manufacture nanowires. In an embodiment, a buffer layer is placed on a nanowire growth substrate and catalytic nanoparticles are added to form a catalytic-coated nanowire growth substrate. Methods to develop and use this catalytic-coated nanowire growth substrate are disclosed. In a further aspect of the invention, in an embodiment a nanowire growth system using a foil roller to manufacture nanowires is provided. | 2010-11-04 |
20100279514 | MULTILAYER DIELECTRIC - A method forms a first inorganic dielectric layer having a first concentration of defects and a second inorganic dielectric layer in contact with a first layer and having a second lesser concentration of defects. | 2010-11-04 |
20100279515 | ATOMIC LAYER DEPOSITION - A method for forming an atomic deposition layer is provided, which includes: (a) performing a first water pulse on a substrate; (b) performing a precursor pulse on the hydroxylated substrate, wherein the precursor reacts with the hydroxyl groups and forms a layer; (c) purging the substrate with an inert carrier gas; (d) exposing the layer to a second water pulse for at least about 3 seconds so that the layer has a minimum of 70 percent of surface hydroxyl groups thereon; (e) purging the layer with the inert carrier gas; and (f) repeating steps (b) to (e) to form a resultant atomic deposition layer. | 2010-11-04 |
20100279516 | APPARATUS AND METHOD OF ALIGNING AND POSITIONING A COLD SUBSTRATE ON A HOT SURFACE - Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers. | 2010-11-04 |
20100279517 | INTERCONNECTION SYSTEM INCORPARATED WITH MAGNETIC ARRANGEMNT - An electrical connector assembly includes a first connector and a second connector each defining a mating end of a regular polygon mating with each other. Each regular polygon defines a centre, an imaginary circle around the centre and a plurality of vertices at the imaginary circle. A plurality of pins are located at the mating ends which composed of one first pin at the centre of the first connector, two second pins at least fulfilling with one half of the vertices and arranged at adjacent vertices in turn, one third pin at the centre of the second connector and two forth pins at the vertices respectively in a condition that said two forth pins spaced from each other with a largest distance. | 2010-11-04 |
20100279518 | ELECTRONIC HUB - Disclosed herein are embodiments on an electronic hub configured to connect electronic devices. In certain embodiments, an electronic hub has a first configuration in which various inputs and outputs are covered and are not available for connecting to other devices. In a second configuration the various inputs and outputs are exposed and are available to connect to electronic devices. In certain embodiments, a cable may wrap around a hub body in the first configuration, thus covering the ports when not in use. In other embodiments, the ports may be disposed within a moveable member. In a first configuration, one or more ports in the moveable member may be covered, while in the second configuration, the moveable member may be moved to expose the one or more ports. Certain embodiments include a reset button that is operable to reset an electronic device connected to the hub. | 2010-11-04 |
20100279519 | Assembly and System of Datacommunication Cables and Connectors - A datacommunication interconnection system includes (a) an extension trunk cable-connector assembly and (b) a trunk cable-connector assembly. The extension trunk cable-connector assembly comprises: a first cable including a plurality of first subunits, each of the first subunits comprising a plurality of twisted pairs of conductors; a jack attached to one end of the cable; and a plug attached to an opposite end of the cable. Each of the jack and the plug includes a contact for each of the conductors of the cable. The trunk cable-connector assembly comprises: a second cable including a plurality of second subunits, each of the second subunits comprising a plurality of twisted pairs of conductors; a plug attached to one end of the second cable and connected with the jack of the extension trunk cable; and a plurality of RJ-45 connectors attached to subunits at an opposite end of the second cable. | 2010-11-04 |
20100279520 | STORAGE CARD SOCKET FOR BIDIRECTIONAL ELECTRICAL CONNECTION - A storage card socket for a bidirectional electrical connection includes a plastic base, a connection slot, a metal casing, at least one row of lower contacts and at least one row of upper contacts. The connection slot disposed at a front end of the plastic base has an inserting port and opposite top and bottom surfaces, and may be connected to a plug of a storage card. The metal casing covers the plastic base and has an opening corresponding to the inserting port of the connection slot. The lower contacts are separately arranged in the connection slot and are directed to the top surface of the connection slot. The upper contacts are separately arranged in the connection slot and are directed to the bottom surface of the connection slot. | 2010-11-04 |
20100279521 | LAND GRID ARRAY (LGA) INTERPOSER UTILIZING METAL-ON-ELASTOMER HEMI-TORUS AND OTHER MULTIPLE POINTS OF CONTACT GEOMETRIES - A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. | 2010-11-04 |
20100279522 | CONNECTOR AND CIRCUIT BOARD HAVING THE SAME - A connector and a circuit board having the same are disclosed. The circuit board includes a body, multiple electronic components and a connector. The electronic components are disposed on the body. The connector includes a base, a side wall, multiple terminals, a cover and a connecting element. The base is disposed on the body. The side wall is connected to the base and surrounds the base. The side wall and the base define a recess. The terminals pass through the base and are located in the recess, and are electrically connected to the body. The connecting element is connected between the side wall and the cover. | 2010-11-04 |
20100279523 | CONNECTING ELEMENT FOR ELECTRIC CONDUCTORS WITH A PRINTED CIRCUIT BOARD - In order to separably connect an electric conductor ( | 2010-11-04 |
20100279524 | CONNECTOR PIN AND METHOD - An electrical connector and method includes a connector and a conforming element proximate to or in contact with the mating end of the connector so as to prevent distortion of a matable end. The matable end of the connector may be of a female or male type and may be of a post, tube, blade, pin, or other configuration. An element made of conforming material, for example, an elastomer, epoxy or rubber type material, is configured and positioned in contact with the matable end of the connector, providing support during assembly to prevent distortion of the matable end. The conforming element may be rectangular, wedge, cylindrical, conical, annular, or of another configuration as required to provide support to the connector pin. The conforming element may be fastened with an adhesive to the matable end to further prevent distortion. | 2010-11-04 |
20100279525 | Reorientable Electrical Receptacle - There is provided systems and methods for a reorientable electrical outlet. In one embodiment, a system includes a housing configured to be coupled to an electrical power source, the housing having a first rotation stop, and an electrical plug receptacle, mountable within the housing, the insert having a second rotation stop, the first and second rotation stops configured to cooperate with each other to limit rotation of the insert within the aperture at a number of degrees, wherein the plug receptacle is configured to receive an electrical plug. | 2010-11-04 |
20100279526 | A STORAGE DEVICE WITH A CASING WITH A PLUG MOVABLE PARALLEL TO A SECOND PLUG IN THE CASING - A storage device having detachable multiple-in-one connector has a casing with one opening; a multiple-in-one plug part mounted inside the casing, exposed beyond the opening and having first and second plug assemblies detachably stacked with a gap formed therebetween; a movable assembly mounted inside the casing, connected with the second plug assembly and penetrating through the casing; and a circuit board mounted inside the casing and electrically connected with the first and the second plug assemblies, having an automatic interface switching procedure and a plurality of interface connecting procedures, having a control circuit determining the plug assembly currently in use, and selecting the interface connecting procedure corresponding to the plug assembly currently in use. Due to the multiple-in-one design, the size of the storage device can be reduced, and the storage device can be selectively plugged in a multiple-in-one or single socket connector. | 2010-11-04 |
20100279527 | ELECTRONIC DEVICE - An electronic device includes a housing having a sidewall, a socket assembled in the housing, and a protection cover slidably assembled on the sidewall of the housing. The sidewall of the housing defines a sliding slot and a socket hole. The socket is exposed by the socket hole. The protection cover includes a main body, a latching portion and a sliding block connecting the main body and the latching portion. The main body and the latching portion are respectively positioned on opposite sides of the sidewall. The sliding block is slidably engaged in the sliding slot, thus enabling the main body to slide between a first and a second positions to expose or cover the socket. | 2010-11-04 |
20100279528 | STACKED CARD EDGE CONNECTOR ASSEMBLY HAVING EJECTOR FOR REMOVING INSERTED CARDS SIMULTANEOUSLY - A card edge connector assembly includes a first connector comprising a first insulative housing defining a first central slot expanding along a transverse direction and a pair of first side arms disposed at opposite ends thereof. A plurality of first terminals are arranged at opposite sides of the first central slot. A second connector stacked with the first connector includes a second insulative housing defining a second central slot expanding along the transverse direction and a pair of second side arms disposed at opposite ends thereof. A plurality of second terminals are arranged at opposite sides of the second central slot. An ejecting device has a first and a second ejecting portions thereon for respectively projecting into the first and second central slots, therefore the ejecting device can release two cards at one time. | 2010-11-04 |
20100279529 | ELECTRICAL CONNECTOR ASSEMBLY WITH A DETACHABLE WIRE ROUTING COVER - An electrical connector assembly includes a housing body and a wire routing cover. The housing body having a box-shaped configuration has a plurality of terminal-receiving holes formed therethrough, a pair of rail-receiving channels formed into opposing side walls and at least one latch projection. The wire routing cover includes a base panel with a pair of rail members and at least one latch element attached to the base panel. The base panel has a plurality of wire routing holes formed therethrough. Upon releasably connecting the housing body and the wire routing cover together, respective ones of the pair of rail-receiving channels slidably receive at least a portion of the respective ones of the pair of rail members, the at least one latch projection is releasably captured by the at least one latch element and the plurality of terminal-receiving holes and the plurality of wire routing holes register with one another. | 2010-11-04 |
20100279530 | Snap-in Electrical Connector with Locking Cam and Method of Use - A connector assembly including a connector body with a locking cam defined on an external surface. In a method of use the locking cam cooperates with a perimeter of a knock-out hole into which the connector is to be inserted. During insertion of the connector body the locking cam engages the knock-out hole and deforms a retainer ring so as to permit further insertion. Once the connector body is fully seated, the locking cam cooperates with a locking tang on the retainer ring to hold the connector assembly together. | 2010-11-04 |
20100279531 | CARD EDGE CONNECTOR ASSEMBLY WITH ROTATABLE CARD EJECTING DEVICE - A card edge connector includes an insulative housing defining a central slot expanding along a transverse direction with a plurality of contacts disposed therein, and a pair of side arms disposed at opposite ends thereof. A pair of card ejecting devices are assembled on the side arms, each comprising an ejecting member attached to the side arm and an operation member which can rotate in a plane perpendicular to the card edge connector. The ejecting member comprises a block portion projecting into the central slot and moving along a front-to-rear direction perpendicular to the transverse direction by the urging of the operation member. | 2010-11-04 |
20100279532 | OUTLET AND CONNECTOR - An outlet ( | 2010-11-04 |
20100279533 | ELECTRICAL CONNECTOR WITH EXPANDED COVER - An electrical connector for electrically connecting a module to a printed circuit board, comprises an insulative housing receiving the module, a plurality of contacts received in the insulative housing and a cover pivotally assembled to the insulative housing. The cover presses upon the module and extends beyond a rear end of the insulative housing to further limit or press a part of the module exposed outside the insulative housing. The electrical connector can reliably retain the module. | 2010-11-04 |
20100279534 | HEADER CONNECTORS WITH RIGID LATCHES - This approach generally pertains to a header connector with rigid latches. The connector includes columns with column cavities therein and latching mechanisms having latch beams and latching ends, with a plurality of mating contacts with mounting pins affixed to a dielectric housing. A harness is securable to the header connector generally between the latching mechanisms. The harness is insertable and removable. The harness provides easy access to a tool that can facilitate extraction of the harness from the header connector. | 2010-11-04 |
20100279535 | LOCKING APPARATUS FOR ELECTRICAL CONNECTORS - An apparatus suitable for locking two electrical connectors together is provided, the apparatus comprising: a first assembly comprising a locking member having a radially extending element; a collar with a through hole for receiving the locking member; and a spring positioned between the locking member and the collar, and a second assembly comprising a retaining member having a guide channel such that in use the radially extending element of the locking member is adapted to cooperate with the guide channel to form a bayonet type connection and lock the first assembly and second assembly together. | 2010-11-04 |
20100279536 | Low Resistance Connector For Printed Circuit Board - An electrical connector has first and second connector bodies. The first connector body has an inclined surface and the second connector body has arms that correspond to the inclined surfaces. At the end of the inclined surfaces are generally flat portions forming a ledge that prevent the connector bodies from separating. To unmate the connector bodies, one connector body is rotated relative to the other, causing the arms to move from the generally flat portion to the outer surface of the second connector to allow them to be moved axially away from one another. | 2010-11-04 |
20100279537 | Cord and Cable Fastening System and Method - A system and method for providing cord and cable fastening (CCF) so Industrial, Commercial and Home users (ICAHUs) can assure that cords and cables, including but not limited to electrical cords, cannot be accidentally disconnected or unplugged. The system and method allows ICAHUs to work safely and efficiently and to avoid cords and cables that may accidentally disconnect or unplug themselves in the course of everyday use. ICAHUs can easily apply collar mechanisms to the end of cords or cables aft of said cord's respective plug ends or cables ends, and then subsequently attach said collar mechanisms together using a series of collar ties that are adjustable in length and tension, and tie connectors which facilitate said adjustment of said collar ties. The method comprises a system in which cords and cables, including but not limited to standard electrical cords may be fastened together then held tightly together without easily becoming accidentally unplugged. Said system and method also supports securing said cord or cable to itself, to another, or to an object to secure and store either before or after said cords and cables are used. | 2010-11-04 |
20100279538 | GROUND CONNECTOR - A ground connector comprises facing pieces one ends of which are interconnected via a connecting section, a pair of holding pieces formed by folding back the other ends defining an opening into the space defined by the facing pieces, a displacement section connected between the internal surfaces if the facing pieces and forming a V shape projecting toward the opening, and a piercing piece. A ground wire is inserted into a ground-wire insertion space, the ground connector is attached to an end edge of a vehicle body panel through the opening, the insertion force of the vehicle body panel causes the vehicle body panel to push the displacement section toward the connecting section thus to reverse the projection of the displacement section toward the connecting section and the piercing piece pierces the insulation cover of the ground wire to come into contact with the conductor of the ground wire. | 2010-11-04 |
20100279539 | LIGHTING CONNECTOR DEVICES AND USES THEREOF - A lighting connector which includes (a) an upper housing having plural connector pins, and one or more interlocking grooves; and (b) a lower housing, the lower housing having a plurality of connector pin guide holes, and one or more interlocking tongue portions. The lower housing is connectable with the upper housing to form the lighting connector by coupling at least one of the one or more interlocking grooves with at least one of the one or more interlocking tongue portions, and by coupling at least one of the plural connector pins with at least one of the connector pin guide holes. | 2010-11-04 |
20100279540 | WIRE ETC, CONNECTORS - A connector or locking device for wires (or wire ropes) W has a body ( | 2010-11-04 |
20100279541 | WATERPROOF CONNECTOR FOR FLEXIBLE SUBSTRATE - A waterproof connector for a flexible substrate includes: a flexible substrate which includes an insulating film with a conductive pattern formed thereon; a connection terminal joined to the conductive pattern at a terminal section of the flexible substrate; a housing which accommodates the connection terminal; a retainer which includes a vertically assembled pair of members, a forward end thereof holding the connecting section of the conductive pattern and the connection terminal and a rear end thereof surrounding the flexible substrate; a hot-melt adhesive provided on an inner circumference of the retainer at non-joint areas with the flexible substrate and provided on an outer circumference of the retainer so as to make the flexible substrate and the retainer adhere closely to each other; engaging member provided in the outer circumference of the retainer; and receiving member provided in the housing. The engaging member and the receiving member are engaged together to fix the retainer and the housing. | 2010-11-04 |
20100279542 | METHODS AND KITS FOR COVERING ELECTRICAL CABLES AND CONNECTIONS - A method for forming a connection assembly includes: forming an electrical connection between first and second electrical cables, the first cable including a first primary conductor and a first neutral conductor, the second cable including a second primary conductor and a second neutral conductor; and providing an integral, unitary cover assembly. The cover assembly includes: an inner elastomeric sleeve defining a cable passage to receive the electrical connection and the first and second primary conductors; and an outer elastomeric sleeve surrounding the inner sleeve. The method further includes: mounting the cover assembly on the cables such that the electrical connection and the first and second primary conductors extend through the cable passage; installing a first protective sleeve on a first neutral segment of the first neutral conductor; routing the first neutral segment and the first protective sleeve exteriorly of the outer sleeve to a second neutral segment of the second neutral conductor; and mechanically and electrically coupling the first and second neutral segments to thereby provide electrical continuity between the first neutral conductor and the second neutral conductor. | 2010-11-04 |
20100279543 | COLD-SHRINK SEPARABLE CONNECTOR - A cold-shrink article having a chamber with an enlarged interior section to prevent the collapse of an end of a support core placed in the chamber. | 2010-11-04 |
20100279544 | RUGGED LOW LIGHT REFLECTIVITY ELECTRICAL CONTACT - The Low Reflectivity Contact has a low coefficient of light reflection, is rugged with respect to harsh ambient environmental conditions, provides a low resistance electrical connection, and is adapted for use in quick-connect applications. Light reflectivity of the contact is minimized by the use of a conductive mesh that is used to implement the electrical contact. The weave density and wire diameter of the conductive mesh maximizes the attenuation of reflected light in the visible spectrum, yet maintains high electrical conductivity and a lack of sensitivity to contamination via the choice of materials used to implement the Low Reflectivity Contact. | 2010-11-04 |