44th week of 2011 patent applcation highlights part 41 |
Patent application number | Title | Published |
20110269237 | CATALYTICALLY-GENERATED GAS IN HYDROCARBON BEARING SOURCE ROCKS - The present disclosure is directed to assaying rock samples (e.g., core samples) for the presence of catalytically-generated gases, such as methane for example. According to one or more aspects of the present disclosure, a method for assaying a rock sample comprises sealing a carbonaceous rock sample in a container having an atmosphere and assaying for a quantity of catalytically-generated gas in the sealed container. The method may comprise generating the catalytically-generated gas in response to a catalytic reaction between the carbonaceous material in the carbonaceous rock sample and a low-valent transition metal that is present in the carbonaceous rock sample. The catalytic reaction may occur in a static atmosphere of the sealed container. | 2011-11-03 |
20110269238 | ENHANCED SCHEDULING SAMPLE PROCESSING SYSTEM AND METHODS OF BIOLOGICAL SLIDE PROCESSING - A sample processing system | 2011-11-03 |
20110269239 | Apparatus for Automatically Performing Analyses - The present invention relates to an apparatus and a method for automatically performing chemical, biochemical and biological analyses. | 2011-11-03 |
20110269240 | IMMOBILIZING CHEMICAL OR BIOLOGICAL SENSING MOLECULES ON SEMI-CONDUCTING NANOWIRES - The present invention is drawn toward a chemical or biological sensor that can comprise a semi-conducting nanowire and a chemical or biological sensing molecule tethered to the semi-conducting nanowire through a spacer group including a hydrophilic reactive group. In one embodiment, the semi-conducting nanowire can be part of an array of like or similar semi-conducting nanowires. Electrical leads can provide an electrical current to the array, and a signal measurement apparatus can be electrically coupled to the array, and can be configured for detecting changes in the electrical current of the array. | 2011-11-03 |
20110269241 | Methods And Kits For The Determining The Presence Or Absence Of Cyanobacteria Toxins - Embodiments of the present invention are directed to kits and methods for the detection of toxins produced by cyanobacteria. The methods and kits feature sample preparation steps with weak cationic and anionic exchange resins and small particle analytical columns operating at 4,000 to 15,000 psi. | 2011-11-03 |
20110269242 | TIME TEMPERATURE INDICATOR COMPRISING INDOLENIN BASED SPIROPYRANS - The present invention relates to time-temperature indicator (TTI) systems comprising indolenin based spiropyrans containing a cyclohexyl residue of formula (I), a method of manufacturing the time temperature indicator system, and a method of determining the time temperature history of perishable goods using the system. Moreover, the invention relates to a matrix selected from a printing ink or printing ink concentrate, paint, varnish, label, packaging material, and polymeric material comprising the system. | 2011-11-03 |
20110269243 | SYSTEMS AND METHODS RELATED TO OPTICAL NANOSENSORS COMPRISING PHOTOLUMINESCENT NANOSTRUCTURES - Systems and methods related to optical nanosensors comprising photoluminescent nanostructures are generally described. | 2011-11-03 |
20110269244 | LIGAND-DIRECTED COVALENT MODIFICATION OF PROTEIN - The present invention relates to enzyme inhibitors. More specifically, the present invention relates to ligand-directed covalent modification of proteins; method of designing same; pharmaceutical formulation of same; and method of use. | 2011-11-03 |
20110269245 | METHODS AND KITS FOR DETECTION OF TOXEMIA - Various embodiments of methods and kits are disclosed for prognosis, detection, and/or diagnosis of toxemia in a subject patient by analyzing an aliquot of the subject patient's extracellular fluid (e.g., blood serum) that contains carrier proteins. | 2011-11-03 |
20110269246 | MEASURING LEVELS OF FRATAXIN - This document relates to methods and materials involved in measuring levels of a frataxin polypeptide present in a biological sample. For example, methods and materials related to the use of anti-frataxin antibody-bound microspheres and biotinylated anti-frataxin antibodies to measure the levels of a frataxin polypeptide in a biological sample from a mammal (e.g., a newborn human) are provided. | 2011-11-03 |
20110269247 | MEASUREMENT KIT AND AN IMMUNOCHROMATOGRAPHY METHOD - It is an object of the present invention to provide a measurement kit for developing a first developing solution and a second developing solution from different directions to suppress background noise, and an immunochromatography kit. The present invention provides a measurement kit, which comprises a first developing member for supplying a first developing solution and a second developing member for supplying a second developing solution, wherein the developing direction of the first developing solution is allowed to intersect with the developing direction of the second developing solution, so that development is carried out by developing the first and second developing solutions in different developing directions, and a water absorbent portion is established on the downstream of each of the developing directions. | 2011-11-03 |
20110269248 | BIO-MARKERS FOR DIAGNOSING DIABETIC RETINOPATHY - Disclosed herein are bio-markers for diagnosing diabetic retinopathy, a use of proteins, whose expression level down-regulated or up-regulated in the tears of a non-proliferative diabetic retinopathy (NPDR) patient, as bio-markers for diagnosing diabetic retinopathy, and a composition and kit for diagnosing diabetic retinopathy comprising antibodies against said proteins. | 2011-11-03 |
20110269249 | DISTRIBUTION OF PARTICLES IN CHAMBER BY APPLICATION OF MAGNETIC FIELD - The present invention relates to a device and a method for clustering and subsequently distributing a plurality of paramagnetic particles in a small volume liquid in a chamber, said chamber having a first wall and an opposite second wall, said method comprising the steps of a) providing a liquid comprising the plurality of paramagnetic particles, b) subjecting the paramagnetic particles to a first magnetic field by means of a first field generating means having first and second mutually spaced opposite poles and defining a first pole axis extending between the poles, the field generating means being arranged relative to the first wall so that the first pole axis (a | 2011-11-03 |
20110269250 | GROWTH METHOD OF FE3N MATERIAL - A kind of growth method of Fe | 2011-11-03 |
20110269251 | Spin Transfer Torque Memory Device Having Common Source Line and Method for Manufacturing the Same - A spin transfer torque memory device and a method for manufacturing the same. The spin transfer torque memory device comprises a MRAM cell using a MTJ and a vertical transistor. A common source line is formed in the bottom of the vertical transistor, thereby obtaining the high-integrated and simplified memory device. | 2011-11-03 |
20110269252 | METHOD FOR POSITIONING SPACERS FOR PITCH MULTIPLICATION - Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed. | 2011-11-03 |
20110269253 | MANUFACTURING THIN FILM TRANSISTOR ARRAY PANELS FOR FLAT PANEL DISPLAYS - A thin film transistor array panel for a flat panel display includes a substrate, a first signal line formed on the substrate, a second signal line intersecting and insulated from the first signal line, a switching element having a first terminal connected to the first signal line, a second terminal connected to the second signal line, and a third terminal, a pixel electrode connected to the third terminal of the switching element, and first and second light blocking members extending parallel to the second signal line, each being disposed on an opposite side of and partially overlapping an respective edge of the second signal line, an interval between the first and second light blocking members being in a range of from more than 1.5 μm to less than 4 μm. The array panel prevents light leakage from the display and improves its transmittance, aperture ratio and color reproducibility. | 2011-11-03 |
20110269254 | THIN-FILM TRANSISTOR SUBSTRATE, METHOD OF MANUFACTURING SAME AND DISPLAY APPARATUS HAVING SAME - Contamination is blocked from material of a color filter layer provided on a thin-film transistors (TFT) supporting substrate by sealing over the color filter layer with an inorganic insulating layer. During mass production manufacture, a plasma surface cleaning step is employed after the color filter layer is deposited but before the inorganic insulating layer is deposited. A low temperature CVD process is used to deposit the inorganic insulating layer with a substantially uniform thickness conformably over the color filter layer including conformably into openings provided through the color filter layer. | 2011-11-03 |
20110269255 | Compositions and Methods for Manufacturing Light-emissive Devices - A composition adapted for use in the manufacture of an organic light-emissive device by passing the composition through one or more openings under pressure to deposit the composition, the composition comprising: a semi-conductive organic host material; a luminescent metal complex; and a first solvent, wherein the first solvent has a structure: | 2011-11-03 |
20110269256 | VAPOR DEPOSITION APPARATUS AND PROCESS FOR CONTINUOUS INDIRECT DEPOSITION OF A THIN FILM LAYER ON A SUBSTRATE - An apparatus and related process are provided for vapor deposition of a sublimated source material as a thin film on a photovoltaic (PV) module substrate. A deposition head is configured for sublimating a source material supplied thereto. The sublimated source material condenses onto a transport conveyor disposed below the deposition head. A substrate conveyor is disposed below the transport conveyor and conveys substrates in a conveyance path through the apparatus such that an upper surface of the substrates is opposite from and spaced below a lower leg of the transport conveyor. A heat source is configured adjacent the lower leg of the transport conveyor. The source material plated onto the transport conveyor is sublimated along the lower leg and condenses onto to the upper surface of substrates conveyed by the substrate conveyor. | 2011-11-03 |
20110269257 | Method and System for Large Scale Manufacture of Thin Film Photovoltaic Devices Using Multi-Chamber Configuration - A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. That is, the method includes in-situ monitoring of the physical, electrical, and optical properties of the thin films. These properties are used to determine and adjust process conditions for subsequent processes. | 2011-11-03 |
20110269258 | SOLID-STATE IMAGING DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a solid-state imaging device in which: photo sensor portions are formed in a silicon layer over a substrate, a first conductivity type region being included in the photo sensor portions and a second conductivity type region being formed in the silicon layer implanted from a rear-surface of the solid-state imaging device by ion implantation; a wiring portion is formed above the silicon layer; and a supporting substrate is bonded to the wiring portion, wherein, the solid-state imaging device is configured for receiving incident light via the rear-surface of the solid-state imaging device. | 2011-11-03 |
20110269259 | SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD THEREOF, AND ELECTRONIC DEVICE - A solid-state imaging device which includes a pixel section, a peripheral circuit section, a first isolation region formed with a STI structure on a semiconductor substrate in the peripheral circuit section, and a second isolation region formed with the STI structure on the semiconductor substrate in the pixel section. The portion of the second isolation region buried into the semiconductor substrate is shallower than the portion buried into the semiconductor substrate of the first isolation region, and the height of the upper face of the second isolation region is equal to that of the first isolation region. A method of producing the solid-state imaging device and an electronic device provided with the solid-state imaging devices are also disclosed. | 2011-11-03 |
20110269260 | Consumable Adhesive Layer for Thin Film Photovoltaic Material - A method for forming a thin film photovoltaic device. The method includes providing a transparent substrate comprising a surface region. The method forms a first electrode layer overlying the surface region of the transparent substrate. The method also forms a thin layer of indium material, using a sputtering target of indium material, overlying the first electrode layer to act as an intermediary glue layer to facilitate attachment to the first electrode layer. In a specific embodiment, the method forms a copper material overlying the thin layer of indium material. The method also forms an indium layer overlying the copper material to form a multi layered structure including at least the thin layer of indium material, copper material, and the indium layer. In a preferred embodiment, the multi-layered structure has a first thickness. In a specific embodiment, the method also subjects at least the multi-layered structure to thermal treatment process in an environment containing a sulfur bearing species to form a copper indium disulfide alloy material while consuming substantially all of the indium layer from at least the treatment process of the multi-layered structure. In a preferred embodiment, the copper indium disulfide alloy material comprises an atomic ratio of copper indium ranging from about 1.35 to about 3.00. In a specific embodiment, the copper indium disulfide alloy material has a second thickness of more than two times of the first thickness of the multi-layered structure. The method consumes substantially all of the thin layer of indium material into a portion of the copper indium disulfide alloy material during at least the thermal treatment process. The method causes formation of a copper sulfide material overlying the copper indium disulfide alloy material during at least the thermal treatment process. | 2011-11-03 |
20110269261 | DEVICES AND METHODS OF PROTECTING A CADMIUM SULFIDE FOR FURTHER PROCESSING - Methods for protecting a cadmium sulfide layer on a substrate are provided. The method can include sputtering a cadmium sulfide layer onto a substrate from a cadmium sulfide target at a sputtering pressure (e.g., about 10 mTorr to about 150 mTorr), and sputtering a cap layer directly on the cadmium sulfide layer. The cap layer can be sputtered directly onto the cadmium sulfide layer without breaking vacuum of the sputtering pressure. Methods are also provided for manufacturing a cadmium telluride based thin film photovoltaic device through depositing a cadmium sulfide layer on a substrate, depositing a cap layer directly on the cadmium sulfide layer, heating the substrate to sublimate at least a portion of the cap layer from the cadmium sulfide layer, and then depositing a cadmium telluride layer on the cadmium sulfide layer. | 2011-11-03 |
20110269262 | Method and System for Large Scale Manufacture of Thin Film Photovoltaic Devices Using Multi-Chamber Configuration - A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. That is, the method includes in-situ monitoring of the physical, electrical, and optical properties of the thin films. These properties are used to determine and adjust process conditions for subsequent processes. | 2011-11-03 |
20110269263 | METHOD FOR IMPLANTING IMPURITIES INTO A SUBSTRATE AND METHOD FOR MANUFACTURING A SOLAR CELL USING THE SAME - In a method for implanting impurities into a substrate and a method for manufacturing a solar cell using the method, a substrate is dipped into a first solution including a first impurity, and a laser is irradiated to a first region of the substrate dipped into the first solution is irradiated with laser to implant a first dopant generated from the first impurity into the first region. Accordingly, the first dopant generated from the first impurity is implanted into the substrate at room temperature to improve reliability for implanting the first dopant. | 2011-11-03 |
20110269264 | METHODS FOR FABRICATION OF NANOWALL SOLAR CELLS AND OPTOELECTRONIC DEVICES - A photovoltaic device that includes a substrate and a nanowall structure disposed on the substrate surface. The device also includes at least one layer conformally deposited over the nanowall structure. The conformal layer(s) is at least a portion of a photoactive junction. A method for making a photovoltaic device includes generating a nanowall structure on a substrate surface and conformally depositing at least one layer over the nanowall structure thereby forming at least one photoactive junction. A solar panel includes at least one photovoltaic device based on a nanowall structure. The solar panel isolates such devices from its surrounding atmospheric environment and permits the generation of electrical power. Optoelectronic device may also incorporate a photovoltaic device based on a nanowall structure. | 2011-11-03 |
20110269265 | METHODS OF PREPARING SEMICONDUCTIVE COMPOSITIONS AND DEVICES - An amic acid or amic ester precursor can be applied to a substrate and thermally converted into a semiconducting layer of the corresponding arylene diimide. This semiconducting thin film can be used in various articles including thin-film transistor devices that can be incorporated into a variety of electronic devices. In this manner, the arylene diimide need not be coated but is generated in situ from a solvent-soluble, easily coated precursor compound. | 2011-11-03 |
20110269266 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including an oxide semiconductor with stable electric characteristics and high reliability is provided. An island-shaped oxide semiconductor layer is formed by using a resist mask, the resist mask is removed, oxygen is introduced (added) to the oxide semiconductor layer, and heat treatment is performed. The removal of the resist mask, introduction of the oxygen, and heat treatment are performed successively without exposure to the air. Through the oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor layer, whereby the oxide semiconductor layer is highly purified. Chlorine may be introduced to an insulating layer over which the oxide semiconductor layer is formed before formation of the oxide semiconductor layer. By introducing chlorine, hydrogen in the insulating layer can be fixed, thereby preventing diffusion of hydrogen from the insulating layer into the oxide semiconductor layer. | 2011-11-03 |
20110269267 | ALD PROCESSING TECHNIQUES FOR FORMING NON-VOLATILE RESISTIVE-SWITCHING MEMORIES - ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer. | 2011-11-03 |
20110269268 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - The degree of freedom of the chip layout in a semiconductor device is improved, and improvement in packaging density is aimed at. | 2011-11-03 |
20110269269 | LASER ABLATION ALTERNATIVE TO LOW COST LEADFRAME PROCESS - The present inventions relate generally to methods for packaging integrated circuits using thin foils that form electrical interconnects for the package. The foil includes a base layer (such as copper) with an optional plating layer (such as silver) suitable for improving adhesion of the bonding wires (or other connectors) to the foil. The base layer (or the plated surface if the foil is preplated) of the foil is patterned by laser ablation to define components (e.g. contacts) of a device area. The patterning is arranged to ablate entirely through selected portions of the plating layer and part, but not all, of the way through corresponding underlying portions of the base layer. In some embodiments, the metallic foil is partially etched after the laser ablation in order to deepen the trenches that define the patterning of the foil. Multiple dice may then be attached to die attach pad areas of the plated foil and electrically coupled to electrical contacts. Some embodiments contemplate encapsulating the dice, bonding wires, and portions of the plated foil with a plastic molding material. Portions of the metallic foil may then be removed by etching, laser ablation, or grinding. The resulting structure may then be singulated to form individual integrated circuit packages. | 2011-11-03 |
20110269270 | STACKABLE LAYER CONTAINING BALL GRID ARRAY PACKAGE - Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package. | 2011-11-03 |
20110269271 | NANOTUBE BASED VAPOR CHAMBER FOR DIE LEVEL COOLING - The formation of electronic assemblies is described. In one embodiment, an electronic assembly includes a semiconductor die and a plurality of spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a fluid positioned between the spaced apart nanotube structures on the semiconductor die. The electronic assembly also includes a endcap covering the plurality of nanotube structures and the fluid, wherein the endcap is positioned to define a gap between the nanotube structures and an interior surface of the endcap. The endcap is also positioned to form a closed chamber including the working fluid, the nanotube structures, and the gap between the nanotube structures and the interior surface of the endcap. | 2011-11-03 |
20110269272 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 2011-11-03 |
20110269273 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 2011-11-03 |
20110269274 | THIN FILM TRANSISTORS HAVING MULTIPLE DOPED SILICON LAYERS - Embodiments of the present invention generally relate to a TFT and a method for its fabrication. The TFT disclosed herein is a silicon based TFT in which the active channel comprises amorphous silicon. Over the amorphous silicon, multiple layers of doped silicon are deposited in which the resistivity of the doped silicon layers is higher at the interface with the amorphous silicon layer as compared to the interface with the source and drain electrodes. Alternatively, a single doped silicon layer is deposited over the amorphous silicon in which the properties of the single doped layer change throughout the thickness. It is better to have a lower resistivity at the interface with the source and drain electrodes, but lower resistivity usually means less substrate throughput. By utilizing multiple or graded layers, low resistivity can be achieved. The embodiments disclosed herein include low resistivity without sacrificing substrate throughput. | 2011-11-03 |
20110269275 | Static Random Access Memory (SRAM) Cell and Method for Forming Same - An embodiment is a method for forming a static random access memory (SRAM) cell. The method comprises forming transistors on a semiconductor substrate and forming a first linear intra-cell connection and a second linear intra-cell connection. Longitudinal axes of the active areas of the transistors are parallel. A first pull-down transistor and a first pull-up transistor share a first common gate structure, and a second pull-down transistor and a second pull-up transistor share a second common gate structure. The first linear intra-cell connection electrically couples active areas of the first pull-down transistor and the first pull-up transistor to the second common gate structure. The second linear intra-cell connection electrically couples active areas of the second pull-down transistor and the second pull-up transistor to the first common gate structure. | 2011-11-03 |
20110269276 | METHOD TO OPTIMIZE WORK FUNCTION IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) STRUCTURES - In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer. | 2011-11-03 |
20110269277 | Reduced STI Topography in High-K Metal Gate Transistors by Using a Mask After Channel Semiconductor Alloy Deposition - In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors. | 2011-11-03 |
20110269278 | Stress Memorization with Reduced Fringing Capacitance Based on Silicon Nitride in MOS Semiconductor Devices - In sophisticated semiconductor devices, stress memorization techniques may be applied on the basis of a silicon nitride material, which may be subsequently modified into a low-k dielectric material in order to obtain low-k spacer elements, thereby enhancing performance of sophisticated semiconductor devices. The modification of the initial silicon nitride-based spacer material may be accomplished on the basis of an oxygen implantation process. | 2011-11-03 |
20110269279 | METHOD FOR FORMING JUNCTIONS OF VERTICAL CELLS IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a plurality of active regions that are separated from each other by a plurality of trenches, respectively, wherein the trenches are formed by etching a substrate, forming an insulation layer having openings that each expose a portion of a first sidewall of each active region, forming a filling layer which fills the openings, forming a diffusion control layer over a substrate structure including the filling layer, and forming a junction on a portion of the first sidewall of each active region. | 2011-11-03 |
20110269280 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device, including: a first group of transistors formed on a semiconductor substrate; and a second group of transistors formed on the semiconductor substrate, each of which is lower in operating voltage than each of the transistors in the first group; wherein each of the transistors in the first group includes a first gate electrode formed on the semiconductor substrate through a first gate insulating film, and a silicide layer formed on the first gate electrode; each of the transistors in the second group includes a second gate electrode formed in a trench for gate formation, formed in an insulating film above the semiconductor substrate, through a second gate insulating film; and a protective film is formed so as to cover the silicide layer on each of the first gate electrodes of the first group of transistors. | 2011-11-03 |
20110269281 | Transistor with Longitudinal Strain in Channel Induced by Buried Stressor Relaxed by Implantation - Processes for making field effect transistors relax a buried stressor layer to induce strain in a silicon surface layer above the buried stressor layer. The buried stressor layer is relaxed and the surface layer is strained by implantation into at least the buried stressor layer, preferably on both sides of a portion of the surface layer that is to be stressed. For example, implanting ions through the surface silicon layer on either side of the gate structure of the preferred FET implementation into an underlying stressor layer can induce strain in a channel region of the FET. This process can begin with a silicon or silicon-on-insulator substrate with a buried silicon germanium layer having an appropriate thickness and germanium concentration. Other stressor materials can be used. | 2011-11-03 |
20110269282 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device having a FIN type transistor including a FIN-shape semiconductor portion improved for reliability by suppressing scattering of the characteristics of the FIN-shape transistor by decreasing a difference between impurity concentration at an upper surface and impurity concentration on a lateral side of the FIN-shape semiconductor portion, in which a pad insulating film at a thickness of about 2 to 5 nm is formed to the upper surface of the FIN-shape semiconductor portion, cluster ions are implanted to one lateral side of the FIN-shape semiconductor portion from an oblique direction at a first implantation angle θ1 and then cluster ions are implanted to another lateral side of the FIN shape semiconductor portion from an oblique direction at a second implantation angle θ2 in symmetrical with the first implantation angle θ1 and, subsequently, the cluster ions implanted to the FIN-shape semiconductor portion | 2011-11-03 |
20110269283 | High Voltage Transistor with Improved Driving Current - A semiconductor device and its method of manufacture are provided. Embodiments forming an active region in a semiconductor substrate, wherein the active region is bounded by an isolation region; forming a first doped region within the active region; forming a gate electrode over the active region, wherein the gate electrode overlies a portion of the first doped region; forming at least one dielectric layer over sidewalls of the gate electrode; forming a pair of spacers on the dielectric layer; and forming a second doped region substantially within the portion of the first doped region adjacent the one of the spacers and spaced apart from the one of the spacers. | 2011-11-03 |
20110269284 | SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHODS FOR THEM - The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film. On this account, on fabricating the semiconductor device having a high-performance integration system by forming the non-singlecrystalline Si semiconductor element and the singlecrystalline Si semiconductor element on the large insulating substrate, the process for making the singlecrystalline Si is simplified. Further, the foregoing arrangement provides a semiconductor substrate and a fabrication method thereof, which ensures device isolation of the minute singlecrystalline Si semiconductor element without highly-accurate photolithography, when the singlecrystalline Si semiconductor element is transferred onto the large insulating substrate. | 2011-11-03 |
20110269285 | FIELD TRANSISTORS FOR ELECTROSTATIC DISCHARGE PROTECTION AND METHODS FOR FABRICATING THE SAME - A field transistor for electrostatic discharge (ESD) protection and method for making such a transistor is described. The field transistor includes a gate conductive layer pattern formed on a field oxide layer. Since the gate conductive layer pattern is formed on the field oxide layer, a thin gate insulating layer having a high possibility of insulation breakdown is not used. To form an inversion layer for providing a current path between source and drain regions, a field oxide layer is interposed to form low concentration source and drain regions overlapped by the gate conductive layer pattern. | 2011-11-03 |
20110269286 | HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME - A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region. | 2011-11-03 |
20110269287 | METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS - An embodiment of the disclosure includes doping a FinFET. A dopant-rich layer comprising an dopant is formed on a top surface and sidewalls of a semiconductor fin of a substrate. A cap layer is formed to cover the dopant-rich layer. The substrate is annealed to drives the dopant from the dopant-rich layer into the semiconductor fin. | 2011-11-03 |
20110269288 | Methods of Forming CoSi2, Methods of Forming Field Effect Transistors, and Methods of Forming Conductive Contacts - The invention included to methods of forming CoSi | 2011-11-03 |
20110269289 | TRANSISTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A method of manufacturing a transistor device ( | 2011-11-03 |
20110269290 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a method of manufacturing a semiconductor device includes forming a first film containing boron (B) on a member to be etched, the member being a semiconductor substrate, or a film formed on the semiconductor substrate, and forming a second film formed of a silicon oxide film on the first film. The method further includes pressing an original plate having a pattern formed in an uneven shape onto the second film to transfer the pattern to the second film, and etching the first film by using the second film where the pattern is transferred as a mask, with an etching gas that contains fluoromethane (CH | 2011-11-03 |
20110269291 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING CAPACITIVE ELEMENTS - A technology capable of reducing the fraction defective of a MOS capacitor without the need to perform a screening is provided. | 2011-11-03 |
20110269292 | ISOLATING WIRE BONDING IN INTEGRATED ELECTRICAL COMPONENTS - An electrical component includes a semiconductor layer having a first conductivity type and a interconnect layer disposed adjacent to a frontside of the semiconductor layer. At least one bond pad is disposed in the interconnect layer and formed adjacent to the frontside of the semiconductor layer. An opening formed from the backside of the semiconductor layer and through the semiconductor layer exposes at least a portion of the bond pad. A first region having a second conductivity type extends from the backside of the semiconductor layer to the frontside of the semiconductor layer and surrounds the opening. The first region can abut a perimeter of the opening or alternatively, a second region having the first conductivity type can be disposed between the first region and a perimeter of the opening. | 2011-11-03 |
20110269293 | Reduced STI Loss for Superior Surface Planarity of Embedded Stressors in Densely Packed Semiconductor Devices - A reduction in material loss of trench isolation structures prior to forming a strain-inducing semiconductor alloy in transistor elements may result in superior device uniformity, for instance with respect to drive current and threshold voltage. To this end, at least one etch process using diluted hydrofluoric acid may be omitted when forming the shallow trench isolations, while at the same time providing a high degree of compatibility with conventional process strategies. | 2011-11-03 |
20110269294 | METHOD OF FORMING A HARD MASK AND METHOD OF FORMING A FINE PATTERN OF SEMICONDUCTOR DEVICE USING THE SAME - A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer. A fine pattern of a semiconductor device, such as a trench isolation region or a pattern of contact holes, can be formed using the hard mask as an etch mask. | 2011-11-03 |
20110269295 | Method of Forming a Semiconductor Wafer that Provides Galvanic Isolation - A semiconductor wafer that provides galvanic isolation is formed in a very cost efficient manner by attaching a non-conductive wafer to a silicon wafer to form a hybrid wafer, and then simultaneously wet etching a large number of hybrid wafers to form a thin non-conductive wafer that is attached to a thick silicon wafer. After a large number of high-voltage devices have been formed on the thin non-conductive wafer, the thick silicon wafer is thinned or removed so that the hybrid wafer is suitable for packaging. | 2011-11-03 |
20110269296 | METHOD FOR SEPARATING SEMICONDUCTOR WAFER INTO CHIPS - A method for separating a semiconductor wafer into chips includes the steps of sandwiching a soluble spacer between a wafer and a substrate to form a laminate, etching the wafer into a plurality of chips attached on the spacer, positioning the laminate in a chamber of an apparatus in a way that the etched wafer faces a stage of the apparatus, and introducing a solvent into the chamber to dissolve the soluble spacer so as to facilitate the chips to be supported on the stage. | 2011-11-03 |
20110269297 | METHOD FOR SYNTHESISING SEMICONDUCTOR QUANTUM DOTS - The invention can be used for producing different luminescent materials and as a basis for producing subminiature light-emitting diodes, white light sources, single-electron transistors, nonlinear optical devices and photosensitive and photovoltaic devices. The inventive method for producing semiconductor quantum dots involves synthesizing nanocrystal nuclei from a chalcogen-containing precursor and a precursor containing a group II or IV metal using an organic solvent and a surface modifier. The method is characterized in that (aminoalkyl)trialkoxysilanes are used as the surface modifier , core synthesis is carried out at a permanent temperature ranging from 150 to 250 C for 15 seconds to 1 hour and in that the reaction mixture containing the nanoclystal is additionally treated by UV-light for 1-10 minutes and by ultrasound for 5-15 minutes. The invention makes it possible to increase the photostability of semiconductor quantum dots up to 34% and the capacity thereof to be dispersed in both non-polar and polar solvents, so that the quantum yields are preserved and increased. | 2011-11-03 |
20110269298 | Irradiation assisted nucleation of quantum confinements by atomic layer deposition - A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition. | 2011-11-03 |
20110269299 | DIRECT CHEMICAL VAPOR DEPOSITION OF GRAPHENE ON DIELECTRIC SURFACES - A substrate is provided that has a metallic layer on a substrate surface of a substrate. A film made of a two dimensional (2-D) material, such as graphene, is deposited on a metallic surface of the metallic layer. The metallic layer is dewet and/or removed to provide the film on the substrate surface. | 2011-11-03 |
20110269300 | Integrated Assist Features for Epitaxial Growth - A method for making a semiconductor device is provided which comprises (a) creating a data set ( | 2011-11-03 |
20110269301 | MANUFACTURING METHOD OF SINGLE CRYSTAL SEMICONDUCTOR FILM AND MANUFACTURING METHOD OF ELECTRODE - To provide a method of obtaining a single crystal semiconductor film by a method that is simple and low-cost. A single crystal semiconductor film | 2011-11-03 |
20110269302 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The invention relates to a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate and locally heating the semiconductor substrate by using a heated tip structure. Locally heating the semiconductor substrate is carried out to locally modify the electrical properties of the semiconductor substrate. The semiconductor substrate can be implanted with dopants, so that locally heating step causes a local activation of the implanted dopants. Furthermore, the semiconductor substrate can be provided with a dopant layer, so that locally heating step causes dopants to diffuse into the semiconductor substrate. | 2011-11-03 |
20110269303 | Reduced Defectivity in Contacts of a Semiconductor Device Comprising Replacement Gate Electrode Structures by Using an Intermediate Cap Layer - Superior contact elements may be formed in semiconductor devices in which sophisticated replacement gate approaches may be applied. To this end, a dielectric cap layer is provided prior to patterning the interlayer dielectric material so that any previously created cracks may be reliably sealed prior to the deposition of the contact material, while the removal of any excess portion thereof may be performed without an undue interaction with the electrode metal of the gate electrode structures. Consequently, a significantly reduced defect rate may be achieved. | 2011-11-03 |
20110269304 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a multilayer, forming a plurality of patterns by etching the multilayer and a portion of the substrate, forming a supporter to support the plurality of patterns, and removing residues formed during the etching. | 2011-11-03 |
20110269305 | METHOD FOR FORMING A FLOATING GATE USING CHEMICAL MECHANICAL PLANARIZATION - An improved process forming a floating gate region of a semiconductor memory device. The process includes using a ceria slurry for chemical mechanical planarization to provide “stop on polysilicon” capabilities, allowing a thin nitride layer, or in the alternative no nitride layer, to be used and reducing the number of processing steps required to form the floating gate region. | 2011-11-03 |
20110269306 | SOLDER BUMP, ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE ELECTRONIC COMPONENT - An electronic component includes a plurality of first electrode pads arranged on a first substrate, a plurality of second electrode pads arranged at positions corresponding to the first electrode pads on a second substrate and a plurality of solder bumps which join together the first electrode pads and the second electrode pads. Here, the first substrate is located over the second substrate so that the first electrode pads and the second electrode pads are at positions which are shifted from opposite positions where the first electrode pads opposite to the second electrode pads, and at least a part of the solder bumps are solidified into hourglass-shaped. | 2011-11-03 |
20110269307 | Method for Making Integrated Circuit Device Using Copper Metallization on 1-3 PZT Composite - Provided herein is a method of making an integrated circuit device using copper metallization on 1-3 PZT composite. The method includes providing an overlay of electroplated immersion of gold (Au) to cover copper metal traces, the overlay preventing oxidation on 1:3 PZT composite with material. Also included is the formation of immersion Au nickel electrodes on the 1-3 PZT composite to achieve pad metallization for external connections. | 2011-11-03 |
20110269308 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, a first Ti film, a titanium nitride (TiN) film, a second Ti film, a first aluminum (Al) film and a second Al film are formed sequentially in a contact hole formed in a second interlayer insulating film and on a Cu wire. The first titanium (Ti) film is formed so that a ratio of a thickness of a first portion of the first Ti film on a bottom face of the contact hole to a thickness of a second portion of the first Ti film on the second interlayer insulating film becomes equal to or smaller than 5/100. Moreover, the second Al film is formed using an aluminum reflow method, in which the second Ti film and the first Al film are alloyed with each other to form an Al—Ti alloy film. | 2011-11-03 |
20110269309 | PHOTORESIST COMPOSITION, METHOD OF FORMING PATTERN BY USING THE PHOTORESIST COMPOSITION, AND METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - Provided are a photoresist composition having superior adhesion to an etch target film, a method of forming a pattern by using the photoresist composition, and a method of manufacturing a thin-film transistor (TFT) substrate. The photoresist composition includes an alkali-soluble resin; a photosensitive compound; a solvent; and 0.01 to 0.1 parts by weight of a compound represented by Formula 1: | 2011-11-03 |
20110269310 | SELECTIVE SILICIDE PROCESS - A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations. | 2011-11-03 |
20110269311 | GOLD-TIN ETCH USING COMBINATION OF HALOGEN PLASMA AND WET ETCH - The present disclosure relates to an implantable medical device. The implantable medical device includes a component comprising a first substrate bonded to a second substrate. A method for forming the component includes removing a first portion of tin (Sn) from gold tin (AuSn) through a halogen plasma. A first portion of gold (Au) is exposed in response to removing the first portion of the Sn. The first portion of the Au through a wet etch. A second portion of the Sn is exposed in response to removing the first portion of Au. | 2011-11-03 |
20110269312 | CHEMICAL MECHANICAL POLISHING (CMP) POLISHING SOLUTION WITH ENHANCED PERFORMANCE - This invention relates to a chemical composition for chemical mechanical polishing (CMP) of substrates that are widely used in the semiconductor industry. The inventive chemical composition contains additives that are capable of improving consistency of the polishing performance and extending the lifetime of a polishing pad. | 2011-11-03 |
20110269313 | SEMICONDUCTOR SUBSTRATE SURFACE TREATMENT METHOD - In one embodiment, a method for treating a surface of a semiconductor substrate is disclosed. The semiconductor substrate has a first pattern covered by a resist and a second pattern not covered by the resist. The method includes supplying a resist-insoluble first chemical solution onto a semiconductor substrate to subject the second pattern to a chemical solution process. The method includes supplying a mixed liquid of a water repellency agent and a resist-soluble second chemical solution onto the semiconductor substrate after the supply of the first chemical solution, to form a water-repellent protective film on a surface of at least the second pattern and to release the resist. In addition, the method can rinse the semiconductor substrate using water after the formation of the water-repellent protective film, and dry the rinsed semiconductor substrate. | 2011-11-03 |
20110269314 | PROCESS CHAMBERS HAVING SHARED RESOURCES AND METHODS OF USE THEREOF - Process chambers having shared resources and methods of use are provided. In some embodiments, substrate processing systems may include a first process chamber having a first substrate support disposed within the first process chamber, wherein the first substrate support has a first heater and a first cooling plate to control a temperature of the first substrate support; a second process chamber having a second substrate support disposed within the second process chamber, wherein the second substrate support has a second heater and a second cooling plate to control a temperature of the second substrate support; and a shared heat transfer fluid source having an outlet to provide a heat transfer fluid to the first cooling plate and the second cooling plate and an inlet to receive the heat transfer fluid from the first cooling plate and the second cooling plate. | 2011-11-03 |
20110269315 | THIN FILM FORMATION METHOD AND FILM FORMATION APPARATUS - A thin film formation method to form a silicon film containing an impurity on a surface of an object to be processed in a process chamber that allows vacuum exhaust includes alternately and repeatedly performing a first gas supply process in which a silane-based gas composed of silicon and hydrogen is supplied into the process chamber in a state that the silane-based gas is adsorbed onto the surface of the object to be processed and a second gas supply process in which an impurity-containing gas is supplied into the process chamber, to form an amorphous silicon film containing an impurity. Accordingly, an amorphous silicon film containing an impurity having good filling characteristics can be formed even at a relatively low temperature. | 2011-11-03 |
20110269316 | Wafer Support Ring - A wafer support ring and a method of using the same are disclosed herein. The support ring supports a wafer during a first processing operation. A top surface of the support ring is in contact with a first plurality of locations on a surface of the wafer during the first processing operation. A second wafer support structure is used to support the wafer during a second processing operation. A top surface of the second wafer support structure is in contact with a second, different plurality of locations on the surface of the wafer during the second processing operation. The wafer support ring may also have an outer lip disposed about an outer periphery of the support ring that has a depth such that it does not form part of the top surface of the support ring. | 2011-11-03 |
20110269317 | Energy transfer via rolling elements of rolling-element bearings - Systems and methods are disclosed for x-y tables wherein rolling elements of rolling-element bearings are transferring electrical energy between a fixed part of the x-y table and a movable part of the x-y table. The electrical energy transferred could be power to electrical devices as well as signals to and from devices on the movable part of the x-y table. Electrically conducting rolling elements are moving on electrically conducting grooves on the fixed and movable part of the x-y table. Conductor tracks on the fixed and movable part are connected to the grooves and to devices on the movable platform. In a preferred embodiment of the invention the x-y table is part of a camera wherein linear motors, preferably with integrated position sensing, are moving the x-y table back to a home position in case of a dislocation due to a mechanical shock. The invention allows an exact and fast positioning of an x-y table without requiring a flexible cable. The rolling-element bearings could be ball bearings, roller bearings, needle bearings, or other kind of bearings having electrically conductive rolling elements. | 2011-11-03 |
20110269318 | CONNECTOR - The present invention provides a technique that is easy for soldering fixture to a printed circuit board and is easy to handle. Regarding a connector having an insulating base portion and a conductive portion, in at least one direction of a surface to which the conductive portion is exposed, a metal plate extending from a side constituting the surface to another side not adjacent to the side is included. The metal plate can be fixed to a circuit board with solder, and deformation of the connector can be made less likely to occur. | 2011-11-03 |
20110269319 | PRINTED CIRCUIT BOARD MODULE - A PCB module includes a first rigid PCB having a first edge connector, a second rigid PCB having a second edge connector, and a connecting mechanism. The connecting mechanism includes a flexible connecting board, an elastic member, and a fixing member. The flexible connecting has a number of connecting circuit traces isolated from each other. The flexible connecting board is bent in such a manner that a first end portion is in contact with the first edge connector, and a second end portion is in contact with the second edge connector. Thus, the first edge connector is electrically connected with the second edge connector by the traces. The elastic member is compressed between the end portions of the flexible connecting board. The fixing member is configured to fix the first rigid PCB to the second rigid PCB and compress the elastic member. | 2011-11-03 |
20110269320 | MEANS FOR SECURING A POWER SUPPLY TO A BUS BAR - Means for securing a power supply terminal to a bus bar, the securing means comprising: a securing base; a stud rigidly mounted in the securing base; and a securing nut, wherein the stud is arranged to receive, in use, a bus bar mounted on a circuit board and a power supply terminal, the bus bar and terminal being secured in electrical contact with one another by the securing nut. | 2011-11-03 |
20110269321 | CONNECTOR STRUCTURE - A connector structure which can realize height reduction of connecting portions and space saving and which prevents separation of a female connector and a male connector from each other due to an impact or vibrations, wherein a conduction structure is formed by bringing connecting pins ( | 2011-11-03 |
20110269322 | ELECTRICAL CONNECTOR HAVING IMPROVED INSULATIVE HOUSING - An electrical connector includes an insulative housing having a base portion and a tongue portion extending forwardly from the base portion. The base portion has a mounting surface for being mounted to a printed circuit board upwardly, and a lower surface opposite to the mounting surface. The tongue portion has an upper side face, and a lower side face opposite to the upper side face. The mounting surface and the upper side face essentially are lied in a planar surface. A plurality of contacts are received the insulative housing and have contact portions exposed upon the upper side face of the tongue portion. | 2011-11-03 |
20110269323 | GROUND JOINT CONNECTOR AND WIRE HARNESS INCLUDING THE SAME - The present invention provides a ground joint connector capable of collectively connecting a plurality of grounding wires included in a wire harness for a vehicle, to a given ground site, while occupying a little space. The ground joint connector JC comprises a plurality of wire terminals to be attached to respective terminal ends of the grounding wires, a grounding conductor a connector housing holding the grounding conductor. The grounding conductor includes a plurality of wire-side terminal portions to be fitted to the respective wire terminals in a terminal fitting direction and a ground-side terminal portion to be connected to the ground site while fixed onto the wall surface around the ground site. The wire-side terminal portions aligned in a direction approximately perpendicular to the terminal fitting direction and parallel to the wall surface, and integrally joined to the ground-side terminal portion. The connector housing holds the grounding conductor to allow the ground-side terminal portion to protrude to outside and includes a plurality of terminal receiving chambers and a plurality of terminal locking portions. The terminal locking portions lock the respective wire terminals inserted into the respective terminal receiving chambers and fitted with the respective wire-side terminal portions. | 2011-11-03 |
20110269324 | High frequency socket connector - A high frequency socket connector has an insulating housing, a mounting bracket, multiple first terminals, multiple second terminals and a shell. The first and second terminals are mounted in the insulating housing, are capable of implementing USB 3.0 protocol. The shell covers the insulating housing and terminals. Each of the terminals has a SMT soldering section adapted to SMT soldering processes. All the SMT soldering sections are arranged in a transverse row to make the socket connector compact. | 2011-11-03 |
20110269325 | AIRCRAFT ELECTRICAL CONNECTOR WITH DIFFERENTIAL ENGAGEMENT AND OPERATIONAL RETENTION FORCES - An aircraft powering system is provided which includes an aircraft electrical connector is provided with features to allow facile engagement with an aircraft and strong retention forces. The aircraft powering system may include the aircraft electrical connector having a unique biasing mechanism and modular construction, wherein the biasing mechanism is configured to place differential forces onto mating electrical connectors from an aircraft. The biasing mechanism may be operatively coupled to a handle or trigger, which may be easily engageable by an operator. | 2011-11-03 |
20110269326 | INDEPENDENT LOADING MECHANISM STRUCTURE HAVING LEVER INCORPORATED WITH ROLLER - An independent loading mechanism (ILM) for an electrical connector comprises a stiffener, a load plate and a lever pivotally mounted to two opposite sides of the stiffener. The lever stamped and bent from a metal sheet is configured with a depressing portion having a cam tab bent from one side thereof, a pair of rollers mounted onto the depressing portion, an operating portion interconnected to the depressing portion. The cam tab can press the load plate toward the stiffener. The rollers located at two sides of the cam tab can engage with the stiffener to reduce rotational friction between the stiffener and the lever when rotating the operating portion from a horizontal direction to a vertical direction. | 2011-11-03 |
20110269327 | MODULAR CONNECTOR SYSTEM - The present invention provides a modular connector system for, in some embodiments, interconnecting circuit boards. In some embodiments, the modular connector system includes a header assembly for blind mating with an adapter assembly. | 2011-11-03 |
20110269328 | ELECTRICAL CARD CONNECTOR HAVING IMPROVED CARD RETAINING ELEMENTS - An electrical card connector ( | 2011-11-03 |
20110269329 | Multiple Function RJ Connector with Split Internal Housing Opening Cavity - A modular RJ-type connector includes a female receptacle having an internal cavity, and first and second sets of rigid contacts disposed in back-to-back spaced relation to each other and in spaced relation to interior surfaces of the female receptacle that define the internal cavity. The first and second sets of rigid contacts can be disposed adjacent an edge of a support that is positioned in the internal cavity facing an open, plug receiving end of the female receptacle. A male plug can be provided which includes first and second sets of spaced facing contacts that make contact with the contacts of the first and second sets of rigid contacts of the female receptacle when the male plug is inserted in the open, plug receiving end of the female receptacle. | 2011-11-03 |
20110269330 | SOCKET CONNECTOR WITH CONTACT HAVING DUAL-CONTACTING-PORTION CREATED BY SPLITTING AND TWISTING - A socket connector includes a socket body having an array of passageways; and an array of contacts received in passageways respectively. Each contact includes a retaining section received within the passageway, an engaging section extending from the retaining section. The engaging section has an oblique resilient arm extending out of the passageway. The resilient arm is split and altered so that a pair of split surfaces are formed as contacting surfaces which are substantially exposed upwardly. | 2011-11-03 |
20110269331 | Locking Device For Connectors - A connector for high amperage, AC or DC connection includes a plug and a receptacle configured to securely mate and lock with each other. Connector receptacles include a locking mechanism having a sleeve unit having a plurality of openings configured to receive a plurality of alignment members, a control unit in communication with the alignment members, and at least one extension member coupling the sleeve unit to the control unit. The control unit is configured to bias the alignment members to engage a groove in a plug in a locked position. Upon rotation of the control unit, the control unit engages the sleeve unit and allows the alignment members to freely move, thus allowing a user to connect or disconnect the plug from the receptacle. | 2011-11-03 |
20110269332 | BREAKAWAY MECHANISM FOR CHARGING CABLES OF ELECTRIC VEHICLE CHARGING STATIONS - A breakaway mechanism for a charging cable of an electric vehicle charging station includes a retention component and a breakaway component. The retention component is secured to the charging station and the breakaway component is secured to the charging cable. The charging cable passes through the breakaway component and includes charging wires that connect to connectors on the charging station. The breakaway component is adapted to disengage from the retention component at a predetermined pull force thereby causing the charging wires to disconnect from the connectors on the charging station. | 2011-11-03 |
20110269333 | Connection system enabling the tightening torque of a screw terminal to be indicated - A screw terminal with creep compensation comprises a pressure device enabling a clamping energy of the terminal to be stored. According to the invention, means for detecting the tightening torque enable the user to identify the force required for connection and to check that the creep is in fact compensated. The means for detecting comprise an element securedly affixed to the pressure device and an element securedly affixed to a wall of the housing in which the terminal is fitted, the distance between the two elements being determined by means enabling indicating means to be actuated when the distance is smaller than a threshold corresponding to a predetermined tightening torque. | 2011-11-03 |
20110269334 | CONNECTING MEMBER - A connecting member includes a cable used to transmit signal, a first connector and a second connector connected to the cable, and an elastic member mounted on the cable. The first connector and the second connector are configured for being electronically connected to two electronic components. The elastic member is elastically deformable between a first state, where the elastic member and the cable are constricted, and a second state, where the elastic member and the cable are extended. | 2011-11-03 |
20110269335 | Plug and Electronic Device with the Plug - The present invention relates to electronic technologies, and in particular, to a plug and an electronic device with the plug. The present invention solves the following problem: In the conventional art, an electronic device with a plug occupies too large space in the direction vertical to the surface of an external device when the electronic device is inserted in a slot of the external device. A plug of the present invention takes on the following features: when a head end of the plug is inserted in a slot of an external device, the plug is electrically connected to the slot; a back end of the plug is electrically connected to a main circuit board of an electronic device equipped with the plug; a sliding structure is set on the plug and integrated with the electronic device equipped with the plug; and the plug can slide relative to a shell of the electronic device through the sliding structure, and a head end of the plug can slide out of an edge of the shell in a direction that intersects a maximum extension direction of the shell through the sliding structure. The electronic device with the plug includes the shell, the main circuit board located in the shell, and the plug disclosed herein. The present invention is applicable to an electronic device with a plug. | 2011-11-03 |
20110269336 | ELECTRICAL EQUIPMENT SYSTEMS - An electrical equipment system may include a battery for an electrical power tool, an electrical equipment except for the electrical power tool, and an adapter that is capable of electrically and mechanically connecting the battery and the electrical equipment. The adapter has a battery side connecting portion that is capable of being detachably connected to the battery and an electrical equipment side connecting portion that is capable of being connected to the electrical equipment. | 2011-11-03 |