44th week of 2012 patent applcation highlights part 20 |
Patent application number | Title | Published |
20120274327 | MAGNETIC SHIELDING MATERIAL FOR SUPERCONDUCTING MAGNET - A magnetic shielding material which can decrease the thickness by having excellent conductivity even at low temperatures of, for example, 77 K or lower, in a strong magnetic field of a magnetic flux density of 1 T or more is provide. A magnetic shielding material to be used at low temperatures of 77 K or lower in the magnetic field of a magnetic flux density of 1 T or more, comprises aluminum having a purity of 99.999% by mass or more. | 2012-11-01 |
20120274328 | AXIAL HIGH VOLTAGE TRANSFORMER WITH SIGNAL PASS-THROUGH ABILITY - A high voltage power supply particularly for use in small diameter spaces such as in oil well logging devices. An axial linear high voltage step-up transformer has an integral through hole in the internal ferrite, low voltage sensing signals may be passed through from the output section of the power supply. In addition, a magnetic field shield is designed into the device to prevent eddy currents from forming in the metallic pressure vessel housing which is used to contain the neutron generating tube which is under pressure of an insulating gas such as sulfur hexafluoride. By constructing an axial transformer, and passing the signal leads through the internal hole, the largest amount of internal dielectric may be utilized, increasing the reliability of the transformer. By containing the magnetic field and limiting the eddy currents induced in outside metals, the converter efficiency may be raised to the maximum possible. | 2012-11-01 |
20120274329 | Imaging in Oil-Based Mud by Synchronizing Phases of Currents Injected Into a Formation - Disclosed is an apparatus for estimating a property of an earth formation penetrated by a borehole. The apparatus includes a carrier configured to be conveyed through the borehole. A first transmitter electrode and a second transmitter electrode are disposed at the carrier and configured to inject an electrical current into the earth formation. A first measurement electrode and a second measurement electrode are disposed at the carrier and configured to measure the electrical current to estimate the property of the earth formation. A first bucker amplifier is coupled to the first measurement electrode and a second bucker amplifier is coupled to the second measurement electrode, wherein the first and second bucker amplifiers are configured to equalize electrical potentials of areas in front of the first and second measurement electrodes. | 2012-11-01 |
20120274330 | UNDERGROUND CAVITY DETECTION BY ELECTROMAGNETIC SHOCK WAVES - A method for detection of underground anomalies including in a system of distributed antennas ( | 2012-11-01 |
20120274331 | Method and Apparatus for Determining the State-of-Charge of a Battery - A method and apparatus for determining the state-of-charge of a battery. In response to detecting that the battery is in a rest state, a pre-conditioning current is drawn from the battery to affect a correlation between the state-of-charge of the battery and an open-circuit voltage of the battery. Thereafter, the open-circuit voltage of the battery is measured, and used to determine the state-of-charge. | 2012-11-01 |
20120274332 | ALGORITHM FOR IN-SITU QUANTIFICATION OF PEMFC MEMBRANE HEALTH OVER ITS LIFE - A method for determining the health of the membranes in a fuel cell stack. The total parasitic current of the fuel cells in the stack is determined. From the total parasitic current, the shorting resistance and the cross-over parasitic current are determined. The health of the membranes is then determined from the cross-over parasitic current and the shorting resistance. | 2012-11-01 |
20120274333 | METHOD AND APPARATUS FOR CHARACTERIZING PROCESS CONTROL EQUIPMENT INTEGRITY - In a process plant, a first series of impedance measurements from a valve body are received. The first series of impedance measurements are stored. A second series of impedance measurements from the valve body are received. The second series of impedance measurements from the valve body are stored. The first series and second series of impedance measurements are compared. An indication of loss of integrity of the valve body is generated if the first series of impedance measurements deviates from the second series of impedance measurements. | 2012-11-01 |
20120274334 | METHOD AND APPARATUS FOR CHARACTERIZING PROCESS CONTROL EQUIPMENT COUPLING INTEGRITY - In a process plant, a first series of measurements from a coupling interface are received. The first series of measurements are stored. A second series of measurements from a coupling interface are received. The second series of measurements. The first series and second series of measurements are compared. An indication of loss of clamping force is generated if the first series of measurements deviates from the second series of measurements. | 2012-11-01 |
20120274335 | BATTERY PACK, METHOD OF DETERMINING MALFUNCTION, AND A MALFUNCTION DECISION CIRCUIT - Application of rechargeable battery 1 charging voltage is determined by a signal applied to a battery-connect terminal | 2012-11-01 |
20120274336 | ARCHITECTURE AND METHOD TO DETERMINE LEAKAGE IMPEDANCE AND LEAKAGE VOLTAGE NODE - A circuit, system, machine-readable storage medium and method for detecting the presence of a leakage path in a multi-cell voltage source is described. The system includes a detection circuit, the detection circuit having a first, second and third amplifiers, a first input of the first amplifier connected to a first terminal of the voltage source and the first input of the second amplifier connected to a second terminal of the voltage source, a second input of each of the first and second amplifiers connected to a reference capacitor, and an output of each of the first, second and third amplifiers connected to a respective first, second and third outputs of the detection circuit; and a processor having inputs connected to the first and second outputs of the detection circuit. | 2012-11-01 |
20120274337 | Method and Apparatus for Diagnosing Electrochemical Sensor - A method and apparatus for diagnosing an electrochemical sensor that detects the concentration of a gas are operative for diagnosing whether or not the sensor is in an error state due to a rise in a resistance in the electrolyte of the sensor. Such detection is made on the basis of a current flowing between a sensing electrode and an opposite electrode or a voltage corresponding to the current. A method for diagnosing an electrochemical sensor having a solid or liquid electrolyte between a sensing electrode and an opposite electrode detects the concentration of the gas to be detected on the basis of a current flowing between the sensing electrode and the opposite electrode, or a voltage corresponding to the current. Whether or not the electrochemical sensor is in an error state is diagnosed on the basis of a resistance of the electrolyte between the two electrodes of the electrolyte. | 2012-11-01 |
20120274338 | HIGH PERFORMANCE TIME DOMAIN REFLECTOMETRY - Methods and systems for high-bandwidth time domain reflectometry include a printed circuit board (PCB) and a probe. The PCB includes at least one signal terminal connected to at least one signal via at least three guide terminals arranged around the at least one high-frequency signal terminal. At least one of the guide terminals is connected to at least one ground via. The probe includes at least one biased pin to contact the at least one signal terminal and at least three fixed guide pins arranged about the at least one biased pin to facilitate alignment of said at least one biased pin by first engaging at least one guide terminal area, such that the at least one mechanically biased pin is guided to the at least one contact point. | 2012-11-01 |
20120274339 | ELECTROMAGNETIC SENSOR SYSTEM AND ANTENNA LOOP LAYOUT METHOD THEREOF - An antenna loop layout method for an electromagnetic sensor board is provided. The electromagnetic sensor board has a plurality of inductive antennas which are arranged abreast of each other. One end of the inductive antennas is coupled to each other, and the other end of the inductive antennas have a switch. The method comprises the following steps: first, a pre-determined interval value is provided. Then, the switches are closed in sequence by the pre-determined interval value to form a plurality of physical antenna loops. The pre-determined interval value can be changed dynamically. | 2012-11-01 |
20120274340 | CIRCUIT AND METHOD FOR SENSING A DIFFERENTIAL CAPACITANCE - A circuit and a method for sensing differential capacitance involve using plural storing capacitors to repeatedly sample charges of the differential capacitance in an over-sampling manner, and storing the charges sampled in different transfer rounds into different storing capacitors instead of repeatedly transferring charges for a single storing capacitor, so as to collect charge averages about both inputs and noises and in turn effectively reduce RF interference and source noises. | 2012-11-01 |
20120274341 | RESISTANCE MEASUREMENT CIRCUIT AND MEASURING METHOD EMPLOYING THE SAME - A resistance measurement circuit used in a power circuit includes an analog to digital converter (ADC), a signal control module, and a potentiometer. The ADC can receive an output voltage from the power circuit and convert the output voltage from the power circuit to digital signals. The signal control module compares two consecutive digital signals to establish any voltage difference according to the comparison. If the voltage difference is outside a predetermined voltage range, the signal control module adjusts the resistance of the potentiometer and the output voltage from the power circuit until the voltage difference is within the predetermined voltage range. | 2012-11-01 |
20120274342 | TRAUMA DETECTION SYSTEM - A trauma detecting body wear apparatus that may be configured with an outer conductive layer, and a medium layer proximate to the outer conductive layer. The medium layer may include an insulating material configured to prevent current flow to the outer layer. There may be an inner conductive layer configured with a penetration-resistant material, and the inner layer may also be configured with a conductive coating treatment, and may be further connected to an energized power source. The body wear apparatus may also include a transmitter configured to transmit a signal when current flows from the energized power source to the outer conductive layer. | 2012-11-01 |
20120274343 | Method for Measuring the Electrical Resistance of a Glow Plug - The invention relates to a method for measuring the electrical resistance of a glow plug, wherein a test current is set by closed-loop control to a constant value using a constant-current source, and is directed through the plug. A value of the electrical resistance of the glow plug is determined by evaluating a feedback signal of the constant-current source. | 2012-11-01 |
20120274344 | TESTING SYSTEM FOR PRINTED CIRCUIT BOARD - A test system includes a testing power supply unit which includes a rectifier and filter circuit and a voltage output circuit, a dropping voltage circuit which includes a primary coil and a secondary coil, a PWM regulator, and a control circuit. The rectifier and filter circuit receives an AC voltage and converts the AC voltage into a square wave signal. The primary coil is connected to the rectifier and filter circuit and receives the square wave signal. The secondary coil is connected to the voltage output circuit. The PWM regulator is connected to the primary coil. The PWM regulator generates a pulse signal to turn on and turn off the primary coil periodically. The control circuit is connected to the PWM regulator. The control circuit controls a duty cycle of the pulse signal to adjust time of the primary coil being on in a cycle. | 2012-11-01 |
20120274345 | RADIO FREQUENCY TESTING APPARATUS - A radio frequency (RF) testing apparatus, for testing device under test (DUT) comprising a receiving antenna, includes a pair of transmitting antennas transmitting wireless communication signals to the receiving antenna, a shielding box, a first filter and a second filter. The shielding box includes a transmitting box, a receiving box for receiving the DUT, a connecting box connecting between the transmitting box and the receiving box and a pair of transmitting antennas fixed on the transmitting box and suspending towards the connecting box. The connecting box includes a microwave absorption medium on the connecting box and communicates with the receiving box. The first filter is mounted on the connecting box and the transmitting box to electrically connect with the transmitting antenna. The second filter is mounted on the receiving box to electrically connect with the DUT. | 2012-11-01 |
20120274346 | TESTING SYSTEM WITH CAPACITIVELY COUPLED PROBE FOR EVALUATING ELECTRONIC DEVICE STRUCTURES - Conductive electronic device structures such as a conductive housing member that forms part of an antenna may be tested during manufacturing. A test system may be provided that has a capacitive coupling probe. The probe may have electrodes. The electrodes may be formed from patterned metal structures in a dielectric substrate. A test unit may provide radio-frequency test signals in a range of frequencies. The radio-frequency test signals may be applied to the conductive housing member or other conductive structures under test using the electrodes. Complex impedance data, forward transfer coefficient data, or other data may be used to determine whether the structures are faulty. A fixture may be used to hold the capacitive coupling probe in place against the conductive electronic device structures during testing. | 2012-11-01 |
20120274347 | INTEGRATED HIGH-SPEED PROBE SYSTEM - An integrated high-speed probe system is provided. The integrated high-speed probe system includes a circuit substrate for transmitting low-frequency testing signals from a tester through a first probe of the probe assembly to a DUT, and a high-speed substrate for transmitting high-frequency testing signals from the tester to the DUT. The high-speed substrate extends from the upper surface of the circuit substrate in the testing area to the lower surface of the circuit substrate in the probe area for being adjacent to the probe assembly and electrically connecting the second probe. In this way, the tester can transmit testing signals of different frequencies through the integrated high-speed probe system. | 2012-11-01 |
20120274348 | TEST CIRCUIT AND METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via receives an input voltage. The voltage driving unit is connected to the through via to receive the input voltage, changes a level of the input voltage in response to a test control signal, and generates a test voltage. The determination unit compares the input voltage with the test voltage to outputs a resultant signal. | 2012-11-01 |
20120274349 | DEBUG CARD FOR MOTHERBOARD - A debug card includes a connector, a driving circuit, a switching circuit, and a testing circuit. The connector is connected to an expansion slot of a motherboard. The switching circuit is connected between the connector and the testing circuit to select data channels between the connector and the testing circuit through a low level signal or a high level signal received by a ground pin of the connector. The driving circuit is connected to the connector, the switching circuit, and the testing circuit, to provide voltages to the switching circuit and the testing circuit through the connector and the expansion slot. | 2012-11-01 |
20120274350 | SYSTEMS AND METHODS FOR PROVIDING USER-INITIATED LATCH UP TO DESTROY SRAM DATA - Systems and methods are provided for destroying or erasing circuitry elements, data, or both, such as transistors, volatile keys, or fuse blocks, located in an integrated circuit device. An initiation signal may be provided to induce latch-up in a circuitry element in response to a user command, a tampering event, or both. As a result of the latch-up effect, the circuitry element, data, or both may be destroyed or erased. | 2012-11-01 |
20120274351 | METHOD AND APPARATUS FOR SECURING A PROGRAMMABLE DEVICE USING A KILL SWITCH - A kill switch is provided that, when triggered, may cause the programmable logic device (PLD) to become at least partially reset, disabled, or both. The kill switch may be implemented as a fuse or a volatile battery-backed memory bit. When, for example, a security threat is detected, the switch may be blown, and a reconfiguration of the device initiated in order to zero or clear some or all of the memory and programmable logic of the PLD. | 2012-11-01 |
20120274352 | SINGLE EVENT TRANSIENT DIRECT MEASUREMENT METHODOLOGY AND CIRCUIT - A circuit and method of directly measuring the Single Event Transient (SET) performance of a combinatorial circuit includes a measurement chain. The measurement chain includes a plurality of cells, each in turn including a pair of SR latches, a dual-input inverter, and a target. During measurement and testing, the targets are irradiated, and a pulse signal caused by an SET event is allowed to propagate through the measurement chain only if the pair of SR latches are active at the same time. The pulse signal is latched by the measurement chain, thus allowing the presence of an SET event to be detected. | 2012-11-01 |
20120274353 | SYSTEMS AND METHODS FOR PREVENTING DATA REMANENCE IN MEMORY SYSTEMS - Methods, circuits, and systems for preventing data remanence in memory systems are provided. Original data is stored in a first memory, which may be a static random access memory (SRAM). Data is additionally stored in a second memory. Data in the first memory is periodically inverted, preventing data remanence in the first memory. The data in the second memory is periodically inverted concurrently with the data in the first memory. The data in the second memory is used to keep track of the inversion state of the data in the first memory. The original data in the first memory can be reconstructed performing a logical exclusive-OR operation between the data in the first memory and the data in the second memory. | 2012-11-01 |
20120274354 | LOGIC CIRCUIT DESIGN METHOD, LOGIC DESIGN PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT - A computer device which performs logic synthesis using hardware description and a component in a cell library and generates a net list of a logic circuit including a series path of a clock synchronous sequential circuit and a combinational circuit performs optimization processing for decreasing the number of gate stages in a critical path between sequential circuits in the data path by using a third sequential circuit having a negative-logic input terminal and a negative-logic non-inverted output terminal and a fourth sequential circuit having a negative-logic input terminal and a negative-logic inverted output terminal in addition to a first sequential circuit having a positive-logic input terminal and a positive-logic non-inverted output terminal and a second sequential circuit having a positive-logic input terminal and a positive-logic inverted output terminal. | 2012-11-01 |
20120274355 | PROGRAMMABLE LOGIC DEVICE - An object of the present invention is to provide a programmable logic device which has short start-up time after supply of power is stopped, is highly integrated, and operates with low power. In a programmable logic device including an input/output block, a plurality of logic blocks each including a logic element, and a wiring connecting the plurality of logic blocks, the logic element has a configuration memory for holding configuration data and a look-up table including a selection circuit. The configuration memory includes a plurality of memory elements each of which includes a transistor whose channel region is in an oxide semiconductor film and an arithmetic circuit provided between the transistor and the selection circuit. Configuration data is selectively changed and output by the selection circuit in accordance with an input signal. | 2012-11-01 |
20120274356 | SIGNAL PROCESSING UNIT - A signal processing unit with reduced power consumption is provided. A transistor in which a channel is formed in an oxide semiconductor is used for a storage circuit included in the signal processing unit, so that data can be held (stored) even while supply of power is stopped. Non-destructive reading can be performed on the data stored in the storage circuit even when supply of power to the signal processing unit is stopped. | 2012-11-01 |
20120274357 | Reducing Narrow Gate Width Effects in an Integrated Circuit Design - A method for reducing narrow gate width effects in an integrated circuit includes finding the smallest transistor channel widths that are larger than the minimum width for the technology for library cells that produce logic blocks that meet timing constraints while using the least amount of power and have the smallest possible area. The method may include characterizing a device library while varying process, voltage and temperature parameters, and synthesizing an HDL representation of a functional logic block including cells from the device library. The method may also include determining whether timing, area, and power values of the functional logic block are within a predetermined range. In response to the timing, area, and power values not being within the predetermined range, iteratively increasing the channel width of at least a portion of the transistors of at least one of the cells in the device library. | 2012-11-01 |
20120274358 | IDENTICAL-DATA DETERMINATION CIRCUIT - A identical-data determination circuit includes a first activation unit configured to activate an output signal when first and second signals each have a first level, a second activation unit configured to activate the output signal when the first and second signals each have a second level different from the first level, an initialization unit configured to deactivate the output signal when an initialization signal is applied, and a storage unit configured to store the output signal. | 2012-11-01 |
20120274359 | HIGH-SPEED DIFFERENTIAL COMPARATOR CIRCUITRY WITH ACCURATELY ADJUSTABLE THRESHOLD - A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit. | 2012-11-01 |
20120274360 | SWITCHED CAPACITANCE VOLTAGE DIFFERENTIAL SENSING CIRCUIT WITH NEAR INFINITE INPUT IMPEDANCE - A circuit may sense the differential voltage across two nodes that each have a non-zero common mode voltage. The circuit may have a positive input impedance that is imposed across the nodes. An impedance compensation circuit may generate a compensation current that is delivered to the nodes that substantially cancels the loading effect of the positive input impedance. The impedance compensation circuit may generate a negative input impedance that is imposed across the two nodes that is substantially the same as the positive input impedance. The impedance compensation circuit may instead be configured to deliver the compensation current to the nodes. | 2012-11-01 |
20120274361 | COMPARATOR AND SEMICONDUCTOR DEVICE INCLUDING COMPARATOR - A chopper comparator with a novel structure is provided. The comparator includes an inverter, a capacitor, a first switch, a second switch, and a third switch. An input terminal and an output terminal of the inverter are electrically connected to each other through the first switch. The input terminal of the inverter is electrically connected to one of a pair of electrodes of the capacitor. A reference potential is applied to the other of the pair of electrodes of the capacitor through the second switch. A signal potential input is applied to the other of the pair of electrodes of the capacitor through the third switch. A potential output from the output terminal of the inverter is an output signal. A transistor whose channel is formed in an oxide semiconductor layer is used as the first switch. | 2012-11-01 |
20120274362 | TRACKING AND HOLD OPERATIONS FOR AN ANALOG-TO-DIGITAL CONVERTER - Various exemplary embodiments relate to a tracking system and method. The system includes a transistor switch having a gate node and a source node, a power source circuit connected to the gate node, and a bootstrapping circuit connected to the source node and to the gate node. The power source circuit charges the switch during a first tracking phase, and the bootstrapping circuit charges the switch during a second tracking phase. | 2012-11-01 |
20120274363 | NOISE CANCELLATION SYSTEM AND METHOD FOR AMPLIFIERS - An architecture of an integrated circuit allows for the canceling of noise sampled on a capacitor in the integrated circuit, after an input signal has already been sampled. Thermal noise correlated with an arbitrary input signal may be canceled after selectively controlling a plurality of switching devices during a sequence of clock phases. An auxiliary capacitor may be used to store a voltage equal to the thermal noise and enable the cancellation of the thermal noise from the sampled signal in conjunction with a noise cancellation unit. | 2012-11-01 |
20120274364 | Method and Apparatus of Using Time-Domain Interpoolators for Sampling Time Adjustment, Sampling Rate Change, and Sampling Misalignment Compensation in Optical Communications - An apparatus comprising an analog-to-digital converter (ADC); a frequency-domain equalizer (FDEQ); a time-domain interpolator positioned between the ADC and the FDEQ, wherein the time domain interpolator is coupled to the ADC and the FDEQ and configured to perform a time-domain interpolation to compensate a signal sample for a plurality of ADC induced changes. | 2012-11-01 |
20120274365 | RECEIVING CIRCUIT HAVING A LIGHT RECEIVING ELEMENT WHICH RECEIVES A LIGHT SIGNAL - According to one embodiment, a receiving circuit is provided. The receiving circuit has a first light receiving element, a signal voltage generator, a second light receiving element, a delay element and a comparator. The first light receiving element receives a light signal and converts the light signal into a first current. The signal voltage generator converts the first current into a signal voltage. The second light receiving element receives the light signal and converts the light signal into a second current. The reference voltage generator converts the second current into a voltage and outputs the voltage as a reference voltage. The delay element delays and reduces a signal component of the reference voltage. The comparator compares the signal voltage from the signal voltage generator with a threshold voltage based on an output voltage of the delay element. | 2012-11-01 |
20120274366 | Integrated Power Stage - In one implementation, an integrated power stage includes a common die situated over a load stage, the common die includes a driver stage and power switches. The power switches include a control transistor and a sync transistor. A drain of the control transistor receives an input voltage of the common die on one side (e.g., on a top surface) of the common die. A source of the control transistor is coupled to a drain of the sync transistor and provides an output voltage of the common die on an opposite side (e.g., on a bottom surface) of the common die. An interposer may be included under the power stage and includes an output inductor and optionally an output capacitor coupled to the output voltage of the common die on the opposite side of the common die. | 2012-11-01 |
20120274367 | Front-End Transceiver - In an embodiment, a front-end transceiver may be provided. The front-end transceiver may include a receiver path, including a first receiver frequency converter configured to convert a received signal with a receiver frequency into a first receiver intermediate signal with a first receiver intermediate frequency; and a receiver direct conversion stage coupled to the first receiver frequency converter so as to receive the first receiver intermediate signal. The front-end transceiver may further include an oscillator signal generator respectively coupled to the first receiver frequency converter and to the receiver direct conversion stage so as to provide a first oscillator signal with a first oscillator frequency to the first receiver frequency converter and a first stabilizing signal with a first stabilizing frequency to the receiver direct conversion stage; wherein the oscillator signal generator may be configured so that the first oscillator frequency of the first oscillator signal may be selected such that any integer multiple of the first oscillator frequency of the first oscillator signal may be different from any integer multiple of the receiver frequency of the received signal. The front-end transceiver may also include a transmitter path. | 2012-11-01 |
20120274368 | METHOD AND CIRCUIT FOR WAVEFORM GENERATION - A programmable waveform generator, comprising: a controllable waveform generator configured to generate an initial bandwidth signal having an initial frequency bandwidth; a tone generator configured to generate a plurality of tone signals, each tone signal having a different frequency; a first bandwidth-multiplying circuit, including a first mixer having a first input port configured to receive the low-bandwidth signal; a first switch configured to choose one of the plurality of tone signals or a phase shifted version of one of the plurality of tone signals and output the chosen signal as a first chosen tone; a controller configured to control the operation of the bandwidth multiplying block, wherein the first mixer is further configured to receive the first chosen tone at a second input port, wherein the first mixer is further configured to mix the initial bandwidth signal and the first chosen tone to generate a first bandwidth signal at an output port, the first bandwidth signal having a first frequency bandwidth, wherein the first frequency bandwidth is greater than the initial frequency bandwidth, and wherein the first frequency bandwidth is an integer multiple of the initial frequency bandwidth. | 2012-11-01 |
20120274369 | POWER-ON-RESET CIRCUIT AND RESET METHOD - Apparatus and methods for a power-on-reset (POR) circuit are provided. In an example, a (POR) circuit can include a self-bias module configured to provide a reference voltage, a feedback module configured to provide a feedback voltage, a comparison module configured to compare the feedback voltage to the reference voltage and to provide an output signal, an inverter configured to couple the output of the comparison module to an enable input of the self-bias module, and a switch module coupled to the inverter, wherein the switch module and the inverter are configured to disabled the self bias module when the feedback voltage exceeds the reference voltage. | 2012-11-01 |
20120274370 | Reducing Spurs in Injection-Locked Oscillators - Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms. | 2012-11-01 |
20120274371 | METHOD FOR ENCODER FREQUENCY SHIFT COMPENSATION - The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input encoder signal to determine values of frequency-shifts and compensating for the values of the frequency-shifts to generate a frequency-shift compensated clock. | 2012-11-01 |
20120274372 | Phase Locked Loop Frequency Synthesizer Circuit with Improved Noise Performance - A phase locked loop frequency synthesizer comprises a voltage controlled oscillator; a loop filter for supplying a control voltage to the oscillator; a phase frequency detector arranged to detect a phase difference between a reference signal and a feedback signal generated from the oscillator signal and generate pulses on detector UP signals (UP/DN) dependent on the sign of the phase difference; and a charge pump ( | 2012-11-01 |
20120274373 | SEMICONDUCTOR DEVICE AND DELAY LOCKED LOOP CIRCUIT THEREOF - A semiconductor device includes a first phase detector for detecting a phase of a second clock by comparing the phase of the second clock with the phase of the first clock, a second phase detector for detecting a phase of a clock obtained by delaying the second clock by a set delay amount, a third phase detector for detecting the phase of the second clock by delaying the first clock by the set delay amount, and a phase difference detection signal generator for setting a logic level of a phase difference detection signal corresponding to a phase difference between the first and second clocks detecting that the phase of the first or second clock is changed, and change the logic level of the phase difference detection signal. | 2012-11-01 |
20120274374 | FAST MEASUREMENT INITIALIZATION FOR MEMORY - Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during each feedback cycle, thereby making it possible to achieve a phase lock faster and more efficiently. In some embodiments, such adaptive functionality can be incorporated into existing circuits with minimal impact. | 2012-11-01 |
20120274375 | FREQUENCY CONTROL CLOCK TUNING CIRCUITRY - Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes multiple programmable fuses coupled to a control block. The programmable fuses used may be one-time programmable (OTP) fuses. The control block reads settings or data stored in the programmable fuses. A tuning circuit coupled to the control block receives the delay transmitted by the control block. The tuning circuit allows tuning of the IC without changes to the fabrication mask. The tuning circuit may include delay chains to provide additional delay to the IC when needed and the delay in the tuning circuit is configured based on the delay value stored in the programmable fuses and transmitted by the control block. | 2012-11-01 |
20120274376 | DUTY CYCLE CORRECTOR CIRCUITS - Duty cycle corrector circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the number of the fine unit delay elements of the delay lines by placing a fine delay element granularity at the most critical timings to sense and adjust for the portion of the clock signal time period that are high speed or critical. | 2012-11-01 |
20120274377 | SINGLE-TRIGGER LOW-ENERGY FLIP-FLOP CIRCUIT - One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. The output signal Q is set or reset at the rising clock edge using a single-trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock. | 2012-11-01 |
20120274378 | MEMORY CIRCUIT, SIGNAL PROCESSING CIRCUIT, AND ELECTRONIC DEVICE - A signal processing circuit using a nonvolatile memory circuit with a novel structure is provided. The nonvolatile memory circuit is formed using a transistor including an oxide semiconductor and a capacitor connected to one of a source electrode and a drain electrode of the transistor. A high-level potential is written to the memory circuit in advance, and this state is kept in the case where data to be saved has a high-level potential, whereas a low-level potential is written to the memory circuit in the case where data to be saved has a low-level potential. Thus, a signal processing circuit with improved writing speed can be provided. | 2012-11-01 |
20120274379 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device which stops and resumes the supply of power supply voltage without the necessity of saving and returning a data signal between a volatile storage device and a nonvolatile storage device is provided. In the nonvolatile semiconductor storage device, the volatile storage device and the nonvolatile storage device are provided without separation. Specifically, in the semiconductor storage device, data is held in a data holding portion connected to a transistor including a semiconductor layer containing an oxide semiconductor and a capacitor. The potential of the data held in the data holding portion is controlled by a data potential holding circuit and a data potential control circuit. The data potential holding circuit can output data without leaking electric charge, and the data potential control circuit can control the potential of the data held in the data holding portion without leaking electric charge by capacitive coupling through the capacitor. | 2012-11-01 |
20120274380 | INTERNAL VOLTAGE GENERATION CIRCUIT - An internal voltage generation circuit includes a first detection unit, a second detection unit, a control unit, and a voltage pumping unit. The first detection unit compares an internal voltage with a first reference voltage to generate a first detection signal when the first detection unit is activated in response to a first enable signal. The second detection unit compares the internal voltage with a second reference voltage to generate a second detection signal. The control unit generates the first enable signal and a second enable signal in response to the first detection signal and the second detection signal. The voltage pumping unit generates the internal voltage in response to the second enable signal. | 2012-11-01 |
20120274381 | OFFSET COMPENSATION APPARATUS FOR MAGNETIC DETECTION CIRCUIT AND METHOD THEREOF - Disclosed herein are an offset compensation apparatus for a magnetic detection circuit, and a method thereof. The offset compensation apparatus includes: an amplifying unit amplifying an output voltage, and outputting the amplified voltages; an offset detection unit detecting an offset; a comparison unit determining whether or not the offset output from the offset detection unit is greater than a pre-set positive reference value or smaller than a pre-set negative reference value; a counter unit; and a current supply. | 2012-11-01 |
20120274382 | LEVEL-SHIFTER CIRCUIT USING LOW-VOLTAGE TRANSISTORS - A level-shifter circuit may include a pair of inputs which receive a first and a second low-voltage phase signal having a first voltage dynamic with a first maximum value. The level-shifter circuit may also include a pair of outputs which supply a first high-voltage phase signal and a second high-voltage phase signal, level-shifted with respect to the low-voltage signals and having a second voltage dynamic with a second maximum value, higher than the first maximum value. The level-shifter circuit may further include transfer transistors coupled between one of a first reference terminal and a second reference terminal, which are set at one of a first reference voltage and a second reference voltage, and the first output or second output. Protection elements may be coupled to a respective transfer transistor to protect from overvoltages between at least one of the corresponding conduction terminals and control terminals. | 2012-11-01 |
20120274383 | ORTHOGONAL CHANNEL DATA SWITCH - An integrated circuit device for switching data has a plurality of input channels and a plurality of output channels. The device includes a switch for selectively connecting a subset of the output channels, mutually orthogonal, to the input channels by providing signal paths between the selected mutually orthogonal output channels and the input channels. The selected output channels are not orthogonal to the output channels that are not selected. | 2012-11-01 |
20120274384 | SEMICONDUCTOR DEVICE - The present invention discloses a semiconductor device and relates to the semiconductor field. The semiconductor device comprises: a PMOS transistor for processing a input signal, the PMOS transistor comprising a gate and a source, the source being connected to a first voltage source; and a restoring circuit connected to the PMOS transistor for preventing degradation of the PMOS transistor, wherein the restoring circuit makes the gate voltage of the PMOS transistor to be higher than the voltage of the first voltage source, when the input signal is at a high level. According to the semiconductor device of the present invention, a positive bias voltage is applied on the gate of the PMOS transistor through the restoring circuit when the PMOS transistor is turned off, which can accelerate electric parameter recovery for PMOS transistors and therefore improve the performance of PMOS transistors. | 2012-11-01 |
20120274385 | Transmission Gate - A transmission gate includes first and second transmission path terminals, a series connection of first and second field effect transistors (FETs), and a control circuit. The channels of the first and second FETs are coupled in series between the first transmission path terminal and the second transmission path terminal, such that a channel contact of the first FET is coupled to the second transmission path terminal and a channel contact of the second FET is coupled to the first transmission path terminal. The control circuit is configured to provide a control voltage for a gate contact of the first FET and a control voltage for a gate contact of the second FET, such that the control voltage for the gate contact of the first FET is, in a switch-off state of the transmission gate, based on a voltage present at the first transmission path terminal, and such that the control voltage for the gate contact of the second FET is, in the switch-off state of the transmission gate, based on a voltage present at the second transmission path terminal. | 2012-11-01 |
20120274386 | SEMICONDUCTOR CIRCUIT - A semiconductor circuit which can have stable input output characteristics is provided. Specifically, a semiconductor circuit in which problems caused by the leakage current of a switching element are suppressed is provided. A field-effect transistor in which a wide band gap semiconductor, such as an oxide semiconductor, is used in a semiconductor layer where a channel is formed is used for a switching element included in a switched capacitor circuit. Such a transistor has a small leakage current in an off state. When the transistor is used as a switching element, a semiconductor circuit which has stable input output characteristics and in which problems caused by the leakage current are suppressed can be fabricated. | 2012-11-01 |
20120274387 | RF Switching System, Module, and Methods with Improved High Frequency Performance - Embodiments of radio frequency switching systems, modules, and methods with improved high frequency performance are described generally herein where the switching module may include a first switch module coupled in series to a second switch module, and a third switch module coupled between the first and the second module and ground. A controllable element of the second module may have a lower off capacitance than a controllable element of the first module. Other embodiments may be described and claimed. | 2012-11-01 |
20120274388 | SWITCHING ELEMENT HAVING AN ELECTROMECHANICAL SWITCH AND METHODS FOR MAKING AND USING SAME - A switching element having an electromechanical switch (such as an electrically conductive membrane switch, for example a graphene membrane switch) is disclosed herein. Such a switching element can be made and used in a switching power converter to reduce power loss and to maximize efficiency of the switching power converter. | 2012-11-01 |
20120274389 | JUNCTION BOX - A junction box electronically connected to a solar panel and connected to a plurality of solar cell strings connected in series includes a first bypass diode string and at least one second bypass diode. The first bypass diode string includes a plurality of first bypass diodes forwardly connected in series, and each of the plurality of first bypass diodes is connected to a corresponding one of the plurality of solar cell strings in parallel. The at least one second bypass diode connected to at least two neighboring solar cell strings in parallel, turns on to bypass the at least two neighboring solar cell strings upon the condition that the at least two neighboring solar cell strings are abnormal simultaneously. | 2012-11-01 |
20120274390 | POWER SUPPLY CIRCUIT - The power supply circuit which includes a first power circuit, a second power circuit, and a third power circuit is used for supplying power to loads. The first power circuit is connected between a control terminal of a control circuit and the load, and includes a switching unit including a first terminal, a second terminal, and a switching terminal controlling connection and disconnection between the first terminal and the second terminal The first terminal is connected to a power source, the second terminal is connected to the load, and the switching terminal is connected to the control terminal. The second power circuit and the third power circuit further includes a delay circuit relative to the first power circuit, the delay circuit is connected between the control terminal and the switching terminal, a delay time of the third power circuit is greater than the delay time of the second power circuit. | 2012-11-01 |
20120274391 | FUSE CIRCUIT FOR SEMICONDUCTOR DEVICE - A fuse circuit of a semiconductor device includes a transfer unit configured to selectively transfer a corresponding address signal in response to a first test mode signal, a fuse control unit configured to drive an output end with a first voltage in response to an output signal of the transfer unit, a fuse unit including a MOS transistor having a gate coupled to the output end, and a fuse enable unit configured to selectively supply a second voltage to a source/drain of the MOS transistor of the fuse unit in response to the first test mode signal, wherein the fuse circuit is programmed by causing a breakdown of the MOS transistor in response to a voltage difference between the first voltage and the second voltage that are applied to the gate and the source/drain of the MOS transistor of the fuse unit. | 2012-11-01 |
20120274392 | ADAPTIVE CHARGE PUMP - A method of adaptively controlling a charge pump including coupling the charge pump to a control node, toggling a clock input between supply voltage levels to charge an a charge pump output, monitoring the charge pump output, maintaining the control node at a supply voltage level when a supply voltage magnitude does not exceed a threshold level, and adjusting the control node to maintain the charge pump output at a limit level when the supply voltage magnitude exceeds the threshold level. A positive charge pump embodiment charges the output to twice the positive supply voltage up to no more than a limit level. A negative charge pump embodiment charges the output to the same magnitude with opposite polarity as the positive supply voltage, and decreases the output magnitude if the positive supply voltage is above the threshold level. A Zener diode and controlled current mirror may be used for control. | 2012-11-01 |
20120274393 | DYNAMIC BIASING CIRCUIT FOR A PROTECTION STAGE USING LOW VOLTAGE TRANSISTORS - A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors. | 2012-11-01 |
20120274394 | CHARGE PUMP FEEDBACK CONTROL DEVICE AND METHOD USING THE SAME - Charge pump feedback control device and method are provided. The device is coupled to the charge pump unit which receives an input voltage so as to generate an output voltage and has switches and at least one capacitor, the device includes: a compensation unit, a modulation unit, and a phase control unit. The compensation unit receives the output voltage, compensates the output voltage for stability, and generates an error signal. The modulation unit receives the error signal, modulates the error signal, and correspondingly generates a modulation signal. The phase control unit receives the modulation signal so as to generate phase signal, and controls the plurality of switches of the charge pump unit according to the plurality of phase signal so as to generate the output voltage through the input voltage charging/discharging at least one capacitor of the charge pump unit. | 2012-11-01 |
20120274395 | BATTERY MANAGEMENT SYSTEM WITH MOSFET BOOST SYSTEM - A boost converter for driving the gate of n-channel MOSFET power devices is described. The boost converter includes a monitoring circuit and a kick start circuit to quickly bring the boost converter online when required to drive the MOSFET on. | 2012-11-01 |
20120274396 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME - A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node. | 2012-11-01 |
20120274397 | METHOD AND SYSTEM FOR A PROCESS SENSOR TO COMPENSATE SOC PARAMETERS IN THE PRESENCE OF IC PROCESS MANUFACTURING VARIATIONS - Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined amount of process variation may be compensated by utilizing a process dependent current, a bandgap current, and a current associated with a present temperature of the transistor. The process dependent current, the bandgap current and the current associated with the present temperature of the transistor may be combined to generate an output current. A voltage generated across a variable resistor may be determined based on the generated output current. | 2012-11-01 |
20120274398 | RF AGC Control - Embodiments of the present invention may provide a signal processor with a wide gain range. The signal processor may comprise at least a discrete step gain stage and a continuous variable gain amplifier (VGA) stage. The discrete step gain stage may comprise a programmable gain amplifier (PGA) (e.g., low noise amplifiers | 2012-11-01 |
20120274399 | Pop-Up Noise Reduction in a Device - A device implementing a scheme for reduction of pop-up noise is disclosed. The device comprises an audio sub-system ( | 2012-11-01 |
20120274400 | LOW POWER DISCRETE-TIME ELECTRONIC CIRCUIT - A low power discrete-time electronic circuit includes an amplifier, and a variable current supply. The variable current supply is electrically connected to the amplifier, and is utilized for supplying high current to the amplifier during a switching operation and supplying low current to the amplifier during a non-switching period. | 2012-11-01 |
20120274401 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - An object is to suppress operation delay caused when a semiconductor device that amplifies and outputs an error between two potentials returns from a standby mode. Electrical connection between an output terminal of a transconductance amplifier and one electrode of a capacitor is controlled by a transistor whose channel is formed in an oxide semiconductor layer. Consequently, turning off the transistor allows the one electrode of the capacitor to hold charge for a long time even if the transconductance amplifier is in the standby mode. Moreover, when the transconductance amplifier returns from the standby mode, turning on the transistor makes it possible to settle charging and discharging of the capacitor in a short time. As a result, the operation of the semiconductor device can enter into a steady state in a short time. | 2012-11-01 |
20120274402 | HIGH ELECTRON MOBILITY TRANSISTOR - A high electron mobility transistor (HEMT) includes a substrate, a heterojunction on the substrate including a first layer having a Group III-nitride semiconductor material interfaced to a second layer having a doped Group III-nitride semiconductor material. A gate electrode is on a surface of the heterojunction, and a source and a drain are on opposite sides of said gate electrode. A patterned field shaping (FS) layer formed from a wide band-gap semiconductor material is over the heterojunction on at least a portion between the gate electrode and the drain. | 2012-11-01 |
20120274403 | AMPLIFIER WITH INTEGRATED FILTER - An amplifier with integrated filter (e.g., an LNA) is described. In one design, the amplifier may include a gain stage, a filter stage, and a buffer stage. The gain stage may provide signal amplification for an input signal. The filter stage may provide filtering for the input signal. The buffer stage may buffer a filtered signal from the filter stage. The amplifier may further include a second filter stage and a second buffer stage. The second filter stage may provide additional filtering for the input signal. The second buffer stage may buffer a second filtered signal from the second filter stage. All of the stages may be stacked and coupled between a supply voltage and circuit ground. The filter stage(s) may implement an elliptical lowpass filter. Each filter stage may include an inductor and a capacitor coupled in parallel and forming a resonator tank to attenuate interfering signals. | 2012-11-01 |
20120274404 | MIXED-SIGNAL INTEGRATOR ARCHITECTURE - A mixed signal correlator utilizes coherent detection within a capacitance measurement application. In some applications, the mixed signal correlator is used to measure capacitance of a touch screen display. An external capacitor whose capacitance is measured is kept small for improved sensitivity and can be used for a variety of applications having varied integration periods for measurement. The external capacitor is kept small and can be used for varied applications by adjusting the output voltage within a range that is less than the supply voltage, and maintaining a count of the adjustments to later reconstruct an actual output voltage for the integration period. An output is a weighted sum of an analog integrator output and a digital counter output. | 2012-11-01 |
20120274405 | AMPLIFIER - An amplifier including: an output stage having two first power supply terminals capable of receiving a first voltage defined by first positive and negative variable potentials with respect to a reference potential; and a circuit for controlling the current in transistors of the output stage with a reference value, wherein the output stage includes a first and a second MOS transistors in series between the first two terminals, the junction point of this series association defining an output terminal of the amplifier; the control circuit includes two measurement MOS transistors having their respective sources and gates coupled to the respective sources and gates of the first and second transistors of the output stage; at least one control branch, comprising transistors in series between two terminals of application of a second voltage, defines nodes connected to the gates of the output transistors, said second voltage being greater than the first one. | 2012-11-01 |
20120274406 | LOW NOISE-LINEAR POWER DISTRIBUTED AMPLIFIER - The present disclosure describes a distributed amplifier (DA) that includes active device cells within sections that are configured to provide an input gate termination that is conducive for relatively low noise and high linearity operation. A section adjacent to an output of the DA is configured to effectively terminate the impedance of an input transmission line of the DA. Each active device cell includes transistors coupled in a cascode configuration that thermally distributes a junction temperature among the transistors. In this manner, noise generated by a common source transistor of the cascode configuration is minimized. The transistors coupled in the cascode configuration may be fabricated using gallium nitride (GaN) technology to reduce physical size of the DA and to further reduce noise. | 2012-11-01 |
20120274407 | LDO WITH DISTRIBUTED OUTPUT DEVICE - A method and apparatus for supplying independently switched, regulated power to a plurality of loads is disclosed. | 2012-11-01 |
20120274408 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode | 2012-11-01 |
20120274409 | INJECTION LOCKING BASED POWER AMPLIFIER - A method, an apparatus and/or a system of injection locking based power amplifier is disclosed. A method includes inputting a reference signal through an injection circuit of an oscillator circuit that generates an output signal of high power that oscillates at an inherent frequency of oscillation of the oscillator circuit. The method also includes reducing a frequency of the reference signal through a differential transistor pair coupled to the injection circuit of the oscillator circuit. The method further includes locking through a tuning circuit of the oscillator circuit coupled to the differential transistor pair a frequency of the output signal to the reduced frequency of the reference signal based on the power of the reference signal to amplify the power of the reference signal through the oscillator circuit. The frequency of the reference signal is higher than the frequency of the output signal. | 2012-11-01 |
20120274410 | OSCILLATOR - The present invention relates to an oscillator. The oscillator includes a resonator unit configured to resonate terahertz waves generated by an active layer using intersubband transitions of a carrier. The oscillator further includes a strain generating unit configured to generate strain of the active layer. Still furthermore, the oscillator includes a control unit configured to control the strain generating unit in accordance with the oscillation characteristic (the frequency or the output) of the terahertz waves resonated by the resonator unit. | 2012-11-01 |
20120274411 | Pulse Width Modulation Driving IC and Pulse Width Modulation Output Signal Generating Method - The present invention discloses a pulse width modulation driving IC. The pulse width modulation driving IC includes a first pin, for receiving a first signal, a second pin, for receiving a second signal, a comparing unit, for comparing the first signal with a reference voltage, to generate a comparison result indicating a operating mode of the pulse width modulation driving IC, and an output unit, for outputting a pulse width modulation output signal according to the first signal, the second signal and the comparison result. | 2012-11-01 |
20120274412 | REMOVABLE COLLAR FOR MATCHING HIGH FREQUENCY IMPEDANCE AND HIGH FREQUENCY CABLE TELEVISION USING THE SAME - A cable television device with high frequency impedance matching includes a housing and a removable collar. The removable collar is disposed on a signal inputting port or a signal outputting port of the housing and a cable wire is connected to the signal inputting port or a signal outputting port. When a high frequency is inputted, the impedance of the removable collar is substantially close to the impedance of the cable wire to reduce the reflected amount of the transmitting signal and the attenuation of the transmitting high frequency signal. | 2012-11-01 |
20120274413 | MONOLITHIC POWER SPLITTER FOR DIFFERENITAL SIGNAL - A monolithic power splitter is used to split a pair of input differential signals into two pairs of output differential signals in the present invention. The monolithic power splitter has two input terminals to receive a pair of input differential signals, and it has two one-by-two power splitters integrated in one single chip to split a pair of input differential signals into two pairs of output differential signals with equal power. And, the monolithic power splitter has four output terminals to output two pairs of output differential signals. In one embodiment, the first one-by-two power splitter and the second one-by-two power splitter are made on the same surface of the substrate. In another embodiment, the first one-by-two power splitter and the second one-by-two power splitter are made on opposite surfaces of the substrate. The monolithic power splitter can be used as a power combiner based on the reciprocal property of the power splitter circuit. | 2012-11-01 |
20120274414 | ISOLATED ZERO DEGREE REACTIVE RADIO FREQUENCY HIGH POWER COMBINER - An exemplary communication device includes a combiner having a first transmission line configured to be coupled with a first communication component. A second transmission line is configured to be coupled with a second communication component. A third transmission line is coupled with the first and second transmission lines. An isolation module is coupled with the first and second transmission lines. The isolation module has a resistance, a capacitance and an inductance configured to isolate the first communication component from the second communication component if one of the components is inoperative. The isolation module components are also configured to provide RF matching for the first and second transmission lines if one of the components is inoperative. | 2012-11-01 |
20120274415 | WIDE BANDWIDTH INTEGRATED 2X4 RF DIVIDER - An improved implementation of a 2×4 divider formed from a bridge junction is described. The bridge junction uses parallel and series connections of coaxial lines to eliminate impedance transformers that are normally required in a 2×4 power divider. In a preferred embodiment, the bridge junction is comprised of UT-085 coax transmission lines, 20 gauge twin lead wire and SB-805-61 ferrite beads with ½ turn windings to provide a wide bandwidth, compact, high power and rugged arrangement. | 2012-11-01 |
20120274416 | LADDER FILTER, DUPLEXER AND MODULE - A ladder filter includes at least one series resonator connected in series between an input terminal and an output terminal, at least one parallel resonator connected in parallel with the at least one series resonator, an additional resonator connected in series between the at least one series resonator and one of the input terminal and the output terminal, and an inductor connected in series to the additional resonator, the additional resonator having a resonance frequency higher than an anti-resonance frequency of the at least one series resonator. | 2012-11-01 |
20120274417 | MULTIPLEXER - A multiplexer that includes three or more band-pass filters having different pass bands and has a reduced size, includes a duplexer and a third band-pass filter connected to an antenna terminal, the duplexer and the third band-pass filter are connected in parallel, the duplexer includes a first band-pass filter having a first pass band and a second band-pass filter having a second pass band different from the first pass band, and the third band-pass filter has a third pass band different from the first and second pass bands. | 2012-11-01 |
20120274418 | BRANCHING FILTER - A branching filter includes a ladder-type elastic wave filter unit connected between an antenna terminal and a transmission signal terminal and a longitudinally coupled resonator-type elastic wave filter unit connected between an antenna terminal and first and second balanced reception signal terminals while maintaining the isolation characteristics between the transmission signal terminal and the first and second reception signal terminals. In a duplexer, a transmission signal propagation direction is perpendicular or substantially perpendicular to each of a first reception signal propagation direction and a second reception signal propagation direction. | 2012-11-01 |
20120274419 | PHASE SHIFTER USING SUBSTRATE INTEGRATED WAVEGUIDE - Provided is a phase shifter using a substrate integrated waveguide (SIW). The phase shifter includes: a substrate; and a waveguide integrated on the substrate, wherein the waveguide includes an input port, an out port, two columns of via walls which are separated by a width of the waveguide and are arranged parallel to each other, and either a plurality of air holes which are formed to shift a phase of a signal between the input port and the output port or a plurality of rods, each including an air hole and a dielectric material inserted into the air hole. | 2012-11-01 |
20120274420 | FILTER CIRCUIT - A bandpass filter includes a multilayer body, which includes a plurality of dielectric layers stacked on top of one another, a first inductor and a second inductor connected in series with each other, and a third inductor connected to a connection point between the first and second inductors, and a ground potential. The first inductor is defined by substantially open-loop-shaped first electrode patterns provided on the dielectric layers being superposed with one another in the stacking direction of the multilayer body. The second inductor and the third inductor are defined by second electrode patterns and third electrode patterns provided on the dielectric layers being superposed with one another in the stacking direction. | 2012-11-01 |
20120274421 | FILTER, DUPLEXER AND COMMUNICATION MODULE - A filter includes at least one series resonator and parallel resonators, the at least one series resonator and the parallel resonators including excitation electrodes and reflectors, the parallel resonators having different resonance frequencies, and at least one of the parallel resonators other than the parallel resonator having the highest resonance frequency being configured to have a pitch of reflectors that is smaller than that of excitation electrodes. | 2012-11-01 |
20120274422 | TUNABLE BANDPASS FILTER - Tunable bandpass filters are provided. In one embodiment, the invention relates to a tunable bandpass filter including a dielectric substrate having a first surface opposite to a second surface, a conductive ground plane disposed on the first surface, a microstrip conductive trace pattern disposed on the second surface, the trace pattern defining a phase velocity compensation transmission line section including a series of spaced alternating T-shaped conductor portions, at least one varactor diode coupled to a first T-shaped conductor portion of the series of T-shaped conductor portions and to the conductive ground plane, and bias control circuitry coupled to the first T-shaped conductor portion, wherein the bias control circuitry is configured to control the at least one varactor diode. | 2012-11-01 |
20120274423 | HIGH-FREQUENCY SIGNAL TRANSMISSION LINE - A flexible high-frequency signal transmission line includes a dielectric body including laminated flexible dielectric layers. A signal line is provided in the dielectric body. A grounding conductor is arranged in the dielectric body to be opposed to the signal line via one of the dielectric layers. The grounding conductor is of a ladder structure including a plurality of openings and a plurality of bridges arranged alternately along the signal line. A characteristic impedance of the signal line changes between two adjacent ones of the plurality of bridges such that the characteristic impedance of the signal line rises from a minimum value to an intermediate value and to a maximum value and falls from the maximum value to the intermediate value and to the minimum value in this order. | 2012-11-01 |
20120274424 | HIGH PERFORMANCE COUPLED COPLANAR WAVEGUIDES WITH SLOW-WAVE FEATURES - A device that includes a coplanar waveguide structure is disclosed. In an example, a device includes a coplanar waveguide structure that is oriented in a first direction, and a slot-type floating shield structure oriented proximate to the coplanar waveguide structure. The slot-type floating shield structure includes a first portion that extends transversely to the coplanar waveguide structure in a second direction and a second portion that extends from the first portion in a third direction that is perpendicular to the first direction and the second direction. | 2012-11-01 |
20120274425 | WIDEBAND ACTIVE QUASI-CIRCULATOR - Aspects describe a wideband active quasi-circulator that has the advantages of small size, lightweight, and compatibility with monolithic microwave integrated circuit (MMIC) technology. An active quasi-circulator is provided that comprises both a power amplifier and a low noise amplifier. The active quasi-circulator can operate over a wide frequency range with isolation or substantial isolation between a power amplifier and a low noise amplifier that is tunable with isolation or substantial isolation at any frequency within the wide frequency range. The provided quasi-circulator is suitable for use in mobile units in multi-band radio frequency communication systems, as well as in other configurations. | 2012-11-01 |
20120274426 | COUPLER AND ELECTRONIC APPARATUS - According to one embodiment, a coupler transmits and receives an electromagnetic wave by electromagnetic coupling between the coupler and another coupler. The coupler includes a line-shaped coupling element having a first open end and a second open end, a ground plane, a feeding element connecting the coupling element and a feed point, and a short circuiting element connecting the coupling element and the ground plane. The feeding element comprises a first end connected to an intermediate portion of the coupling element between the first open end and the second open end, and a second end connected to the feed point. The short circuiting element comprises a third end connected to the intermediate portion of the coupling element, and a fourth end connected to the ground plane. | 2012-11-01 |