44th week of 2009 patent applcation highlights part 19 |
Patent application number | Title | Published |
20090267630 | TESTING DEVICE OF SEMICONDUCTOR DEVICE - A testing device of a semiconductor device includes a first board having a plurality of openings; a frame body provided in the openings, the frame body having a frame in which a plurality of probe needles is provided; and a plurality of second boards provided perpendicular to the first board in the periphery of the openings, the second boards being connected to the first board; wherein the probe needles pierce the frame so as to be connected to the second boards from the periphery of the frame body via the openings. | 2009-10-29 |
20090267631 | Large Component Thermal Head Adapter - A thermal head adapter for testing a device under test is provided that can accommodate a large device and will improve the airflow through the thermal head to the device under test and out into the shroud. The thermal head adapter comprises a first section with a first perimeter and a second section with a second perimeter. The shroud is sealed onto an upper surface of first section, and the base of the second section attaches to a printed board. The perimeter of the first section is greater than the perimeter of the second section. The upper surface of the first section may comprise ridges that effectively form a moat-like structure to capture fallen condensation from the shroud walls. A drain may take the liquid within the boundary of the ridges to a desired location outside of the thermal head adapter. | 2009-10-29 |
20090267632 | SYSTEM AND METHOD FOR TESTING A SOLAR PANEL - A system for testing a solar panel is described. | 2009-10-29 |
20090267633 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor device includes: a command control circuit for decoding a command signal to output a test signal and a normal control signal; a normal circuit for performing a predetermined operation in response to the normal control signal; and a test circuit for testing electrical characteristics of unit elements provided in the normal circuit in response to the test signal. | 2009-10-29 |
20090267634 | Switch Module for Semiconductor Characteristic Measurement and Measurement Method of Semiconductor Characteristics - A switch module is disclosed for semiconductor characteristic measurement and a semiconductor characteristic measurement method is disclosed with which the impact of the recovery effect after stress signal elimination is reduced in BTI testing. The switch module for semiconductor characteristic measurement includes a first input terminal for receiving stress signals from a stress signal source, a second input terminal for receiving signals from a first non-stress signal source, a first output terminal for outputting output signals, and a switch part for controlling the connection of the first output terminal and the first input terminal or the second input terminal, wherein the switch part detects a first voltage transition of the signals transmitted to the second input terminal and modifies the connection. | 2009-10-29 |
20090267635 | METHOD AND APPARATUS FOR HIGH DENSITY SUPERCONDUCTOR CIRCUIT - The disclosure relates to a method for providing a logic circuit element. The method includes arranging a series of Josephson junctions between a first Josephson junction and a second Josephson junction, the first Josephson junction having a first critical current (I | 2009-10-29 |
20090267636 | Security circuit having an electrical fuse ROM - A security circuit includes an electrical fuse read only memory (ROM) including a plurality of electrical fuse units. The electrical fuse units are arranged to correspond to bit values of an initial security key before the electrical fuse ROM is programmed. | 2009-10-29 |
20090267637 | DEVICE AND METHOD FOR TESTING A RESISTANCE VALUE OF ON-DIE-TERMINATION DEVICE AND SEMICONDUCTOR DEVICE HAVING THE SAME - A device and a method for testing a resistance value of an on-die-termination (ODT) device and a semiconductor device having the same are presented. The device can include a comparator, a storage unit and and an output unit. When in an ODT test operation mode, the comparator compares a reference voltage against an input data input to a pad to determine the resistance value of the ODT device and outputs a determination data on the resistance value of the ODT device corresponding to the determination results. The storage unit stores the output of the comparator in synchronization with a clock signal. When in the ODT test operation mode, the output unit outputs the determination data on the resistance value of the ODT device stored in the storage unit to the pad. Thereby not only is the device configured to determine whether or not a defect of the resistance value of the ODT device exists but the device and the method are able to achieve this task in a substantially shorter testing time period. | 2009-10-29 |
20090267638 | Apparatus, System and Method of Power State Control - An apparatus, system and method for asynchronously reducing power in a power domain. In one embodiment, the method includes: (1) receiving a sleep command for the power domain, (2) receiving, upon receiving the sleep command, an affirmative retention status signal denoting that a retention area in the power domain has stored data, (3) receiving, upon receiving the sleep command, an affirmative isolation status signal that denotes that an isolation of the power domain has occurred and (4) providing a power domain off command to the power domain upon receiving at least the sleep command, the affirmative status retention signal and the affirmative status isolation signal. In another embodiment, multiple enable signals are employed to generate a “glitch-free” control for a power switch. | 2009-10-29 |
20090267639 | INPUT CANCELLATION CIRCUIT - A system and method are provided for isolating an input without adding significant distortion and without significantly adversely affecting the bandwidth of input circuits. In one embodiment, a single ended signal is substantially cancelled by an arrangement including an input resistance path in parallel with a negative resistance path wherein both paths substantially match in resistance. In another embodiment, a differential signal is substantially cancelled by a pseudo differential arrangement including two independent input resistance paths each in parallel with a corresponding negative resistance path, wherein the resistance paths substantially match the input resistance paths. In yet another embodiment, a differential signal is substantially cancelled by a differential arrangement including two resistance paths wherein a first negative resistance path is coupled between the first differential input and the second differential output and the second negative resistance path is coupled between the second input and the first output. In yet another embodiment, a current controlled current source may provide the negative amplification for the negative resistance path. | 2009-10-29 |
20090267640 | SYSTEM INCLUDING PREEMPHASIS DRIVER CIRCUIT AND METHOD - A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver. | 2009-10-29 |
20090267641 | I/O Driver For Integrated Circuit With Output Impedance Control - An I/O driver has v/i characteristic control for maintaining a substantially flat output impedance response using a transmission gate configuration at an I/O output pad. The configuration includes a linear resistive element electrically connected at an I/O pad for limiting a processed data I/O signal, an active impedance element for receiving and processing the data signal, which comprises data represented by a series of voltage state transitions, and pull-up and pull-down array calibration words, for generating and outputting a processed I/O output signal to the resistive element to output a substantially flat v/i response at switching of the data signal. | 2009-10-29 |
20090267642 | METHOD AND APPARATUS FOR OUTPUT DRIVER CALIBRATION, AND MEMORY DEVICES AND SYSTEM EMBODYING SAME - A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average of a plurality of pull-up count signals. The calibration circuit further includes a pull-down calibration circuit configured to generate an averaged pull-down count signal for calibrating n-channel devices in the output driver with the averaged pull-down count signal being an average of a plurality of pull-down count signals. | 2009-10-29 |
20090267643 | FLEXIBLE ADDER CIRCUITS WITH FAST CARRY CHAIN CIRCUITRY - Configurable adder circuitry is provided on an integrated circuit that includes redundant circuitry. The integrated circuit may contain nonvolatile memory and logic circuitry that produces a redundancy control signal. During manufacturing, the integrated circuitry may be tested. If a defect is identified on the integrated circuit, the redundancy control signal may be used in switching redundant circuitry into place bypassing the defect. The integrated circuit may contain an array of logic regions. Each logic region may contain adders and multiplexer circuitry for selectively combining the multiplexers to form larger adders. The multiplexer circuitry in each logic region may be controlled by propagate signals from the adders and by static redundancy control signals. | 2009-10-29 |
20090267644 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit has a voltage supply terminal; a first input terminal fed with a first input signal; an output terminal that outputs an output signal; a second input terminal fed with a second input signal; a first MOS transistor having one end connected to the voltage supply terminal and a gate electrode connected to the first input terminal; a second MOS transistor having one end connected to a first potential, an other end connected to the output terminal, and a gate electrode connected to the second input terminal; and a program element acting as a MOS transistor having one end connected to the other end of the second MOS transistor and an other end connected to a second potential higher than the first potential. | 2009-10-29 |
20090267645 | PASSGATE STRUCTURES FOR USE IN LOW-VOLTAGE APPLICATIONS - Enhanced passgate structures for use in low-voltage systems are presented in which the influence of V | 2009-10-29 |
20090267646 | Nano-Electron Fluidic Logic (NFL) Device - A nano-electron fluidic logic (NFL) device for controlling launching and propagation of at least one surface plasma wave (SPW) is disclosed. The NFL device comprises a metallic gate patterned with a plurality of terminals at which SPWs may be launched and a plurality of drain terminals at which the SPWs may be detected. A wave guiding structure such as a 2 DEG EF facilitates propagation of the SPW within the structure so as to scatter/steer the SPW in a direction different from a pre-scattering direction. A bias SPW is excited by an application of a control SPW with a momentum vector at an angle to the bias SPW and a control current with a wavevector which scatters the bias SPW in the direction of at least one output SPW, towards a drain terminal. The NFL device being rendered with device speed as a function of SPW propagation velocity. | 2009-10-29 |
20090267647 | Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics - A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer. | 2009-10-29 |
20090267648 | Apparatus for configuring I/O signal levels of interfacing logic circuits - Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible. | 2009-10-29 |
20090267649 | Clock Gating System and Method - A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal. | 2009-10-29 |
20090267650 | PASSIVE OFFSET AND OVERSHOOT CANCELLATION FOR SAMPLED-DATA CIRCUITS - A zero-crossing detector with effective offset cancellation includes a set of series connected capacitors and an amplifier having an input terminal. An offset capacitor is operatively connected between the amplifier and the set of series connected capacitors. A switch is operatively connected to the input terminal, and an offset sampling capacitor is operatively connected to the switch. The switch connects the offset sampling capacitor to the input terminal of the amplifier during a charge transfer phase. | 2009-10-29 |
20090267651 | SWITCH STATE DETECTOR AND ENCODER - A switch state detector for use in a system wherein a plurality of n switches (S | 2009-10-29 |
20090267652 | METHODS AND CIRCUITS FOR TRIODE REGION DETECTION - The present invention relates to circuits and methods for detecting transistor operation in the triode region including a circuit for a transistor in a constant current source. The circuit comprises a detector having a first input, a second input, and an output. The first input of the detector is coupled to the source of the transistor and the second input of the detector is coupled to the set point terminal of the constant current source. The circuit also comprises a flag coupled to the detector output. The detector has parameters selected so that, when the voltage at the source of the transistor satisfies a reference condition, the output of the detector sets the flag. The reference condition is established relative to the voltage at the set point terminal of the constant current source and relative to the triode transition voltage of the transistor at a selected drain-source current. | 2009-10-29 |
20090267653 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - For a semiconductor integrated circuit device such as AFE including a CDS amplifier, in case of excessive signal input to the CDS amplifier, a technique capable of preventing the response characteristic of the CDS amplifier from deteriorating is provided. In the AFE including the CDS amplifier, the CDS amplifier is prevented from becoming saturated by detecting an excessive signal input and triggering the reset of the CDS amplifier. Thereby, no abnormality occurs in the transient response of the CDS amplifier. Specifically, comparison of input signals to the CDS amplifier is performed by a comparator and the CDS amplifier is reset by a reset circuit (by fixing the input terminals of the CDS amplifier to a constant voltage) in case of excessive signal input, so that the CDS amplifier will not amplify excessive signal inputs. | 2009-10-29 |
20090267654 | High-Speed Transmit Driver Switching Arrangement - The invention relates to a line driver to drive a transmission line with a differentially balanced signal, with selectable signal amplitude, with output impedance matched to a characteristic impedance of the transmission line, and with reduced dissipation. The line driver includes a first driver subcircuit including a first and a second group of resistors. To drive an output node with a first signal sense, the first group of resistors is selectively coupled to a first bias voltage terminal and the second group to a second bias voltage terminal. To drive the first output node with a second signal sense, the first and second groups of resistors are both selectively coupled to the second bias voltage terminal. The line driver includes a second driver subcircuit. The second driver subcircuit includes a third and fourth group of resistors that are correspondingly switched. | 2009-10-29 |
20090267655 | ANALOG BUFFER WITH VOLTAGE COMPENSATION MECHANISM - An analog buffer having voltage compensation mechanism is disclosed for use in a source driving circuit of a liquid crystal display. The analog buffer includes a reference voltage generator, a plurality of capacitors, a plurality of switches, and a plurality of transistors. Each of the capacitors is utilized to store the gate-source voltage of the corresponding turn-on transistor for performing gate-source voltage compensation operation based on the reference voltages provided by the reference voltage generator. Each of the switches functions to control gate-source voltage compensation operation and is turned on/off in response to a corresponding control signal. The analog buffer is capable of compensating the gate-source voltages of turn-on transistors for generating an output voltage having an acceptable tiny offset with respect to an input voltage. | 2009-10-29 |
20090267656 | PRECISION TRIANGLE WAVEFORM GENERATOR - A triangle waveform generator is set forth that comprises a capacitive element, a regulator, and a control circuit. The regulator is configured to charge the capacitive element in responsive to a first control signal and to discharge the capacitive element in response to a second control signal. The control circuit is responsive to a reference waveform to generate the first and second control signals. In one example, the control circuit generates the first and second control signals in response to the amplitude, frequency, phase, and symmetry of the reference waveform. | 2009-10-29 |
20090267657 | METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION - A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other. | 2009-10-29 |
20090267658 | Synchronizing Frequency and Phase of Multiple Variable Frequency Power Converters - In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other. Each synchronization circuit is operable to: receive a first input signal indicative of the beginning of a switching period for the associated variable frequency power converter; receive a second input signal indicative of the end of the switching period for the associated variable frequency power converter; generate a first output signal for directing a pulse width modulation of the associated variable frequency power converter; and generate a second output signal for coordinating a phase relationship with another variable frequency power converter in the system. | 2009-10-29 |
20090267659 | POWER-ON RESET CIRCUIT AND ELECTRONIC DEVICE USING THE SAME - A power-on reset circuit, connected to an external direct current (DC) power source, to receive DC power signals and generate a reset signal, includes a delay circuit, a combination circuit and a shaping circuit. The delay circuit comprises a plurality of delay units, to delay the received DC power signals and output a plurality of delayed DC power signals. The combination circuit is connected to the delay circuit, to combine the delayed DC power signals into a combination signal, and output the combination signal. The shaping circuit is connected to and turns the combination circuit on and off according to the combination signal and outputs the reset signal. | 2009-10-29 |
20090267660 | Circuit and design structure for synchronizing multiple digital signals - Disclosed is a circuit configured to synchronize multiple signals received by one clock domain from a different asynchronous clock domain, when simultaneous movement of the signals between the clock domains is intended. In the circuit multiple essentially identical pipelined signal paths receive digital input signals. XOR gates are associated with each of the signal paths. Each XOR gate monitors activity in a given signal path and controls, directly or indirectly (depending upon the embodiment), advancement of signal processing in the other signal path(s) to ensure that, if warranted, output signals at the circuit output nodes are synchronized. In a two-signal path embodiment, advancement of signal processing in one signal path is triggered, whenever transitioning digital signals are detected within the other signal path. In an n-signal path advancement of signal processing is triggered in all signal paths, whenever transitioning digital signals are detected on at least one signal path. | 2009-10-29 |
20090267661 | PLL CONTROL CIRCUIT - A PLL control circuit, which outputs a PLL clock in response to a reference clock, is provided with a frequency adjustment circuit which performs frequency adjustment such that the PLL clock frequency is substantially constant even when the reference clock varies. The frequency adjustment circuit changes a set value in a counter, which determines the PLL clock frequency, in accordance with the variation in the reference clock frequency. | 2009-10-29 |
20090267662 | FAST RESPONSE PHASE-LOCKED LOOP CHARGE-PUMP DRIVEN BY LOW VOLTAGE INPUT - Phase-locked loop charge pump driven by low voltage input. In one aspect, a charge pump for a phase-locked loop circuit includes a sourcing current transistor providing a sourcing current, wherein the sourcing current transistor is coupled to a high-voltage operating voltage supply. A sourcing control circuit uses low-voltage sourcing control signals to selectively cause the charge pump to source the sourcing current to an output of the charge pump, and a sinking control circuit uses low-voltage sinking control signals to selectively cause the charge pump to sink the sinking current from the output. | 2009-10-29 |
20090267663 | ELECTRONIC SYSTEM THAT ADJUSTS DLL LOCK STATE ACQUISITION TIME - One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode. | 2009-10-29 |
20090267664 | PLL CIRCUIT - In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked. | 2009-10-29 |
20090267665 | SEMICONDUCTOR MEMORY DEVICE FOR GENERATING A DELAY LOCKED CLOCK IN EARLY STAGE - A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output. | 2009-10-29 |
20090267666 | Phase Difference Detector And Phase Difference Detection Method - A phase difference detector for detecting a phase difference between input clocks which both have a same first frequency, including: a pulse width conversion unit for converting the input clocks into a phase difference signal indicating by a pulse width a phase difference between the input clocks; and a counter unit which samples a level of the phase difference signal using a reference clock having a second frequency which is slower than the first frequency, and counts the number of levels of the phase difference signal using a first weighting according to the sampled level of the phase difference signal. When the count value of the counter unit transits in a predetermined range, the phase difference between the input clocks is detected according to the first weighting. | 2009-10-29 |
20090267667 | Low Power Programmable Clock Delay Generator with Integrated Decode Function - A programmable Local Clock Buffer has a single inverter between the clock input and the delayed clock output. A transistor switch modulates the single inverter stage between a clock signal transmit state and a non-transmitting state. A combination of delay select bits control the timing of the beginning and ending of the transmit state of the inverter relative to the clock input via the transistor switch. | 2009-10-29 |
20090267668 | METHOD AND APPARATUS FOR CALIBRATING A DELAY CHAIN - Apparatus and methods are provided for calibration within a delay chain. In various embodiments, such apparatus and techniques can be used to address delay mismatch, but are not limited to such applications. Additional apparatus, systems, and methods are disclosed. | 2009-10-29 |
20090267669 | Microwave Generating Apparatus and Microwave Generating Method - The present invention is a microwave generating apparatus comprising: a switch signal generator that generates a square wave switch signal having a fundamental frequency of a microwave band; a switching power amplifier that performs a switching power amplification based on the switch signal so as to output an amplified signal; a variable voltage supplier that is capable of variably supplying a driving voltage for amplification to the switching power amplifier; a microwave selector that extracts from the amplified signal a sine wave signal of the same frequency as the fundamental frequency of the switch signal so as to output the same as a microwave; an output signal detector that detects the microwave; and a driving voltage controller that controls the variable voltage supplier based on a result detected by the output signal detector. | 2009-10-29 |
20090267670 | CIRCUIT WITH PARALLEL FUNCTIONAL CIRCUITS WITH MULTI-PHASE CONTROL INPUTS - A circuit has a plurality of functional circuits ( | 2009-10-29 |
20090267671 | OPTIMIZATION OF LIBRARY SLEW RATIO BASED CIRCUIT - Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions. | 2009-10-29 |
20090267672 | SERIAL PERIPHERAL INTERFACE (SPI) CIRCUIT AND DISPLAY USING THE SAME - A serial peripheral interface (SPI) circuit and a display using the same are provided. The SPI circuit includes a mater device and a slave device. A serial data input pin and a serial data output pin of the slave device are both electrically connected to a data input/output pin of the master device. When a read instruction is sent from the master device to the slave device, the master device is set in a read status, and the slave device outputs data to the master device via the serial data output pin in response to the read instruction. When a write instruction is sent from the master device to the slave device, the master device is set in a write status, and writes data to the slave device via the serial data input pin thereof in response to the write instruction. | 2009-10-29 |
20090267673 | SIGNAL GENERATION CIRCUIT - A signal generation circuit that uses a waveform generation mechanism to generate predetermined waveform(s) when triggered. A triggering mechanism is configured to repeatedly trigger the waveform generation mechanism at times that are dependent on data provided by a data source. The predetermined waveform may be a bandwidth-limited pulse, but might also be a rising edge or a falling edge of a pulse. Various consecutive waveforms may be summed together to thereby formulate a continuous signal. The waveform may have particular characteristics by design. | 2009-10-29 |
20090267674 | Clock control circuit and semiconductor memory device using the same - A clock control circuit comprises a control signal generating unit configured to generate a control signal disabled in a predetermined state while in an active mode, and a clock transferring unit configured to transfer an external clock in response to the control signal. | 2009-10-29 |
20090267675 | Offset compensation using non-uniform calibration - Methods and systems for offset compensation using calibration are provided. Embodiments enable offset compensation using non-uniform calibration. Embodiments enable calibration schemes configurable according to the probability distribution function (PDF) of the random offset. Embodiments enable calibration schemes configurable with multiple levels of calibration resolution according to the PDF of the random offset. Embodiments enable calibration schemes configurable with multiple calibration step values according to the PDF of the random offset. Embodiments can be implemented for various types of random offset, including, without limitation, Gaussian-, Bernoulli-, uniformly-, Chi-, exponentially-, Gamma-, and Pareto-distributed offset. | 2009-10-29 |
20090267676 | MULTI-INPUT MIXER, MIXER DEVICE, AND MIXING METHOD - A mixer device includes a differential circuit, a transconductance circuit, and a selecting circuit. The differential circuit receives a differential input signal and generates a differential output signal. The transconductance circuit is coupled to the differential circuit, receives a plurality of radio frequency input signals, and determines to mix at least one of the radio frequency input signals with the differential input signal according to an enable signal. The selecting circuit receives a control signal and generates the enable signal according to the control signal. | 2009-10-29 |
20090267677 | COMPACT EJECTABLE COMPONENT ASSEMBLIES IN ELECTRONIC DEVICES - Electronic devices are provided with ejectable component assemblies. The ejectable component assembly may include a tray that can be loaded with one or more removable modules, wafers coupled to circuit boards, cages and retaining plates to assist in retaining the tray within the assembly. The ejectable component assembly may include springs operative to engage detents in the tray to retain the tray in the assembly. The ejectable component assembly may include a tray ejector mechanism for ejecting the tray from the assembly. | 2009-10-29 |
20090267678 | Integrated Circuit with Improved Data Rate - An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed. | 2009-10-29 |
20090267679 | Analog multiplexer and its select signal generating method - To provide an analog multiplexer capable of extending the frequency characteristic of the analog multiplexer in terms of frequency band. The analog multiplexer | 2009-10-29 |
20090267680 | POWER DRIVING DEVICE FOR ELECTRONIC DEVICE - The present invention discloses a power driving device for an electronic device, comprising: a data input terminal capable of receiving a sequential data comprising at least a first power control sequential data and at least a second power control sequential data; an operation module capable of performing operation on the first power control sequential data and the second power control sequential data to generate a control signal; and a power control module coupled to the operation module to generate at least an output power according to the control signal. Therefore, the control signal can be used to control various power states of an electronic device. | 2009-10-29 |
20090267681 | Integrated Circuit and Method of Configuring an Integrated Circuit - An integrated circuit comprises an output terminal to be coupled to a non-linear circuit element, an output circuit coupled to the output terminal, the output circuit being configured to supply an operating signal to the non-linear circuit element, a measuring circuit coupled to the output terminal, the measuring circuit being configured to sense on the output terminal a signal value outside an operating regime of the non-linear circuit element, and a control circuit coupled to the measuring circuit, the control circuit being configured to configure at least one function of the integrated circuit on the basis of the signal value sensed by the measuring circuit. | 2009-10-29 |
20090267682 | HIGH PRECISION POWER-ON-RESET CIRCUIT WITH AN ADJUSTABLE TRIGGER LEVEL - An electronic device comprising circuitry for providing a Power-on-Reset (POR) signal as a function of a supply voltage level of the circuitry. The circuitry comprises a Vbe-cell or a Vgs-cell comprising a first current path including a first transistor and a second current path including a second transistor. Each transistor has a control terminal for controlling a first current in the first current path and a second current in the second current path, wherein a control voltage level is commonly applied to the control terminals of the first and the second transistor. The control voltage level is derived from the current supply voltage level of the circuitry, and the circuitry further comprises a POR output node for providing a POR output signal, which changes from a first state to a second state in response to the ratio of the magnitudes of the first current and the second current. | 2009-10-29 |
20090267683 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR DEVICE - Embodiments of the present invention are directed to provide an internal voltage generator of a semiconductor memory device for generating a predetermined stable level of an internal voltage. The semiconductor memory device includes a control signal generator, an internal voltage generator and an internal voltage compensator. The control signal generator generates a reference signal and a compensating signal which are corresponding to voltage level of the reference signal. The internal voltage generator generates an internal voltage in response to the reference signal. The internal voltage compensator compensates the internal voltage in response to the compensating signal. | 2009-10-29 |
20090267684 | INTERNAL VOLTAGE GENERATING CIRCUIT OF SEMICONDUCTOR DEVICE - An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driver configured to pull up the internal voltage terminal during a predefined time in each period corresponding to a frequency of an external clock. | 2009-10-29 |
20090267685 | Circuit and method for controlling internal voltage - A circuit for controlling an internal voltage is provided. | 2009-10-29 |
20090267686 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed. The second circuit block has an input unit which receives signals supplied from the first circuit block, and the input unit of the second circuit block has an input circuit which, in accordance with a control signal sent from said third circuit block to said second circuit block, causes a specific signal level to be maintained in compliance with the operating voltage of the second circuit block irrespective of the signal supplied from the first circuit block when the third circuit block instructs the second power supply state to the first circuit block. | 2009-10-29 |
20090267687 | CHOPPER-STABILIZED AMPLIFIER AND MAGNETIC FIELD SENSOR - A chopper-stabilized amplifier has switching networks arranged to support a high frequency clocking signal and to provide a high common mode rejection and a high rejection of an offset component of an input signal. A magnetic field sensor includes a Hall effect element coupled to a modulation circuit. The modulation circuit provides a signal to the chopper-stabilized amplifier. The chopper-stabilized amplifier provides an output signal to a low pass filter, which provides an output signal from the magnetic field sensor. | 2009-10-29 |
20090267688 | COMBINED FEEDBACK AND FEED-FORWARD LINEARIZATION OF RF POWER AMPLIFIERS - A power amplifier module and corresponding system are disclosed for linearizing the output from a power amplifier. Both a feedback system, containing a compensator and the power amplifier in a feedback loop, and a pre-distortion compensation system injecting pre-distortion signals into or before the feedback system are used to compensate for non-linearities in the overall system. The pre-distortion signals may be mixed with signals from the compensator or may be filtered to take into account the loop compensator transfer function of the feedback loop, mixed with baseband signals and then converted into analog signals that are provided to the feedback loop. In modules containing a tracking power supply, an envelope calculator calculates an RF envelope of the baseband signals, which the pre-distortion system uses in conjunction with the baseband signals to generate the pre-distortion signals mixed with the signals from the compensator. | 2009-10-29 |
20090267689 | HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE - A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts. | 2009-10-29 |
20090267690 | SIGNAL MODULATION DEVICE AND SIGNAL AMPLIFIER COOPERATIVE THEREWITH - A signal modulation device and a signal amplifier cooperative therewith. The signal modulation device includes a local oscillation signal source, a baseband signal source, a first NMOS transistor, and a second NMOS transistor, wherein the first and second NMOS transistors are coupled with the baseband signal source and form a circuit architecture of a Gilbert-cell based differential pair to be directly switched by a differential baseband signal, and a high-frequency signal from the local oscillation signal source is controlled by the baseband signal so as to generate an amplitude-modulation high-frequency signal at an output end. The single-stage signal power amplifier amplifies the amplitude-modulation signal from the preceding circuit so as to increase the magnitude of signals transmitted and simplify the preceding digital/analog signal conversion circuit in a conventional amplitude-modulation circuit. | 2009-10-29 |
20090267691 | AMPLIFIER CIRCUIT - A differential amplifier circuit | 2009-10-29 |
20090267692 | DIGITALLY VARIABLE GAIN AMPLIFIER USING MULTIPLEXED GAIN BLOCKS - A digitally variable gain amplifier comprising a front-end stage, a level shifter stage, and an output amplifier stage. The front-end stage comprises a high gain pre-amplifier and a low gain pre-amplifier driven in parallel by a differential input signal. A coarse gain control is realized by enabling only one pre-amplifiers at a time, while the differential input signal remains connected to the inputs of the disabled pre-amplifier. An attenuator following each pre-amplifier provides fine gain control. The enabled pre-amplifier amplifies the differential input signal and outputs a first dc voltage level. The disabled pre-amplifier is placed into a standby ready mode and outputs a second dc voltage level that is greater in magnitude than the first dc voltage level. The level shifter stage performs a minimum voltage selection operation to automatically select and level shift the amplified differential input signal, and further pass the signal to the output amplifier stage. | 2009-10-29 |
20090267693 | RESISTOR SELF-TRIM CIRCUIT FOR INCREASED PERFORMANCE - In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors. | 2009-10-29 |
20090267694 | APPARATUS FOR RECEIVING INPUT AND BIAS SIGNALS AT COMMON NODE - An apparatus includes an input-bias node and an internal load. The input-bias node is configured to simultaneously receive an input signal and a bias signal through an input-bias port. The internal load is connected between the input-bias node and multiple output ports, at least one of the output ports outputting an output signal based on the input signal received at the input-bias node. | 2009-10-29 |
20090267695 | Class AB output stage with programmable bias point control - A class AB output stage includes a driver to generate a first drive signal and a second drive signal, and two bias voltage sources to provide two bias voltages to level shift the first and second drive signals, in order to drive a pair of high side and low side transistors, respectively. A control circuit provides a control signal to adjust the first and second bias voltages, so as to shift the bias point of the class AB output stage. The control signal is determined according to the currents in the high side and low side transistors and a programmable parameter. By adjusting the parameter, the bias point deviation can be removed to obtain both low quiescent current and best THD performance. | 2009-10-29 |
20090267696 | HIGH SLEW RATE AMPLIFIER, ANALOG-TO-DIGITAL CONVERTER USING SAME, CMOS IMAGER USING THE ANALOG-TO-DIGITAL CONVERTER AND RELATED METHODS - An amplifier, which may be used in a pipelined analog-to-digital converter, includes a first amplifier stage driving a second amplifier stage. At least one compensation capacitor is coupled to provide negative feedback through the capacitor from the second amplifier stage to the first amplifier stage. The slew rate of the amplifier is enhanced by substantially reducing the negative feedback coupled through the capacitor during a period following the transition of a signal applied to an input terminal of the amplifier. If the first stage of the amplifier has complementary signal nodes, the negative feedback coupled through the capacitor may be reduced, for example, by closing a switch coupled between first and second complementary nodes of the first amplifier stage. | 2009-10-29 |
20090267697 | Frequency synthesizer using a phase-locked loop and single side band mixer - A frequency synthesizer is built using a phase locked loop incorporating a single side band mixer in the input. The single side band mixer is preferably realized with digital logic and FETs, and the resulting frequency synthesizer simultaneously improves control over the frequency resolution, noise floor and operating frequency range. | 2009-10-29 |
20090267698 | DUAL SUPPLY INVERTER FOR VOLTAGE CONTROLLED RING OSCILLATOR - A voltage controlled ring oscillator reduces sensitivity of an oscillation frequency to a control voltage by using a dual supply inverter logic circuit. The dual supply inverter logic circuit includes two inverter circuits coupled in parallel between an input terminal and an output terminal. The first inverter circuit is powered by a variable supply voltage while the second inverter circuit is powered by a substantially fixed supply voltage. The variable supply voltage serves as the control voltage for the voltage controlled ring oscillator and sets the oscillation frequency. The sensitivity of the oscillation frequency to changes in the variable supply voltage is reduced due to the parallel connection of the second inverter circuit powered by a different supply voltage. | 2009-10-29 |
20090267699 | TIMING OSCILLATORS AND RELATED METHODS - Timing oscillators as well as related methods and devices are described. A timing oscillator may include a mechanical resonating structure with major elements and minor elements coupled to the major element. The timing oscillator can generate stable signals with low phase noise at very high frequencies which allows a timing oscillator to be used effectively in a number of devices including computers and mobile phones for time and data synchronization purposes. The signal generated by the timing oscillator can be tuned using a driver circuit and a compensation circuit. | 2009-10-29 |
20090267700 | TIMING OSCILLATORS AND RELATED METHODS - Timing oscillators as well as related methods and devices are described. A timing oscillator may include a mechanical resonating structure with major elements and minor elements coupled to the major element. The timing oscillator can generate stable signals with low phase noise at very high frequencies which allows a timing oscillator to be used effectively in a number of devices including computers and mobile phones for time and data synchronization purposes. The signal generated by the timing oscillator can be tuned using a driver circuit and a compensation circuit. | 2009-10-29 |
20090267701 | QUADRATURE MODULATOR AND CALIBRATION METHOD - A quadrature modulator and a method of calibrating same by applying a first test tone signal to an in-phase modulation branch input of the modulator and a ninety degree phase-shifted version of the first test tone signal to a quadrature modulation branch input of the modulator. The carrier leakage level in an output signal of the modulator is measured and in response base band dc offset voltages are adjusted to minimize the carrier leakage. A second test tone signal is applied to the in-phase modulation branch input and a ninety degree phase-shifted version of the second test tone signal to the quadrature modulation branch input. The level of an undesired upper sideband frequency component in the output signal is measured and in response base band gains the in-phase and quadrature modulation branches and a local oscillator phase error are adjusted to minimize the undesired side band. | 2009-10-29 |
20090267702 | PRINTED CIRCUIT BOARD FOR DECREASING WIRELESS WIDE AREA NETWORK NOISE - A printed circuit board (PCB) capable of decreasing wireless wide area network (WWAN) noise generated due to internal signal interference occurring in the PCB is disclosed. The PCB printed circuit board includes a first layer, a second layer, and at least one insulating layer formed between the first and second layers. The PCB board further includes a first signal line group disposed on the first layer while including a plurality of first signal lines each supplying a first signal, isolation patterns disposed on the first layer such that the isolation patterns are arranged between adjacent ones of the first signal lines, respectively, to prevent the adjacent first signal lines from interfering with each other, and a second signal line group disposed on the second layer while including a plurality of second signal lines each supplying a second signal different from the first signal. The second signal line group corresponds to the isolation patterns. | 2009-10-29 |
20090267703 | DYNAMICALLY ADAPTABLE IMPEDANCE MATCHING CIRCUITRY BETWEEN AN ELECTRO-OPTICAL LOAD AND A DRIVING SOURCE - A system including a driving source that supplies an alternating current (AC) electrical signal is provided. At least one electro-optical device is coupled as an electrical load of the driving source. The system further includes an apparatus configured to provide a dynamically adaptable electrical impedance matching between the driving source and the electro-optical load over a frequency range. | 2009-10-29 |
20090267704 | CAPACITOR DEVICES WITH A FILTER STRUCTURE - A capacitor device is provided. The capacitor device includes at least one capacitor. The capacitor device also includes a first capacitor and a first filter coupling the first capacitor and a conductive region, wherein the first capacitor has a first resonance frequency and the first filter is configured to operate at a first frequency band covering the first resonance frequency. | 2009-10-29 |
20090267705 | TUNABLE MATCHING NETWORK CIRCUIT TOPOLOGY SELECTION - Tunable matching network topologies are disclosed. A network in accordance with the present invention comprises at least one inductor, and at least one tunable capacitor, in parallel with the inductor, wherein the at least one tunable capacitor tunes the at least one inductor self-resonant frequency. | 2009-10-29 |
20090267706 | RESONATOR AND FABRICATION METHOD THEREOF - A resonator fabrication method is provided. A method includes providing a plurality of electrode patterns disposed apart from each other on a substrate using a nano-imprint technique; and forming an extended electrode pattern connected to a plurality of electrode patterns, and forming a nano structure laid across an extended electrode patterns. Therefore, a nano-electromechanical system (NEMS) resonator is easily fabricated at a nanometer level. | 2009-10-29 |
20090267707 | ELASTIC WAVE DEVICE - An elastic wave device is described which includes a piezoelectric substrate, comb-shaped electrodes having teeth electrodes that are disposed so as to face each other on the piezoelectric substrate, a non-overlapping area in which the teeth electrodes of the comb-shaped electrodes do not overlap each other, and a overlapping area in which the teeth electrodes overlap each other and the velocity of sound is higher than that in the non-overlapping area. | 2009-10-29 |
20090267708 | Dielectric Filter - A dielectric filter having a dielectric block disposed on a mount board. The dielectric block includes inner conductor holes having open ends on the front surface of the dielectric block. Input/output electrodes are disposed on the undersurface of the dielectric block. Each of the input/output electrodes extends from the boundary between a side surface and the undersurface of the dielectric block to the boundary between the front surface and the undersurface of the dielectric block. An outer conductor includes undersurface electrode corner portions and an undersurface electrode main portion. Each of the undersurface electrode corner portions is disposed at a corner formed by the front surface and one of the side surfaces of the dielectric block. | 2009-10-29 |
20090267709 | WIRELESS NON-RADIATIVE ENERGY TRANSFER - The electromagnetic energy transfer device includes a first resonator structure receiving energy from an external power supply. The first resonator structure has a first Q-factor. A second resonator structure is positioned distal from the first resonator structure, and supplies useful working power to an external load. The second resonator structure has a second Q-factor. The distance between the two resonators can be larger than the characteristic size of each resonator. Non-radiative energy transfer between the first resonator structure and the second resonator structure is mediated through coupling of their resonant-field evanescent tails. | 2009-10-29 |
20090267710 | WIRELESS NON-RADIATIVE ENERGY TRANSFER - The electromagnetic energy transfer device includes a first resonator structure receiving energy from an external power supply. The first resonator structure has a first Q-factor. A second resonator structure is positioned distal from the first resonator structure, and supplies useful working power to an external load. The second resonator structure has a second Q-factor. The distance between the two resonators can be larger than the characteristic size of each resonator. Non-radiative energy transfer between the first resonator structure and the second resonator structure is mediated through coupling of their resonant-field evanescent tails. | 2009-10-29 |
20090267711 | High frequency circuit - A circuit has a first coplanar line including a first strip conductor formed on the first plane of a dielectric substrate and a first grounded conductor formed on the first plane and disposed on one side of the first strip conductor, and a second coplanar line including a second strip conductor formed on a second plane of the dielectric substrate and a second grounded conductor formed on the second plane and disposed on one side of the second strip conductor, where the first strip conductor and the second strip conductor are electrically connected in parallel and are plane symmetric with respect to the dielectric substrate, and the first grounded conductor and the second grounded conductor are electrically connected in parallel and are plane symmetric with respect to the dielectric substrate. | 2009-10-29 |
20090267712 | FEED THRU WITH FLIPPED SIGNAL PLANE USING GUIDED VIAS - An embodiment of the invention includes a high speed feed thru connecting a first circuit outside a housing to a second circuit inside the housing. The first circuit includes a first high speed integrated circuit chip and the second circuit includes a second high speed integrated circuit chip or optoelectronic device. The high speed feed thru includes an inside coplanar structure positioned at least partially inside the housing, the inside coplanar structure connected to the second circuit. The high speed feed thru also includes an outside coplanar structure positioned at least partially outside the housing, the outside coplanar structure connected to the first circuit. A material separates the inside coplanar structure and the outside coplanar structure. At least one guided via extends through the material, connecting the inside coplanar structure and the outside coplanar structure. | 2009-10-29 |
20090267713 | HIGH-FREQUENCY TRANSMISSION LINE - A high-frequency transmission line includes: a dielectric substrate; a signal line formed on one surface of the dielectric substrate; a first and a second surface ground patterns formed so as to sandwich the signal line at a given distance from the signal line on the surface of the dielectric substrate; a backside surface ground pattern formed on another surface of the dielectric substrate; and a plurality of contacts penetrating the dielectric substrate for connecting the first and the second surface ground pattern to the backside surface ground pattern. In a given frequency range, the sum of the shortest distance from any point of the first and the second surface ground patterns to the nearest contact and the thickness of the dielectric substrate is shorter than ¼ of the effective wavelength of a transmission signal converted in the effective permittivity of the dielectric substrate. | 2009-10-29 |
20090267714 | SWITCH-STATE MONITORING DEVICE - Provision is made for a switch-state monitoring device that not only monitors the state of a switch but also prevents a motor burnout. A switch-state monitoring device for a switch that opens and closes a main circuit by use of a motor is provided with an operating time measuring unit for detecting an operating time for the motor when the switch is opened or closed; a first determination unit for comparing an operating time for the motor detected by the operating time measuring unit with an continuous-operating-capable setting time for the motor and determining whether or not the operating time for the motor has exceeded the continuous-operating-capable setting time; a protection device for halting energization of the motor in the case where, based on an output of the first determination unit, it is determined that the operating time for the motor has exceeded the continuous-operating-capable setting time. | 2009-10-29 |
20090267715 | ELECTROMAGNETIC RELAY - An electromagnetic relay capable of smoothly rotating a movable iron member by eliminating the effect of foreign matters produced on the contact surface of the movable iron piece on a core even if the drive voltage of an electromagnetic block is small. The attracting surface ( | 2009-10-29 |
20090267716 | SUPERCONDUCTING MAGNET - A persistent current switch in a superconducting magnet, includes: a winding part in which a superconducting wire is noninductively wound; a winding-heating heater provided around the winding part; a vessel provided around the winding part with a space; and an anti-convective material provided in the space between the vessel and the winding part. | 2009-10-29 |
20090267717 | Magnetic Mat for Holding Surgical Instruments - A magnetic mat for holding surgical instruments. The mat includes a plurality of magnet holders configured to removably receive magnets therein. The magnet holders are connected together using a plurality of links so as to form a two dimensional mat adjustable in size. As a result, the effective magnetic surface area of the mat may be extended to provide adequate coverage for larger patients and thereby prevent instruments from falling off the patients' surface. In embodiments, the magnet holders may be opened such that different magnets may be inserted, removed, replaced and/or exchanged. Additionally, the magnet holders, links, and/or magnets may be independently sterilized, and/or replaced. In embodiments, the magnet holders include an open cage structure to hold a magnet with minimal obstruction of its magnetic field. | 2009-10-29 |
20090267718 | Magnetic-field cancellation type transformer - A magnetic-filed cancellation type transformer includes a primary winding wire and a secondary winding wire which generate magnetic flux when energized, and a core constituted by a magnetic leg portion about which the primary winding wire and the secondary winding wire are wound, and a base for fixing the magnetic leg portion. The primary winding wire and the secondary winding wire are alternately piled and wound on the magnetic leg portion, so that the direction of magnetic flux generated from the primary winding wire and the secondary winding wire are opposite to each other in any couple selected from among the pieces of magnetic flux, and the magnetic flux is cancelled out with each other. | 2009-10-29 |
20090267719 | SPLITTER - The present invention provides a splitter including a seat, a first inner core, a second inner core, a first coil, an outer core and a second coil. The seat has a bobbin, and the first coil is wound on the bobbin. The first inner core and the second inner core, disposed on the bobbin, are assembled with each other to cover the bobbin. The outer core and the first inner core are assembled with each other. The second coil is disposed between the outer core and the first inner core. | 2009-10-29 |
20090267720 | METHODS AND APPARATUS FOR ELECTROMAGNETIC COMPONENT - The invention comprises a power filtering method and apparatus. | 2009-10-29 |
20090267721 | COIL UNIT AND ELECTRONIC APPARATUS USING THE SAME - A coil unit includes a coil and a magnetic substance for receiving magnetic force lines generated by the coil, the magnetic substance including a first magnetic substance having a first magnetic permeability and a second magnetic substance having a second magnetic permeability. | 2009-10-29 |
20090267722 | GROUNDING OF MAGNETIC CORES - An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The magnetic core includes a first magnetic layer and a second magnetic layer. In addition, the apparatus may include a conductive pattern. The conductive pattern may be at a third layer between the first and second magnetic layers. The apparatus may be included in inductors, transformers, transmission lines, and other components using ferromagnetic cores or shields. Such components may be integrated on a chip or die. | 2009-10-29 |
20090267723 | Electrical fuse devices - An electrical fuse device includes a cathode and an anode formed apart from each other and a fuse link connecting the cathode and the anode. The cathode includes a first region and a second region. The second region is arranged between the first region and the fuse link. A width of the second region may be greater than a width of the first region. | 2009-10-29 |
20090267724 | Temperature control switch - The present invention is to provide a temperature control switch, comprising a switch casing, which contains a springy slice, where the springy slice is provided with a thermostatic bimetal strip on its bouncing end. The thermostatic bimetal strip is provided with an electric heating device, where the first end and second end of the device are respectively connected in series between a first control terminal and the thermostatic bimetal strip. The elevated end of the thermostatic bimetal strip links one end of an uplifted metal slice to form an incompletely fixed link point, while the other end of the uplifted metal slice features a swaying contact, which corresponds to the contact point that a second control terminal joins. The uplifted metal slice joins a springy element at its middle portion, where the springy element is fixed in the switch casing. Being subject to the heat, the one end of the thermostatic bimetal strip deforms, which drives the link point to pass the line formed by the two ends of the springy element, where both ends of the uplifted metal slice are coincidently uplifted momentarily, enabling the swaying contact apart from the contact point. The prompt disconnection of the electricity can then be achieved, which surely avoids the contact point being burnt by the grave heat. | 2009-10-29 |
20090267725 | SURFACE MOUNT VARIABLE RESISTOR - A surface mount variable resistor meets the needs of user for front and rear terminals of an insulating substrate. The surface mount variable resistor includes an insulating substrate | 2009-10-29 |
20090267726 | METAL FOIL RESISTOR - The metal foil resistor having a metal foil resistive element | 2009-10-29 |
20090267727 | Thin film resistor element and manufacturing method of the same - In order to provide a thin-film resistor and a manufacturing method thereof capable of restraining reduction of a Q-value of varactor by reducing a parasitic capacitance between the resistor and the substrate, the thin-film resistor includes a semiconductor substrate | 2009-10-29 |
20090267728 | METHOD OF VISITING A SITE - A method and system for providing an interactive experience to a visitor of an entertainment venue comprising a plurality of locations. The visitor is assigned a portable identification device having stored thereon information uniquely identifying the visitor. A central computer then randomly directs the visitor to a first one of the locations and retrieves at the first location the information from the identification device in order to identify the visitor. In this manner, the visitor can be presented with content customized according to his/her unique profile. | 2009-10-29 |
20090267729 | Anti-counterfeiting system - A method and apparatus for verifying the authenticity of, and detecting tampering with, an item is disclosed. An RFID transponder comprises an antenna resonant circuit which is coupled to an associated integrated circuit when the integrated circuit is positioned proximately to the antenna resonant circuit, thereby enabling the integrated circuit to receive and respond to a radiofrequency query signal. The antenna resonant circuit can be integrated with a capsule or other form of removable packaging, such that it is destroyed upon removal of, or tampering with, the packaging. | 2009-10-29 |