43rd week of 2013 patent applcation highlights part 47 |
Patent application number | Title | Published |
20130280804 | DIFFERENTIATION OF HUMAN PLURIPOTENT STEM CELLS TO MULTIPOTENT NEURAL CREST CELLS - The present invention relates to the differentiation of human pluripotent cells, including human pluripotent stems cells to produce a self-renewing multipotent neural crest cell population in a single step method without the requirement of isolation of intermediate cells and without appreciable contamination (in certain preferred instances, virtually none) with Pax6+ neural progenitor cells in the population of p75+ Hnk1+ Ap2+ multipotent neural crest-like cells. The multipotent neural crest cell population obtained can be clonally amplified and maintained for >25 passages (>100 days) while retaining the capacity to differentiate into peripheral neurons, smooth muscle cells and mesenchymal precursor cells. | 2013-10-24 |
20130280805 | Dendritic Cell Compositions and Methods - Methods are provided for the production of dendritic cells from monocytes that have been incubated at a temperature of 1° C.-34° C. for a period of approximately 6 to 96 hours from the time they are isolated from a subject. After the incubation period, the monocytes can then be induced to differentiate into dendritic cells. Mature dendritic cells made by the methods of the invention have increased levels of one or more of CD80, CD83, CD86, MHC class I molecules, or MHC class II molecules as compared to mature dendritic cells prepared from monocytes that have not been held at 1° C.-34° C. for at least 6 hours from the time they were isolated from a subject. Dendritic cells made by the methods of the invention are useful for the preparation of vaccines and for the stimulation of T cells. | 2013-10-24 |
20130280806 | MAMMALIAN GENES INVOLVED IN INFECTION - The present invention relates to cellular proteins that are involved in infection or are otherwise associated with the life cycle of one or more pathogens. | 2013-10-24 |
20130280807 | CELL CULTURE CHAMBER, METHOD FOR PRODUCING SAME, TISSUE MODEL USING CELL CULTURE CHAMBER, AND METHOD FOR PRODUCING SAME - A single cell-culture chamber is provided that includes a dried vitrigel membrane covering and secured to one open end surface of a tubular frame. Also provided is a double cell-culture chamber that includes two tubular frames of substantially the same planar cross-sectional shape adhesively secured to each other with a dried vitrigel membrane interposed between the opposing open end surfaces of the tubular frames so as to form a first chamber and a second chamber via the dried vitrigel membrane. | 2013-10-24 |
20130280808 | COMPOSITION FOR REPROGRAMMING SOMATIC CELLS TO GENERATE INDUCED PLURIPOTENT STEM CELLS, COMPRISING Oct4 IN COMBINATION WITH Bmi1 OR ITS UPSTREAM REGULATOR, AND METHOD FOR GENERATING INDUCED PLURIPOTENT STEM CELLS USING THE SAME - Disclosed is a composition for reprogramming somatic cells to generate embryonic stem cell-like cells, comprising: a) a Bmi1 (B cell-specific Moloney murine leukemia virus integration site 1) protein or a nucleic acid molecule coding for Bmi1; and b) an Oct4 protein or a nucleic acid molecule coding for Oct4. Also, a method is provided for reprogramming somatic cells to generate embryonic stem cell-like cells using the composition. In addition to reducing the number of the genetic factors conventionally needed, the composition and method allow the generation of pluripotent embryonic stem cell-like cells which have high potential in the cell therapy of various diseases. | 2013-10-24 |
20130280809 | REPROGRAMMING OF CELLS TO A NEW FATE - Methods and compositions for transdifferentiation of an animal cell from (i) a first pluripotent cell fate to a second nonpluripotent cell fate or (ii) from a non-pluripotent mesodermal, endodermal, or ectodermal cell fate to a different non-pluripotent mesodermal, endodermal, or ectodermal cell fate. | 2013-10-24 |
20130280810 | METHOD FOR THE SELECTION OF RECOMBINANT CLONES COMPRISING A SEQUENCE ENCODING AN ANTIDOTE PROTEIN TO TOXIC MOLECULE - The present invention is related to a method for the selection of recombinant clones having integrated a gene of interest and a nucleotide sequence encoding a functional antidote protein to a toxic molecule, wherein said recombinant clones are the ones which survive following their integration into a host cell comprising in its genome a nucleotide sequence encoding said toxic molecule. The present invention is also related to a nucleic acid construct, a vector comprising said nucleic acid construct, a host cell and a cloning and/or sequencing kit for performing said method. | 2013-10-24 |
20130280811 | PLASMIDS AND PHAGES FOR HOMOLOGOUS RECOMBINATION AND METHODS OF USE - Lambda phages that can be used to introduce recombineering functions into host cells are disclosed. Also disclosed are plasmids that can be used to confer recombineering functions to a variety of strains of | 2013-10-24 |
20130280812 | APPARATUS AND METHOD FOR THERMAL ASSISTED DESORPTION IONIZATION SYSTEMS - The present invention is directed to a method and device to desorb an analyte using heat to allow desorption of the analyte molecules, where the desorbed analyte molecules are ionized with ambient temperature ionizing species. In various embodiments of the invention a current is passed through a mesh upon which the analyte molecules are present. The current heats the mesh and results in desorption of the analyte molecules which then interact with gas phase metastable neutral molecules or atoms to form analyte ions characteristic of the analyte molecules. | 2013-10-24 |
20130280813 | METHODS AND APPARATUS FOR DETECTING MOLECULAR INTERACTIONS USING FET ARRAYS - Methods and apparatuses relating to large scale FET arrays for analyte detection and measurement are provided. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. | 2013-10-24 |
20130280814 | METHOD AND KIT FOR PROTEIN LABELING - The present invention relates to a method for labeling proteins in a sample prior to separation thereof using a protein reactive dye, comprising the following steps a) dissolving the proteins in, or diluting the proteins with, or exchanging an existing protein buffer with, a labeling buffer comprising a dye-reactant (reacting with the protein reactive dye) to form a mixture, b) adding protein reactive dye to said mixture, c) incubating said mixture wherein the labeling of said proteins with said dye can be completed within 5 minutes, and wherein both the proteins and the dye-reactant form measurable reaction products with said dye, and d) separating said reaction products. The invention also relates to a kit for pre-labeling of proteins, comprising a labeling buffer, a dye, a molecular weight marker, and a sample gel loading buffer. | 2013-10-24 |
20130280815 | DUAL WAVELENGTH ISOELECTRIC FOCUSING FOR DETERMINING DRUG LOAD IN ANTIBODY DRUG CONJUGATES - Provided herein are IEF focusing methods for determining the number of drug molecules present in at least one antibody-drug conjugate (ADC) species subpopulation. In one embodiment, the method comprises performing free solution isoelectric focusing on a sample comprising at least one ADC species, to obtain a focused sample. The absorbance of the sample at two different wavelengths is then measured, for example, over a range of pI values. Absorbance values at the two different wavelengths are compared at at least one corresponding pI value, where the at least one corresponding pI value is the pI of the ADC subpopulation. The number of drug molecules in the at least one ADC species subpopulation is then determined based on the comparison. The methods provided herein can also be used to determine the number of specific binding pair members bound to its target specific binding pair member. | 2013-10-24 |
20130280816 | ApoIII and the Treatment and Diagnosis of Diabetes - The present invention provides methods of identifying candidate compounds for the treatment of type I diabetes comprising contacting pancreatic β cells with an amount of apolipoprotein CIII (“apoCIII”) effective to increase intracellular calcium concentration, in the presence of one or more test compounds, and identifying those test compounds that inhibit an apoCIII-induced increase in intracellular calcium concentration in the pancreatic β cells. The present invention also provides methods for treating patients with type I diabetes comprising administering to the patient an amount effective of an inhibitor of apoCIII to reduce apoCIII-induced increase in intracellular calcium concentration in pancreatic β cells. | 2013-10-24 |
20130280817 | MULTIFUNCTIONAL DETECTOR FOR GASEOUS COMPOUNDS, AND USES THEREOF - The invention relates to a multifunctional detector for gaseous compounds, or mixtures of gaseous compounds, selected from NH | 2013-10-24 |
20130280818 | LIGHT ABSORBANCE MEASUREMENT METHOD AND APPARATUS - Methods and apparatuses for measuring a light absorbance are provided. The method measures light absorbance of at least one detection chamber of a microfluidic device, including the detection chamber and at least one reference chamber. The detection chamber may accommodate a test subject. The method includes detecting a plurality of reference transmitted light intensities for the at least one reference chamber and estimating a value between the plurality of reference transmitted light intensities through nonlinear approximation. The estimated value is then applied to light absorbance measurement of the detection chamber to reduce a light absorbance error of the detection chamber. | 2013-10-24 |
20130280819 | SYNCHRONIZATION OF ION GENERATION WITH CYCLING OF A DISCONTINUOUS ATMOSPHERIC INTERFACE - The invention generally relates to methods and devices for synchronization of ion generation with cycling of a discontinuous atmospheric interface. In certain embodiments, the invention provides a system for analyzing a sample that includes a mass spectrometry probe that generates sample ions, a discontinuous atmospheric interface, and a mass analyzer, in which the system is configured such that ion formation is synchronized with cycling of the discontinuous atmospheric interface. | 2013-10-24 |
20130280820 | BIOMARKERS FOR PSORIASIS - A group of polypeptides that are modulated in a psoriatic sample as compared to a normal sample is provided. These polypeptides can be used as biomarkers for diagnosis and monitoring treatment of psoriasis. | 2013-10-24 |
20130280821 | METHOD FOR DETECTING AN INFECTION BY HEPATITIS B VIRUS - An immunological confirmation method is disclosed for the detection of hepatitis B virus infection wherein the testing of certain samples showing unclear reactivity is repeated once without and once in the presence of recombinantly produced HBcAg particles. If the sample is truly hepatitis B virus core antibody positive, the rHBcAg will trap the anti-HBcAg antibodies and influence the readout accordingly. | 2013-10-24 |
20130280822 | METHOD FOR REPAIRING DRIVER CIRCUIT STRUCTURE - Disclosed is a driver circuit structure integrated in a display panel. The driver circuit structure includes a plurality of transistors and a backup transistor. After completing the driver circuit structure, the disclosure inspects it to find an inactive transistor. The inspection process first, isolates the electrical connection between the inactive transistor and the first electrode line and/or the electrical connection between the inactive transistor and the second electrode line. Next, the source electrode of the backup transistor and the first electrode line and/or electrically connecting the drain electrode of the backup transistor and the second electrode line are electrical connected. | 2013-10-24 |
20130280823 | Apparatus for Monitoring Ion Implantation - An apparatus for monitoring an ion distribution of a wafer comprises a first sensor and a sensor. The first sensor, the second senor and the wafer are placed in an effective range of a uniform ion implantation current profile. A controller determines the ion dose of each region of the wafer based upon the detected signal from the first sensor and the second senor. In addition, the controller adjusts the scanning frequency of an ion beam or the movement speed of the wafer to achieve a uniform ion distribution on the wafer. | 2013-10-24 |
20130280824 | APPARATUS AND METHOD FOR MEASURING RADIATION ENERGY DURING THERMAL PROCESSING - Embodiments of the present invention provide apparatus and method for reducing heating source radiation influence in temperature measurement during thermal processing. In one embodiment of the present invention, background radiant energy, such as an energy source of a thermal processing chamber, is marked within a selected spectrum, a characteristic of the background is then determined by measuring radiant energy at a reference wavelength within the selected spectrum and a comparing wavelength just outside the selected spectrum. | 2013-10-24 |
20130280825 | PEELING SYSTEM, PEELING METHOD, AND COMPUTER STORAGE MEDIUM - A peeling system includes: a carry-in/carry-out station that loads/unloads substrates to be processed, support substrates, or stacked substrates in which these are made to adhere; a peeling process station that carries out prescribed processing on substrates to be processed, support substrates and stacked substrates; and a transport station provided between the carry-in/carry-out station and the peeling process station. The peeling process station has a peeling device that peels the stacked substrates, a first washing apparatus that washes peeled substrates to be processed, and a second washing apparatus that washes the peeled support substrates. The pressure inside the transport station is a positive pressure in relation to the pressure inside the peeling device, the pressure inside the first washing apparatus, and the pressure inside the second washing apparatus. The pressure inside a transport apparatus is a positive pressure in relation to the pressure inside the peeling device and the pressure inside the first washing apparatus. | 2013-10-24 |
20130280826 | ADAPTIVE PATTERNING FOR PANELIZED PACKAGING - An adaptive patterning method and system for fabricating panel based package structures is described. A plurality of semiconductor die comprising a copper column disposed over the active surface of each semiconductor die is provided. An embedded die panel is formed by disposing an encapsulant around each of the plurality of semiconductor die. A true position and rotation of each semiconductor die within the embedded die panel is measured. A unit-specific pattern is formed to align with the true position of each semiconductor die in the embedded die panel. The unit-specific pattern as a fan-out structure disposed over the semiconductor die, over the encapsulant, and coupled to the copper columns. A fan-in redistribution layer (RDL) can extend over the active surface of each semiconductor die such that the copper columns formed over the fan-in RDLs. The unit-specific pattern can be directly coupled to the copper columns. | 2013-10-24 |
20130280827 | METHOD OF CONTROLLING POLISHING USING IN-SITU OPTICAL MONITORING AND FOURIER TRANSFORM - A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values. | 2013-10-24 |
20130280828 | MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA - PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits. | 2013-10-24 |
20130280829 | GRAPHENE DEPOSITION AND GRAPHENATED SUBSTRATES - Methods, devices, systems and/or articles related to techniques for forming a graphene film on a substrate, and the resulting graphene layers and graphenated substrates are generally disclosed. Some example techniques may be embodied as methods or processes for forming graphene. Some other example techniques may be embodied as devices employed to manipulate, treat, or otherwise process substrates, graphite, graphene and/or graphenated substrates as described herein. Graphene layers and graphenated substrates produced by the various techniques and devices provided herein are also disclosed. | 2013-10-24 |
20130280830 | CARBON NANOTUBE FIELD EMISSION DEVICE WITH OVERHANGING GATE - A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed. | 2013-10-24 |
20130280831 | PERMANENTLY BONDED FLUID CHANNEL NOZZLE PLATE FABRICATION - Fabricating a printhead includes providing a silicon wafer including first and second surfaces and a nozzle membrane layer on the first surface of the silicon wafer. The silicon wafer is sized to a thickness ranging from 10 to 250 microns. A plurality of chambers is defined on the second surface of the silicon wafer by depositing and patterning a mask on the second surface of the silicon wafer. The plurality of chambers is formed in the silicon wafer by etching portions of the silicon wafer that are exposed by the mask. A second wafer, permanently bonded to the second surface of the silicon wafer, includes a material property that is compatible with a material property of the silicon wafer. A preformed fluid channel of the second wafer is in fluid communication with the plurality of chambers of the silicon wafer after permanent bonding of the wafers. | 2013-10-24 |
20130280832 | FABRCATION METHOD OF LIGHT-EMITTING DEVICE - A fabrication method of a light-emitting device comprises providing a growth substrate; forming a protective layer on a first surface of the growth substrate; and forming a first semiconductor layer on a second surface of the growth substrate opposite to the first surface, wherein the coefficient of thermal expansion of the growth substrate is smaller than that of the protective layer and the first semiconductor layer. | 2013-10-24 |
20130280833 | Reactor for Atomic Layer Deposition (ALD), Application to Encapsulation of an OLED Device by Deposition of a Transparent Al2O3 Film - The present invention relates to a reactor for atomic layer deposition (ALD), comprising a reaction chamber comprising a platen and bounded internally by surfaces; at least one inlet orifice and at least one outlet orifice, each emerging from one of the surfaces bounding the chamber. The reactor furthermore comprises, within it, at least one wall apertured with at least one orifice, the apertured wall extending around the platen and over at least most of the height between the lower surface and the upper surface, at least one orifice in at least one of the apertured walls not facing the inlet orifice so as to form chicanes in the flow of gaseous precursor from each inlet orifice to the platen. | 2013-10-24 |
20130280834 | METHOD FOR MANUFACTURING LED - A method for manufacturing an LED package includes following steps: providing a base with an LED chip mounted on the base; providing a porous carrier with a plurality of holes, and disposing the base on the porous carrier; providing a film with a phosphor layer attached on the film; providing a mold, and putting the porous carrier, the base, the LED chip, and the film into the mold; extracting air from the mold to an external environment through the holes of the porous carrier, and/or, blowing air toward the film to urge the film to move toward the LED chip, resulting in that the film is conformably attached onto the LED chip and the base; and solidifying the phosphor layer on the LED chip by means of heating whereby the phosphor is conformably and securely attached on the LED chip. | 2013-10-24 |
20130280835 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE CHIP - A method for manufacturing a light emitting diode includes providing an epitaxial wafer having a substrate and an epitaxial layer allocated on the substrate. The epitaxial layer comprises a first semiconductor layer, an active layer, a second semiconductor layer sequentially allocated, and at least one blind hole penetrating the second semiconductor layer, the active layer and inside the first semiconductor layer; then a first electrode is formed on the first semiconductor layer inside the at least one blind hole and a second electrode is formed on the second semiconductor layer; thereafter a first supporting layer is allocated on the first electrode and a second supporting layer is allocated on the second electrode. | 2013-10-24 |
20130280836 | METHOD AND SYSTEM FOR PRODUCING HIGH RESOLUTION PATTERNS IN REGISTRATION ON THE SURFACE OF A SUBSTRATE - A method of selectively applying a material to a surface of a substrate from a stamp with a raised surface using an energy activated release layer is provided. The release layer is applied to at least a first portion of a surface of the stamp. A layer of the material is applied to the raised surface of the stamp. The raised surface of the stamp is placed in contact with the surface of the substrate such that the material layer is situated therebetween. Thereafter, the release layer is activated with energy, causing the material layer to release from the raised surface of the stamp, and to adhere to the surface of the substrate. Alternatively, the entire stamp surface may be coated with the release layer and the release layer may be selectively activated in the areas in which the material on the stamp surface is in contact with the substrate. | 2013-10-24 |
20130280837 | METHOD FOR FABRICATING GROUP-III NITRIDE SEMICONDUCTOR LASER DEVICE - A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade | 2013-10-24 |
20130280838 | METHOD FOR FABRICATING ARRAY SUBSTRATE AND FABRICATION APPARATUS USED THEREFOR - Provided is a method for fabricating an array substrate. The method for fabricating the array substrate includes forming a semiconductor layer on a substrate, forming a gate electrode which is insulated from the semiconductor layer, forming source and drain electrodes which are insulated from the gate electrode and connected to the semiconductor layer, and forming a pixel electrode connected to the drain electrode. Here, at least one of the forming of the gate electrode, the forming of the source and drain electrodes, and the forming of the pixel electrode includes forming a conductive layer on the substrate, cooling the substrate on which the conductive layer is formed to a temperature of no greater than about 0° C., heating the cooled substrate, and patterning the conductive layer. | 2013-10-24 |
20130280839 | METHOD FOR FORMING VAPOR DEPOSITION FILM, AND METHOD FOR PRODUCING DISPLAY DEVICE - On a surface of a substrate ( | 2013-10-24 |
20130280840 | VAPOR DEPOSITION DEVICE, VAPOR DEPOSITION METHOD, AND METHOD OF MANUFACTURING ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE - A vapor deposition device ( | 2013-10-24 |
20130280841 | LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A high-quality light emitting device is provided which has a long-lasting light emitting element free from the problems of conventional ones because of a structure that allows less degradation, and a method of manufacturing the light emitting device is provided. After a bank is formed, an exposed anode surface is wiped using a PVA (polyvinyl alcohol)-based porous substance or the like to level the surface and remove dusts from the surface. An insulating film is formed between an interlayer insulating film on a TFT and the anode. Alternatively, plasma treatment is performed on the surface of the interlayer insulating film on the TFT for surface modification. | 2013-10-24 |
20130280842 | MICROELECTROMECHANICAL DEVICE INCLUDING AN ENCAPSULATION LAYER OF WHICH A PORTION IS REMOVED TO EXPOSE A SUBSTANTIALLY PLANAR SURFACE HAVING A PORTION THAT IS DISPOSED OUTSIDE AND ABOVE A CHAMBER AND INCLUDING A FIELD REGION ON WHICH INTEGRATED CIRCUITS ARE FORMED, AND METHODS FOR FABRICATING SAME - There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide. | 2013-10-24 |
20130280843 | Method for a single precursor ionic exchange to prepare semiconductor nanocrystal n-type thermoelectric material - Herein disclosed is a method of forming a thermoelectric material having an optimized stoichiometry, the method comprising: reacting a precursor material including a population of nanocrystals with a first ionic solution and a second ionic solution to form a reacted mixture. | 2013-10-24 |
20130280844 | COATING APPARATUS AND COATING METHOD - A coating apparatus including a coating part which has a nozzle which ejects a liquid material including an oxidizable metal from a tip portion, and a relative driving unit which moves a substrate and the nozzle in relation to each other so that the tip portion passes through the substrate, such that at least the tip portion of the nozzle provides an affinity control part which is formed so that affinity between the affinity control part and the liquid material is less than that between the liquid materials. | 2013-10-24 |
20130280845 | PHOTOVOLTAIC CELL CONTAINING A POLYMER ELECTROLYTE - A photovoltaic cell comprises a membrane electrode assembly obtainable by the in situ polymerisation between two electrodes of one or more monomers to form a polymer, and then infusing an activating agent into the polymer, wherein the activating agent enables the membrane electrode assembly to function as a photovoltaic cell. | 2013-10-24 |
20130280846 | IMAGE SENSOR AND METHOD FOR FABRICATING THE SAME - An image sensor includes a trench formed by a shallow trench isolation (STI) process, a channel stop layer formed over a substrate in the trench, an isolation structure filled in the trench, and a photodiode formed in the substrate adjacent to a sidewall of the trench. In more detail of the image sensor, a trench is formed in a substrate through a STI process, and a channel stop layer is formed over the substrate in the trench. An isolation structure is formed in the trench, and a photodiode is formed in the substrate adjacent to a sidewall of the trench. | 2013-10-24 |
20130280847 | TRANSPARENT CONTACTS ORGANIC SOLAR PANEL BY SPRAY - A method of fabricating organic solar panels with transparent contacts. The method uses a layer-by-layer spray technique to create the anode layer. The method includes placing the substrate on a flat magnet, aligning a magnetic shadow mask over the substrate, applying photoresist to the substrate using spray photolithography, etching the substrate, cleaning the substrate, spin coating a tuning layer on substrate, spin coating an active layer of P3HT/PCBM on the substrate, spray coating the substrate with a modified PEDOT solution, and annealing the substrate. | 2013-10-24 |
20130280848 | SOLID-STATE IMAGING DEVICE AND ELECTRONIC EQUIPMENT - A solid-state imaging device including a substrate; a wiring layer formed on a front side of the substrate in which pixels are formed; a surface electrode pad section formed in the wiring layer; a light-shielding film formed on a rear side of the substrate; a pad section base layer formed in the same layer as the light-shielding film; an on-chip lens layer formed over the light-shielding film and the pad section base layer in a side opposite from the substrate side; a back electrode pad section formed above the on-chip lens layer; a through-hole formed to penetrate the on-chip lens layer, the pad section base layer, and the substrate so as to expose the surface electrode pad section; and a through-electrode layer which is formed in the through-hole and connects the surface electrode pad section and the back electrode pad section. | 2013-10-24 |
20130280849 | Image Sensor Isolation Region and Method of Forming the Same - Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material. | 2013-10-24 |
20130280850 | Methods of Fabricating CMOS Image Sensors - An image sensor device includes a substrate including a light sensing region therein and a reflective structure on a first surface of the substrate over the light sensing region. An interconnection structure having a lower reflectivity than the reflective structure is provided on the first surface of the substrate adjacent to the reflective structure. A microlens is provided on a second surface of the substrate opposite the first surface. The microlens is configured to direct incident light to the light sensing region, and the reflective structure is configured to reflect portions of the incident light that pass through the light sensing region back toward the light sensing region. Related devices and fabrication methods are also discussed. | 2013-10-24 |
20130280851 | SEMICONDUCTOR DEVICES AND METHODS FOR FORMING PATTERNED RADIATION BLOCKING ON A SEMICONDUCTOR DEVICE - Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer. | 2013-10-24 |
20130280852 | DEVICE FOR JETTING GAS AND SOLAR CELL MANUFACTURING METHOD USING THE SAME - A device for disposing a gas, the device including: a chamber; a plurality of gas jetting plates disposed in the chamber, each gas jetting plate of the plurality of gas jetting plates including a plurality of gas jetting holes disposed on a surface thereof; and a gas pipe fluidly connected to the gas jetting plate and extending outside the chamber, wherein each gas jetting plate includes a first stage, which is fluidly connected to the gas pipe, and a final stage, which includes the plurality of gas jetting holes. | 2013-10-24 |
20130280853 | Combinatorial Methods for Making CIGS Solar Cells - The present disclosure is directed to methods of forming different types of Cu | 2013-10-24 |
20130280854 | SINTERED DEVICE - A method for the production of an inorganic film on a substrate, the method comprising: (a) depositing a layer of nanoparticles on the substrate by contacting the substrate with a nanoparticle dispersion; (b) treating the deposited layer of nanoparticles to prevent removal of the nanoparticles in subsequent layer depositing steps; (c) depositing a further layer of nanoparticles onto the preceding nanoparticle layer on the substrate; (d) repeating treatment step (b) and deposition step (c) at least one further time; and (e) optionally thermally annealing the multilayer film produced following steps (a) to (d); wherein the method comprises at least one thermal annealing step in which the layer or layers of nanoparticles are thermally annealed. | 2013-10-24 |
20130280855 | METHOD FOR PRODUCING COMPOUND HAVING CHALCOPYRITE STRUCTURE - To obtain high-quality chalcopyrite particles having a small particle size using a relatively inexpensive raw material in a simple and easy process in which complicated equipment (such as vacuum equipment) is not necessary. Provided is a method for producing a compound having a chalcopyrite structure represented by a compositional formula: ABC | 2013-10-24 |
20130280856 | PHOTO SENSOR, METHOD OF MANUFACTURING PHOTO SENSOR, AND DISPLAY APPARATUS - A photo sensor, a method of manufacturing the photo sensor, and a display apparatus, the photo sensor including a substrate; a light receiving unit on the substrate, the light receiving unit including an amorphous semiconductor material; a first adjacent unit and a second adjacent unit formed as one body with the light receiving unit, the first adjacent unit and the second adjacent unit being separated from each other by the light receiving unit; a first photo sensor electrode electrically connected to the first adjacent unit; and a second photo sensor electrode electrically connected to the second adjacent unit, wherein at least one of the first adjacent unit and the second adjacent unit includes a crystalline semiconductor material. | 2013-10-24 |
20130280857 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - It is an object to provide a manufacturing method of a structure of a thin film transistor including an oxide semiconductor film, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible. A protective insulating layer is formed to cover a thin film transistor including an oxide semiconductor layer that is dehydrated or dehydrogenated by first heat treatment, and second heat treatment at a temperature that is lower than that of the first heat treatment, in which the increase and decrease in temperature are repeated plural times, is performed, whereby a thin film transistor including an oxide semiconductor layer, in which threshold voltage at which a channel is formed is positive and as close to 0 V as possible without depending on the channel length, can be manufactured. | 2013-10-24 |
20130280858 | SEMICONDUCTOR DEVICE - A semiconductor device includes an oxide semiconductor layer provided over a substrate having an insulating surface; a gate insulating film covering the oxide semiconductor layer; a first conductive layer and a second conductive layer laminated in this order over the gate insulating film; an insulating film covering the oxide semiconductor layer and a gate wiring including a gate electrode (the first and second conductive layers); and a third conductive layer and a fourth conductive layer laminated in this order over the insulating film and electrically connected to the oxide semiconductor layer. The gate electrode is formed using the first conductive layer. The gate wiring is formed using the first conductive layer and the second conductive layer. A source electrode is formed using the third conductive layer. A source wiring is formed using the third conductive layer and the fourth conductive layer. | 2013-10-24 |
20130280859 | THIN-FILM TRANSISTOR AND METHOD FOR MANUFACTURING SAME - Provided are a thin film transistor and a method of manufacturing the same. The thin film transistor includes: a gate electrode; source and drain electrodes spaced apart in a up and down direction from the gate electrode and in a horizontal direction from each other; a gate dielectric formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode; and an active layer formed between the gate dielectric and the source electrode and between the gate dielectric and the drain electrode, wherein the active layer is formed of at least two zinc oxide thin layers doped with an element. | 2013-10-24 |
20130280860 | METHOD FOR SYNTHESIZING A MATERIAL, IN PARTICULAR DIAMONDS, BY CHEMICAL VAPOR DEPOSITION, AS WELL AS DEVICE FOR APPLYING THE METHOD - Method for synthesising a material by chemical vapour deposition (CVD), according to which a plasma is created in a vacuum chamber in the vicinity of a substrate, and according to which a carbon-carrying substance and H | 2013-10-24 |
20130280861 | METHODS FOR FORMING SEMICONDUCTOR DEVICE PACKAGES - Methods for forming semiconductor device packages include applying an underfill material over a semiconductor wafer including conductive elements such that an average thickness of the underfill material is at least about 80% of an average height of the conductive elements and each conductive element is covered by underfill material. Underfill material covering tips of conductive elements is removed. Other methods include positioning a stencil over a semiconductor wafer and applying an underfill material to a major surface of the semiconductor wafer through the stencil. Additional methods include aligning and associating conductive elements having a surface substantially free of underfill material with bond pads of a substrate, melting and flowing the underfill material, and heating the conductive elements and underfill material to melt tip portions of the conductive elements and cure the underfill material. | 2013-10-24 |
20130280862 | SEMICONDUCTOR STORAGE DEVICE AND MANUFACTURING METHOD THEREOF - According to one embodiment, a semiconductor storage device includes an organic board provided with external connection terminals on one surface and formed as an individual piece into a plane shape substantially identical to that of an area where the external connection terminals are provided, a lead frame having a mounting area positioned relative to the organic board, and a semiconductor memory chip bonded to the mounting area. | 2013-10-24 |
20130280863 | VERTICALLY STACKABLE DIES HAVING CHIP IDENTIFIER STRUCTURES - A particular method of making a stacked multi-die semiconductor device includes forming a stack of at least two dies. Each die includes a chip identifier structure that includes a first set of at least two through vias that are each hard wired to a set of external electrical contacts. Each die further includes chip identifier selection logic coupled to the chip identifier structure. Each die further includes a chip select structure that includes a second set of at least two through vias coupled to the chip identifier selection logic. The method further includes coupling each external electrical contact to a voltage source or ground. Each of the first set of through vias has a pad that is coupled to an adjacent through via and each of the second set of through vias is coupled to its own respective pad. | 2013-10-24 |
20130280864 | STACKED INTERCONNECT HEAT SINK - A heat spreader that is configured to be attached to an integrated circuit substrate. The heat spreader includes a thermally conductive core and a heat spreader via that passes through the thermally conductive core. A connection point of the thermally conductive core is configured to form a solder connection to an integrated circuit substrate plug. | 2013-10-24 |
20130280865 | QFN Package and Manufacturing Process Thereof - The present invention provides a Quad Flat Non-leaded (QPN) package, which comprises a chip, a lead frame, a plurality of composite bumps and an encapsulant. The chip has a plurality of pads, and the lead frame has a plurality of leads. Each of the plurality of composite bumps has a first conductive layer and a second conductive layer. The first conductive layer is electrically connected between one of the pads and the second conductive layer, and the second conductive layer is electrically connected between the first conductive layer and one of the leads. The encapsulant encapsulates the chip, the leads and the composite bumps. Thereby, a QFN package with composite bumps and a semi-cured encapsulant is forming between the spaces of leads of lead frame before chip bonded to the lead frame are provided. | 2013-10-24 |
20130280866 | LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE - A package includes a first plated area, a second plated area, a die attached to the first plated area, and a bond coupling the die to the second plated area. The package further includes a molding encapsulating the die, the bond, and the top surfaces of the first and second plated areas, such that the bottom surfaces of the first and second plated areas are exposed exterior to the package. Additional embodiments include a method of making the package. | 2013-10-24 |
20130280867 | METHODS FOR MANUFACTURING THIN FILM TRANSISTOR AND DISPLAY DEVICE - The present invention provides a method for manufacturing a highly reliable semiconductor device with a small amount of leakage current. In a method for manufacturing a thin film transistor, etching is conducted using a resist mask to form a back channel portion in the thin film transistor, the resist mask is removed, a part of the back channel is etched to remove etching residue and the like left over the back channel portion, whereby leakage current caused by the residue and the like can be reduced. The etching step of the back channel portion can be conducted by dry etching using non-bias. | 2013-10-24 |
20130280868 | FABRICATING METHOD OF THIN FILM TRANSISTOR - A thin film transistor including a substrate, a semiconductor layer, a patterned doped semiconductor layer, a source and a drain, a gate insulation layer, and a gate is provided. The semiconductor layer is disposed on the substrate. The patterned doped semiconductor layer is disposed on opposite sides of the semiconductor layer. The source and the drain are disposed on the patterned doped semiconductor layer and the opposite sides of the semiconductor layer, wherein a part of the semiconductor layer covered by the source and the drain has a first thickness, a part of the semiconductor layer disposed between the source and the drain and not covered by the source and the drain has a second thickness ranging from 200 Å to 800 Å. The gate insulation layer is disposed on the source, the drain and the semiconductor layer. The gate is disposed on the gate insulation layer. | 2013-10-24 |
20130280869 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a substrate, a carrier transit layer disposed above the substrate, a compound semiconductor layer disposed on the carrier transit layer, a source electrode disposed on the compound semiconductor layer, a first groove disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate, a drain electrode disposed in the inside of the first groove, a gate electrode located between the source electrode and the first groove and disposed on the compound semiconductor layer, and a second groove located diagonally under the source electrode and between the source electrode and the first groove and disposed from the back of the substrate up to the inside of the carrier transit layer while penetrating the substrate. | 2013-10-24 |
20130280870 | FABRICATION OF MOS DEVICE WITH INTEGRATED SCHOTTKY DIODE IN ACTIVE REGION CONTACT TRENCH - Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer, having a body top surface and a body bottom surface; forming a source; forming an active region contact trench that extends through the source and the body into the drain, wherein bottom surface of the active region contact trench is formed to include at least a portion that is shallower than the body bottom surface; and disposing a contact electrode within the active region contact trench. | 2013-10-24 |
20130280871 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device includes performing pre-halo ion implantation on a semiconductor substrate, forming a first epitaxial layer over the entire upper surface of the semiconductor substrate, forming a second epitaxial layer over the entire surface of the first epitaxial layer, and forming a transistor at an active region of the second epitaxial layer. The first epitaxial layer prevents the ions implanted in the semiconductor substrate in the pre-halo implantation process from diffused into the second epitaxial layer under the effects of a process used to form the transistor. | 2013-10-24 |
20130280872 | SEMICONDUCTOR DEVICE INCLUDING WORK FUNCTION ADJUSTING ELEMENT, AND METHOD OF MANUFACTURING THE SAME - A semiconductor device has a substrate; and an N-channel MIS transistor and a P-channel MIS transistor provided on the same substrate; each of the N-channel MIS transistor and the P-channel MIS transistor having a Hf-containing, high-k gate insulating film, and a gate electrode provided over the high-k gate insulating film, the N-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains a first work function adjusting element, provided between the substrate and the high-k gate insulating film, and, the P-channel MIS transistor having a silicon oxide film or a silicon oxynitride film, which contains the first work function adjusting element same as that contained in the N-channel MIS transistor, provided between the high-k gate insulating film and the gate electrode. | 2013-10-24 |
20130280873 | ENHANCED DEVICE RELIABILITY OF A SEMICONDUCTOR DEVICE BY PROVIDING SUPERIOR PROCESS CONDITIONS IN HIGH-K FILM GROWTH - When forming sophisticated circuit elements, such as transistors, capacitors and the like, using a combination of a conventional dielectric material and a high-k dielectric material, superior performance and reliability may be achieved by forming a hafnium oxide-based high-k dielectric material on a conventional dielectric layer with a preceding surface treatment, for instance using APM at room temperature. In this manner, sophisticated transistors of superior performance and with improved uniformity of threshold voltage characteristics may be obtained, while also premature failure due to dielectric breakdown, hot carrier injection and the like may be reduced. | 2013-10-24 |
20130280874 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes the following steps. At first, two gate stack layers are formed on a semiconductor substrate, and a material layer covering the gate stack layers is formed on the semiconductor substrate. Subsequently, a part of the material layer is removed to form a sacrificial layer between the gate stack layers, and a spacer at the opposite lateral sides of the gate stack layers. Furthermore, a patterned mask covering the gate stack layers and the spacer and exposing the sacrificial layer is formed, and the sacrificial layer is removed. | 2013-10-24 |
20130280875 | METHOD OF MANUFACTURING STRAINED SOURCE/DRAIN STRUCTURES - A method includes forming a gate structure over a semiconductor substrate. The gate structure defines a channel region in the semiconductor substrate. Trenches are formed in the semiconductor substrate, and the trenches are interposed by the channel region. A first semiconductor layer is epitaxially grown in the trenches, and the first semiconductor layer has a first dopant with a first dopant concentration. A second semiconductor layer is epitaxially grown over the first semiconductor layer, and the second semiconductor layer has a second dopant with a second dopant concentration. The second dopant has an electrical carrier type opposite to an electrical carrier type of the first dopant. | 2013-10-24 |
20130280876 | Techniques for FinFET Doping - A method of forming an integrated circuit includes providing a semiconductor wafer including a semiconductor fin dispatched on a surface of the semiconductor wafer; forming a dopant-rich layer having an impurity on a top surface and sidewalls of the semiconductor fin, wherein the impurity is of n-type or p-type; performing a knock-on implantation to drive the impurity into the semiconductor fin; and removing the dopant-rich layer. | 2013-10-24 |
20130280877 | METHODS FOR FABRICATING HIGH VOLTAGE FIELD EFFECT TRANSITOR FINGER TERMINATIONS - Methods for fabricating a field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends are disclosed. The methods provide field effect transistors that each include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. At least one method includes etching at least one gate channel into the passivation layer with a predetermined slope that reduces electric fields at a gate edge. Other methods include steps for fabricating a sloped gate foot, a round end, and/or a chamfered end to further improve high voltage operation. | 2013-10-24 |
20130280878 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A gate structure is formed on a substrate. An oxide layer is formed and covers the gate structure and the substrate. A plasma process without oxygen is performed to densify the oxide layer. A material layer is formed and covers the oxide layer. The material layer and the oxide layer are etched to form a dual spacer. | 2013-10-24 |
20130280879 | Method for Producing a Conductor Line - A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed. | 2013-10-24 |
20130280880 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device with improved deposition characteristic and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate having a phase-change area, a first material-rich first phase-change layer forming an inner surface of the phase-change area and comprised of a hetero compound of the first material and a second material, and a second phase-change layer formed on a surface of the first phase-change layer to fill the phase-change area. | 2013-10-24 |
20130280881 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer. | 2013-10-24 |
20130280882 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. The method includes forming semiconductor patterns on a semiconductor substrate, such that sides are surrounded by a lower interlayer insulating layer. A lower insulating layer is formed that covers the semiconductor patterns and the lower interlayer insulating layer. A contact structure is formed that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns. The contact structure has an upper surface higher than the semiconductor patterns. An upper insulating layer is formed covering the contact structure and the lower insulating layer. The upper and lower insulating layers form insulating patterns exposing the semiconductor patterns and covering the contact structure, and each of the insulating patterns includes a lower insulating pattern and an upper insulating pattern sequentially stacked. After the insulating patterns are formed, metal-semiconductor compounds are formed on the exposed semiconductor patterns. | 2013-10-24 |
20130280883 | METHODS OF FORMING BULK FINFET DEVICES SO AS TO REDUCE PUNCH THROUGH LEAKAGE CURRENTS - Disclosed are methods of forming bulk FinFET semiconductor devices to reduce punch through leakage currents. One example includes forming a plurality of trenches in a semiconducting substrate to define a plurality of spaced-apart fins, forming a doped layer of insulating material in the trenches, wherein an exposed portion of each of the fins extends above an upper surface of the doped layer of insulating material while a covered portion of each of the fins is positioned below the upper surface of the doped layer of insulating material, and performing a process operation to heat at least the doped layer of insulating material to cause a dopant material in the doped layer to migrate from the doped layer of insulating material into the covered portions of the fins and thereby define a doped region in the covered portions of the fins that is positioned under the exposed portions of the fins. | 2013-10-24 |
20130280884 | Methods for the Formation of a Trap Rich Layer - An integrated circuit chip is formed with an active layer and a trap rich layer. The active layer is formed with an active device layer and a metal interconnect layer. The trap rich layer is formed above the active layer. In some embodiments, the active layer is included in a semiconductor wafer, and the trap rich layer is included in a handle wafer. | 2013-10-24 |
20130280885 | LASER-INITIATED EXFOLIATION OF GROUP III-NITRIDE FILMS AND APPLICATIONS FOR LAYER TRANSFER AND PATTERNING - A pulsed laser-initiated exfoliation method for patterning a Group III-nitride film on a growth substrate is provided. This method includes providing a Group III-nitride film a growth substrate, wherein a growth substrate/Group III-nitride film interface is present between the Group III-nitride film and the growth substrate. Next, a laser is selected that provides radiation at a wavelength at which the Group III-nitride film is transparent and the growth substrate is absorbing. The interface is then irradiated with pulsed laser radiation from the Group III-nitride film side of the growth substrate/Group III-nitride film interface to exfoliate a region of the Group III-nitride from the growth substrate. A method for transfer a Group-III nitride film from a growth substrate to a handle substrate is also provided. | 2013-10-24 |
20130280886 | WAFER PROCESSING LAMINATE, WAFER PROCESSING MEMBER, TEMPORARY BONDING ARRANGEMENT, AND THIN WAFER MANUFACTURING METHOD - A wafer processing laminate is provided comprising a support ( | 2013-10-24 |
20130280887 | Method For Releasing a Thin-Film Substrate - The present disclosure relates to methods for selectively etching a porous semiconductor layer to separate a thin-film semiconductor substrate (TFSS) having planar or three-dimensional features from a corresponding semiconductor template. The method involves forming a conformal sacrificial porous semiconductor layer on a template. Next, a conformal thin film silicon substrate is formed on top of the porous silicon layer. The middle porous silicon layer is then selectively etched to separate the TFSS and semiconductor template. The disclosed advanced etching chemistries and etching methods achieve selective etching with minimal damage to the TFSS and template. | 2013-10-24 |
20130280888 | Methods of Forming Semiconductor Devices - In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed. | 2013-10-24 |
20130280889 | SEMICONDUCTOR DEVICE AND METHOD CAPABLE OF SCRIBING CHIPS WITH HIGH YIELD - A semiconductor device comprising scribe areas that include dicing areas for separating chip areas, a groove forming area surrounding each chip area, and includes interlayer insulating lamination disposed above the semiconductor wafer; a multilayer wiring structure formed in the interlayer insulating lamination, the multilayer wiring structure including wiring layers disposed in the chip area, and dummy wirings disposed in the chip area and the scribe area, the wiring layers and the dummy wirings being formed from same mother layers; a cover layer including a passivation layer, the cover layer covering the multilayer wiring structure; and a groove formed in each groove forming area, the groove surrounding the chip areas and extending from a surface of the semiconductor wafer and at least through the passivation layer; wherein the multilayer wiring structure includes no dummy wirings in the groove forming area at least in an uppermost wiring layer. | 2013-10-24 |
20130280890 | LASER AND PLASMA ETCH WAFER DICING USING UV-CURABLE ADHESIVE FILM - Laser and plasma etch wafer dicing using UV-curable adhesive films is described. In an example, a method includes forming a mask above the semiconductor wafer. The semiconductor wafer is coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The UV-curable adhesive film is then irradiated with ultra-violet (UV) light. The singulated integrated circuits are then detached from the carrier substrate. | 2013-10-24 |
20130280891 | METHOD AND APPARATUS FOR GERMANIUM TIN ALLOY FORMATION BY THERMAL CVD - A method and apparatus for forming semiconductive semiconductor-metal alloy layers is described. A germanium precursor and a metal precursor are provided to a chamber, and an epitaxial layer of germanium-metal alloy, optionally including silicon, is formed on the substrate. The metal precursor is typically a metal halide, which may be provided by evaporating a liquid metal halide, subliming a solid metal halide, or by contacting a pure metal with a halogen gas. A group IV halide deposition control agent is used to provide selective deposition on semiconductive regions of the substrate relative to dielectric regions. The semiconductive semiconductor-metal alloy layers may be doped, for example with boron, phosphorus, and/or arsenic. The precursors may be provided through a showerhead or through a side entry point, and an exhaust system coupled to the chamber may be separately heated to manage condensation of exhaust components. | 2013-10-24 |
20130280892 | METHODS OF DEPOSITING A SEMICONDUCTOR MATERIAL ON A SUBSTRATE - Methods of depositing material on a substrate include forming a precursor gas and a byproduct from a source gas within a thermalizing gas injector. The byproduct may be reacted with a liquid reagent to form additional precursor gas, which may be injected from the thermalizing gas injector into a reaction chamber. Thermalizing gas injectors for injecting gas into a reaction chamber of a deposition system may include an inlet, a thermalizing conduit, a liquid container configured to hold a liquid reagent therein, and an outlet. A pathway may extend from the inlet, through the thermalizing conduit to an interior space within the liquid container, and from the interior space within the liquid container to the outlet. The thermalizing conduit may have a length that is greater than a shortest distance between the inlet and the liquid container. Deposition systems may include one or more such thermalizing gas injectors. | 2013-10-24 |
20130280893 | METHOD FOR PRODUCTION OF SELECTIVE GROWTH MASKS USING IMPRINT LITHOGRAPHY - The present invention discloses a method for production of selective growth masks using imprint lithography. The method includes steps of: providing a sapphire substrate, forming a GaN layer, an insulation layer, and a photo-resistive layer, performing imprint lithography, performing exposure and development, performing dry etching, and removing the remained photo-resistive layer. The selective growth masks produced by the method of the present invention make the growth of nanowires cylindrical and perpendicular to the GaN layer, and each nanowire is parallel to one another. | 2013-10-24 |
20130280894 | METHOD FOR PRODUCTION OF SELECTIVE GROWTH MASKS USING UNDERFILL DISPENSING AND SINTERING - The present invention discloses a method for production of selective growth masks using underfill dispensing and sintering. The method includes steps of: providing a sapphire substrate, growing a gallium nitride base layer on the sapphire substrate, coating a photoresist layer, performing imprint lithography, exposure and development, performing underfill dispensing, and performing sintering. The production method of the present invention can be applied in the atmosphere, and vacuum chambers as known production approaches are unnecessary. The selective growth masks produced by the method of the present invention make the growth of nanowires cylindrical and perpendicular to the gallium nitride base layer, and each nanowire is parallel to one another. | 2013-10-24 |
20130280895 | LASER CRYSTALLIZATION APPARATUS AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - Laser crystallization equipment includes a laser generator generating a laser beam, the laser beam being directed toward a processing target substrate, and a blade member over the processing target substrate, the blade member being configured to chop the laser beam with a predetermined width in two directions, wherein two ends of the laser beam chopped by the blade member are irradiated to the processing target substrate as diffraction light. | 2013-10-24 |
20130280896 | APPARATUS FOR PRODUCING POLYCRYSTALLINE SILICON AND METHOD THEREFOR - To provide an apparatus for producing polycrystalline silicon and a method therefor to allow improvement in efficiency of polycrystalline silicon production by minimizing reactor downtime and to allow polycrystalline silicon production at a relatively low cost and in a large amount in a zinc reduction process for recovering formed silicon in a solid state. In a silicon producing apparatus for producing polycrystalline silicon by reducing silicon tetrachloride with zinc, vertical reactor | 2013-10-24 |
20130280897 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a MOS transistor, a source electrode and a drain electrode on the MOS transistor each include a first carbon doped silicon layer including carbon at a first carbon concentration and phosphorus at a first phosphorus concentration and a second carbon doped silicon layer over the first silicon carbide layer, which includes phosphorus at a second phosphorus concentration higher than the first phosphorus concentration, and which includes carbon at a second carbon concentration less than or equal to the first carbon concentration. | 2013-10-24 |
20130280898 | METHOD FOR FORMING A DOPANT PROFILE - A method is provided for forming a dopant profile based on a surface of a wafer-like semiconductor component with phosphorus as a dopant. The method includes the steps of applying a phosphorus dopant source onto the surface, forming a first dopant profile with the dopant source that is present on the surface, removing the dopant source, and forming a second dopant profile that has a greater depth in comparison to the first dopant profile. In order to form an optimized dopant profile, the dopant source is removed after forming the first dopant profile, and precipitates that are crystallized selectively on or in the surface from the precipitates Si | 2013-10-24 |
20130280899 | SILICIDE FORMATION AND ASSOCIATED DEVICES - Improved silicide formation and associated devices are disclosed. An exemplary method includes providing a semiconductor material having spaced source and drain regions therein, forming a gate structure interposed between the source and drain regions, performing a gate replacement process on the gate structure to form a metal gate electrode therein, forming a hard mask layer over the metal gate electrode, forming silicide layers on the respective source and drain regions in the semiconductor material, removing the hard mask layer to expose the metal gate electrode, and forming source and drain contacts, each source and drain contact being conductively coupled to a respective one of the silicide layers. | 2013-10-24 |
20130280900 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING METAL GATE - A manufacturing method for a semiconductor device having a metal gate is provided. First and second gate trenches are respectively formed in first and second semiconductor devices. A work-function metal layer is formed in the first and second gate trenches. A shielding layer is formed on the substrate. A first removing step is performed, so that the remaining shielding layer is at bottom of the second gate trench and fills up the first gate trench. A second removing step is performed, so that the remaining shielding layer is at bottom of the first gate trench to expose the work-function metal layer at sidewall of the first gate trench and in the second gate trench. The work-function metal layer not covered by the remaining shielding layer is removed, so that the remaining work-function metal layer is only at bottom of the first gate trench. The remaining shielding layer is removed. | 2013-10-24 |
20130280901 | INTERFACE-FREE METAL GATE STACK - A non-transitory computer readable medium encoded with a program for fabricating a gate stack for a transistor is disclosed. The program includes instructions configured to perform a method. The method includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer. | 2013-10-24 |
20130280902 | STRATIFIED GATE DIELECTRIC STACK FOR GATE DIELECTRIC LEAKAGE REDUCTION - A stratified gate dielectric stack includes a first high dielectric constant (high-k) gate dielectric comprising a first high-k dielectric material, a band-gap-disrupting dielectric comprising a dielectric material having a different band gap than the first high-k dielectric material, and a second high-k gate dielectric comprising a second high-k dielectric material. The band-gap-disrupting dielectric includes at least one contiguous atomic layer of the dielectric material. Thus, the stratified gate dielectric stack includes a first atomic interface between the first high-k gate dielectric and the band-gap-disrupting dielectric, and a second atomic interface between the second high-k gate dielectric and the band-gap-disrupting dielectric that is spaced from the first atomic interface by at least one continuous atomic layer of the dielectric material of the band-gap-disrupting dielectric. The insertion of the band-gap disrupting dielectric results in lower gate leakage without resulting in any substantial changes in the threshold voltage characteristics and effective oxide thickness. | 2013-10-24 |
20130280903 | Memory Cell Layout - A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once the spacers have been formed, the dummy layers may be removed and the spacers may be used as a mask. By using the spacers instead of a standard lithographic process, the inherent limitations of the lithographic process can be avoided and further scaling of FinFET devices can be achieved. | 2013-10-24 |