42nd week of 2013 patent applcation highlights part 47 |
Patent application number | Title | Published |
20130273679 | DEPOSITION METHOD, DEPOSITION FILM, AND METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENCE DISPLAY DEVICE - A vapor deposition method of the present invention includes the steps of (i) preparing a mask unit including a shadow mask ( | 2013-10-17 |
20130273680 | Light-Emitting Element and Light-Emitting Device - To provide a light-emitting element, a light-emitting device, and an electronic device each fowled using the organometallic complex represented by General Formula (G1) as a guest material and a low molecule compound as a host material. | 2013-10-17 |
20130273681 | MANUFACTURING METHOD OF LIGHT EMITTING DEVICE HAVING AUTO-CLONING PHOTONIC CRYSTAL STRUCTURES - A light emitting device having auto-cloning photonic crystal structures comprises a substrate, a first semiconductor layer, an active emitting layer, a second semiconductor layer and a saw-toothed multilayer film comprising auto-cloning photonic crystal structures. The saw-toothed multilayer film provides a high reflection interface and a diffraction mechanism to prevent total internal reflection and enhance light extraction efficiency. The manufacturing method of the light emitting device having auto-cloning photonic crystal structures is presented here. | 2013-10-17 |
20130273682 | GRAPHENE PRESSURE SENSORS - Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device. | 2013-10-17 |
20130273683 | Method of Fabricating An Electromechanical Structure Including at Least One Mechanical Reinforcing Pillar - The invention provides a method of fabricating an electromechanical structure presenting a first substrate including a layer of monocrystalline material covered in a sacrificial layer that presents a free surface, the structure presenting a mechanical reinforcing pillar in the sacrificial layer, the method including etching a well region in the sacrificial layer to define a mechanical pillar; depositing a first functionalization layer of the first material to at least partially fill the well region and cover the free surface of the sacrificial layer around the well region; depositing a second material different from the first material for terminating the filling of the well region to thereby cover the first functionalization layer around the well region, planarizing the filler layer, the pillar being formed by the superposition of the first material and second material in the well region; and releasing the electromechanical structure by removing at least partially the sacrificial layer. | 2013-10-17 |
20130273684 | PROCESS FOR THE PRODUCTION OF PHOTOVOLTAIC CELLS - The present invention is related to a process for the manufacturing of a photovoltaic cell comprising the steps of:—providing a semiconductor substrate said semiconductor substrate comprising an insulating layer on its top surface;—implanting semiconductor ions selected from the group consisting of silicon, germanium and their mixture by ionic implantation in the insulating layer for obtaining an implanted insulating layer, the ionic implantation fluence being higher than 1.1017at./cm2, the maximum semiconductor concentration in the insulating layer after implantation being higher than the solubility of the semiconductor in the insulating layer;—thermally treating the implanted insulating layer for inducing the precipitation of the semiconductor into quantum dots;—depositing at least two conducting contacts for collecting, in use, the generated current. | 2013-10-17 |
20130273685 | PROCESS FOR ANNEALING PHOTOVOLTAIC ENCAPSULATION POLYMER FILM - A process for annealing photovoltaic polymer encapsulation film ( | 2013-10-17 |
20130273686 | Image Sensor Manufacturing Methods - Semiconductor devices and back side illumination (BSI) sensor manufacturing methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece and forming an integrated circuit on a front side of the workpiece. A grid of a conductive material is formed on a back side of the workpiece using a damascene process. | 2013-10-17 |
20130273687 | SOLAR CELL AND MANUFACTURING METHOD OF THE SAME - A method for manufacturing a solar cell, comprising steps of: a) providing a semiconductor substrate having a light-receiving side and a back side, wherein a passivation layer is formed on the back side; b) forming a silver conductor pattern on the back side of the semiconductor substrate; c) forming an aluminum conductor pattern on the back side of the semiconductor substrate, at least part of the aluminum conductor pattern being superimposed on at least part of the silver conductor pattern; and d) firing the silver conductor pattern and the aluminum conductor pattern at the same time, thereby forming an electric contact between the semiconductor substrate and the aluminum conductor pattern by way of fire through in a region where the silver conductor pattern and the aluminum conductor pattern are superimposed. | 2013-10-17 |
20130273688 | ORGANIC THIN-FILM TRANSISTORS - A thin-film transistor comprises a semiconducting layer comprising a semiconducting material selected from Formula (I) or (II): | 2013-10-17 |
20130273689 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided an electronic device including at least a first electrode, a second electrode disposed to be spaced apart from the first electrode, and an active layer disposed over the second electrode from above the first electrode and formed of an organic semiconductor material. A charge injection layer is formed between the first electrode and the active layer and between the second electrode and the active layer, and the charge injection layer is formed of an organic material having an increased electric conductivity when the charge injection layer is oxidized. | 2013-10-17 |
20130273690 | MIXED VALENT OXIDE MEMORY AND METHOD - Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure. | 2013-10-17 |
20130273691 | APPARATUS AND METHOD FOR THIN DIE-TO-WAFER BONDING - A method is provided for bonding a die to a base technology wafer and includes: providing a device wafer having a front, back, at least one side, and at least one TSV, wherein the back contains a substrate material; providing a carrier wafer having a front, back, and at least one side; bonding the wafers using an adhesive; removing the substrate material and wet etching, from the device wafer's back side, to expose at least one metallization scheme feature; processing the device wafer's back side to create at least one backside redistribution layer; removing the device wafer from the carrier wafer; dicing the device wafer into individual die; providing a base technology wafer; coating the front of the base technology wafer with a sacrificial adhesive; placing the front of the individual die onto the front of the base technology wafer; and bonding the individual die to the base technology wafer. | 2013-10-17 |
20130273692 | LEADLESS ARRAY PLASTIC PACKAGE WITH VARIOUS IC PACKAGING CONFIGURATIONS - A leadless integrated circuit (IC) package comprising an IC chip mounted to a die-attach area and a plurality of electrical contacts electrically connected to the IC chip. The IC chip, the electrical contacts, and the die-attach area are all covered with a molding material, with portions of the electrical contacts and die-attach area protruding from a bottom surface of the molding material. | 2013-10-17 |
20130273693 | OFF-CHIP VIAS IN STACKED CHIPS - A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements. | 2013-10-17 |
20130273694 | Integrated Thermal Solutions for Packaging Integrated Circuits - A method includes attaching a wafer on a carrier through an adhesive, and forming trenches in the carrier to convert the carrier into a heat sink. The heat sink, the carrier, and the adhesive are sawed into a plurality of packages. | 2013-10-17 |
20130273695 | SELECTIVE TRANSFER OF ACTIVE COMPONENTS - A method for selectively transferring active components ( | 2013-10-17 |
20130273696 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A technology with which the reliability of a package making up a semiconductor device can be enhanced is provided. A feature of the technical idea of the invention is that: a heat sink unit and an outer lead unit are separated from each other; and the outer lead unit is provided with chip placement portions and each of the chip placement portions and each heat sink are joined together. As a result, when a sealing body is formed at a resin sealing step, tying portions function as a stopper for preventing resin leakage and the formation of resin burr in a package product can be thereby prevented. In addition, camber does not occur in the heat sink unit and cracking in a sealing body caused by winding (camber) can be suppressed. | 2013-10-17 |
20130273697 | FABRICATION METHOD OF A MIXED ALLOY LEAD FRAME FOR PACKAGING POWER SEMICONDUCTOR DEVICES - This invention discloses a mixed alloy lead frame for power semiconductor devices, which includes a plurality of heat sinks and a pin array; the heat sinks are made of the first material, with positioning holes on their upper parts and welding zones at the center of their lower parts, while the pin array is made of the second material, which is different from the first material, with a plurality of sets of terminals leading out from its upper end and lower end respectively. The heat sinks are positioned on the lead frame assembly welding plate, the pin is positioned in the area between the upper heat sinks and lower heat sinks on the lead frame assembly welding plate. The mixed alloy lead frame for power semiconductor devices in this invention improves the heat dissipation of lead frame, reduces the fabrication cost of lead frame, and enhances the flexibility of fabrication. | 2013-10-17 |
20130273698 | Methods for Forming Through Vias - Methods for forming through vias in an integrated circuit package are disclosed. A substrate having a first surface is covered with an encapsulation layer of uncured material; the method includes inserting an upper mold tool having a first plurality of pillars into the encapsulation layer to imprint through vias extending to the first surface of the substrate; curing the encapsulation layer and the through vias; removing the upper mold tool from the encapsulation layer; and disposing conductor material within the through vias to make electrical connectors within the through vias. In additional methods, a method for forming an encapsulation layer using an upper and lower mold tool to form through vias and a mold cavity is disclosed. | 2013-10-17 |
20130273699 | MOS HAVING A SIC/SIGE ALLOY STACK - A delta doping of silicon by carbon is provided on silicon surfaces by depositing a silicon carbon alloy layer on silicon surfaces, which can be horizontal surfaces of a bulk silicon substrate, horizontal surfaces of a top silicon layer of a semiconductor-on-insulator substrate, or vertical surfaces of silicon fins. A p-type field effect transistor (PFET) region and an n-type field effect transistor (NFET) region can be differentiated by selectively depositing a silicon germanium alloy layer in the PFET region, and not in the NFET region. The silicon germanium alloy layer in the PFET region can overlie or underlie a silicon carbon alloy layer. A common material stack can be employed for gate dielectrics and gate electrodes for a PFET and an NFET. Each channel of the PFET and the NFET includes a silicon carbon alloy layer, and is differentiated by the presence or absence of a silicon germanium layer. | 2013-10-17 |
20130273700 | FABRICATING 3D NON-VOLATILE STORAGE WITH TRANSISTOR DECODING STRUCTURE - Disclosed herein are techniques for fabricating a 3D stacked memory device having word line (WL) select gates. The bodies of the WL select gates may be formed from the same material (e.g., highly doped polysilicon) that the word lines are formed. Desired doping profiles in a body of a WL select gate may be achieved by various techniques such as counter-doping. The WL select gates may include TFTs that formed by etching holes in the layer in which word lines are formed. Gate electrodes and gate dielectrics may be formed in the holes. Bodies may be formed in the polysilicon outside of the holes. | 2013-10-17 |
20130273701 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A transistor formed on a semiconductor substrate is covered with a first insulating film, and first conductive vias which pierce the first insulating film and which reach the transistor and a second conductive via which pierces the first insulating film and which reaches an inside of the semiconductor substrate are formed. After the formation of the first conductive vias and the second conductive via, a second insulating film is formed over the first insulating film. Conducive portions connected to the first conductive vias leading to the transistor and a conductive portion connected to the second conductive via which reaches the inside of the semiconductor substrate are formed in the second insulating film. By doing so, a multilayer interconnection is formed. | 2013-10-17 |
20130273702 | Integration Flow For LDD And Spacer Fabrication On A Sacrificial Amorphous Carbon Gate Structure - An integration flow for LDD and spacer fabrication on a sacrificial amorphous carbon gate structure, form first spacer by way of depositing on the si substrate which have gate structure first. Gate is provided above the N-well and P-well on substrate. Spin coating a layer of photoresist in the first spacer, patterning the photoresist, and the gate structure above the N-well or P-well is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the first spacer layer, form the second spacer layer by depositing on the surface of the si substrate and gate, and spin coating another photoresist layer on the second spacer layer. Pattern the another photoresist layer, and another side of the gate structure is exposed, ion lightly dope treatment is then used to the whole device. Remove the redundant photoresist and the second spacer layer, form the third spacer layer and SiN layer by depositing on the gate and the Si substrate in turn. Form spacer by removing the redundant the third spacer layer and SiN layer. | 2013-10-17 |
20130273703 | SEMICONDUCTOR DEVICE INCLUDING A MOS TRANSISTOR AND PRODUCTION METHOD THEREFOR - It is intended to provide a semiconductor device including a MOS transistor, comprising: a semiconductor pillar; a bottom doped region formed in contact with a lower part of the semiconductor pillar; a first gate formed around a sidewall of the semiconductor pillar through a first dielectric film therebetween; and a top doped region formed so as to at least partially overlap a top surface of the semiconductor pillar, wherein the top doped region has a top surface having an area greater than that of the top surface of the semiconductor pillar. | 2013-10-17 |
20130273704 | METHODS OF FORMING A POLYSILICON LAYER AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of forming a polysilicon layer includes providing a silicon precursor onto an object loaded in a process chamber to form a seed layer. The silicon precursor includes a nitrogen containing silicon precursor and a chlorine containing silicon precursor. The method further includes providing a silicon source on the seed layer. | 2013-10-17 |
20130273705 | Multi-Fin Device and Method of Making Same - A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned. | 2013-10-17 |
20130273706 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes firstly providing a gate structure disposed on a substrate and a first nitride material layer disposed on the gate structure, secondly performing a protective step to modify the first nitride material layer in the presence of oxygen, then forming a second nitride material layer on the substrate, and later performing a removal step to remove the second nitride material layer without substantially slashing the modified first nitride material layer. | 2013-10-17 |
20130273707 | ALD processing techniques for forming non-volatile resistive switching memories - ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer. | 2013-10-17 |
20130273708 | METHOD OF MANUFACTURING A NANOSTRUCTURE QUICK-SWITCH MEMRISTOR - A nanostructure quick-switch memristor includes an upper electrode, a lower electrode and three layers of nanomembrane provided between the upper electrode and the lower electrode. The three layers of nanomembrane consist of an N-type semiconductor layer, a neutral semiconductor layer on the N-type semiconductor layer, and a P-type semiconductor layer on the neutral semiconductor layer. The nanostructure quick-switch memristor of the present invention has the quick switching speed, simple manufacturing method, and low manufacturing cost. | 2013-10-17 |
20130273709 | METHODS OF RECESSING AN ACTIVE REGION AND STI STRUCTURES IN A COMMON ETCH PROCESS - Generally, the present disclosure is directed to various methods of recessing an active region and an adjacent isolation structure in a common etch process. One illustrative method disclosed includes forming an isolation structure in a semiconducting substrate, wherein the isolation structure defines an active area in the substrate, forming a patterned masking layer above the substrate, wherein the patterned masking layer exposes the active area and at least a portion of the isolation structure for further processing, and performing a non-selective dry etching process on the exposed active area and the exposed portion of the isolation structure to define a recess in the substrate and to remove at least some of the exposed portions of the isolation structure. | 2013-10-17 |
20130273710 | SUBSTRATE FINS WITH DIFFERENT HEIGHTS - A device includes a number of fins. Some of the fins have greater heights than other fins. This allows the selection of different drive currents and/or transistor areas. | 2013-10-17 |
20130273711 | METHOD OF FORMING A FINFET DEVICE - A method for fabricating a device is disclosed. An exemplary method includes providing a substrate and forming a plurality of fins over the substrate. The method further includes forming a first opening in the substrate in a first longitudinal direction. The method further includes forming a second opening in the substrate in a second longitudinal direction. The first and second longitudinal directions are different. The method further includes depositing a filling material in the first and second openings. | 2013-10-17 |
20130273712 | PROCESS FOR FABRICATING A SILICON-ON-INSULATOR STRUCTURE EMPLOYING TWO RAPID THERMAL ANNEALING PROCESSES, AND RELATED STRUCTURES - A method for fabricating a silicon-on-insulator structure includes forming a first oxide layer on a silicon donor substrate, forming a second oxide layer on a supporting substrate, and forming a weakened zone in the donor substrate. The donor substrate is bonded to the supporting substrate by establishing direct contact between the first oxide layer on the silicon donor substrate and the second oxide layer on the supporting substrate and establishing a direct oxide-to-oxide bond therebetween. The donor substrate is split along the weakened zone to form a silicon-on-insulator structure, and the silicon-on-insulator structure is subjected to two successive rapid thermal annealing processes at temperatures T1 and T2 respectively, wherein T1 is less than or equal to T2, T1 is between 1200° C. and 1300° C., T2 is between 1240° C. and 1300° C., and when T1 is below 1240° C., then T2 is above 1240° C. | 2013-10-17 |
20130273713 | PROCESS FOR THE TRANSFER OF A THIN FILM COMPRISING AN INCLUSION CREATION STEP - A process for transferring a thin film includes forming a layer of inclusions to create traps for gaseous compounds. The inclusions can be in the form of one or more implanted regions that function as confinement layers configured to trap implanted species. Further, the inclusions can be in the form of one or more layers deposited by a chemical vapor deposition, epitaxial growth, ion sputtering, or a stressed region or layer formed by any of the aforementioned processes. The inclusions can also be a region formed by heat treatment of an initial support or by heat treatment of a layer formed by any of the aforementioned processes, or by etching cavities in a layer. In a subsequent step, gaseous compounds are introduced into the layer of inclusions to form micro-cavities that form a fracture plane along which the thin film can be separated from a remainder of the substrate. | 2013-10-17 |
20130273714 | METHOD FOR PREPARING SEMICONDUCTOR SUBSTRATE WITH INSULATING BURIED LAYER BY GETTERING PROCESS - A method for preparing a semiconductor substrate with an buried insulating layer by a guttering process, includes the following steps: providing a device substrate and a supporting substrate; forming an insulating layer on a surface of the device substrate; performing a heating treatment on the device substrate, so as to form a denuded zone on the surface of the device substrate; bonding the device substrate having the insulating layer with the supporting substrate, such that the insulating layer is sandwiched between the device substrate and the supporting substrate; annealing and reinforcing a bonding interface, such that an adherence level of the bonding interface meets requirements in the following chamfering grinding, thinning and polishing processes; performing the chamfering grinding, thinning and polishing processes on the device substrate which is bonded. | 2013-10-17 |
20130273715 | SILICON-ON-INSULATOR SUBSTRATE WITH BUILT-IN SUBSTRATE JUNCTION - A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer. | 2013-10-17 |
20130273716 | METHOD OF DICING SUBSTRATE - In a step of performing dicing by sticking a protective tape for protecting a wafer surface, in order to obtain a dicing method which ensures that there is no paste residue on a chip side face and that the protective tape is prevented from peeling from the wafer during the dicing and which is excellent in productivity, in a step of performing dicing by sticking a surface protective adhesive tape having an energy ray-curable adhesive layer on one surface of a substrate, thereby performing surface protection for the surface of the semiconductor wafer where an integrated circuit is to be formed, the energy ray-curable adhesive layer is cured by radiating energy rays beforehand to an inner circumferential portion of the wafer, and dicing is performed, with the energy ray-curable adhesive layer kept in an uncured condition by ensuring that energy rays are not radiated to an outer peripheral portion. | 2013-10-17 |
20130273717 | Apparatus and Method for the Singulation of a Semiconductor Wafer - The present disclosure is directed to an apparatus for the singulation of a semiconductor substrate or wafer. In some embodiments the singulation apparatus comprises a plurality of cutting devices. The cutting devices are configured to form multiple concurrent cutting lines in parallel on a surface of the semiconductor wafer. In some embodiments, the singulation apparatus comprises at least two dicing saws or laser modules. The disclosed singulation apparatus can dice the semiconductor wafer into individual chips by dicing in a direction across a complete circumferential edge of the wafer, thereby decreasing process time and increasing throughput. | 2013-10-17 |
20130273718 | TAPE FOR PROCESSING WAFER, METHOD FOR MANUFACTURING TAPE FOR PROCESSING WAFER, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a wafer processing tape, circular or tongue-shaped notched parts facing the center of an adhesive layer, as seen in a plan view, are formed so as to correspond to a pasting region to a wafer ring to a depth that reaches a release substrate from the side of a base material film. Due to the formation of the notched parts, when a peeling force acts on the wafer processing tape, portions of a tacky material layer and the base material film which are more outward than the notched parts are peeled off first, and a portion that is more inward than the notched parts remains on the wafer ring in a protruding state. Accordingly, a peeling strength between the wafer processing tape and the wafer ring can be increased and the wafer processing tape can be suppressed from being peeled off from the wafer ring during processes. | 2013-10-17 |
20130273719 | METHOD OF MANUFACTURING ANNEALED WAFER - Annealed wafers having reduced residual voids after annealing and reduced deterioration of TDDB characteristics of an oxide film formed on the annealed wafer, while extending the range of nitrogen concentration contained in a silicon single crystal, are prepared by a method wherein crystal pulling conditions are controlled such that a ratio V/G between a crystal pulling rate V and an average axial temperature gradient G is ≧0.9×(V/G) | 2013-10-17 |
20130273720 | GRAPHENE LAYER FORMATION ON A CARBON BASED SUBSTRATE - A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source. | 2013-10-17 |
20130273721 | Trench Formation Method For Releasing A Thin-Film Substrate From A Reusable Semiconductor Template - A method is provided for fabricating a thin-film semiconductor substrate by forming a porous semiconductor layer conformally on a reusable semiconductor template and then forming a thin-film semiconductor substrate conformally on the porous semiconductor layer. An inner trench having a depth less than the thickness of the thin-film semiconductor substrate is formed on the thin-film semiconductor substrate. An outer trench providing access to the porous semiconductor layer is formed on the thin-film semiconductor substrate and is positioned between the inner trench and the edge of the thin-film semiconductor substrate. The thin-film semiconductor substrate is then released from the reusable semiconductor template. | 2013-10-17 |
20130273722 | CONTACT ON A HETEROGENEOUS SEMICONDUCTOR SUBSTRATE - A method for producing a microelectronic device with plural zones made of a metal and semiconductor compound, from semiconductor zones made of different semiconductor materials, and on which a thin semiconductor layer is formed prior to the deposition of a metal layer so as to lower the nucleation barrier of the semiconductor zones when reacting with the metal layer. | 2013-10-17 |
20130273723 | GRAPHENE LAYER FORMATION AT LOW SUBSTRATE TEMPERATURE ON A METAL AND CARBON BASED SUBSTRATE - A system and method for forming graphene layers on a substrate. The system and methods include direct growth of graphene on diamond and low temperature growth of graphene using a solid carbon source. | 2013-10-17 |
20130273724 | METHOD FOR CRYSTALLIZING AMORPHOUS SILICON THIN FILM AND METHOD FOR FABRICATING POLY CRYSTALLINE THIN FILM TRANSISTOR USING THE SAME - Provided is a method of crystallizing an amorphous silicon thin film transistor and a method of fabricating a polycrystalline thin film transistor using the same, in which the polycrystalline thin film transistor indicating leakage current characteristics of a level that is applicable for active matrix organic light emitting diode displays (AMOLEDs) can be manufactured by using a silicide seed induced lateral crystallization (SILC) method. The amorphous silicon thin film transistor crystallizing method includes the steps of: forming an amorphous silicon layer on a substrate; forming an active region by patterning the amorphous silicon layer; forming a crystallization induced metal layer in both a source region and a drain region that are placed on both side ends of the active region; forming a number of dot-shaped metal silicide seeds on the surfaces of the source region and the drain region made of amorphous silicon by removing the crystallization induced metal layer; and crystallizing the active region formed of the amorphous silicon layer by heat-treating the substrate by using the metal silicide seeds as crystallization seeds. | 2013-10-17 |
20130273725 | METHOD OF FABRICATING A STRUCTURED SEMICONDUCTOR SUBSTRATE - A method is provided for fabricating a structured semiconductor substrate including: i) depositing, on the surface of a semiconductor material, a sacrificial layer of material different from the semiconductor material. At step ii), the sacrificial layer, formed in step i) is etched at least in part so as to form sacrificial layer islets on the surface of the semiconductor material. The semiconductor material of step ii) is etched at least in part, in zones that are not protected by said islets, so as to form a structured semiconductor material, this step iii) being performed in the presence of oxygen so as to deposit an oxide layer on the surface of the semiconductor material. The sacrificial layer islets and the oxide layer are eliminated from the surface of the semiconductor material obtained in step iii), so as to form the structured substrate. | 2013-10-17 |
20130273726 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE INCLUDING PROCESS MONITORING PATTERN HAVING OVERLAPPING INPUT/OUTPUT PAD ARRAY AREA - The semiconductor device includes a process monitoring pattern and an input/output (I/O) pad array area, the process monitoring pattern including a lower layer having a peripheral area surrounding a first internal area, the first internal area exposed by an internal open area, an external structure on the peripheral area of the lower layer, and a first dam disposed in the peripheral area spaced apart from the external structure by an external open area, the first dam defining the first internal area. The peripheral area overlaps the input/output (I/O) pad array area of the semiconductor device. | 2013-10-17 |
20130273727 | SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME - A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride layer, a metal-silicon oxide layer, and a metal-silicon nitride layer. | 2013-10-17 |
20130273728 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including forming a charge storage layer, and forming a first tunnel insulating layer covering the charge storage layer, the forming of the first tunnel insulating layer including heat treating the charge storage layer. | 2013-10-17 |
20130273729 | HIGH-K METAL GATE ELECTRODE STRUCTURES FORMED BY SEPARATE REMOVAL OF PLACEHOLDER MATERIALS IN TRANSISTORS OF DIFFERENT CONDUCTIVITY TYPE - In a replacement gate approach, a superior cross-sectional shape of the gate opening may be achieved by performing a material erosion process in an intermediate state of removing the placeholder material. Consequently, the remaining portion of the placeholder material may efficiently protect the underlying sensitive materials, such as a high-k dielectric material, when performing the corner rounding process sequence. | 2013-10-17 |
20130273730 | METHOD TO REALIZE FLUX FREE INDIUM BUMPING - A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited. | 2013-10-17 |
20130273731 | FAN-OUT CHIP SCALE PACKAGE - A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads. | 2013-10-17 |
20130273732 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller. | 2013-10-17 |
20130273733 | Methods for Depositing Manganese and Manganese Nitrides - Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film. | 2013-10-17 |
20130273734 | METHOD OF MANUFACTURING METAL SALICIDE LAYERS - A method of manufacturing salicide layers includes the following steps. Firstly, a silicon substrate with a patterned stack structure of a silicon layer and a first cap layer sequentially formed thereon is provided. Then, a second cap layer is formed on the exposed silicon substrate. The materials of the first cap layer and the second cap layer are different. Then, the first cap layer is removed to expose the silicon layer. Then, a first metal layer is formed on the silicon layer and reacted with the silicon layer to produce a first salicide layer. Afterward, the second cap layer is removed, and a second metal layer is formed over the surface of the silicon substrate and reacted with the silicon substrate to produce a second salicide layer. | 2013-10-17 |
20130273735 | Oxidation-Free Copper Metallization Process Using In-situ Baking - A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing a plasma process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer | 2013-10-17 |
20130273736 | METHOD FOR FABRICATING MOS TRANSISTOR - A method for fabricating metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate having a silicide thereon; performing a first rapid thermal process to drive-in platinum from a surface of the silicide into the silicide; and removing un-reacted platinum in the first rapid thermal process. | 2013-10-17 |
20130273737 | Method for Cleaning Semiconductor Substrate - Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate. | 2013-10-17 |
20130273738 | MASK BLANK, METHOD OF MANUFACTURING THE SAME, TRANSFER MASK, AND METHOD OF MANUFACTURING THE SAME - Provided is a method of manufacturing a mask blank that is improved in cleaning resistance to ozone cleaning or the like, thus capable of preventing degradation of the mask performance due to the cleaning. The method is for manufacturing a mask blank having, on a substrate, a thin film which is formed at its surface with an antireflection layer made of a material containing a transition metal, and carries out a treatment of causing a highly concentrated ozone gas with a concentration of 50 to 100 vol % to act on the antireflection layer to thereby form a surface modified layer comprising a strong oxide film containing an oxide of the transition metal at a surface of the antireflection layer. | 2013-10-17 |
20130273739 | AQUEOUS POLISHING COMPOSITION AND PROCESS FOR CHEMICALLY MECHANICALLY POLISHING SUBSTRATES HAVING PATTERNED OR UNPATTERNED LOW-K DIELECTRIC LAYERS - An aqueous polishing composition comprising (A) abrasive particles and (B) an amphiphilic nonionic surfactant selected from the group consisting of water-soluble or water-dispersible surfactants having (b1) hydrophobic groups selected from the group consisting of branched alkyl groups having 10 to 18 carbon atoms; and (b2) hydrophilic groups selected from the group consisting of polyoxyalkylene groups comprising (b21) oxyethylene monomer units and (b22) substituted oxyalkylene monomer units wherein the substituents are selected from the group consisting of alkyl, cycloalkyl, or aryl, alkyl-cycloalkyl, alkyl-aryl, cycloalkyl-aryl and alkyl-cycloalkyl-aryl groups, the said polyoxyalkylene group containing the monomer units (b21) and (b22) in random, alternating, gradient and/or blocklike distribution; a CMP process for substrates having patterned or unpatterned low-k or ultra-low-k dielectric layers making use of the said aqueous polishing composition; and the use of the said aqueous polishing composition for manufacturing electrical, mechanical and optical devices. | 2013-10-17 |
20130273740 | FILM PORTION AT WAFER EDGE - A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer. | 2013-10-17 |
20130273741 | GAP EMBEDDING COMPOSITION, METHOD OF EMBEDDING GAP AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE BY USING THE COMPOSITION - A gap embedding composition used for embedding a patterned gap formed between photosensitive resin film portions on a semiconductor substrate surface, the gap embedding composition, at least having: a hydrolysis condensate of an aryloxysilane raw material; and an aromatic compound, as a solvent. | 2013-10-17 |
20130273742 | METHOD OF FORMING CONNECTION HOLES - The present invention provides a method of forming connection holes. The method utilizes two different gases to perform two etching processes for the interlayer dielectric layer so as to form connection holes. The etching rate of the interlayer dielectric layer in the first etching process using the first etching gas is proportional to the size of the openings which defines the connection hole while the etching rate of the interlayer dielectric layer in the second etching process using the second etching gas is inversely related with size of the openings. According to the present invention, the first etching gas and the second etching gas compensate for each other to eliminate the loading effect, thus the connection holes are formed with almost the same depth. Therefore the damage of the etching stopper layer due to the high etching rate in the larger connection holes can be avoided, which prevents the excessive variation of the connecting resistance and expands the process window. | 2013-10-17 |
20130273743 | WAFER BACKSIDE DEFECTIVITY CLEAN-UP UTILIZING SELECTIVE REMOVAL OF SUBSTRATE MATERIAL - A wafer and a fabrication method include a base structure including a substrate for fabricating semiconductor devices. The base structure includes a front side where the semiconductor devices are formed and a back side opposite the front side. An integrated layer is formed in the back side of the base structure including impurities configured to alter etch selectivity relative to the base structure such that the integrated layer is selectively removable from the base structure to remove defects incurred during fabrication of the semiconductor devices. | 2013-10-17 |
20130273744 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A method of processing a substrate is disclosed. The method uses a substrate processing apparatus including a processing tank that retains a processing liquid and that accommodates a workpiece substrate, a recirculation system recirculating the processing liquid into the processing tank by supplying the processing liquid heated by a recirculation system heater from a lower portion of the processing tank and collecting the processing liquid from an upper portion of the processing tank, a plurality of heaters distributed on an upper portion and a lower portion of the processing tank to heat the processing liquid. The method includes setting a first temperature setpoint to a heater located on the upper portion of the processing tank, and setting a second temperature setpoint lower than the first temperature setpoint to a heater located on the lower portion of the processing tank. | 2013-10-17 |
20130273745 | ETCHING PASTE, PRODUCTION METHOD THEREOF, AND PATTERN FORMING METHOD USING THE SAME - An etching paste and a method of forming a pattern, the etching paste including an organic binder; phosphoric acid; a nitrogen-containing compound; and a solvent, the nitrogen-containing compound including at least one selected from amine compounds represented by Formula 1 and ammonium compounds represented by Formula 2. | 2013-10-17 |
20130273746 | VAPOR DEPOSITION DEVICE AND VAPOR DEPOSITION METHOD - A vapor deposition device ( | 2013-10-17 |
20130273747 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE, SUBSTRATE PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device, includes: forming a film containing a predetermined element on a substrate by performing a cycle a predetermined number of times, the cycle including: supplying a first precursor containing the predetermined element and a halogen group to the substrate; supplying a second precursor containing the predetermined element and an amino group to the substrate; and supplying a reducing agent not containing halogen, nitrogen and carbon to the substrate. | 2013-10-17 |
20130273748 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device is provided, including: forming an oxynitride film having a specific film thickness on a substrate by performing multiple numbers of times a cycle of: forming a specific element-containing layer on the substrate by supplying a source gas containing a specific element into a processing vessel in which the substrate is housed; changing the specific element-containing layer to a nitride layer by supplying a nitrogen-containing gas into the processing vessel; and changing the nitride layer to an oxynitride layer by supplying an oxygen-containing gas and an inert gas into the processing vessel, with this sequence as one cycle, wherein a composition ratio of the oxynitride film having the specific film thickness is controlled by controlling a partial pressure of the oxygen-containing gas in the processing vessel, in changing the nitride layer to the oxynitride layer. | 2013-10-17 |
20130273749 | LASER ANNEALING APPARATUS AND LASER ANNEALING METHOD - A laser annealing apparatus carries out an annealing treatment an amorphous silicon film on a TFT substrate. The apparatus includes: a mask having a plurality of apertures; a microlens substrate having a plurality of microlenses arranged on a surface thereof and configured to focus the plurality of laser beams Lb, that have passed through the respective apertures of the mask, onto the TFT substrate to apply a predetermined energy to the amorphous silicon film; a pair of guides each having a semi-cylindrical shape and disposed along both sides across the microlens substrate so that the axes of the guides are parallel to each other and that the tips of the guides protrude from the positions of tips of the microlenses toward the TFT substrate; and a film that is provided in a tensioned state between the pair of guides so as to be movable and that transmits a laser beam. | 2013-10-17 |
20130273750 | Layer Alignment in FinFET Fabrication - Methods for aligning layers more accurately for FinFETs fabrication. An embodiment method includes forming a first pattern in a workpiece using a first photomask, forming a second pattern in the workpiece using a second photomask, the second photomask aligned to the first pattern, and aligning a third pattern to the first and the second patterns by aligning a first feature of the third pattern to a first feature of the first pattern in a first direction, and aligning a second feature of the third pattern to a first feature of the second pattern in a second direction orthogonal to the first direction. | 2013-10-17 |
20130273751 | SUBSTRATE PROCESSING WITH REDUCED WARPAGE AND/OR CONTROLLED STRAIN - Provided are systems and methods for processing the surface of substrates that scan a laser beam at one or more selected orientation angles. The orientation angle or angles may be selected to reduce substrate warpage. When the substrates are semiconductor wafers having microelectronic devices, the orientation angles may be selected to produce controlled strain and to improve electronic performance of the devices. | 2013-10-17 |
20130273752 | INTERPOSER CONNECTORS WITH MAGNETIC COMPONENTS - Disclosed are interposer electrical connector embodiments including magnetic components used to facilitate interconnection of peripheral devices to standard input/output, or “I/O”, connectors (such as USB connectors) of devices such as mobile communications products (e.g. smart phones, tablets, and personal computers). The interposer connector embodiments disclosed include those in which a plurality of discrete permanent magnets are arranged with magnetic poles aligned in the same orientation perpendicular to and on one side of the electrical interface. Other embodiments include a plurality of bar permanent magnets located on opposite sides of the interface with all poles of the same type directed at the interface, but each one opposing a ferromagnetic element. These arrangements provide self-aligning capabilities useful for electrical connections that have restrictions on visibility or connection approach geometries. Other embodiments have a single magnet per mated connector pair and magnetic pole pieces and/or actuators to concentrate magnetic flux providing the magnetic attractive force for a plurality of electrical connections. | 2013-10-17 |
20130273753 | BOARD CONNECTING TERMINAL AND HOLDING STRUCTURE OF CIRCUIT BOARD - A board connecting terminal includes a contact that comes into contact with a mate side terminal, an indent that comes into contact with a pad formed on a circuit board, a terminal attaching part connected to the indent to attach the board connecting terminal to the circuit board, and an engaging piece connected to the contact and having a part held by a holder on which the circuit board is mounted. In the terminal attaching part, when the board connecting terminal is attached to the circuit board, a part of the terminal attaching part enters a through hole passing through the circuit board in a thickness direction thereof to restrain the indent from moving in a planar direction of the circuit board. | 2013-10-17 |
20130273754 | CONNECTOR - Provided is a connector to be securely fixed on a board, especially, the connector having a high-strength shell prevented from detached from the connector. The connector has a mating portion, a plurality of the contacts, a holding member holding the contacts and a shell and to he connected with a mating connector in a front-back direction. The mating portion is positioned in forward part of the connector. The holding member is formed with a protrusive portion protruding back ward. The protrusive portion is formed with a receiving portion. An edge of the shell is formed a stopper portion. The stopper portion and the receiving portion face to each other in the front-back direction. The contact has a contact-fixing portion fixed on the board. The shell has a shell-fixing portion fixed on the board. A distance between the shell-fixing portion and the mating portion is larger than another distance between the contact-fixing portion and the mating portion. | 2013-10-17 |
20130273755 | BATTERY SYSTEM FOR VEHICLE - There is provided a battery system for a vehicle. The battery system includes: a battery module; a junction box which connects the battery module to other electronic components; and a case which includes the battery module and the junction box. The junction box is integrally mounted on a side surface of the battery module which is fixed to the case, and at least the junction box is non-contact with an inner surface of the case. | 2013-10-17 |
20130273756 | ELECTRICAL CONNECTOR HAVING RIBBED GROUND PLATE WITH ENGAGEMENT MEMBERS - An electrical connector includes a dielectric housing, a plurality of electrical signal contacts supported by the dielectric housing, and an electrically conductive ground plate supported by the dielectric housing. The dielectric hosing defines at least one protrusion, and the ground plate defines at least one aperture that receives the protrusion. The apertures can define a first dimension along a select direction and a second dimension along the select direction, wherein the first dimension is greater than the second dimension so as to define a lead-in for the protrusion. The protrusion can be press-fit to the electrically conductive ground plate at the second dimension of the aperture so as to secure the ground plate to the dielectric housing. | 2013-10-17 |
20130273757 | POWER-TRACK COUPLING - A coupling is used with a U-section longitudinally extending power track having a floor and a pair of side walls defining a longitudinally and transversely open retaining channel and provided on the side walls with respective dielectric support rails each carrying a respective longitudinally extending main conductor transversely exposed in the slot and connected to phase or ground. The coupling has a dielectric coupling housing extending along an axis and having center structure defining a center symmetry plane perpendicular to the axis and end formations projecting axially oppositely from the center structure and each fittable longitudinally into the channel at an end of the power track to an insertion depth determined by the center structure. Two L-section and longitudinally extending metallic contact strips are carried on and transversely limitedly movable in a predetermined transverse direction in the dielectric housing. | 2013-10-17 |
20130273758 | POWER TRACK - A metal power track has a U-section body having a pair of parallel side walls joined by a floor wall and delimiting a longitudinally extending retaining channel. Respective longitudinally extending and dielectric support rails are carried on the side walls, and a ground strip is provided on the floor wall. Two respective longitudinally extending, uninsulated bare main conductors are carried on each of the the dielectric support rails and are adapted to conduct power. Respective longitudinally extending uninsulated secondary conductors are carried on each of the dielectric support rails between the respective main conductors but out of electrical contact therewith. The conductors are all exposed transversely in the retaining channel. Each of the secondary conductors is adapted to carry electrical control signals or act as light-duty power feed lines. | 2013-10-17 |
20130273759 | USB Interface and Data Product with the Interface - The present invention discloses a USB interface comprising a turnover joint ( | 2013-10-17 |
20130273760 | ELECTRICAL CONNECTOR - An efficient removal operation of a signal transmission medium is enabled with a simple configuration. A lock mechanism having a latch lock part, which retains an inserted state of the signal transmission medium by engagement with the signal transmission medium inserted in an insulating housing, is provided with an unlock maintaining part, which retains the latch lock part at a detachment position in conjunction with an unlock operation. It is configured so that, when the latch lock part of the lock mechanism is to be detached from the signal transmission medium by the unlock operation, an unlock maintaining part, which is moved in conjunction with the unlock operation, causes the latch lock part to be retained in a state in which it is detached from the signal transmission medium, and the signal transmission medium is maintained in a removable state thereafter even without continuing the unlock operation so that the unlock operation is completed at first for example only with one hand, and the signal transmission medium can be removed thereafter. | 2013-10-17 |
20130273761 | CONTINUITY MAINTAINING BIASING MEMBER - A post having a first end, a second end, and a flange proximate the second end, wherein the post is configured to receive a center conductor surrounded by a dielectric of a coaxial cable, a connector body attached to the post, a coupling element attached to the post, the coupling element having a first end a second end, and a biasing member disposed within a cavity formed between the first end of the coupling element and the connector body to bias the coupling element against the post is provided. Moreover, a connector body having a biasing element, wherein the biasing element biases the coupling element against the post, is further provided. Furthermore, associated methods are also provided. | 2013-10-17 |
20130273762 | COVER FOR CABLE CONNECTORS - A cover and a system of covers for placement in sealed relation over a connector or a pair of connectors that is or are adapted to terminate a cable or splice together a pair of cables. The covers include a cable end that sealingly receives a cable therein, an elongated body that provides secure cover to a cable connector, and an end that abuts a bulkhead or sealingly engages with a second cover when used in a splicing application. | 2013-10-17 |
20130273763 | DETACHABLE CONNECTOR - An easily detachable connector comprises a female connector and a male connector. The female connector has a wall body and a sleeve opening enclosed by the wall body. A through hole is disposed on the wall body. The male connector comprises a protruding body corresponding to the sleeve opening. The protruding body comprises a protruding piece disposed in a position corresponding to that of the through hole. When the connector is connected, the protruding body is inserted inside the sleeve opening and the protruding piece is fitted inside the through hole. | 2013-10-17 |
20130273764 | CONNECTOR - A connector ( | 2013-10-17 |
20130273765 | ELECTRIC CONNECTOR - The electric connector includes a housing having a groove into which a signal-transmission medium is inserted at opposite edges thereof, and a lock device including a locker for locking the signal-transmission medium at the groove and allowing the signal-transmission medium to be released out of the groove, the locker moving up beyond and moving down below a first inner surface of the groove extending in parallel with a direction in which the signal-transmission medium is inserted into the groove, the locker being energized towards a second inner surface of the groove situated opposing to the first inner surface, the lock device further including a compressor for compressing the signal-transmission medium towards the second inner surface so as to allow the signal-transmission medium to be released out of the groove. | 2013-10-17 |
20130273766 | PLUG-IN CONNECTOR FOR HIGH DATA TRANSMISSION RATES - A so-called QSFP-plug-in connector is suggested for high performance-plug-in connections in data centers, which comprises a one-piece metallic exterior housing and in which a one-piece locking device is embodied, which via a latch attached thereat can be released from an appropriately embodied cage-like counter connector. | 2013-10-17 |
20130273767 | PLUG CONNECTOR WITH MIS-INSERT FEATURES AND CORRESPONDING RECEPTACLE CONNECTOR THEREWITH - A plug connector ( | 2013-10-17 |
20130273768 | Connector With A Guiding Portion - The invention is directed towards a connector with a guiding portion having a housing, a connecting interface having a plurality of conductive terminals, and a first guiding post disposed along the housing, whereby the first guiding post has a sloping guiding portion. | 2013-10-17 |
20130273769 | PLUG CONNECTOR COMPRISING INSULATION DISPLACEMENT TERMINALS AND A CAPTIVE INSULATING BODY - An insulating body ( | 2013-10-17 |
20130273770 | TEXTURING AN LED OPENING IN A CONNECTOR BODY - Connector inserts and receptacles that may have indicators that are easy to manufacture, may have an attractive appearance, reduce reflections, and may provide a consistent indication independent of viewing angle. One example may provide a connector insert having an opening to provide light from an LED. The opening may be filled with an adhesive or other material. A surface of the adhesive may be textured, for example by chemical etch, laser, sand or glass bead blasting, through the use of texture tape or other stamp, or in other ways. An entire connector or just the indication itself may be etched. Masking may be used to protect a connector body during texturing. | 2013-10-17 |
20130273771 | Cable Lug Pad - An electrical system includes an electrical device mounted within an electrical enclosure. A electrical cable is coupled to an electrical junction of the electrical device via a cable lug, the cable lug having at least two lug holes. A lug pad attaches the cable lug to the electrical device and has at least two pad holes. Each of the pad holes is aligned with a respective one of the lug holes, and at least one of the lug holes and the pad holes is a slotted hole for permitting angular adjustable positioning of the cable lug relative to the lug pad. | 2013-10-17 |
20130273772 | METER SOCKET BLOCK ASSEMBLY - A meter socket block assembly for a meter socket connected to a meter having at least one meter blade, wherein the meter socket includes at least one conductor. The meter socket block assembly includes at least one lug and jaw body, the body having a lug portion and a first jaw portion which are unistructurally formed and wherein the lug portion is connected to the conductor. The meter socket block assembly also includes a second jaw portion attached to the first jaw portion to form a jaw for connecting to the meter blade. Further, the meter socket block assembly includes a base having a lug cavity for receiving the body and at least one snap tab for attaching the body to the base. | 2013-10-17 |
20130273773 | ELECTRICAL CONNECTOR - An electrical connector includes a first insulating housing having a base board and a tongue board extending forwards from a front of the base board. Two opposite sides of the base board extend downward to form a pair of clamping boards spaced from each other. A second insulating housing is assembled to the first insulating housing. The second insulating housing has a base portion resisting against rear edges of the clamping boards. A tongue portion protrudes forwards from a front of the base portion to be clamped between the clamping boards. A terminal group includes a plurality of flat terminals and a plurality of spring terminals. The flat terminals are molded in the first insulating housing and the spring terminals are molded in the second insulating housing. A metal shell encloses both the first insulating housing and the second insulating housing. | 2013-10-17 |
20130273774 | COMBINATION ELECTRCIAL CONNECTOR AND ASSMBLY OF THE SAME - An electrical connector comprises an insulating housing, a contact module and a metal shell. The insulating housing defines a front face and rear face, and a receiving space running through the front face and the rear face. The contact module includes a plurality of first contacts loaded thereon and is received in the receiving space, the contacting comprising board connecting tail exposing to the rear face of the housing. The metal shell is received in the receiving space and surrounds the contact module second connector port located beside and separated from the first connector port in said lengthwise direction. Wherein the metal shell is inserted and retained with the insulating housing from the front face, the contact module is inserted and retained with the insulating housing from the rear face. | 2013-10-17 |
20130273775 | FILTER PLUG - A filter plug comprises a terminal holder with a recess body, a toroidal inductor and a cable. A plurality of conductive terminals are arranged on the recess body in a first direction thereof; a plurality of wire grippers are arranged on the recess body in a second direction thereof; and there is an angle between the first direction and the second direction. The toroidal inductor is arranged inside the recess body and comprises a magnetic ring with independent conductive coils wound thereon; two ends of the conductive coils are respectively connected to the conductive terminal and the wire gripper. The cable comprises a plurality of wires respectively connected to the wire grippers. The filter plug described above has filtering functions and is easy to assemble and can save space effectively. | 2013-10-17 |
20130273776 | Conversion Adaptor and LCD Inspection System - The present invention publishes a conversion adaptor used for LCD panel inspection. The conversion adaptor comprises in order: a first connector plug, an adaptor main body, and a second connector plug; wherein, the first connector plug is used to connect to the connector of a test signal source, and the second connector plug is used to connect to the connector of a connecting cable to an LCD device. The present invention also includes an LCD inspection system. By adding a conversion adaptor, the present invention prevents damage done to the test signal source caused by frequent plugging and unplugging of LVDS cables from its external connector. | 2013-10-17 |
20130273777 | Electrical Connector - An electrical connector includes a plurality of channels and at least one module. The channels transmit a plurality of electrical signals, wherein each channel generates at least one crosstalk coupling with the other channels; the at least one crosstalk coupling varies with frequency. The crosstalk couplings between the channels are added as a crosstalk coupling sum. Each modulation module is connected with the channels, and the at least one modulation module adjusts the at least one crosstalk coupling to decrease the crosstalk coupling sum according to the relation between the at least one crosstalk coupling and the other crosstalk couplings. | 2013-10-17 |
20130273778 | HIGH-SPEED CONNECTOR WITH CONDUCTIVE PLASTIC BLOCKS IN CONTACT WITH CONTACT SECTIONS OF SIGNAL TERMINALS - The connector has an insulating base, a plurality of terminals, and at least two conductive plastic blocks. The insulating base has a tongue plate configured with at least an indentation. The terminals contains a first signal terminal set, a second signal terminal set, and a power terminal set configured on the tongue plate. The terminals are either positive or negative terminals, and each terminal has a contact section. The contact sections of the first signal terminal set are configured at a distance above the indentation. The conductive plastic blocks are in contact with the contact sections of the negative terminals of the first and second signal terminal sets, respectively. The distance provides additional contact area with the air so that the electrical property is improved and higher transmission speed is achieved. The shielding effect of the conductive plastic blocks reduces cross interference between adjacent terminals. | 2013-10-17 |