42nd week of 2014 patent applcation highlights part 15 |
Patent application number | Title | Published |
20140306280 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - In the method, a plurality of gate structures may be formed on a substrate and be spaced apart from each other in a first direction. An insulation layer pattern may be formed by performing a chemical vapor deposition process using SiH | 2014-10-16 |
20140306281 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film. | 2014-10-16 |
20140306282 | MULTI LEVEL PROGRAMMABLE MEMORY STRUCTURE - A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer. | 2014-10-16 |
20140306283 | SUPERJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device that includes the following is manufactured: an n | 2014-10-16 |
20140306284 | Semiconductor Device and Method for Producing the Same - A trench gate MOS transistor is provided. It includes a semiconductor substrate with a trench including a gate electrode, a source region, a body contact region adjacent to a channel region, wherein the dopant concentration in the channel region varies in a lateral direction and has at least one minimal value in a direction from the gate electrode to the body contact region, which is distanced from the gate electrode. Further, a method for producing the transistor is provided. | 2014-10-16 |
20140306285 | SEMICONDUCTOR POWER DEVICE - Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer. | 2014-10-16 |
20140306286 | TAPERED FIN FIELD EFFECT TRANSISTOR - A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor. | 2014-10-16 |
20140306287 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor substrate, and a remaining portion thereof is insulated from the semiconductor substrate, gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated from the semiconductor substrate, and to surround a side and an upper surface of the active region, and having a stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer, a source region formed in the active region connected to the semiconductor substrate, and a drain region formed in the active region insulated from the semiconductor substrate between the gate structures. | 2014-10-16 |
20140306288 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided is a flexible device with fewer defects caused by a crack or a flexible device having high productivity. A semiconductor device including: a display portion over a flexible substrate, including a transistor and a display element; a semiconductor layer surrounding the display portion; and an insulating layer over the transistor and the semiconductor layer. When seen in a direction perpendicular to a surface of the flexible substrate, an end portion of the substrate is substantially aligned with an end portion of the semiconductor layer, and an end portion of the insulating layer is positioned over the semiconductor layer. | 2014-10-16 |
20140306289 | SELF-ALIGNED STRUCTURE FOR BULK FinFET - A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins. Also disclosed is a method for forming a FinFET device. | 2014-10-16 |
20140306290 | Dual Silicide Process Compatible with Replacement-Metal-Gate - In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s). | 2014-10-16 |
20140306291 | Dual Silicide Process Compatible with Replacement-Metal-Gate - In one aspect, a method for fabricating an electronic device includes the following steps. A wafer is provided having at least one first active area and at least one second active area defined therein. One or more p-FET/n-FET devices are formed in the active areas, each having a p-FET/n-FET gate stack and p-FET/n-FET source and drain regions. A self-aligned silicide is formed in each of the p-FET/n-FET source and drain regions, wherein the self-aligned silicide in each of the p-FET source and drain regions has a thickness T1 and the self-aligned silicide in each of the n-FET source and drain regions having a thickness T2, wherein T1 is less than T2. During a subsequent trench silicidation in the p-FET/n-FET source and drain regions, the trench silicide metal will diffuse through the thinner self-aligned silicide in the p-FET device(s) but not through the thicker self-aligned silicide in the n-FET device(s). | 2014-10-16 |
20140306292 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A first transistor includes a first impurity layer of a first conduction type formed in a first region of a semiconductor substrate, a first epitaxial semiconductor layer formed above the first impurity layer, a first gate insulating film formed above the first epitaxial semiconductor layer, a first gate electrode formed above the first gate insulating film, and first source/drain regions of a second conduction type formed in the first epitaxial semiconductor layer and in the semiconductor substrate in the first region. A second transistor includes a second impurity layer of the first conduction type formed in a second region of the semiconductor substrate, a second epitaxial semiconductor layer formed above the second impurity layer and being thinner than the first epitaxial semiconductor layer, a second gate insulating film formed above the second epitaxial semiconductor layer, a second gate electrode formed above the second gate insulating film, and second source/drain regions of the second conduction type formed in the second epitaxial semiconductor layer and in the semiconductor substrate in the second region. | 2014-10-16 |
20140306293 | SEMICONDUCTOR MEMORY DEVICE INCLUDING GUARD BAND - The semiconductor memory device including a first sense amplifier region including first metal-oxide-semiconductor (MOS) transistors disposed in a well on a semiconductor substrate, a second sense amplifier region adjacent to the well and including second MOS transistors disposed on the semiconductor substrate, a guard band having a bar type structure and provided between the first MOS transistors in the well, and a guard ring partially or fully enclosing the second sense amplifier region in the semiconductor substrate may be provided. | 2014-10-16 |
20140306294 | Gap Fill Self Planarization on Post EPI - The present disclosure relates to an integrated chip IC having transistors with structures separated by a flowable dielectric material, and a related method of formation. In some embodiments, an integrated chip has a semiconductor substrate and an embedded silicon germanium (SiGe) region extending as a positive relief from a location within the semiconductor substrate to a position above the semiconductor substrate. A first gate structure is located at a position that is separated from the embedded SiGe region by a first gap. A flowable dielectric material is disposed between the gate structure and the embedded SiGe region and a pre-metal dielectric (PMD) layer disposed above the flowable dielectric material. The flowable dielectric material provides for good gap fill capabilities that mitigate void formation during gap fill between the adjacent gate structures. | 2014-10-16 |
20140306295 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a substrate including a first region and a second region. The semiconductor device also includes first and second gate laminated bodies respectively formed on the first region and the second region, wherein the first gate laminated body includes a first gate insulating film that is in contact with the substrate and that includes a first high-k dielectric film; a first lower laminated body on the first gate insulating film; and a first upper laminated body on the first lower laminated body. The first lower laminated body includes a titanium nitride film, an aluminum film, and a titanium nitride film, laminated in sequence; and the second gate laminated body includes a second gate insulating film in contact with the substrate and including a second high-k dielectric film. Additionally, a second laminated body is formed on the second gate insulating film. | 2014-10-16 |
20140306296 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - In one embodiment, the semiconductor device includes at least one active fin protruding from a substrate, a first gate electrode crossing the active fin, and a first impurity region formed on the active fin at a first side of the first gate electrode. At least a portion of the first impurity region is formed in a first epitaxial layer portion on the active fin. A second impurity region is formed on the active fin at a second side of the first gate electrode. The second impurity region has at least a portion not formed in an epitaxial layer. | 2014-10-16 |
20140306297 | RECESSING STI TO INCREASE FIN HEIGHT IN FIN-FIRST PROCESS - A method includes forming a semiconductor fin over top surfaces of insulation regions, and forming a gate stack on a top surface and sidewalls of a middle portion of the semiconductor fin. The insulation regions include first portions overlapped by the gate stack, and second portions misaligned from the gate stack. An end portion of the semiconductor fin is etched to form a recess located between the second portions of the insulation regions. An epitaxy is performed to grow a source/drain region from the recess. After the epitaxy, a recessing is performed to recess the second portions of the insulation regions, with the second portions of the insulation regions having first top surfaces after the first recessing. A dielectric mask layer is formed on the first top surfaces of the second portions of the insulation regions. The dielectric mask layer further extends on a sidewall of the gate stack. | 2014-10-16 |
20140306298 | Semiconductor Device with Compensation Regions - A semiconductor device includes a semiconductor body including an inner region, and an edge region, a first doped device region of a first doping type in the inner region and the edge region and coupled to a first terminal, and at least one second doped device region of a second doping type complementary to the first doping type in the inner region and coupled to a second terminal. Further, the semiconductor device includes a minority carrier converter structure in the edge region. The minority carrier converter structure includes a first trap region of the second doping type adjoining the first doped device region, and a conductor electrically coupling the first trap region to the first doped device region. | 2014-10-16 |
20140306299 | MICROPHONE - A microphone has a base substrate comprising a main surface, an acoustic sensor mounted on the main surface, and a circuit element stacked on the acoustic sensor. A hollow space is formed between the acoustic sensor and the circuit element. The acoustic sensor has a sensor substrate having a first surface opposed to the base substrate, a second surface on a side opposite to the first surface, and a cavity formed while recessed with respect to the second surface, and a movable electrode that covers the cavity from the second surface side. A through-hole is formed in the base substrate while piercing the base substrate in a thickness direction. A communication hole is formed in the sensor substrate while piercing the sensor substrate from the first surface to the second surface. The communication hole causes the through-hole and the hollow space to communicate with each other. | 2014-10-16 |
20140306300 | Component and Method for Producing a Component - A micromechanical component formed from, a substrate ( | 2014-10-16 |
20140306301 | SILICON SUBSTRATE MEMS DEVICE - A MEMS device includes a silicon substrate. The silicon substrate includes a plurality of dielectric material grooves spaced apart from each other. The silicon substrate also includes a through hole with a portion of the through hole being located between the plurality of dielectric material grooves when viewed from a direction perpendicular to a surface of the silicon substrate. | 2014-10-16 |
20140306302 | Fully Compensated Synthetic Antiferromagnet for Spintronics Applications - A synthetic antiferromagnet serving as a reference layer for a magnetic tunnel junction is a laminate with a plurality of “x+1” magnetic sub-layers and “x” non-magnetic spacers arranged in an alternating fashion, with a magnetic sub-layer at the top and bottom of the laminated stack. Each spacer has a top and bottom surfaces that interface with adjoining magnetic sub-layers generating antiferromagnetic coupling between the adjoining sub-layers. Perpendicular magnetic anisotropy is induced in each magnetic sub-layer through an interface with a spacer. Thus the dipole field exerted on a free layer is substantially reduced compared with that produced by a conventional synthetic antiferromagnetic reference layer. Magnetic sub-layers are preferably Co while Ru, Rh, or Ir may serve as non-magnetic spacers. | 2014-10-16 |
20140306303 | Seed Layer for Perpendicular Magnetic Anisotropy (PMA) Thin Film - A magnetic thin film deposition having PMA (perpendicular magnetic anisotropy) is a multilayered fabrication of materials having differing crystal symmetries that smoothly transition by use of a seed layer that promotes symmetry matching. An interface between layers in the deposition, such as an interface between a layer of MgO and an Fe-containing ferromagnetic layer, is a source of perpendicular magnetic anisotropy which then propagates throughout the remainder of the deposition by means of the symmetry matching seed layer. | 2014-10-16 |
20140306304 | METHOD TO MAKE INTEGRATED DEVICE USING OXYGEN ION IMPLANTATION - A method to make magnetic random access memory (MRAM), or integrated device in general, is provided. Oxygen ion implantation is used to convert the photolithography exposed areas into metal oxide dielectric matrix. To confine the oxygen ions within the desired region, heavy metals with large atomic number, such as Hf, Ta, W, Re, Os, Ir, Pt, Au is used as ion mask and bottom ion-stopping layer. An oxygen gettering material, selected from Mg, Zr, Y, Th, Ti, Al, Ba is added above and below the active device region to effectively capture the impinging oxygen. After a high temperature anneal, a buried metal oxide layer with sharp oxygen boundaries across the active device region can be obtained. | 2014-10-16 |
20140306305 | Magnetic Tunnel Junction for MRAM Applications - A MTJ in an MRAM array is disclosed with a composite free layer having a lower crystalline layer contacting a tunnel barrier and an upper amorphous NiFeX layer for improved bit switching performance. The crystalline layer is Fe, Ni, or FeB with a thickness of at least 6 Angstroms which affords a high magnetoresistive ratio. The X element in the NiFeX layer is Mg, Hf, Zr, Nb, or Ta with a content of 5 to 30 atomic %. NiFeX thickness is preferably between 20 to 40 Angstroms to substantially reduce bit line switching current and number of shorted bits. In an alternative embodiment, the crystalline layer may be a Fe/NiFe bilayer. Optionally, the amorphous layer may have a NiFeM | 2014-10-16 |
20140306306 | PROTECTIVE INSULATING LAYER AND CHEMICAL MECHANICAL POLISHING FOR POLYCRYSTALLINE THIN FILM SOLAR CELLS - A method for forming a photovoltaic device includes forming an absorber layer with a granular structure on a conductive layer; conformally depositing an insulating protection layer over the absorber layer to fill in between grains of the absorber layer; and planarizing the protection layer and the absorber layer. A buffer layer is formed on the absorber layer, and a top transparent conductor layer is deposited over the buffer layer. | 2014-10-16 |
20140306307 | BACKSIDE NANOSCALE TEXTURING TO IMPROVE IR RESPONSE OF SILICON SOLAR CELLS AND PHOTODETECTORS - The absorption coefficient of silicon for infrared light is very low and most solar cells absorb very little of the infrared light energy in sunlight. Very thick cells of crystalline silicon can be used to increase the absorption of infrared light energy but the cost of thick crystalline cells is prohibitive. The present invention relates to the use of less expensive microcrystalline silicon solar cells and the use of backside texturing with diffusive scattering to give a very large increase in the absorption of infrared light. Backside texturing with diffusive scattering and with a smooth front surface of the solar cell results in multiple internal reflections, light trapping, and a large enhancement of the absorption of infrared solar energy. | 2014-10-16 |
20140306308 | Wafer-Level Array Cameras And Methods For Fabricating The Same - A wafer-level array camera includes (i) an image sensor wafer including an image sensor array, (ii) a spacer disposed on the image sensor wafer, and (iii) a lens wafer disposed on the spacer, wherein the lens wafer includes a lens array. A method for fabricating a plurality of wafer-level array cameras includes (i) disposing a lens wafer, including a plurality of lens arrays, on an image sensor wafer, including a plurality of image sensor arrays, to form a composite wafer and (ii) dicing the composite wafer to form the plurality of wafer-level array cameras, wherein each of the plurality of wafer-level array cameras includes a respective one of the plurality of lens arrays and a respective one of the plurality of image sensor arrays. | 2014-10-16 |
20140306309 | PHOTOELECTRIC CONVERSION APPARATUS - A photoelectric conversion apparatus includes a semiconductor substrate having a photoelectric conversion portion. An insulator is provided on the semiconductor substrate. The insulator has a hole corresponding to the photoelectric conversion portion. A waveguide member is provided in the hole. An in-layer lens is provided on a side of the waveguide member farther from the semiconductor substrate. A first intermediate member is provided between the waveguide member and the in-layer lens. The first intermediate member has a lower refractive index than the in-layer lens. | 2014-10-16 |
20140306310 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes: a solid-state imaging device photoelectrically converting light taken by a lens; and a light shielding member shielding part of light incident on the solid-state imaging device from the lens, wherein an angle made between an edge surface of the light shielding member and an optical axis direction of the lens is larger than an incident angle of light to be incident on an edge portion of the light shielding member. | 2014-10-16 |
20140306311 | SOLID-STATE IMAGING ELEMENT - Provided is a solid-state imaging element for effectively reducing a dark current. The solid-state imaging element includes a substrate | 2014-10-16 |
20140306312 | MEMS Sensor Packaging and Method Thereof - A micro electro mechanical systems (MEMS sensor packaging includes a first wafer having a readout integrated circuit (ROIC) formed thereon., a second wafer disposed corresponding to the first wafer and having a concave portion on one side thereof and a MEMS sensor prepared on the concave portion, joint solders formed along a surrounding of the MEMS sensor and sealing the MEMS sensor jointing the first and second wafers, and pad solders formed to electrically connect the ROIC circuit of the first wafer and the MEMS sensor of the second wafer. According to the present disclosure, in joining and packaging a wafer having the ROIC formed thereon and a wafer having the MEMS sensor formed thereon, the size of a package can be reduced and an electric signal can be stably provided by forming internally pad solders for electrically connecting the ROIC and the MEMS sensor. | 2014-10-16 |
20140306313 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR, AND ELECTRONIC APPARATUS - A semiconductor device includes: a first semiconductor chip; and a second semiconductor chip that is stacked on the first semiconductor chip. The first semiconductor chip includes a first wiring portion of which a side surface is exposed at a side portion of the first semiconductor chip. The second semiconductor chip includes a second wiring portion of which a side surface is exposed at a side portion of the second semiconductor chip. The respective side surfaces of the first wiring portion and the second wiring portion, which are exposed at the side portions of the first semiconductor chip and the second semiconductor chip, are covered by a conductive layer, and the first wiring portion and the second wiring portion are electrically connected to each other through the conductive layer. | 2014-10-16 |
20140306314 | PHOTODIODE ARRAY - A light receiving region includes a plurality of light detecting sections | 2014-10-16 |
20140306315 | ENHANCED ELECTRON MOBILITY AT THE INTERFACE BETWEEN GD2O3(100)/N-SI(100) - A multilayered structure is provided. The multilayered structure may include a silicon substrate and a film of gadolinium oxide disposed on the silicon substrate. The top surface of the silicon substrate may have silicon orientated in the 100 direction (Si(100)) and the gadolinium oxide disposed thereon may have an orientation in the 100 direction (Gd | 2014-10-16 |
20140306316 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface. The method further includes removing the sacrificial layer so that the second insulator remains, after the first and second interconnects are formed. | 2014-10-16 |
20140306317 | FINFET FIN HEIGHT CONTROL - Fin height control techniques for FINFET fabrication are disclosed. The technique includes a method for controlling the height of plurality of fin structures to achieve uniform height thereof relative to a top surface of isolation material located between fin structures on a semiconductor substrate. The isolation material located between fin structures may be selectively removed after treatment to increase its mechanical strength such as by, for example, annealing and curing. A sacrificial material may be deposited over the isolation material between the fin structures in a substantially uniform thickness. The top portion of the fin structures may be selectively removed to achieve a uniform planar surface over the fin structures and sacrificial material. The sacrificial material may then be selectively removed to achieve a uniform fin height relative to the isolation material. | 2014-10-16 |
20140306318 | TRENCH FORMATION METHOD AND A SEMICONDUCTOR STRUCTURE THEREOF - In one embodiment, a method of making a trench for a semiconductor device can include: (i) providing a semiconductor substrate; (ii) forming a patterned hard mask layer with an opening on the semiconductor substrate, where a thickness of the patterned hard mask layer is from about 100 nm to about 400 nm; and (iii) using the patterned hard mask layer as a mask, and etching the semiconductor substrate to form the trench in the semiconductor substrate. | 2014-10-16 |
20140306319 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - There are included: forming element isolation regions in a semiconductor substrate; introducing a first impurity of a first conductivity type, to thereby form a first well, and a second well of the first conductivity type; introducing a second impurity of a second conductivity type, to thereby form a third well of the second conductivity type and introducing the second impurity into a region between the first well and the second well, to thereby form a separation well of the second conductivity type; and further introducing a third impurity of the second conductivity type into the region between the first well and the second well. | 2014-10-16 |
20140306320 | METHODS OF FABRICATING SEMICONDUCTOR STRUCTURES OR DEVICES USING LAYERS OF SEMICONDUCTOR MATERIAL HAVING SELECTED OR CONTROLLED LATTICE PARAMETERS - Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature. | 2014-10-16 |
20140306321 | SEMICONDUCTOR DEVICE FABRICATION METHOD AND SEMICONDUCTOR DEVICE - There is provided a method of fabricating a semiconductor device, the method including: forming a semiconductor component portion at a first surface of a substrate; applying a grinding treatment to a second surface of the substrate that is opposite from the first surface to form a fracture surface; applying a fracture surface removal treatment to predetermined positions of the fracture surface of the second surface; and forming an electrode at the second surface. | 2014-10-16 |
20140306322 | RELIABLE BACK-SIDE-METAL STRUCTURE - A semiconductor structure, method of manufacturing the same and design structure thereof are provided. The semiconductor structure includes a substrate including a semiconductor layer and a plurality of TSVs embedded therein. At least one TSV has a TSV tip extending from a backside surface of the substrate. The semiconductor structure further includes a multilayer metal contact structure positioned on the backside surface of the substrate. The multilayer metal contact structure includes at least a conductive layer covering the backside surface of the substrate and covering protruding surfaces of the TSV tip. The conductive layer has a non-planar first surface and a substantially planar second surface opposite of the first surface. | 2014-10-16 |
20140306323 | Semiconductor Constructions - Some embodiments include semiconductor constructions having semiconductor material patterned into two mesas spaced from one another by at least one dummy projection. The dummy projection has a width along a cross-section of X and the mesas have widths along the cross-section of at least 3X. Some embodiments include semiconductor constructions having a memory array region and a peripheral region adjacent the memory array region. Semiconductor material within the peripheral region is patterned into two relatively wide mesas spaced from one another by at least one relatively narrow projection. The relatively narrow projection has a width along a cross-section of X and the relatively wide mesas have widths along the cross-section of at least 3X. | 2014-10-16 |
20140306324 | SEMICONDUCTOR DEVICE WITH A POLYMER SUBSTRATE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a semiconductor stack structure having a first surface and a second surface. A polymer substrate having a high thermal conductivity and a high electrical resistivity is disposed onto the first surface of the semiconductor stack structure. One method includes providing the semiconductor stack structure with the first surface in direct contact with a wafer handle. A next step involves removing the wafer handle to expose the first surface of the semiconductor stack structure. A following step includes disposing a polymer substrate having high thermal conductivity and high electrical resistivity directly onto the first surface of the semiconductor stack structure. | 2014-10-16 |
20140306325 | COMPENSATION FOR A CHARGE IN A SILICON SUBSTRATE - A silicon device includes an active silicon layer, a buried oxide (BOX) layer beneath the active silicon layer and a high-resistivity silicon layer beneath the BOX layer. The device also includes a harmonic suppression layer at a boundary of the BOX layer and the high-resistivity silicon layer. | 2014-10-16 |
20140306326 | Tunable Semiconductor Component Provided with a Current Barrier - Semiconductor component or device is provided which includes a current barrier element and for which the impedance may be tuned (i.e. modified, changed, etc.) using a focused heating source. | 2014-10-16 |
20140306327 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes a device carrier and a semiconductor chip attached to the device carrier. Further, the semiconductor device includes a lid having a recess. The lid includes a semiconductor material and is attached to the device carrier such that the semiconductor chip is accommodated in the recess. | 2014-10-16 |
20140306328 | SEMICONDUCTOR DEVICE - The semiconductor device includes a semiconductor element, a main lead and a resin package. The semiconductor element includes an obverse surface and a reverse surface spaced apart from each other in a thickness direction. The main lead supports the semiconductor element via the reverse surface of the semiconductor element. The resin package covers the entirety of the semiconductor element. The resin package covers the main lead in such a manner that a part of the main lead is exposed from the resin package. The semiconductor element includes a part that does not overlap the main lead as viewed in the thickness direction. | 2014-10-16 |
20140306329 | SEMICONDUCTOR PACKAGE - A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing 98 wt % or more of one metallic element such as silver having a melting point of 400° C. or higher, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members. | 2014-10-16 |
20140306330 | Low Profile Leaded Semiconductor Package - In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. | 2014-10-16 |
20140306331 | CHIP AND CHIP ARRANGEMENT - Various embodiments provide a chip. The chip may include a body having two main surfaces and a plurality of side surfaces; a first power electrode extending over at least one main surface and at least one side surface of the body; and a second power electrode extending over at least one main surface and at least one side surface of the body. | 2014-10-16 |
20140306332 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A packaged multi-output converter ( | 2014-10-16 |
20140306333 | CAVITY PACKAGE WITH DIE ATTACH PAD - A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer. | 2014-10-16 |
20140306334 | SEMICONDUCTOR PACKAGE - A semiconductor package, wherein, in bonding of members constituting the semiconductor package, by using bonding layers containing copper and a low-melting-point metal such as tin, the bonding is performed in a temperature range where the occurrence of warpage or distortion of the members is suppressed, and after the bonding, a high melting point is obtained; and by configuring the members so that all the surfaces of the members which become bonding surfaces of bonding layers are parallel to each other, all the thickness directions of the bonding layers are aligned to be in the same direction, and during the formation of the bonding layers, the pressing direction is set to be one-way direction which is the direction of laminating the members. | 2014-10-16 |
20140306335 | THERMAL MANAGEMENT FOR SOLID-STATE DRIVE - An electronic device including a printed circuit board (PCB) including a thermal conduction plane and at least one heat generating component mounted on the PCB and connected to the thermal conduction plane. A frame is connected to the PCB so as to define a first thermally conductive path between at least a portion of the frame and the at least one heat generating component. The electronic device further includes at least one thermally conductive layer between the frame and the at least one heat generating component so as to define a second thermally conductive path between at least a portion of the frame and the at least one heat generating component. | 2014-10-16 |
20140306336 | FLUID COOLED SEMICONDUCTOR DIE PACKAGE - A fluid cooled semiconductor die package includes a package support substrate with a die mounting surface and an opposite package mounting surface. The package support substrate has external connector solder deposits on respective external connector pads of the package mounting surface, and a package fluid inlet duct and a package fluid outlet duct each providing fluid communication between the die mounting surface and package mounting surface. A semiconductor die is mounted on the die mounting surface. The die has external terminals electrically connected to the external connector pads. An inlet solder deposit is soldered to an inlet pad of the package mounting surface. The inlet pad surrounds an entrance of the fluid inlet duct. An outlet solder deposit is soldered to an outlet pad of the package mounting surface. The outlet pad surrounds an exit of the package fluid inlet duct. | 2014-10-16 |
20140306337 | SEMICONDUCTOR DEVICE HAVING A BUFFER MATERIAL AND STIFFENER - Semiconductor devices are described that include a semiconductor device having multiple, stacked die on a substrate (e.g., a semiconductor wafer). In one or more implementations, wafer-level package devices that employ example techniques in accordance with the present disclosure include an ultra-thin semiconductor wafer with metallization and vias formed in the wafer and an oxide layer on the surface of the wafer, an integrated circuit chip placed on the semiconductor wafer, an underfill layer between the integrated circuit chip and the semiconductor wafer, a buffer material formed on the semiconductor wafer, the underfill layer, and at least one side of the integrated circuit chip, an adhesive layer placed on the buffer layer and the integrated circuit chip, and a stiffener layer placed on the adhesive layer. The semiconductor device may then be segmented into individual semiconductor chip packages. | 2014-10-16 |
20140306338 | DIE-DIE STACKING STRUCTURE AND METHOD FOR MAKING THE SAME - The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer. The structure and method of present invention at least provide more strength and stress buffer to resist die warpage and absorb thermal cycling stress, and then prevents the bump and dielectric materials in the die-die stacking structure from cracking caused by thermal stress or external mechanical stress. | 2014-10-16 |
20140306339 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion. | 2014-10-16 |
20140306340 | PACKAGE STRUCTURE HAVING EMBEDDED ELECTRONIC COMPONENT - A package structure having an embedded electronic component includes: a carrier having a cavity penetrating therethrough; a semiconductor chip received in the cavity and having solder bumps disposed thereon; a dielectric layer formed on the carrier and the semiconductor chip so as to encapsulate the solder bumps; a wiring layer formed on the dielectric layer; an insulating protection layer formed on the dielectric layer and the wiring layer; and a solder material formed in the dielectric layer and the insulating protection layer for electrically connecting the wiring layer and the solder bumps, thereby shortening the signal transmission path between the semiconductor chip and the carrier to avoid signal losses. | 2014-10-16 |
20140306341 | 3D Packages and Methods for Forming the Same - Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a semiconductor device, the method comprising forming a conductive pad in a first substrate, forming an interconnecting structure over the conductive pad and the first substrate, the interconnecting structure comprising a plurality of metal layers disposed in a plurality of dielectric layers, bonding a die to a first side of the interconnecting structure, and etching the first substrate from a second side of the interconnecting structure, the etching exposing a portion of the conductive pad. | 2014-10-16 |
20140306342 | SEMICONDUCTOR DEVICE, HAVING THROUGH ELECTRODES, A MANUFACTURING METHOD THEREOF, AND AN ELECTRONIC APPARATUS - A semiconductor device includes a semiconductor substrate and a through electrode provided in a through hole formed in the semiconductor substrate. The through electrode partially protrudes from a back surface of the semiconductor substrate, which is opposite to an active surface thereof. The through electrode includes a resin core and a conductive film covering at least a part of the resin core. | 2014-10-16 |
20140306343 | CHIP PACKAGE AND METHOD FOR FABRICATING THE SAME - A chip package is provided, in which includes: a packaging substrate, a chip and a plurality solder balls interposed between the packaging substrate and the chip for bonding the packaging substrate and the chip, wherein the solder balls include a first portion of a first size and a second portion of a second size that is different from the first size. | 2014-10-16 |
20140306344 | WIRING STRUCTURE, SEMICONDUCTOR DEVICE INCLUDING WIRING STRUCTURE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is provided with a wiring structure. The wiring stracture has a damascene wiring structure including a metal wiring. The metal wiring is provided in direct contact with an upper surface of a barrier film (SiC(O, N) film) containing silicon (Si), carbon (C), and at least one of oxygen (O) and nitrogen (N) as constituent components. | 2014-10-16 |
20140306345 | SEMICONDUCTOR DEVICE INCLUDING COPPER WIRING AND VIA WIRING HAVING LENGTH LONGER THAN WIDTH THEREOF AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a first interconnect formed over the semiconductor substrate. An interlayer dielectric film is formed over the first interconnect, and a hole is formed in the interlayer dielectric film such that the hole reaches the first interconnect. A trench is formed in the interlayer dielectric film, and a conductive film is embedded in the hole and the trench, thereby a via is formed in the hole and a second interconnect in the trench. In a planar view, the first interconnect extends in a first direction, the second interconnect extends in a second direction which is perpendicular to the first direction, and a maximum width of the via in the second direction is larger than a maximum width of the via in the first direction. | 2014-10-16 |
20140306346 | SEMICONDUCTOR DEVICE HAVING GROOVE-SHAPED VIA-HOLE - The semiconductor device has insulating films | 2014-10-16 |
20140306347 | Semiconductor Device with an Insulation Layer Having a Varying Thickness - A layer with a laterally varying thickness, a substrate with a first surface and an insulation layer formed on the first surface of the substrate is provided. A plurality of at least one of recesses and openings is formed in the insulation layer, wherein the plurality is arranged at a pitch. Each of the at least one of recesses and openings has a lateral width, wherein at least one of the pitch and the lateral width varies in a lateral direction. The plurality of the at least one of recesses and openings defines a given region in the insulation layer. The insulation layer having the plurality of the at least one of the recesses and openings is tempered at elevated temperatures so that the insulation layer at least partially diffluences to provide the insulation layer with a laterally varying thickness at least in the given region. | 2014-10-16 |
20140306348 | CHIP ON FILM AND DISPLAY DEVICE HAVING THE SAME - A flexible chip on film includes a base insulating layer, a metal layer disposed on an upper surface of the base insulating layer and including a circuit pattern, an integrated circuit chip disposed on an upper surface of the metal layer and electrically connected to the metal layer, a solder resist layer disposed on the metal layer and insulated from the integrated circuit chip, and a reinforcing layer disposed on an upper surface of the solder resist layer. When the chip on film COF is bent, a neutral surface, in which a vector sum of a tensile force and a compressive force becomes substantially zero, is placed in the metal layer. | 2014-10-16 |
20140306349 | LOW COST INTERPOSER COMPRISING AN OXIDATION LAYER - Some implementations provide an interposer that includes a substrate, a via in the substrate, and an oxidation layer. The via includes a metal material. The oxidation layer is between the via and the substrate. In some implementations, the substrate is a silicon substrate. In some implementations, the oxidation layer is a thermal oxide formed by exposing the substrate to heat. In some implementations, the oxidation layer is configured to provide electrical insulation between the via and the substrate. In some implementations, the interposer also includes an insulation layer. In some implementations, the insulation layer is a polymer layer. In some implementations, the interposer also includes at least one interconnect on the surface of the interposer. The at least one interconnect is positioned on the surface of the interposer such that the oxidation layer is between the interconnect and the substrate. | 2014-10-16 |
20140306350 | METHOD OF MANUFACTURING THROUGH-GLASS VIAS - A method of forming a through-glass via hole involves providing a glass substrate having first and second substantially planar parallel surfaces; masking the first and second substantially planar parallel surfaces to form a via-patterned portion thereon; and etching the via-patterned portion on the first and second substantially planar parallel surfaces to form a first channel in the first substantially planar parallel surface and a second channel in the second substantially planar parallel surface. The first channel and second channel are substantially orthogonal or non-orthogonal to one another. The first channel and the second channel intersect to form a quadrilateral through-glass via hole having via openings at the first and second substantially planar parallel surfaces. A low cost, low complexity and high reliability method for producing a glass substrate having a plurality of through-glass via holes such that the glass substrate can be used, for example, as an interposer. | 2014-10-16 |
20140306351 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device and a semiconductor device formed by the method. The method includes form a stack conductive structure by stacking a first conductive pattern and an insulation pattern over a substrate; forming a sacrificial pattern over sidewalls of the stack conductive structure; forming a second conductive pattern having a recessed surface lower than a top surface of the stack conductive structure; forming a sacrificial spacer to expose sidewalls of the insulation pattern by removing an upper portion of the sacrificial pattern; reducing a width of the exposed portion of the insulation patters; forming a capping spacer to cap the sidewalls of the insulation pattern having the reduced width over the sacrificial spacer; and forming an air gap between the first conductive pattern and the second conductive pattern by converting the sacrificial spacer to volatile byproducts | 2014-10-16 |
20140306352 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide semiconductor devices and fabrication methods. In an exemplary method, a dielectric layer can be formed on a semiconductor substrate. A plurality of pillar structures having a matrix arrangement can be formed on the dielectric layer. A plurality of sidewall spacers can be formed on the dielectric layer. Each sidewall spacer can be formed on a sidewall surface of one of the plurality of pillar structures. A distance between adjacent pillar structures in a same row or in a same column can be less than or equal to a double of a thickness of the each sidewall spacer on the sidewall surface. The plurality of pillar structures can be removed. The dielectric layer can be etched using the plurality of sidewall spacers as an etch mask to form a plurality of trenches or through holes in the dielectric layer. | 2014-10-16 |
20140306353 | 3D MEMORY ARRAY - A 3-D memory is provided. Each word line layer has word lines and gaps alternately arranged along a first direction. Gaps include first group and second group of gaps alternately arranged. A first bit line layer is on word line layers and has first bit lines along a second direction. A first conductive pillar array through word line layers connects the first bit line layer and includes first conductive pillars in first group of gaps. A first memory element is between a first conductive pillar and an adjacent word line. A second bit line layer is below word line layers and has second bit lines along the second direction. A second conductive pillar array through word line layers connects the second bit line layer and includes second conductive pillars in second group of gaps. A second memory element is between a second conductive pillar and an adjacent word line. | 2014-10-16 |
20140306354 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a package substrate. A first semiconductor chip is mounted on the package substrate. The first semiconductor chip includes a first chip region and first chip pads formed on a top surface of the first chip region. A second semiconductor chip is mounted on the package substrate. The second semiconductor chip includes a second chip region and second chip pads formed on a top surface of the second chip region. A boundary region having a groove divides the first chip region and the second chip region. The first chip region, the second chip region and the boundary region share a semiconductor substrate of a one-body type. | 2014-10-16 |
20140306355 | CHIP INTERPOSER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad may face in the same direction as the first pad. | 2014-10-16 |
20140306356 | ARRANGEMENT HAVING A PLURALITY OF CHIPS AND A CHIP CARRIER, AND A PROCESSING ARRANGEMENT - In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess. | 2014-10-16 |
20140306357 | DICING DIE-BONDING FILM AND METHOD OF FORMING A CUT ON THE DICING DIE-BONDING FILM - A dicing die-bonding film and a method of forming a groove in a dicing die-bonding film, the film including a base film; a pressure-sensitive adhesive layer stacked on the base film; and a bonding layer stacked on the pressure-sensitive adhesive layer, wherein the pressure-sensitive adhesive layer includes a first region overlapping with the bonding layer, and a second region not overlapping with the bonding layer, the second region including a third region adjacent to the first region, and a fourth region adjacent to the third region and having a groove formed therein. | 2014-10-16 |
20140306358 | ACCELERATOR DEVICE FOR A CARBURETOR - In at least one implementation a carburetor includes an intake bore with a port opening into the intake bore, a fuel chamber from which fuel is supplied to the intake bore, and an accelerator device including a fuel reservoir. A fuel flow control valve is provided between the fuel chamber and the port to control the flow rate of fuel to the port and at least one passage communicates the fuel reservoir with the port and fuel in the fuel reservoir is supplied to the port therethrough. The passage also communicates the fuel reservoir with the fuel chamber. The fuel flow control valve is located between the fuel reservoir and the port and between the fuel chamber and the port, and the passage includes a portion extending between the fuel reservoir and the fuel chamber independently of the fuel flow control valve. | 2014-10-16 |
20140306359 | Simplified Fuel Cell Humidifier Design - A fuel cell humidifier with a pleated separation layer between a wet side and a dry side is provided. The fuel cell humidifier includes an enclosure having a first inlet, first outlet, and a first gas flow region that allow flow of a first gas through the humidifier. The fuel cell humidifier also includes a second inlet and second outlet, and a second gas flow region that allow flow of a second gas through the humidifier. Characteristically, the first gas has a higher relative humidity than the second gas. A pleated diffusion medium separates the first flow region and the second flow region such that water from the first gas flows to the second gas thereby increasing the relative humidity of the second gas. | 2014-10-16 |
20140306360 | METHOD OF FORMING DUAL SIZE MICROLENSES FOR IMAGE SENSORS - A method of forming microlenses for an image sensor having at least one large-area pixel and at least one small-area pixel is disclosed. The method includes forming a uniform layer of microlens material on a light incident side of the image sensor over the large-area pixel and over the small-area pixel. The method also includes forming the layer of microlens material into a first block disposed over the large-area pixel and into a second block disposed over the small-area pixel. A void is also formed in the second block to reduce a volume of microlens material included in the second block. The first and second blocks are then reflowed to form a respective first microlens and second microlens. The first microlens has substantially the same effective focal length as the second microlens. | 2014-10-16 |
20140306361 | OPHTHALMIC LENS ASSEMBLY HAVING AN INTEGRATED ANTENNA STRUCTURE - Antennas and antenna systems may be designed and configured for incorporation into mechanical devices, including medical devices, such as ophthalmic devices, including contact lenses. These antennas and antenna systems may be utilized to transmit data from the mechanical device to a receiver, to receive data from a transmitter, and/or to inductively charge an electromechanical cell or the like incorporated into the mechanical device. | 2014-10-16 |
20140306362 | METHOD FOR MANUFACTURING LIGHT-GUIDE DEVICE - A method for manufacturing a light-guide device includes: obtaining a substrate having a flow passage; providing inkjet printing equipment having a liquid jetting head apparatus; and injecting an optical wave guide micro-droplet into the flow passage by using the liquid jetting head apparatus of the inkjet printing equipment, to form a light-guide device in the flow passage. | 2014-10-16 |
20140306363 | PROCESS FOR PREPARING BICOMPONENT FIBERS COMPRISING POLY(TRIMETHYLENE TEREPHTHALATE) - Disclosed is a process for preparing crimpable bicomponent fibers from two poly(trimethylene terephthalate) starting materials that differ from one another in intrinsic viscosity. One starting material is characterized by an intrinsic viscosity ≦0.7 dL/g. The relatively low intrinsic viscosity allows the employment of a low melt temperature, with concomitant reduction in the evolution of acrolein, and without significant degradation in the properties or processibility of the bicomponent fiber. | 2014-10-16 |
20140306364 | CONTROLLED CHEMICAL STABILIZATION OF POLYVINYL PRECURSOR FIBER, AND HIGH STRENGTH CARBON FIBER PRODUCED THEREFROM - Method for the preparation of carbon fiber, which comprises: (i) immersing functionalized polyvinyl precursor fiber into a liquid solution having a boiling point of at least 60° C.; (ii) heating the liquid solution to a first temperature of at least 25° C. at which the functionalized precursor fiber engages in an elimination-addition equilibrium while a tension of at least 0.1 MPa is applied to the fiber; (iii) gradually raising the first temperature to a final temperature that is at least 20° C. above the first temperature and up to the boiling point of the liquid solution for sufficient time to convert the functionalized precursor fiber to a pre-carbonized fiber; and (iv) subjecting the pre-carbonized fiber produced according to step (iii) to high temperature carbonization conditions to produce the final carbon fiber. Articles and devices containing the fibers, including woven and non-woven mats or paper forms of the fibers, are also described. | 2014-10-16 |
20140306365 | INDIVIDUAL CAVITY FLOW CONTROL METHODS AND SYSTEMS FOR CO-INJECTION MOLDING - Methods and systems for co-extruding multiple polymeric material flow streams into a mold having a plurality of cavities to produce a plurality of multi-layer polymeric articles each having a consistent coverage of an interior core layer are disclosed herein. In an example method, a flow rate of a first skin material into a cavity is individually controlled for each cavity before initiation of co-injection of a second core material into the cavity, which may address inconsistent interior core layer coverage for articles from different cavities. | 2014-10-16 |
20140306366 | MOLDING DIE AND MOLDING METHOD - A molding die for molding a foam molding in a cavity constituted in the interior by matching a stationary die and a movable die, the cavity being able to be filled with molten resin, and the foam molding being produced using counter-pressure. A seal material for sealing the pressurization area for the counter pressure technique between the stationary die and the movable die is provided to the molding die, and the seal material is constituted of an elastic foam that has open cells. | 2014-10-16 |
20140306367 | MANUFACTURING METHOD OF AN ECO FRIENDLY FOAMING PACKAGE MATERIAL - A manufacturing method of an eco friendly foam package material includes a raw material mixing step for mixing raw materials uniformly and thoroughly to form a mixed raw material, a raw material hybrid-melting step for performing a hybrid-melting process to form a hybrid-melted material, a particle forming step for performing the particle forming process by putting the hybrid-melted material into a pelletizer to form plastic particles, and a foam extrusion step. In the foam extrusion step the plastic particles are melted to become a gelatinous state material, and foamed with non-chemical method. Since the properties of the biodegradable polymer are changed by the decomposition enzyme, and further to mix with bio-cellulose and the industrial starch, such that the eco friendly foam package material with compostability is obtained. | 2014-10-16 |
20140306368 | Method for Producing a Semiconductor Using a Vacuum Furnace - A method of manufacturing a semiconductor includes providing a mold defining a planar capillary space; placing a measure of precursor in fluid communication with the capillary space; creating a vacuum around the mold and within the planar capillary space; melting the precursor; allowing the melted precursor to flow into the capillary space; and cooling the melted precursor within the mold such that the precursor forms a semiconductor, the operations of melting the precursor, allowing the precursor to flow into the capillary space, and cooling the melted precursor occurring in the vacuum. | 2014-10-16 |
20140306369 | BENEFICIATION OF FLY ASH - A method of beneficiating fly ash to produce particulate material for use as a filler/extender in plastics manufacturing. The method includes removal of extraneous surface deposits from surfaces of the particulate material. | 2014-10-16 |
20140306370 | MIXING SEGMENTS FOR AN EXTRUSION APPARATUS AND METHODS OF MANUFACTURING A HONEYCOMB STRUCTURE - A mixing segment for an extrusion apparatus comprises a shaft and a plurality of plow elements aligned along a helical path extending about a rotation axis of the shaft. Each plow element includes an outer peripheral arcuate ramp extending radially outwardly along the helical path from a root to an outer tip of the plow element. Methods of manufacturing a mixing segment and methods of manufacturing a honeycomb structure with an extrusion apparatus are also provided. | 2014-10-16 |
20140306371 | DEVICES AND METHODS FOR PRODUCING PLANAR POLYMERIC MATERIALS USING MICROFLUIDICS - Methods and devices are disclosed for providing the controlled formation of planar homogeneous or heterogeneous materials using microfluidic devices. In one embodiment, a planar array of microfluidic channels is employed to produce a flowing liquid sheet having heterogeneous structure by spatially and temporally controlling dispensing of polymer liquid from selected microchannels. The resulting liquid sheet is solidified to produce a planar heterogeneous material that may be continuously drawn and/or fed from the plurality of microfluidic channels. The polymer liquid may include a payload that may be selectively incorporated into the heterogeneous structure. In some embodiments, the local material composition is controllable, thereby allowing control over local and bulk material properties, such as the permeability and the elasticity, and of creating materials with directionally dependent properties. | 2014-10-16 |
20140306372 | Method And Apparatus For Producing A Fiber-Reinforced Plastics Casting - An apparatus and method for producing a fiber-reinforced plastics casting (FRP), includes a moulding box filled with free flowing moulding material, in what a prototype of casting or a textile preform is inserted, forming a mould cavity for infiltration the inserted preform of textile with synthetic resin material in order to form a fiber-reinforced plastics casting (FRP). | 2014-10-16 |
20140306373 | APPARATUS AND METHOD FOR VOLUMETRIC REDUCTION OF POLYMERIC MATERIAL - The present invention is an apparatus and method for volumetric reduction of polymeric material and in particular synthetic polymeric textile materials. Such materials are typically used in hospital operating rooms and have material memory meaning that they re-expand after compression. Consequently they are difficult to process as waste material. The present invention is a method and apparatus for thermally compacting a polymer comprising a first and second heated surface inclined downwardly towards each other and providing with a passage at their lower ends through which melted polymeric material may pass. | 2014-10-16 |
20140306374 | Method for Arranging Engagement Means in a Concrete Part - A method for arranging engagement means in a concrete body. These engagement means can come into contact with securing means, resulting in a coupling of considerable strength between the concrete part and the securing means. The engagement means may comprise a screw thread, bayonet-like structure or the like arranged in the concrete. However, it is also possible for the engagement means to be designed as a separate component which is placed into the concrete material. This separate component is then provided with the engagement means proper in that it is provided with a screw thread, bayonet catch or the like. In this way, it is possible to secure construction parts to the concrete part, to hoist the concrete part and to carry out further actions with this part. It is also possible to adjust the concrete part with the aid of adjustment bolts which engage in the engagement means. | 2014-10-16 |
20140306375 | RESIN MOLD - Described is a resinous structure derived from fluorine-containing polymers useful as a mold having excellent dimensional stability. | 2014-10-16 |
20140306376 | PRODUCTION APPARATUS AND A METHOD FOR MANUFACTURING ELONGATED PRODUCTS SUCH AS WIND TURBINE BLADES - An apparatus comprising elongated first and second moulds ( | 2014-10-16 |
20140306377 | TOOL TEMPERATURE CONTROL - A tool element assembly ( | 2014-10-16 |
20140306378 | HYBRID STENT AND METHOD OF MAKING - A stent is formed by encasing or encapsulating metallic rings in an inner polymeric layer and an outer polymeric layer. At least one polymer link connects adjacent metallic rings. The stent is drug loaded with one or more therapeutic agent or drug, for example, to reduce the likelihood of the development of restenosis in the coronary arteries. The inner and outer polymeric materials can be of the same polymer or different polymer to achieve different results, such as enhancing flexibility and providing a stent that is visible under MRI, computer tomography and x-ray fluoroscopy. | 2014-10-16 |
20140306379 | DEVICE FOR CONSTRUCTING MODELS IN LAYERS - The invention relates to a device for constructing models in layers. A region for constructing models, preferably a construction platform, and a material applying device ( | 2014-10-16 |