40th week of 2011 patent applcation highlights part 19 |
Patent application number | Title | Published |
20110241146 | MANUFACTURING METHOD AND STRUCTURE OF A WAFER LEVEL IMAGE SENSOR MODULE WITH PACKAGE STRUCTURE - The present invention discloses a manufacturing method and structure of a wafer level image sensor module with package structure. The structure of the wafer level image sensor module with package structure includes a semi-finished product, a plurality of solder balls, and an encapsulant. The semi-finished product includes an image sensing chip and a wafer level lens assembly. The encapsulant is disposed on lateral sides of the image sensing chip and the wafer level lens assembly. Also, the manufacturing method includes the steps of: providing a silicon wafer, dicing the silicon wafer, providing a lens assembly wafer, fabricating a plurality of semi-finished products, performing a packaging process, mounting the solder balls, and cutting the encapsulant. Accordingly, the encapsulant encapsulates each of the semi-finished products by being disposed on the lateral sides thereof. | 2011-10-06 |
20110241147 | WAFER LEVEL IMAGE SENSOR PACKAGING STRUCTURE AND MANUFACTURING METHOD OF THE SAME - The present invention discloses a wafer level image sensor packaging structure and a manufacturing method of the same. The manufacturing method includes the following steps: providing a silicon wafer, dicing the silicon wafer, providing a plurality of transparent lids, fabricating a plurality of semi-finished products, performing a packaging process, mounting solder balls, and cutting an encapsulant between the semi-finished products. The manufacturing method of the invention has the advantage of being straightforward, uncomplicated, and cost-saving. Thus, the wafer level image sensor package structure is lightweight, thin, and compact. To prevent the image sensor chip from cracking on impact during handling, the encapsulant will be arranged on the lateral sides of the semi-finished products during the packaging process. | 2011-10-06 |
20110241148 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT - A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film. | 2011-10-06 |
20110241149 | GEIGER-MODE AVALANCHE PHOTODIODE WITH HIGH SIGNAL-TO-NOISE RATIO, AND CORRESPONDING MANUFACTURING PROCESS - An embodiment of a geiger-mode avalanche photodiode includes: a body of semiconductor material, having a first surface and a second surface; a cathode region of a first type of conductivity, which extends within the body; and an anode region of a second type of conductivity, which extends within the cathode region and faces the first surface, the anode and cathode regions defining a junction. The anode region includes at least two subregions, which extend at a distance apart within the cathode region starting from the first surface, and delimit at least one gap housing a portion of the cathode region, the maximum width of the gap and the levels of doping of the two subregions and of the cathode region being such that, by biasing the junction at a breakdown voltage, a first depleted region occupies completely the portion of the cathode region within the gap. | 2011-10-06 |
20110241150 | AVALANCHE PHOTODIODE - An electron injected APD with an embedded n electrode structure in which edge breakdown can be suppressed without controlling the doping profile of an n-type region of the embedded n electrode structure with high precision. The APD comprising a buffer layer with a low ionization rate is inserted between an n electrode connecting layer and an avalanche multiplication layer. Specifically, the APD is an electron injected APD in which an n electrode layer, the n electrode connecting layer, the buffer layer, the avalanche multiplication layer, an electric field control layer, a band gap gradient layer, a low-concentration light absorbing layer, a p-type light absorbing layer, and a p electrode layer are sequentially stacked, and a light absorbing portion that includes at least the low-concentration light absorbing layer and the p-type light absorbing layer forms a mesa shape. | 2011-10-06 |
20110241151 | IMAGING DEVICE - An imaging device includes a plurality of lower electrodes, an upper electrode, an organic photoelectric conversion layer and a passivation layer. The plurality of lower electrodes are arranged in a two dimensional pattern above a substrate. The upper electrode is arranged above the plurality of lower electrodes so as to oppose the lower electrodes. The organic photoelectric conversion layer is sandwiched between the plurality of lower electrodes and the upper electrode. The passivation layer is provided above the upper electrode and covers the upper electrode. An angle which an end side surface of the lower electrode forms with respect to a surface of a lower layer supporting the lower electrode is 45-degree or more. The passivation layer is formed from a plurality of layers. Film stress of the entire passivation layer ranges from −200 MPa to 250 MPa. | 2011-10-06 |
20110241152 | SENSOR ELEMENT ISOLATION IN A BACKSIDE ILLUMINATED IMAGE SENSOR - The present disclosure provides methods and apparatus for sensor element isolation in a backside illuminated image sensor. In one embodiment, a method of fabricating a semiconductor device includes providing a sensor layer having a frontside surface and a backside surface, forming a plurality of frontside trenches in the frontside surface of the sensor layer, and implanting oxygen into the sensor layer through the plurality of frontside trenches. The method further includes annealing the implanted oxygen to form a plurality of first silicon oxide blocks in the sensor layer, wherein each first silicon oxide block is disposed substantially adjacent a respective frontside trench to form an isolation feature. A semiconductor device fabricated by such a method is also disclosed. | 2011-10-06 |
20110241153 | METHOD FOR THIN FILM THERMOELECTRIC MODULE FABRICATION - Methods of fabrication of a thermoelectric module from thin film thermoelectric material are disclosed. In general, a thin film thermoelectric module is fabricated by first forming an N-type thin film thermoelectric material layer and one or more metallization layers on a substrate. The one or more metallization layers and the N-type thin film thermoelectric material layer are etched to form a number of N-type thermoelectric material legs. A first electrode assembly is then bonded to a first portion of the N-type thermoelectric material legs, and the first electrode assembly including the first portion of the N-type thermoelectric material legs is removed from the substrate. In a similar manner, a second electrode assembly is bonded to a first portion of a number of P-type thermoelectric material legs. The first and second electrode assemblies are then bonded using a flip-chip bonding process to complete the fabrication of the thermoelectric module. | 2011-10-06 |
20110241154 | OPTICAL SENSOR - In an infrared sensor ( | 2011-10-06 |
20110241155 | SEMICONDUCTOR THERMOCOUPLE AND SENSOR - Conventional “on-chip” or monolithically integrated thermocouples are very mechanically sensitive and are expensive to manufacture. Here, however, thermocouples are provided that employ different thicknesses of thermal insulators to help create thermal differentials within an integrated circuit. By using these thermal insulators, standard manufacturing processes can be used to lower cost, and the mechanical sensitivity of the thermocouple is greatly decreased. Additionally, other features (which can be included through the use of standard manufacturing processes) to help trap and dissipate heat appropriately. | 2011-10-06 |
20110241156 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Methods for manufacturing a semiconductor device with alternating P type and N type semiconductor conductive regions are disclosed. One method includes forming a trench in an N type epitaxial layer; forming carbon-contained silicon layer on sidewalls of the trench; and filling the trench with P type semiconductor layer. In another method, the carbon-contained silicon layer is replaced by a carbon film formed by diffusion process. The carbon-contained silicon layer or the carbon film can effectively inhibit the diffusion of P type impurities into the N type semiconductor layers. Further, a semiconductor device having carbon-contained layer or carbon film formed between P type and N type conductive layers is also disclosed. | 2011-10-06 |
20110241157 | METHOD FOR MANUFACTURING A SEMICONDUCTOR SUBSTRATE - The invention relates to a method for manufacturing a semiconductor substrate, in particular a semiconductor-on-insulator substrate by providing a donor substrate and a handle substrate, forming a pattern of one or more doped regions typically inside the handle substrate, and then attaching such as by molecular bonding the donor and the handle substrate to obtain a donor-handle compound. | 2011-10-06 |
20110241158 | ISOLATION TRENCHES - A method is for the formation of at least one filled isolation trench having a protective cap in a semiconductor layer, and a semiconductor device with at least one filled isolation trench having a protective cap. The method allows obtaining, in an easy way, filled isolation trenches exhibiting excellent functional and morphological properties. The method therefore allows the obtainment of effective filled isolation trenches which help provide elevated, reliable and stable isolation properties. | 2011-10-06 |
20110241159 | HIGH EFFICIENCY AMPLIFIER WITH REDUCED PARASITIC CAPACITANCE - A semiconductor amplifier is provided comprising, a substrate and one or more unit amplifying cells (UACs) formed on the substrate, wherein each UAC is laterally surrounded by a first lateral dielectric filled trench (DFT) isolation wall extending at least to the substrate and multiple UACs are surrounded by a second lateral DFT isolation wall of similar depth outside the first isolation walls, and further semiconductor regions lying between the first isolation walls when two or more unit cells are present, and/or lying between the first and second isolation walls, are electrically floating with respect to the substrate. This reduces the parasitic capacitance of the amplifying cells and improves the power added efficiency. Excessive leakage between buried layer contacts when using high resistivity substrates is avoided by providing a further semiconductor layer of intermediate doping between the substrate and the buried layer contacts. | 2011-10-06 |
20110241160 | High Voltage Semiconductor Devices and Methods of Forming the Same - High voltage semiconductor devices and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming first trenches in an insulating material. A trap region is formed in the insulating material by introducing an impurity into the first trenches. The first trenches are filled with a conductive material. | 2011-10-06 |
20110241161 | CHIP PACKAGE WITH CHANNEL STIFFENER FRAME - Various semiconductor chip packages and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing a substrate that has a first side and a first plurality of passive devices on the first side. A stiffener frame is coupled on the first side. The stiffener frame has first and second spaced apart opposing walls that define a channel in which the first plurality of passive devices is positioned, and a central opening that does not cover a central portion of the first side of the substrate. | 2011-10-06 |
20110241162 | Semiconductor Device Comprising Metal-Based eFuses of Enhanced Programming Efficiency by Enhancing Heat Generation - In sophisticated semiconductor devices, electronic fuses may be provided in the metallization system, wherein a superior two-dimensional configuration of the metal line, for instance as a helix-like configuration, may provide superior thermal conditions in a central line portion, which in turn may result in a more pronounced electromigration effect for a given programming current. Consequently, the size of the electronic fuse, at least in one lateral direction, and also the width of corresponding transistors connected to the electronic fuse, may be reduced. | 2011-10-06 |
20110241163 | Semiconductor Device and Method of Forming High-Attenuation Balanced Band-Pass Filter - A semiconductor device has a substrate and band-pass filter formed over the substrate. The band-pass filter includes a first conductive trace wound to exhibit inductive properties with a first end coupled to a first terminal of the semiconductor device and second end coupled to a second terminal of the semiconductor device, and first capacitor coupled between the first and second ends of the first conductive trace. A second conductive trace is wound to exhibit inductive properties with a first end coupled to a third terminal of the semiconductor device and second end coupled to a fourth terminal of the semiconductor device. The second conductive trace has a different size and shape as the first conductive trace. A second capacitor is coupled between the first and second ends of the second conductive trace. A third conductive trace is wound around the first and second conductive traces to exhibit inductive properties. | 2011-10-06 |
20110241164 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a semiconductor substrate, an inter-layer insulating film, a wiring, and a via. The inter-layer insulating film is provided on the semiconductor substrate. The wiring is provided in the inter-layer insulating film. The via is provided in the inter-layer insulating film. Inside the inter-layer insulating film in a circumferential region around a device region, a vertical structure body is formed in which the wiring and the via are vertically connected. At least in an upper portion inside the inter-layer insulating film in an edge region located around the circumferential region and constituting an outer edge portion, no vertical structure body is formed in which the wiring and the via are vertically connected. | 2011-10-06 |
20110241165 | Semiconductor device and communication method - A semiconductor module includes a semiconductor device including a mounting board, a semiconductor chip disposed at a first surface of the mounting board, a first inductor which is provided at a surface side of the semiconductor chip not facing the mounting board in order to perform communication between the semiconductor chip and the outside, a sealing resin layer which is formed at the first surface of the mounting board in order to seal the semiconductor chip, and a recess or an opening which is provided in the sealing resin layer and which includes the inductor inside when seen in a plan view; and a second inductor, which is located in the recess or the opening of the semiconductor device so that the second inductor performs communication with the first inductor. | 2011-10-06 |
20110241166 | Semiconductor Device Comprising a Capacitor Formed in the Contact Level - A contact level in a semiconductor device may be used for providing a capacitor that may be directly connected to a transistor, thereby providing a very space-efficient capacitor/transistor configuration. For example, superior dynamic RAM arrays may be formed on the basis of the capacitor/transistor configuration disclosed herein. | 2011-10-06 |
20110241167 | Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime - Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode. | 2011-10-06 |
20110241168 | PACKAGE ON PACKAGE STRUCTURE - A package on package structure includes a lower package and an upper package. The lower package includes a first semiconductor chip disposed in a chip region of an upper surface of a first substrate. The upper package includes a second semiconductor chip disposed on an upper surface of a second substrate, and a decoupling capacitor disposed in an outer region of a lower surface of the second substrate. The lower surface of the second substrate opposes the upper surface of the second substrate and faces the upper surface of the first substrate. The plane area of the second substrate is larger than the plane area of the first substrate. The outer region of the lower surface of the second substrate extends beyond a periphery of the first substrate. | 2011-10-06 |
20110241169 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A capacitor having a cylindrical shape is increased in capacitance, and a high-resistance region is prevented from being formed in a lower electrode. A semiconductor device includes a capacitor formed to have a cylindrical shape. The semiconductor device includes an insulating film formed over a substrate, a lower electrode formed to have a cylindrical shape, and including a first metal film which is not formed at a bottom portion in a depressed portion provided in the insulating film, but is selectively formed at a sidewall therein and a second metal film which is formed over the bottom portion in the depressed portion and over the first metal film at the sidewall therein, a capacitive film formed over the lower electrode, and an upper electrode formed over the capacitive film. | 2011-10-06 |
20110241170 | MONOLITHIC SEMICONDUCTOR SWITCHES AND METHOD FOR MANUFACTURING - One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively. | 2011-10-06 |
20110241171 | Method of fabricating semiconductor integrated circuit device and semiconductor integrated circuit device fabricated using the method - Provided are a method of fabricating a semiconductor integrated circuit device and a semiconductor integrated circuit device fabricated using the method. The method includes: forming a mask film, which exposes a portion of a substrate, on the substrate; forming a first buried impurity layer, which contains impurities of a first conductivity type and of a first concentration, in a surface of the exposed portion of the substrate by using the mask film; removing the mask film; forming a second buried impurity layer, which contains impurities of a second conductivity type and of a second concentration, using blank implantation; and forming an epitaxial layer on the substrate having the first and second buried impurity layers, wherein the first concentration is higher than the second concentration. | 2011-10-06 |
20110241172 | Charge Balance Techniques for Power Devices - A silicon wafer includes a silicon region of first conductivity type and a plurality of strips of second conductivity type pillars extending in parallel in the silicon region from a location along a perimeter of the silicon wafer to an opposing location along the perimeter of the silicon wafer. The plurality of strips of second conductivity type pillars extend to a predetermined depth within the silicon region. | 2011-10-06 |
20110241173 | RESIST PATTERN FORMATING METHOD - The present invention provides a pattern formation method capable of preventing formation of surface defects. In the method, a resist surface after subjected to exposure is coated with an acidic film and then subjected to heating treatment. This method is suitably adopted in a process employing liquid immersion lithography and/or light of short wavelength, such as ArF excimer laser beams, for producing a very fine pattern. | 2011-10-06 |
20110241174 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed. | 2011-10-06 |
20110241175 | HARDMASK COMPOSITION FOR FORMING RESIST UNDERLAYER FILM, PROCESS FOR PRODUCING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A hardmask composition for forming a resist underlayer film, a process for producing a semiconductor integrated circuit device, and a semiconductor integrated circuit device, the hardmask composition including an organosilane polymer, and a stabilizer, the stabilizer including one of acetic anhydride, methyl acetoacetate, propionic anhydride, ethyl-2-ethylacetoacetate, butyric anhydride, ethyl-2-ethylacetoacetate, valeric anhydride, 2-methylbutyric anhydride, nonanol, decanol, undecanol, dodecanol, propylene glycol propyl ether, propylene glycol ethyl ether, propylene glycol methyl ether, propylene glycol, phenyltrimethoxysilane, diphenylhexamethoxydisiloxane, diphenylhexaethoxydisiloxane, dioctyltetramethyldisiloxane, hexamethyltrisiloxane, tetramethyldisiloxane, decamethyltetrasiloxane, dodecamethylpentasiloxane, hexamethyldisiloxane, and mixtures thereof. | 2011-10-06 |
20110241176 | Substrate Bonding with Bonding Material Having Rare Earth Metal - A microchip has a bonding material that bonds a first substrate to a second substrate. The bonding material has, among other things, a rare earth metal and other material. | 2011-10-06 |
20110241177 | Semiconductor wafer including cracking stopper structure and method of forming the same - A semiconductor includes a semiconductor substrate having a main face, the semiconductor device having a device region and a dicing line and a stack of insulating layers over the semiconductor substrate. There is a multi-level interconnection structure in the stack of insulating layers. A passivation film covers the semiconductor substrate, the passivation film having an opening. The stack of insulating layers has a groove which extends from the opening and penetrates at least one of the insulating layers, the groove is positioned between the device region and the dicing line, and the groove is narrower in width than the opening. | 2011-10-06 |
20110241178 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An organic protective film | 2011-10-06 |
20110241179 | DIFFUSION REGION ROUTING FOR NARROW SCRIBE-LINE DEVICES - The present disclosure provides a method of making an integrated circuit (IC) device. The method includes forming a first IC feature and a second IC feature in a semiconductor substrate, the first and second IC features being spaced from each other and separated by a scribe region; forming, in the semiconductor substrate, a doped routing feature at least partially within the scribe region and configured to connect the first and second IC features; forming a multilayer interconnect (MLI) structure and an interlayer dielectric (ILD) on the semiconductor substrate, wherein the MLI is configured to be absent within the scribe region; and etching the ILD and the semiconductor substrate within the scribe region to form a scribe-line trench. | 2011-10-06 |
20110241180 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE, METHOD FOR DETECTING A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR CHIP PACKAGE - A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness. | 2011-10-06 |
20110241181 | SEMICONDUCTOR DEVICE WITH A CONTROLLED CAVITY AND METHOD OF FORMATION - A semiconductor device includes a first cap wafer having a first opening extending through the first cap wafer, and a second cap wafer bonded to the first cap wafer, wherein the second cap wafer has a second opening extending through the second cap wafer, and wherein the first opening is misaligned with respect to the second opening. The second cap wafer is bonded to a device wafer, wherein a cavity is formed between the device wafer and the second cap wafer, and wherein the device wafer comprises at least one semiconductor device in the cavity. A vacuum sealing layer is formed over the first cap wafer, wherein the sealing layer vacuum seals the first opening. | 2011-10-06 |
20110241182 | DIE SEAL RING - An improved die seal ring is described which includes at least one break. In the region of the break in the die seal ring, the doping is modified so that the impedance of the electrical path across the break through the substrate is increased. Offsets in the break may also be used and the offset may be within a break in a track and/or between breaks in different tracks, where the die seal ring includes more than one track. | 2011-10-06 |
20110241183 | STACKED CHIP PACKAGE WITH REDISTRIBUTION LINES - A chip package comprises a first chip having a first side and a second side, wherein said first chip comprises a first pad, a first trace, a second pad and a first passivation layer at said first side thereof, an opening in said first passivation layer exposing said first pad, said first trace being over said first passivation layer, said first trace connecting said first pad to said second pad; a second chip having a first side and a second side, wherein said second chip comprises a first pad at said first side thereof, wherein said second side of said second chip is joined with said second side of side first chip; a substrate joined with said first side of said first chip or with said first side of said second chip; a first wirebonding wire connecting said second pad of said first chip and said substrate; and a second wirebonding wire connecting said first pad of said second chip and said substrate. | 2011-10-06 |
20110241184 | INTEGRATED CIRCUIT DEVICES HAVING SELECTIVELY STRENGTHENED COMPOSITE INTERLAYER INSULATION LAYERS AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of stacked circuit layers, at least one of the plurality of circuit layers including a composite interlayer insulation layer including laterally adjacent first and second insulating material regions having different mechanical strengths and dielectric properties and a plurality of circuit components disposed in the composite interlayer insulation layer. The first insulating material region may have a lower dielectric constant and a lower mechanical strength than the second insulating material region such that, for example, the first insulating material region may be positioned near signal lines or other circuit features to reduce capacitance while using the second insulating material region near a location that is susceptible to localized mechanical stress, such as a fuse location, an external connection bonding location or a scribe line location. | 2011-10-06 |
20110241185 | SIGNAL SHIELDING THROUGH-SUBSTRATE VIAS FOR 3D INTEGRATION - A shielded through-substrate via (TSV) structure includes a first through-substrate via configured to transmit a signal at least from a top surface of a semiconductor device layer in a substrate to a bottommost surface of the substrate. The shielded TSV structure includes at least one second TSV located on the outside of the first TSV and configured to laterally shield the first TSV from external electrical signals. The at least one second TSV can be a unitary cylindrical structure including the first TSV therein, or a plurality of discrete structures configured to laterally shield the first TSV with gaps thereamongst. The at least one second TSV can include a conductive material that is different from the material of the substrate, or the at least one TSV can include a doped semiconductor material that is derived from the semiconductor material within the substrate. | 2011-10-06 |
20110241186 | FORMING METAL FILLED DIE BACK-SIDE FILM FOR ELECTROMAGNETIC INTERFERENCE SHIELDING WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a carrier material, attaching a die in the cavity, wherein a backside of the die comprises a metal filled DBF, forming a dielectric material adjacent the die and on a bottom side of the carrier material, forming a coreless substrate by building up layers on the dielectric material, and removing the carrier material from the coreless substrate. | 2011-10-06 |
20110241187 | LEAD FRAME WITH RECESSED DIE BOND AREA - A lead frame having a recessed die bond area. The lead frame has top and bottom surfaces and a first lead frame thickness defined as the distance between the top and bottom surfaces. The lead frame has a die bond area surface located within a reduced die bond area. A second thickness is defined as the distance between the die bond area surface and the bottom surface. The second lead frame thickness is less than the first lead frame thickness such that a semiconductor die disposed and attached to the die bond area surface has a reduced overall package thickness. A side wall formed between the die bond area surface and the top surface contains the adhesive material used to attach the die, which reduces adhesive bleeding and prevents wire bonding contamination. | 2011-10-06 |
20110241188 | GRANULAR EPOXY RESIN COMPOSITION FOR ENCAPSULATING SEMICONDUCTOR, SEMICONDUCTOR DEVICE USING THE SAME AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Disclosed is a granular epoxy resin composition for encapsulating a semiconductor used for a semiconductor device obtained by encapsulating a semiconductor element by compression molding, wherein, in the particle size distribution as determined by sieving the whole epoxy resin composition for encapsulating a semiconductor using JIS standard sieves, the ratio of particles having a size of 2 mm or greater is not more than 3% by mass, the ratio of particles having a size of 1 mm or greater, but less than 2 mm is from 0.5% by mass or more to 60% by mass or less, and the ratio of microfine particles having a size of less than 106 μm is not more than 5% by mass. | 2011-10-06 |
20110241189 | APPARATUS FOR AND METHODS OF ATTACHING HEAT SLUGS TO PACKAGE TOPS - A frame includes heat slug pads coupled together in a N×M matrix such that singulation of the heat slug pads consists of one or more passes across the frame, wherein the one or more passes are parallel. A method of attaching heat slug pads to packages includes gathering a plurality of packages, preparing a heat slug frame including a N×M matrix of heat slug pads, dispensing thermally conductive material onto surfaces of the heat slug pads, attaching the plurality of packages onto the heat slug pads, and singulating the heat slug pads, wherein the singulating step consists of one or more parallel passes across the N×M matrix. A method of attaching heat slug foil to packages includes preparing a plurality of packages, laminating the heat slug foil to one side of the plurality of packages using thermally conductive material, and singulating the plurality of packages. | 2011-10-06 |
20110241190 | Semiconductor Package - A method of manufacturing a semiconductor package includes providing a carrier and attaching at least one semiconductor piece to the carrier. An encapsulant is deposited onto the at least one semiconductor piece to form an encapsulated semiconductor arrangement. The encapsulated semiconductor arrangement is then singulated in at least two semiconductor packages, wherein each package includes a semiconductor die separated from the semiconductor piece during singulation. | 2011-10-06 |
20110241191 | SEMICONDUCTOR LAMINATION PACKAGE AND METHOD OF PRODUCING SEMICONDUCTOR LAMINATION PACKAGE - A semiconductor lamination package includes a first package with a first semiconductor chip mounted thereon and a second package with a second semiconductor chip mounted thereon. The first package includes first mounting pads disposed on a bottom surface thereof for transmitting an input/output signal externally from the first semiconductor IC chip. The second package is laminated on the bottom surface of the first package. The second package includes a package substrate having first bonding pads disposed on one surface thereof and second mounting pads disposed on the other surface and electrically connected to the first bonding pads; a first wiring portion for electrically connecting the first bonding pads to a chip pad of the second semiconductor chip; and a package bonding substrate having connecting pads disposed on an upper surface of the second package and a wiring path for electrically connecting the connecting pads and the chip pad. | 2011-10-06 |
20110241192 | Wafer-Level Semiconductor Device Packages with Stacking Functionality - Described herein are wafer-level semiconductor device packages with stacking functionality and related stacked package assemblies and methods. In one embodiment, a semiconductor device package includes a set of connecting elements disposed adjacent to a periphery of a set of stacked semiconductor devices. At least one of the connecting elements is wire-bonded to an active surface of an upper one of the stacked semiconductor devices. | 2011-10-06 |
20110241193 | Semiconductor Device Packages with Fan-Out and with Connecting Elements for Stacking and Manufacturing Methods Thereof - An embodiment of a semiconductor device package includes: (1) an interconnection unit including a patterned conductive layer; (2) an electrical interconnect extending substantially vertically from the conductive layer; (3) a semiconductor device adjacent to the interconnection unit and electrically connected to the conductive layer; (4) a package body: (a) substantially covering an upper surface of the interconnection unit and the device; and (b) defining an opening adjacent to an upper surface of the package body and exposing an upper surface of the interconnect; and (5) a connecting element electrically connected to the device, substantially filling the opening, and being exposed at an external periphery of the device package. The upper surface of the interconnect defines a first plane above a second plane defined by at least a portion of the upper surface of the interconnection unit, and below a third plane defined by the upper surface of the package body. | 2011-10-06 |
20110241194 | Stacked Semiconductor Device Package Assemblies with Reduced Wire Sweep and Manufacturing Methods Thereof - An embodiment of a stacked package assembly includes: (1) a first semiconductor device package including: (a) a semiconductor device including back and lateral surfaces; (b) a package body including an upper surface and substantially covering the back and lateral surfaces of the device; and (c) a first conductive contact adjacent to the upper surface of the body and electrically connected to the device; (2) a second semiconductor device package disposed above the upper surface of the body; (3) a conductive bump adjacent to the first contact and to the second device package; (4) a second conductive contact external to the first and the second device packages; and (5) a conductive wire electrically connecting the first and the second device packages to the second contact, a first end of the wire adjacent to the first contact and at least partially covered by the bump. | 2011-10-06 |
20110241195 | FORMING IN-SITU MICRO-FEATURE STRUCTURES WITH CORELESS PACKAGES - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include attaching a die to a carrier material, forming dielectric material surrounding the die, forming buildup layers in the dielectric material to form a coreless bumpless buildup package structure, and patterning the carrier material to form microchannel structures on the package structure. | 2011-10-06 |
20110241196 | COMPLIANT SPRING INTERPOSER FOR WAFER LEVEL THREE DIMENSIONAL (3D) INTEGRATION AND METHOD OF MANUFACTURING - The present invention is an apparatus for integrating multiple devices. The apparatus includes a substrate having a first via and a second via, a semiconductor chip positioned on a top portion of the substrate and positioned between the first via and the second via, first and second bumps positioned on the semiconductor chip, and an interposer wafer having a first interposer spring assembly and a second interposer spring assembly, the first interposer spring assembly having a first interposer spring and a first electrical connection attached to the first interposer spring, and the second interposer spring assembly having a second interposer spring and a second electrical connection attached to the second interposer spring. | 2011-10-06 |
20110241197 | Device and Method for Manufacturing a Device - A device includes a first semiconductor chip and a first encapsulant that encapsulates the first semiconductor chip and that includes a cavity. A carrier and an electrical component are mounted on the carrier. The carrier is arranged such that the electrical component is enclosed by the cavity. | 2011-10-06 |
20110241198 | Power Semiconductor Module - In a power semiconductor module, a semiconductor device including electrode surfaces for connection on its front side and back side is connected on its back side to a first extraction electrode through soldering; a metal surface of one side of a laminated conductor having a laminated structure in which at least two types of metals are laminated is directly, intermetallically connected to the front side of the semiconductor device; a second extraction electrode is connected to a metal surface of another side of the laminated conductor through soldering; and the laminated conductor includes a plurality of arch-like protrusions and a straight section connecting the arch-like protrusions, the straight section is connected with the front side of the semiconductor device, and the protrusions are connected with the second extraction electrode. | 2011-10-06 |
20110241199 | PROGRAMMABLE SYSTEM IN PACKAGE - Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC's that are arranged within the single IC housing. At least one of the IC's is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC's in the PSiP. The first clock rate is faster than the clock rate of all of the other IC's in the PSiP in some embodiments. | 2011-10-06 |
20110241200 | ULTRA LOW DIELECTRIC CONSTANT MATERIAL WITH ENHANCED MECHANICAL PROPERTIES - An ultra low dielectric constant material is disclosed. The ultra-low dielectric constant material comprises a three dimensional random network porous dielectric comprising atoms of Si, C, O, and H. The ultra-low dielectric constant material also comprises a dielectric constant of not more than 2.6. The ultra-low dielectric constant material further comprises a carbon concentration of at least 15% and a content of carbon that is bonded as —CH2-groups, wherein a concentration of carbon is greater than a concentration of carbon in an ultra low dielectric constant material formed by using a single step ultra-violet curing process. | 2011-10-06 |
20110241201 | Radiate Under-Bump Metallization Structure for Semiconductor Devices - An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions. | 2011-10-06 |
20110241202 | Dummy Metal Design for Packaging Structures - An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad. | 2011-10-06 |
20110241203 | SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, AND PORTABLE APPARATUS - A semiconductor module includes a device mounting board and a semiconductor device. The semiconductor device and the device mounting board are flip-chip connected to each other, and a device electrode provided in the semiconductor device and a substrate electrode provided in the device mounting board are connected by soldering. In a cross section along a line connecting the adjacent substrate electrodes, the width L | 2011-10-06 |
20110241204 | Semiconductor device - A semiconductor device includes an electrode pad provided on a semiconductor chip, in which the electrode pad includes aluminum (Al) as a major constituent and further including copper (Cu), a coupling ball primarily including Cu, the coupling ball is coupled to the electrode pad such that a plurality of layers of Cu and Al alloys are formed at a junction between the electrode pad and the coupling ball, and an encapsulating resin including a halogen of less than or equal to 1000 ppm, the encapsulating resin covering at least the electrode pad and the junction between the electrode pad and the coupling ball. A dimensional area of the plurality of layers of Cu and Al alloys is equal to or larger than 50% of a dimensional area of the junction between the electrode pad and the coupling ball. The plurality of layers of Cu and Al alloys includes a CuAl | 2011-10-06 |
20110241205 | SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT - Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via. | 2011-10-06 |
20110241206 | SEMICONDUCTOR DEVICE - A semiconductor device is provided by the present invention. The semiconductor device includes a first semiconductor die comprising at least a first bond pad; and a second semiconductor die comprising at least a second bond pad with voltage level equivalent to the first bond pad of the first semiconductor die; wherein the first bond pad of the first semiconductor die is electrically connected to the second bond pad of the second semiconductor die via at least a bond wire. The semiconductor device of the present invention is capable of solving the IR drop of the semiconductor die with low cost. | 2011-10-06 |
20110241207 | DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION - Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure. | 2011-10-06 |
20110241208 | MICROELECTRONIC PACKAGE CONTAINING SILICON CONNECTING REGION FOR HIGH DENSITY INTERCONNECTS, AND METHOD OF MANUFACTURING SAME - A microelectronic package comprises a substrate ( | 2011-10-06 |
20110241209 | Substrate comprising alloy film of metal element having barrier function and metal element having catalytic power - It is an object of the present invention to provide a layer having a barrier function and catalytic power and excelling in formation uniformity and coverage of an ultrathin film, provide a pretreatment technique making it possible to form an ultrafine wiring and form a thin seed layer of uniform film thickness, and provide a substrate including a thin seed layer formed with a uniform film thickness by electroless plating by using the aforementioned technique. The present invention provides a substrate in which an alloy film of one or more metal elements, having a barrier function, selected from among tungsten, molybdenum and, niobium and a metal element or metal elements, having catalytic power with respect to electroless plating, composed of ruthenium and/or platinum is formed by chemical vapor deposition (CVD) on a base to a film thickness of 0.5 nm to 5 nm in a composition with a content ratio of the one or more metal element having a barrier function of equal to or greater than 5 at. % and equal to or less than 90 at. %. | 2011-10-06 |
20110241210 | COMPOSITION FOR SEALING SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - The invention provides a composition for sealing a semiconductor, the composition being able to form a thin resin layer, suppress the diffusion of a metal component to a porous interlayer dielectric layer, and exhibit superior adherence with respect to an interconnection material. The composition for sealing a semiconductor contains a resin having two or more cationic functional groups and a weight-average molecular weight of from 2,000 to 100,000; contains sodium and potassium each in an amount based on element content of not more than 10 ppb by weight; and has a volume average particle diameter, measured by a dynamic light scattering method, of not more than 10 nm. | 2011-10-06 |
20110241211 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device has forming, in a dielectric film, a first opening and a second opening located in the first opening, forming a first metal film containing a first metal over a whole surface, etching the first metal film at a bottom of the second opening using a sputtering process and forming a second metal film containing a second metal over the whole surface, and burying a conductive material in the second opening and the first opening. | 2011-10-06 |
20110241212 | STRESS LAYER STRUCTURE - A stress layer structure includes an active stress portion and a dummy stress portion, both formed of a stress material and disposed on the substrate. The active stress portion includes first and second active stress patterns in a region where active devices are formed. The first and second active stress patterns coverrespective active regions, and are separated from each other. The dummy stress portion includes a first dummy stress pattern formed directly on the substrate and disposed between and separated from the first and second active stress patterns. | 2011-10-06 |
20110241213 | Silicide Contact Formation - A method for forming a silicide contact includes depositing a metal layer on silicon such that the metal layer intermixes with the silicon to form an intermixed region on the silicon; removing an unintermixed portion of the metal layer from the intermixed region; and annealing the intermixed region to form a silicide contact on the silicon. A semiconductor device comprising a silicide contact located over a silicon layer of the semiconductor device, the silicide contact comprising nickel (Ni) and silicon (Si) and having Ni amount equivalent to a thickness of about 21 angstroms or less. | 2011-10-06 |
20110241214 | Virtually Substrate-less Composite Power Semiconductor Device and Method - A virtually substrate-less composite power semiconductor device (VSLCPSD) and method are disclosed. The VSLCPSD has a power semiconductor device (PSD), a front-face device carrier (FDC) made out of a carrier material and an intervening bonding layer (IBL). Both carrier and IBL material can be conductive or non-conductive. The PSD has back substrate portion, front semiconductor device portion with patterned front-face device metallization pads and a virtually diminishing thickness T | 2011-10-06 |
20110241215 | EMBEDDED SEMICONDUCTIVE CHIPS IN RECONSTITUTED WAFERS, AND SYSTEMS CONTAINING SAME - A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are embedded in the rigid mass. The plurality of dice include terminals that are exposed through coplanar with the flat surface. A process of forming the reconstituted wafer includes removing some of the rigid mass to expose the terminals, while retaining the plurality of dice in the rigid mass. A process of forming an apparatus includes separating one apparatus from the reconstituted wafer. | 2011-10-06 |
20110241216 | Semiconductor device - A semiconductor device includes a substrate over which a circuit is formed, a multi-layer wiring layer having a plurality of wiring layers formed over the substrate and a pad formed in a predetermined location of an uppermost layer of the wiring layers, a new pad provided in an appropriate location over the multi-layer wiring layer, and a redistribution layer provided with a redistribution line coupling the new pad and the pad. In the semiconductor device: the multi-layer wiring layer includes a signal line for transmitting an electric signal to the circuit and a ground line provided in a wiring layer between the redistribution line or the new pad and the circuit; the ground line is formed to correspond to a location where the new pad is assumed to be located and a route along which the redistribution line is assumed to be formed; and the redistribution line is formed along at least a portion of the ground line. | 2011-10-06 |
20110241217 | Multi-Layer Interconnect Structure for Stacked Dies - A multi-layer interconnect structure for stacked die configurations is provided. Through-substrate vias are formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-substrate vias. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-substrate vias. A first conductive element is formed electrically coupled to respective ones of the through-substrate vias and extending over the isolation film. One or more additional layers of isolation films and conductive elements may be formed, with connection elements such as solder balls being electrically coupled to the uppermost conductive elements. | 2011-10-06 |
20110241218 | Electronic Device and Manufacturing Method - A semiconductor package includes a semiconductor chip, an encapsulant embedding the semiconductor chip, first contact pads on a first main face of the semiconductor package and second contact pads on a second main face of the semiconductor package opposite to the first main face. The diameter d in micrometers of an exposed contact pad area of the second contact pads satisfies d≧(8/25)x+142 μm, wherein x is the pitch of the second contact pads in micrometers. | 2011-10-06 |
20110241219 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A first contact hole that passes through a planarizing film layered on a first interlayer insulating film, a second interlayer insulating film that covers the surface of the planarizing film and the inner surface of the first contact hole, a third interlayer insulating film layered on the second interlayer insulating film, and a second contact hole formed with a small inner diameter inside the first contact hole and passing through the first to the third interlayer insulating films are formed. Over the third interlayer insulating film and inside the second contact hole, a second conductive film electrically connected to a first conductive film is formed. | 2011-10-06 |
20110241220 | AIR GAPS IN A MULTILAYER INTEGRATED CIRCUIT AND METHOD OF MAKING SAME - A multilayer integrated circuit (IC) including a cross pattern of air gaps in a wiring layer and methods of making the multilayer IC are provided. The patterning of the air gaps is independent of the wiring layout. Patterns of air gaps including: parallel alternating stripes of air gaps and dielectric that are orthogonal to a uni-directional metal wiring layout; parallel alternating stripes of air gaps and dielectric that are diagonal to either a uni- or bi-directional metal wiring layout; and a checkerboard pattern of air gaps and dielectric that crosses either a uni- or bi-directional metal wiring layout are easily formed by conventional photolithography and provide a comparatively uniform reduction in parasitic capacitance between the wires and the surrounding materials, when about one-half of a total length of the metal wiring layout is disposed within the air gaps. | 2011-10-06 |
20110241221 | SEMICONDUCTOR DEVICE WITH IMPROVED RESIN CONFIGURATION - A semiconductor device comprises a wiring substrate including a wiring pattern; a semiconductor chip installed on the wiring substrate, including a plurality of pads formed on a surface of the semiconductor chip, which opposes the wiring substrate; a first resin layer covering over a part of the wiring pattern within a region of overlapping the semiconductor chip; and a second resin layer installed between the semiconductor chip and the first resin layer. The pads are oppose to and coupled with a part of the wiring pattern exposed over the first resin layer; and the linear expansion coefficient of the wiring substrate is larger than that of the semiconductor chip, the elastic modulus of the wiring substrate is lower than that of the semiconductor chip and the linear expansion coefficient of the first resin layer is larger than that of the second resin layer. The elastic modulus of the first resin layer is lower than that of the second resin layer. | 2011-10-06 |
20110241222 | Semiconductor Package and Manufacturing Method - A polymer layer is generated on a wafer. The wafer is then separated into semiconductor chips. At least two semiconductor chips are placed on a carrier with the polymer layer facing the carrier. The at least two semiconductor chips are covered with an encapsulating material to form an encapsulant. The carrier is removed from the encapsulant, and the encapsulant and the polymer layer are thinned. | 2011-10-06 |
20110241223 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH WIRE-IN-FILM ISOLATION BARRIER AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing an integrated circuit package in package system includes: providing a substrate having a first wire-bonded die with an active side mounted above; connecting the active side of the first wire-bonded die to the substrate with a bond-wire; mounting a wire-in-film adhesive having an isolation barrier over the first wire-bonded die; and encapsulating the first wire-bonded die, the bond-wires, and the wire-in-film adhesive with an encapsulation. | 2011-10-06 |
20110241224 | WIRE BONDING STRUCTURE OF SEMICONDUCTOR DEVICE AND WIRE BONDING METHOD - A wire bonding structure is provided which includes a wire having a first bonding portion and a second bonding portion. The first bonding portion is bonded to an electrode pad of a semiconductor element, whereas the second bonding portion is bonded to a pad portion of a lead. The first bonding portion includes a front bond portion, a rear bond portion, and an intermediate portion sandwiched between these two bond portions. The front bond portion and the rear bond portion are bonded to the electrode pad more strongly than the intermediate portion is. In the longitudinal direction of the wire, the second bonding portion is smaller than the first bonding portion in bonding length. | 2011-10-06 |
20110241225 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other. | 2011-10-06 |
20110241226 | METHOD FOR PRODUCING A MICROFLUID COMPONENT, AS WELL AS MICROFLUID COMPONENT - A method for producing a microfluid component includes: Producing a single polymer layer made of at least one plastic or a plastic composite and having a microfluid structure, fitting the polymer layer with at least one semiconductor element, and/or with at least one electronic component, and/or with an optical or optoelectronic component, sealing the microfluid structure. | 2011-10-06 |
20110241227 | LIQUID RESIN COMPOSITION AND SEMICONDUCTOR DEVICE - The invention is aimed at providing a liquid resin composition capable of densely containing a filler and of filling up a narrow gap in a flip-chip-bonded semiconductor device, and a highly-reliable semiconductor device using the same. The liquid resin composition of the present invention contains (A) an epoxy resin; (B) an epoxy resin curing agent; and (C) a filler, wherein content of (C) the filler is 60% by weight or more and 80% by weight or less of the whole liquid resin composition, and contact angle (θ) of the liquid resin composition, measured at 110° C. in accordance with JIS R3257, is 30° or smaller. | 2011-10-06 |
20110241228 | EPOXY RESIN COMPOSITION FOR SEALING PACKING OF SEMICONDUCTOR, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF - An epoxy resin composition for a underfilling of a semiconductor comprising an epoxy resin, an acid anhydride, a curing accelerator and a flux agent as essential components, wherein the curing accelerator is a quaternary phosphonium salt, as well as a semiconductor device and manufacturing method employing the same. | 2011-10-06 |
20110241229 | ENCAPSULATED NANOPARTICLES - In various embodiments, the present invention relates to production of encapsulated nanoparticles by dispersing said nanoparticles and an encapsulating medium in a common solvent to form a first solution system and applying a stimulus to said first solution system to induce simultaneous aggregation of the nanoparticles and the encapsulating medium. | 2011-10-06 |
20110241230 | Nano-bubble Generator and Treatments - Bubble generator devices to produce a fluid stream comprising bubbles are described. Apparatuses that include any of the described bubble generator devices to treat waste and/or frac-water are also described. | 2011-10-06 |
20110241231 | LIQUID CONTAINER AND LIQUID EJECTING APPARATUS - A liquid container which contains liquid to be supplied to a liquid ejecting apparatus, includes: a containing section which contains liquid and includes a liquid delivery section, an air introduction section, and a deformation section, wherein the deformation section includes a rigid body section and a flexible section, the liquid container further includes a stop section which at least blocks the displacement equal to or greater than a predetermined amount with respect to a portion of the rigid body section, and in displacement of the rigid body section accompanying a reduction in the pressure, in the displacement of the rigid body section accompanying a reduction in the pressure, the air introduction section introduces the air into the containing section by transmission of displacement of the other portion of the rigid body section, the displacement of the portion of which has been blocked. | 2011-10-06 |
20110241232 | HOT WATER DISTRIBUTION SYSTEM AND METHOD FOR A COOLING TOWER - A cooling tower with a hot water distribution system includes a distribution lateral disposed above a hot water basin. The distribution lateral discharges fluid into the hot water basin, which in turn, releases the fluid through a plurality of orifices. As the fluid is released, it falls on heat-exchanging fill material that assists in increasing the cooling rate of the fluid. The distribution lateral is configured structurally to discharge the fluid through a plurality of outlets at one or more angles (as compared to the horizontal) into the hot water basins. In one embodiment, the outlets are arranged into one or more rows that extend along a substantial length of the distribution lateral. Discharging the fluid in this manner enhances and promotes a more even fluid flow within the hot water basin, which results in a more even fluid flow over and onto the fill material, thereby increasing thermal efficiency. | 2011-10-06 |
20110241233 | METHOD FOR MANUFACTURING OPTICAL WAVEGUIDE - A method for manufacturing an optical waveguide in which multiple cores are embedded in a parallel-arranged fashion within a single cladding, the cores having a refractive index of light different from that of the cladding, the method includes forming the multiple cores in a state where the adjacent cores are connected by a rib, forming the cladding around the rib and the multiple cores by curing a cladding material there around, and a cutting to the rib. | 2011-10-06 |
20110241234 | FABRICATION PROCESS FOR MASTERING IMAGING LENS ARRAYS - A process and method for fabricating a master lens array for use in the manufacture of duplicate lens arrays is provided. The fabrication methods provided herein are capable of maximizing the quality of the master lens array in an efficient and cost effective manner, thereby reducing the propagation of errors in the lenses formed using the master lens array. | 2011-10-06 |
20110241235 | PROCESS FOR PREPARING SPRAY-DRIED PARTICLES - The present invention relates to a process of making spray-dried detergent particles comprising the steps: (a) contacting magnesium sulphate with sodium salt of ethylenediamine disuccinic acid to form a premix comprising magnesium salt of ethylenediamine disuccinic acid; (b) contacting said premix with an aqueous slurry comprising detersive surfactant, sodium silicate, and optionally polymer; and (c) spray drying said aqueous slurry to form said spray-dried detergent particles. | 2011-10-06 |
20110241236 | DEFORMABLE GRANULE PRODUCTION - A method of forming granules, the method including forming a suspension of a nanopowder such as a nano zirconia powder containing yttria. The powder is formed from a suspension, and freon is added directly to the suspension as an additive. The suspension is then granulated by spray freeze drying, and the freon subsequently removed by heat treatment. The voids left by the vacated freon provide meso, micro and macro flaws or structural defects in the granules. | 2011-10-06 |
20110241237 | REPAIR OF HEATING WALLS IN A REFRACTORY FURNACE - A method of repairing a refractory brick wall in a furnace that includes: (a) identifying a refractory brick wall or portion thereof that requires repair/reconstruction, pre engineering construction dimensions and accommodating various battery oven designs and oven heating systems; (b) demolishing the refractory brick wall or wall portion thereof identified in step (a); (c) installing outer reusable forms in situ, defining a new wall or portion thereof; (d) installing inner consumable forms defining one or more passageways within the new wall or portion thereof; and (e) pouring castable material into one or more areas bounded by the outer forms; (f) curing said castable material; and (g) removing the outer reuseable forms. | 2011-10-06 |
20110241238 | VALVE GATE SYSTEM - A valve gate assembly comprises a piston that is actuable between a forward position and a rear position and has a piston stop surface and a forward pressure surface. A cylinder has a cylinder stop surface that is disposed to contact the piston stop surface when the piston is in the forward position. The cylinder stop surface is radially outward of at least a portion of the forward pressure surface and a shutoff pin is substantially aligned with the axis. | 2011-10-06 |
20110241239 | OPTICAL MEDIA PRODUCTION SYSTEM AND METHOD FOR CONTROLLING SAME - A nano-imprinting system may be configured to at least one of transport, emboss, coat and slit an optical media according to operational parameters. A control system may be configured to detect one or more attributes of the optical media that result from at least one of the embossing and coating of the optical media, and to adjust at least one of the operational parameters based on the detected one or more attributes. | 2011-10-06 |
20110241240 | APPARATUS FOR PRINTING OF THREE-DIMENSIONAL OBJECTS - An apparatus to help control the quality of printed three-dimensional objects is provided. The apparatus may include a printing head to print a three-dimensional object and a printing tray having defined surface characteristics serving to control adherence of the object being printed to the printing tray and/or prevent deformations in the printed object. | 2011-10-06 |
20110241241 | Startup Control Method and Startup Control Device of Resin Extruder - A startup control method of a resin extruder is provided. The resin extruder extrudes supplied resin material to a die as molten resin by rotating a screw. The resin material is supplied with a low supply amount which is smaller than a target supply amount and the screw is rotated at a low rotational frequency which is smaller than a target rotational frequency when starting the resin extruder. A supply amount of the resin material and a rotational frequency of the screw are gradually increased. After elapse of a set startup time, the supply amount of the resin material is brought into a target supply amount and the rotational frequency of the screw is brought into a target rotational frequency. | 2011-10-06 |
20110241242 | Plastic film - Plastic sheeting with a rough surface to increase the coefficient of friction, whereby at least one side of the sheeting is equipped with a layer ( | 2011-10-06 |
20110241243 | AUTOMATED ASSEMBLY METHODS AND SYSTEMS FOR MOLDED HOUSINGS - A system and method for producing molded parts with a marking component comprising: providing an insert tape comprising an insert portion configured to act as the marking component and a web portion; and molding a part around the insert tape such that the insert portion is exposed and such that the web portion acts as a carrier for the molded part in an automated process. | 2011-10-06 |
20110241244 | METHOD FOR MAKING CARBON NANOTUBE FILM - The present disclosure relates to a method for making a carbon nanotube film. In the method, a bent flexible substrate having a curved surface and a pressing device are provided. A carbon nanotube array is formed on the curved surface. The bent flexible substrate is at least partially unbent, thereby at least partially unbending the carbon nanotube array. The unbent carbon nanotube array is pressed by the pressing device to slant the carbon nanotubes in the unbent carbon nanotube array, thereby forming the carbon nanotube film. | 2011-10-06 |
20110241245 | AXIALLY ORIENTED CONFINED CRYSTALLIZATION MULTILAYER FILMS - A method of forming a confined crystallization multilayer film includes coextruding a plurality of first polymer layers and a plurality of second polymer layer to form a multilayer film wherein each first polymer layer is sandwiched between second polymer layers and axially orienting the multilayer film at a temperature below the melting temperature (T | 2011-10-06 |