40th week of 2008 patent applcation highlights part 63 |
Patent application number | Title | Published |
20080242049 | METHOD FOR GENERATING A MICROMECHANICAL STRUCTURE - In a method for manufacturing a micromechanical structure, first a two-dimensional structure is formed in a substrate. The two-dimensional structure is deflected from the substrate plane by action of force and fixed in the deflected state. | 2008-10-02 |
20080242050 | Method for manufacturing semiconductor device - It is an object of the present invention to manufacture a semiconductor element and an integrated circuit that have high performance over a large-sized substrate with high throughput and high productivity. When single crystal semiconductor layers are transferred from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers divided such that they have the size of semiconductor elements to be manufactured are transferred to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. | 2008-10-02 |
20080242051 | Method for manufacturing semiconductor device - When single crystal semiconductor layers are transposed from a single crystal semiconductor substrate (a bond wafer), the single crystal semiconductor substrate is etched selectively (this step is also referred to as groove processing), and a plurality of single crystal semiconductor layers, which are being divided in size of manufactured semiconductor elements, are transposed to a different substrate (a base substrate). Thus, a plurality of island-shaped single crystal semiconductor layers (SOI layers) can be formed over the base substrate. Further, etching is performed on the single crystal semiconductor layers formed over the base substrate, and the shapes of the SOI layers are controlled precisely by being processed and modified. | 2008-10-02 |
20080242052 | Method of forming ultra thin chips of power devices - A method for making thin semiconductor devices is disclosed. Starting from wafer with pre-fabricated front-side devices, the method includes:
| 2008-10-02 |
20080242053 | INTEGRATED CIRCUIT SYSTEM WITH A DEBRIS TRAPPING SYSTEM - An integrated circuit system including: providing an integrated circuit wafer having an integrated circuit side and a backside; mounting a protective adhesive on the integrated circuit side of the integrated circuit wafer; removing material from the backside of the integrated circuit wafer; and dicing the integrated circuit wafer through the protective adhesive to form an integrated circuit die. | 2008-10-02 |
20080242054 | Dicing and drilling of wafers - Methods and apparatus to dicing and/or drilling of wafers are described. In one embodiment, an electromagnetic radiation beam (e.g., a relatively high intensity, ultra-short laser beam) may be used to dice and/or drill a wafer. Other embodiments are also described. | 2008-10-02 |
20080242055 | WAFER LASER PROCESSING METHOD AND LASER PROCESSING EQUIPMENT - A wafer laser processing method for forming a groove in a wafer having a plurality of areas which are sectioned by streets formed in a lattice pattern on the front surface of a substrate, a device being formed in each of the plurality of areas, and an insulating film being formed on the surfaces of the devices, by applying a pulse laser beam along the streets, the method comprising a heating step for applying a first pulse laser beam set to an output for preheating the insulating film so as to soften it to the insulating film and a processing step for applying a second pulse laser beam set to an output for processing the insulating film and the substrate to the spot position of the first pulse laser beam applied in the heating step, the heating step and the processing step being carried out along the streets alternately. | 2008-10-02 |
20080242056 | SYSTEM AND METHOD FOR CUTTING USING A VARIABLE ASTIGMATIC FOCAL BEAM SPOT - A variable astigmatic focal beam spot is formed using lasers with an anamorphic beam delivery system. The variable astigmatic focal beam spot can be used for cutting applications, for example, to scribe semiconductor wafers such as light emitting diode (LED) wafers. The exemplary anamorphic beam delivery system comprises a series of optical components, which deliberately introduce astigmatism to produce focal points separated into two principal meridians, i.e. vertical and horizontal. The astigmatic focal points result in an asymmetric, yet sharply focused, beam spot that consists of sharpened leading and trailing edges. Adjusting the astigmatic focal points changes the aspect ratio of the compressed focal beam spot, allowing adjustment of energy density at the target without affecting laser output power. Scribing wafers with properly optimized energy and power density increases scribing speeds while minimizing excessive heating and collateral material damage. | 2008-10-02 |
20080242057 | SEMICONDUCTOR DEVICE WITH A THINNED SEMICONDUCTOR CHIP AND METHOD FOR PRODUCING THE THINNED SEMICONDUCTOR CHIP - A semiconductor device with a thinned semiconductor chip and a method for producing the latter is disclosed. In one embodiment, the thinned semiconductor chip has a top side with contact areas and a rear side with a rear side electrode. In this case, the rear side electrode is cohesively connected to a chip pad of a circuit carrier via an electrically conductive layer. In another embodiment, the thinned semiconductor chips of this semiconductor device according to the invention have low-microdefect edge side regions with semiconductor element structures and edge sides patterned by etching technology. | 2008-10-02 |
20080242058 | Adhesive Composition, Adhesive Sheet and Production Process for Semiconductor Device - The adhesive composition according to the present invention is characterized by including an acrylic polymer, an epoxy resin having an epoxy equivalent of 180 g/eq or less and a thermosetting agent. | 2008-10-02 |
20080242059 | Methods of forming nickel silicide layers with low carbon content - A method for forming a nickel silicide layer on a MOS device with a low carbon content comprises providing a substrate within an ALD reactor and performing an ALD process cycle to form a nickel layer on the substrate, wherein the ALD process cycle comprises pulsing a nickel precursor into the reactor, purging the reactor after the nickel precursor, pulsing a mixture of hydrogen and silane into the reactor, and purging the reactor after the hydrogen and silane pulse. The ALD process cycle can be repeated until the nickel layer reaches a desired thickness. The silane used in the ALD process functions as a getterer for the advantageous carbon, resulting in a nickel layer that has a low carbon content. The nickel layer may then be annealed to form a nickel silicide layer with a low carbon content. | 2008-10-02 |
20080242060 | METHOD FOR FORMING AlGaN CRYSTAL LAYER - A method for preparing an AlGaN crystal layer with good surface flatness is provided. A surface layer of AlN is epitaxially formed on a c-plane sapphire single crystal base material by MOCVD method, and the resulting laminated body is then heated at a temperature of 1300° C. or higher so that a template substrate applying in-plane compressive stress and having a surface layer flat at a substantially atomic level is obtained. An AlGaN layer is formed on the template substrate at a deposition temperature higher than 1000° C. by an MOCVD method that includes depositing alternating layers of a first unit layer including a Group III nitride represented by the composition formula Al | 2008-10-02 |
20080242061 | PRECURSOR GAS MIXTURE FOR DEPOSITING AN EPITAXIAL CARBON-DOPED SILICON FILM - A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region. | 2008-10-02 |
20080242062 | FABRICATION OF DIVERSE STRUCTURES ON A COMMON SUBSTRATE THROUGH THE USE OF NON-SELECTIVE AREA GROWTH TECHNIQUES - Diverse semiconductor structures are fabricated on a single substrate or wafer by using a non-selective area growth technique involving deposition of material over the entire substrate. The fabricated structures are obtained by selective removal of portions of the deposited material layers. Single level and multi-level structures are possible. | 2008-10-02 |
20080242063 | Solder composition doped with a barrier component and method of making same - A solder composition and a method of making the composition. The solder composition comprises a Sn-containing base material and a barrier component having a reactivity with Sn which is higher than a reactivity of Ni or Cu with Sn, the barrier component being present in the composition in an amount sufficient to reduce a reactivity of Sn with both Ni and Cu. | 2008-10-02 |
20080242064 | Manufacturing method of semiconductor device - To provide a manufacturing method of a semiconductor device capable of performing a selective growth at a low temperature. A manufacturing method of a semiconductor device for placing in a processing chamber a substrate having at least a silicon surface and an insulating film surface on a surface; and allowing an epitaxial film to selectively grow only on the silicon surface by using a substrate processing apparatus for heating an atmosphere in the processing chamber and the substrate, using a hearting unit disposed outside of the processing chamber, includes a substrate loading step of loading the substrate into the processing chamber; a pre-processing step of supplying dichlorsilane gas and hydrogen gas into the processing chamber while maintaining a temperature in the substrate processing chamber to a prescribed temperature of 700° C. or less, and removing a natural oxide film or impurities formed on the silicon surface; and a substrate unloading step of unloading the substrate to outside of the processing chamber. | 2008-10-02 |
20080242065 | CONTROL OF ION ANGULAR DISTRIBUTION FUNCTION AT WAFER SURFACE - A manufacturing method and apparatus for IC fabrication controls the ion angular distribution at the surface of a wafer with electrodes in a wafer support that produce electric fields parallel to the wafer surface without disturbing plasma parameters beyond the wafer surface. The ion angular distribution function (IADF) at the wafer surface is controlled for better feature coverage or etching. Grid structure is built into the substrate holder within the coating at the top of the holder. The grid components are electrically biased to provide electric fields that combine with the sheath field to distribute the ion incidence angles from the plasma sheath onto the wafer. The grid can be dynamically biased or phased to control uniformity of the effects. | 2008-10-02 |
20080242066 | Method Of Manufacturing Semiconductor - A method of producing ultra shallow junctions ( | 2008-10-02 |
20080242067 | SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE THEREOF - A semiconductor substrate is disclosed, which comprises a lightly doped substrate that contains impurities at a low concentration, a heavily doped diffusion layer which is formed over a top of the lightly doped substrate and is higher in impurity concentration than the lightly doped substrate, and an epitaxial layer which is formed over a top of the heavily doped diffusion layer and contains impurities at a lower concentration than the heavily doped diffusion layer. | 2008-10-02 |
20080242068 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device fabrication method by which CMOS transistors with low-resistance metal gate electrodes each having a proper work function can be fabricated. A HfN layer in which nitrogen concentration in an nMOS transistor formation region differs from nitrogen concentration in a pMOS transistor formation region is formed. A MoN layer is formed over the HfN layer and heat treatment is performed. Nitrogen diffuses from the MoN layer into the HfN layer in which nitrogen concentration is low and a work function is set by the HfN layer according to nitrogen concentration which depends on the nitrogen content of the HfN layer before the heat treatment and the amount of nitrogen that diffuses into the HfN layer. On the other hand, nitrogen hardly diffuses from the MoN layer into the HfN layer which originally has a certain nitrogen content, and a work function is set by the HfN layer according to nitrogen concentration in the HfN layer before the heat treatment. By controlling the nitrogen content of each layer and the amount of nitrogen that diffuses, a low-resistance metal gate electrode having a predetermined work function can be formed in each of the nMOS transistor formation region and the pMOS transistor formation region. | 2008-10-02 |
20080242069 | HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS - Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects. | 2008-10-02 |
20080242070 | INTEGRATION SCHEMES FOR FABRICATING POLYSILICON GATE MOSFET AND HIGH-K DIELECTRIC METAL GATE MOSFET - Multiple integration schemes for manufacturing dual gate semiconductor structures are disclosed. By employing the novel integration schemes, polysilicon gate MOSFETs and high-k dielectric metal gate MOSFETs are formed on the same semiconductor substrate despite differences in the composition of the gate stack and resulting differences in the etch rates. A thin polysilicon layer is used for one type of gate electrodes and a silicon-containing layer are used for the other type of gate electrodes in these integration schemes to balance the different etch rates and to enable etching of the two different gate stacks. | 2008-10-02 |
20080242071 | METHOD FOR PASSIVATING GATE DIELECTRIC FILMS - The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate, forming a dielectric layer over the semiconductor substrate, treating the dielectric layer with a carbon containing group, forming a conductive layer over the treated dielectric layer, and patterning and etching the dielectric layer and conductive layer to form a gate structure. The carbon containing group includes an OCH | 2008-10-02 |
20080242072 | PLASMA DRY ETCH PROCESS FOR METAL-CONTAINING GATES - A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol. | 2008-10-02 |
20080242073 | METHOD FOR FABRICATING A NONVOLATILE MEMORY DEVICE - A method for fabricating a nonvolatile memory device includes forming a gate insulation layer and a gate conductive layer for forming a floating gate over a substrate. A portion of the gate conductive layer, the gate insulation layer, and the substrate is etched to form a trench. An isolation structure is formed by filling in the trench. The isolation structure is recessed to a certain depth in the trench. A buffer layer is formed over the substrate structure. Spacers are formed over sidewalls of the buffer layer corresponding to inner sidewalls of the trench. A portion of the recessed isolation structure is etched to form a depression in the isolation structure using the spacers. The spacers are removed followed by removal of the buffer layer. A dielectric layer is formed over the substrate structure, and a control gate is formed over the dielectric layer. | 2008-10-02 |
20080242074 | Method of Forming Gate Pattern of Flash Memory Device - A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved. | 2008-10-02 |
20080242075 | METHOD FOR FORMING NON-VOLATILE MEMORY DEVICES - According to a nonvolatile memory device having a multi gate structure and a method for forming the same of the present invention, a gate electrode is formed using a damascene process. Therefore, a charge storage layer, a tunneling insulating layer, a blocking insulating layer and a gate electrode layer are not attacked from etching in a process for forming the gate electrode, thereby forming a nonvolatile memory device having good reliability. | 2008-10-02 |
20080242076 | METHOD OF MAKING SEMICONDUCTOR DIE STACK HAVING HEIGHTENED CONTACT FOR WIRE BOND - A method of making a semiconductor device is disclosed including die bond pads which are heightened to allow wire bonding of offset stacked die even in tight offset configurations. After a first die is affixed to a substrate, one or more layers of an electrical conductor may be provided on some or all of the die bond pads of the first substrate to raise the height of the bond pads. The conductive layers may for example be conductive balls deposited on the die bond pads of the first substrate using a known wire bond capillary. Thereafter, a second die may be added, and wire bonding of the first die may be accomplished using a known wire bond capillary mounting a wire bond ball on a raised surface of a first semiconductor die bond pad. | 2008-10-02 |
20080242077 | Strained metal silicon nitride films and method of forming - A method for forming a strained metal nitride film and a semiconductor device containing the strained metal nitride film. The method includes exposing a substrate to a gas containing a metal precursor, exposing the substrate to a gas containing a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the metal precursor or the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the metal precursor or the silicon precursor with a second reactivity characteristic such that a property of the metal silicon nitride film formed on the substrate changes to provide the strained metal silicon nitride film. | 2008-10-02 |
20080242078 | PROCESS OF FILLING DEEP VIAS FOR 3-D INTEGRATION OF SUBSTRATES - A method for filling defect-free conductive material in deep vias or cavities in semiconductor wafers in 3-D integration structures is provided. The process may be performed in at least two steps for depositing the conductive material, including a first deposition step that partially fills the cavity with the conductive material and forms a conformal layer, which may also reduce the depth and width of the cavity, and a second deposition step that completely fills the same conductive material into the space defined by the conformal layer. | 2008-10-02 |
20080242079 | IN-SITU FORMATION OF CONDUCTIVE FILLING MATERIAL IN THROUGH-SILICON VIA - The formation of electronic assemblies including a die having through vias is described. In one embodiment, a method includes providing Si die including a first surface and a second surface opposite the first surface, and forming a via extending through the Si die from the first surface to the second surface. The via is formed to have a larger width at the first surface than at the second surface, the larger width at the first surface being no less than 100 microns. The method also includes placing a plurality of particles in the via, wherein at least some of the particles comprise a polymer and at least some of the particles comprise a metal. The method also includes heating the die and the particles in the via to cross-link at least part of the polymer in the via, and cooling the die to solidify the polymer and form a electrically conductive composite including the cross-linked polymer and the metal in the via. Other embodiments are described and claimed. | 2008-10-02 |
20080242080 | Method for implementing diffusion barrier in 3D memory - One or more diffusion barriers are formed around one or more conductors in a three dimensional or 3D memory cell. The diffusion barriers allow the conductors to comprise very low resistivity materials, such as copper, that may otherwise out diffuse into surrounding areas, particularly at elevated processing temperatures. Utilizing lower resistivity materials allows device dimension to be reduced by mitigating increases in resistance that occur when the size of the conductors is reduced. As such, more cells can be produced over a given area, thus increasing the density and storage capacity of a resulting memory array. | 2008-10-02 |
20080242081 | POLISHING METHOD, POLISHING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A polishing method includes a first polishing step of halfway polishing a film to be polished formed on a substrate, and a second polishing step of further polishing the polished film, wherein a first film thickness profile showing an in-plane distribution of a film thickness of the polished film after the second polishing step for a first substrate is measured, and the first polishing step for a second substrate is executed to obtain a second film thickness profile which has a size relation in a film thickness opposite to the first film thickness profile. | 2008-10-02 |
20080242082 | METHOD FOR FABRICATING BACK END OF THE LINE STRUCTURES WITH LINER AND SEED MATERIALS - A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place. | 2008-10-02 |
20080242083 | Method for Manufacturing Memory Element - A first conductive layer is formed, a composition layer over the first conductive layer is formed by discharging a composition in which nanoparticles comprising a conductive material covered with an organic material are dispersed in a solvent, and the composition layer is dried. Subsequently, pretreatment is performed in which the organic material covering the nanoparticles, which are positioned on a surface of the composition layer, is decomposed, and then baking is performed. In this manner, a second conductive layer is formed by sintering nanoparticles which are positioned on a surface of the composition layer. A memory layer is formed between the first conductive layer and the second conductive layer using the nanoparticles covered with the organic materials to which the pretreatment is not performed. | 2008-10-02 |
20080242084 | METHOD FOR PLANARIZING AN INSULATION LAYER IN A SEMICONDUCTOR DEVICE CAPABLE OF OMITTING A MASK PROCESS AND AN ETCHING PROCESS - In a method for planarizing an insulation layer in a semiconductor device, an insulation layer is formed over a semiconductor substrate having a cell region and a peripheral region. The cell region is higher than the peripheral region due to a capacitor formed in the cell region. A metal layer is formed over the insulation layer. The metal layer is chemical mechanical polished to expose the insulation layer portion in the cell region. The exposed insulation layer portion in the cell region is chemical mechanical polishing to planarize the insulation layer, and the planarized insulation layer and the remaining metal layer are chemical mechanical polishing to remove the metal layer remained in the peripheral region. The method for planarizing an insulation layer does not require a separate photosensitive layer forming process or a dry etching process. | 2008-10-02 |
20080242085 | Showerhead electrodes and showerhead electrode assemblies having low-particle performance for semiconductor material processing apparatuses - Showerhead electrodes for a semiconductor material processing apparatus are disclosed. An embodiment of the showerhead electrodes includes top and bottom electrodes bonded to each other. The top electrode includes one or more plenums. The bottom electrode includes a plasma-exposed bottom surface and a plurality of gas holes in fluid communication with the plenum. Showerhead electrode assemblies including a showerhead electrode flexibly suspended from a top plate are also disclosed. The showerhead electrode assemblies can be in fluid communication with temperature-control elements spatially separated from the showerhead electrode to control the showerhead electrode temperature. Methods of processing substrates in plasma processing chambers including the showerhead electrode assemblies are also disclosed. | 2008-10-02 |
20080242086 | PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS - A plasma processing method, for performing a plasma process on a target substrate by generating a plasma between an upper electrode and a lower electrode facing each other by means of applying a radio frequency power therebetween, includes applying a DC voltage of a positive or negative polarity to an inner electrode of an electrostatic chuck on the lower electrode to attract and hold the target substrate thereon; and changing the positive or negative polarity of the DC voltage applied to the inner electrode of the electrostatic chuck to an opposite polarity thereto between a time when the application of the radio frequency power from the radio frequency power supply is started to perform the plasma process of the target substrate and a time when the plasma process is completed. | 2008-10-02 |
20080242087 | MAGNETRON SPUTTERING APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A magnetron sputtering apparatus includes: a target provided in a sputtering chamber; a susceptor opposed to the target; a high-frequency power supply connected to the susceptor; a plate provided outside the sputtering chamber and coaxial with a central axis of the target; a rotary motion mechanism configured to rotate the plate about the central axis; S-pole magnets placed on one side of the plate with their S-pole end directed to the target; and first and second N-pole magnets placed on the one side of the plate with their N-pole end directed to the target. The first N-pole magnets are placed along a circle coaxial with the plate and opposed to an outer peripheral vicinity of the target. The S-pole magnets are placed inside the first N-pole magnets and along a circle coaxial with the plate. The second N-pole magnets are placed inside the S-pole magnets and along a circle coaxial with the plate. Magnetic flux density of the first N-pole magnets and the second N-pole magnets are higher than magnetic flux density of the S-pole magnets. | 2008-10-02 |
20080242088 | METHOD OF FORMING LOW RESISTIVITY COPPER FILM STRUCTURES - A method for forming low (electrical) resistivity Cu film structures by depositing a metal nitride barrier film on a substrate, depositing a Ru film on the metal nitride barrier film, depositing a Cu seed layer on the Ru film, and depositing bulk Cu metal on the Cu seed layer. The method further includes heat treating the Ru film prior to the Cu seed layer deposition, heat treating the bulk Cu metal, or heat treating both the Ru film prior to the Cu seed layer deposition and the bulk Cu metal. According to one embodiment, a method is provided for forming low resistivity Cu interconnect structures for integrated circuits. | 2008-10-02 |
20080242089 | Method for Distributed Processing at Copper CMP - A method of manufacturing a semiconductor device. A first thickness of a copper layer located over a semiconductor substrate is removed by chemical-mechanical polishing (CMP) on a first platen using a first polishing slurry. The copper layer is located over a barrier layer. A remaining thickness of the copper layer is removed on a second platen using a second polishing slurry. A portion of the barrier layer on the second platen is removed using a third polishing slurry. The third polishing slurry has a substantially different composition from the second polishing slurry. | 2008-10-02 |
20080242090 | METAL-POLISHING LIQUID AND POLISHING METHOD - A metal-polishing liquid used for chemical-mechanical polishing of a conductor film of copper or a copper alloy in a process for manufacturing a semiconductor device, the metal-polishing liquid comprising: (1) an amino acid derivative represented by the formula (I); and (2) a surfactant, | 2008-10-02 |
20080242091 | METAL-POLISHING LIQUID AND POLISHING METHOD - A metal-polishing liquid used for chemical and mechanical polishing of copper wiring in a semiconductor device, the metal-polishing liquid comprising: (a) a tetrazole compound having a substituent in the 5-position; (b) a tetrazole compound not substituted in the 5-position; (c) abrasive grains; and (d) an oxidizing agent. | 2008-10-02 |
20080242092 | METHOD OF MANUFACTURING SPACER - A method of manufacturing an L-shaped spacer is described. First, a substrate is provided and a protruding structure is formed thereon. Next, a dielectric material is formed on the substrate and covers the stacked structure. Then, the dielectric material on the top of the protruding structure and on portions of the substrate is removed to form an L-shaped spacer. | 2008-10-02 |
20080242093 | Method for manufacturing semiconductor integrated circuit device - Cracks are generated in a resist film part used to form an opening part in a photoreceptor part, whereby etching is performed as far as the inter-layer insulating film in unintended portions. In order to prevent this, the resist pattern used as an etching mask is formed in a shape that disperses the stress. The stress is generated because the resist is hardened by post baking after having been exposed and developed. In order to disperse the stress, the opening part of the resist pattern is formed in a planar shape that has no corners. | 2008-10-02 |
20080242094 | METHOD OF MAKING A SEMICONDUCTOR STRUCTURE UTILIZING SPACER REMOVAL AND SEMICONDUCTOR STRUCTURE - A method for making a semiconductor structure ( | 2008-10-02 |
20080242095 | Method for forming trench in semiconductor device - A method for fabricating a trench in a semiconductor device includes forming a mask pattern over a substrate, and etching the substrate to form a trench with a vertical profile, the etching performed at an etching rate of approximately 40 A/sec or less using an etching gas including a gas generating polymers | 2008-10-02 |
20080242096 | METHOD FOR PREPARING BOTTLE-SHAPED DEEP TRENCHES - A method for preparing a bottle-shaped deep trench first forms a first mask with at least one opening on a substrate including a first epitaxy layer, an insulation layer on the first epitaxy layer and a second epitaxy layer on the insulation layer. A first etching process is performed to remove a portion of the substrate under the opening down to the interior of the insulation layer to form a trench, and a thermal treating process is then performed to form a second mask on the inner sidewall of the trench. Subsequently, a second etching process is performed to remove a portion of the substrate under the opening down to the interior of the first epitaxy layer to form a deep trench, and a third etching process is performed to remove a portion of the first epitaxy layer so as to form the bottle-shaped deep trench with an enlarged surface. | 2008-10-02 |
20080242097 | Selective deposition method - The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants. | 2008-10-02 |
20080242098 | Method for forming pattern in semiconductor device - A method for forming a pattern in a semiconductor device includes forming an etch target layer over a substrate, forming a hard mask pattern over the etch target layer, and etching the etch target layer using the hard mask pattern as an etch mask and a gas mixture including a fluorine (F)-based gas and a bromine (Br)-based gas as an etch gas to form a target pattern. | 2008-10-02 |
20080242099 | Method for forming contact hole using dry and wet etching processes in semiconductor device - A method for forming a contact hole in a semiconductor device includes forming an insulation layer over a substrate, forming a hard mask pattern over the insulation layer, forming a first contact hole by partially etching the insulation layer, forming a spacer on sidewalls of the first contact hole, forming a second contact hole to expose the substrate by etching the remaining insulation layer within the first contact hole, forming a third contact hole by horizontally etching the second contact hole, wherein a line width of the third contact hole is wider than that of the first contact hole, and removing the hard mask pattern and the spacer. | 2008-10-02 |
20080242100 | SEMICONDUCTOR DEVICE AND FABRICATIONS THEREOF - A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask. | 2008-10-02 |
20080242101 | Process Control Method in Spin Etching and Spin Etching Apparatus - The present invention provides a process control method in spin etching capable of realizing uniformity in etching amount in etching treatment for even wafers each having various conditions, and achieving uniformity of thickness values among etched wafers. In the present invention, weight of a wafer before etching is measured in units of 1/1000 g, followed by predetermined etching treatment in a spin etching section. Thereafter, weight of the wafer is again measured in units of 1/1000 g after rinsing and drying treatment of the wafer, and then an actual etching amount is calculated from a difference between weight before and after etching of the wafer, confirming an etching rate each time etching to thereby control an etching time. | 2008-10-02 |
20080242102 | CHEMISTRY FOR REMOVAL OF PHOTO RESIST, ORGANIC SACRIFICAL FILL MATERIAL AND ETCH POLYMER - Methods and associated structures of forming a microelectronic device are described. Those methods may include utilizing a cleaning mixture comprising a solvent such as ethylene glycol monopropyl ether, an inorganic base, an organic base, a copper corrosion inhibitor and a surfactant to clean at least one of a polymer residue, a organic sacrificial fill material and etched or un-etched photo resist from a Damascene structure of a microelectronic structure comprising a porous oxide dielectric. | 2008-10-02 |
20080242103 | Method of manufacturing semiconductor device and semiconductor manufacturing apparatus - A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third process of etching the semiconductor substrate having the second temperature by etching liquid having a third temperature, a fourth process of cleaning the semiconductor substrate to which the etching liquid is adhered, by ultrapure water having a fourth temperature, wherein the second temperature is set at the range between the first and the third temperatures. | 2008-10-02 |
20080242104 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THEREOF AND MASK FOR DIVIDING EXPOSURE - A method of manufacturing a semiconductor device has a first exposure to the photoresist by using a first mask having a first portion of a monitor pattern, a second exposure to the photoresist by using a second mask having a second portion of the monitor pattern so that a first image of the first portion and a second image of the second portion are connected. | 2008-10-02 |
20080242105 | Semiconductor manufacturing apparatus, semiconductor wafer manufacturing method using this apparatus, and recording medium having program of this method recorded therein - Foreign particles are prevented from adhering to a semiconductor wafer in a semiconductor manufacturing apparatus including (a) a hot plate which heats a semiconductor wafer to increase its temperature and which has a suction/discharge hole through which a negative pressure is supplied to suck and hold said semiconductor wafer at a rear surface thereof, and through which a gas is ejected to control the increase in temperature of said semiconductor wafer; and (b) a film forming section which forms a film used for production of a semiconductor device on a front surface of the semiconductor wafer, wherein the gas is ejected from the suction/discharge hole when the hot plate is placed on the film forming section and the hot plate does not hold the semiconductor wafer. | 2008-10-02 |
20080242106 | CHEMICAL MECHANICAL POLISHING METHOD AND APPARATUS FOR REDUCING MATERIAL RE-DEPOSITION DUE TO pH TRANSITIONS - A CMP apparatus and process reduces material re-deposition due to pH transitions. The CMP process reduces the re-deposition of material by performing a water rinse between CMP stages. A CMP apparatus, which performs CMP process, may reduce re-deposition by including a water rinse between two CMP stages that utilize different pH slurries. | 2008-10-02 |
20080242107 | Method for manufacturing a semiconductor device by using an ALD technique - A method for manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon substrate, and forming a silicon nitride film on the silicon oxide film. The step of forming the silicon nitride film includes the steps of growing a first silicon layer having a thickness larger than a thickness of a monoatomic silicon layer, nitriding the first silicon layer to form a first silicon nitride layer, growing a second silicon layer on the first silicon layer on the first silicon nitride layer, and nitriding the second silicon oxide layer to form a second silicon nitride layer. | 2008-10-02 |
20080242108 | Method for fabricating semiconductor device - A method for fabricating a semiconductor device is disclosed. The method includes providing a first chamber and a second chamber. The first chamber and the second chamber are connected by a pressure differential unit, for depositing a metallic film over a substrate in the first chamber, transferring the substrate to the second chamber via the pressure differential unit without exposing the substrate to the ambient environment, and depositing a silicon-containing film on the metallic film in the second chamber. | 2008-10-02 |
20080242109 | METHOD FOR GROWING A THIN OXYNITRIDE FILM ON A SUBSTRATE - A method for growing an oxynitride film on a substrate includes positioning the substrate in a process chamber, heating the process chamber, flowing a wet process gas comprising water vapor and a nitriding gas comprising nitric oxide into the process chamber. The wet process gas and the nitriding gas form a processing ambient that reacts with the substrate such that an oxynitride film grows on the substrate. In yet another embodiment, the method further comprises flowing a diluting gas into the process chamber while flowing the wet process gas to control a growth rate of the oxynitride film. In another embodiment, the method further comprises annealing the substrate and the oxynitride film in an annealing gas. According to embodiments of the method where the substrate is silicon, a silicon oxynitride film forms that exhibits a nitrogen peak concentration of at least approximately 6 atomic % and an interface state density of less than approximately 1.5×10 | 2008-10-02 |
20080242110 | Capping Layer Formation Onto a Dual Damescene Interconnect - A process for the formation of a capping layer on a conducting interconnect for a semiconductor device is provided, the process comprising the steps of: (a) providing one or more conductors in a dielectric layer, and (b) depositing a capping layer on an upper surface of at least some of the one or more conductors, characterised in that the process further includes: (c) the step of, prior to depositing the capping layer, reacting the dielectric layer with an organic compound in a liquid phase, the said organic compound having the following general formula: (I) where X is a functional group, R is an organic group or a organosiloxane group, Y1 is either a functional group or an organic group or organosiloxane group, and Y2 is either a functional group or an organic group or organosiloxane group, and where the functional group(s) is/are independently selected from the following: NH2, a secondary amine, a tertiary amine, acetamide, trifluoroacetamide, imidazole, urea, OH, an alkyoxy, acryloxy, acetate, SH, an alkylthiol, sulfonate, methanosulfonate, and cyanide, and salts thereof. | 2008-10-02 |
20080242111 | Atomic layer deposition of strontium oxide via n-propyltetramethyl cyclopentadiendyl precursor - A method of depositing oxide materials on a substrate is provided. A deposition chamber holds the substrate, where the substrate is at a specified temperature, and the chamber has a chamber pressure and wall temperature. A precursor molecule containing a cation material atom is provided to the chamber, where the precursor has a line temperature and a source temperature. An oxidant is provided to the chamber, where the oxidant has a source flow rate. Water is provided to the chamber, where the water has a source temperature. By alternating precursor pulses, the water and the oxidant are integrated with purges of the chamber to provide low contamination levels and high growth rates of oxide material on the substrate, where the pulses and the purge have durations and flow rates. A repeatable growth cycle includes pulsing the precursor, purging the chamber, pulsing the water, pulsing the oxidant, and purging the chamber. | 2008-10-02 |
20080242112 | PHASE-SEPARATED DIELECTRIC STRUCTURE FABRICATION PROCESS - A process for fabricating an electronic device including: depositing a layer comprising a semiconductor; liquid depositing a dielectric composition comprising a lower-k dielectric material, a higher-k dielectric material, and a liquid, wherein the lower-k dielectric material and the higher-k dielectric material are not phase separated prior to the liquid depositing; and causing phase separation of the lower-k dielectric material and the higher-k dielectric material to form a phase-separated dielectric structure wherein the lower-k dielectric material is in a higher concentration than the higher-k dielectric material in a region of the dielectric structure closest to the layer comprising the semiconductor, wherein the depositing the layer comprising the semiconductor is prior to the liquid depositing the dielectric composition or subsequent to the causing phase separation. | 2008-10-02 |
20080242113 | FILM FORMING METHOD OF HIGH-K DIELECTRIC FILM - A method for forming a high-K dielectric film on a silicon substrate includes the steps of processing a surface of the silicon substrate with a diluted hydrofluoric acid, conducting nucleation process of HfN, after the step of processing with the diluted hydrofluoric acid, by supplying a metal organic source containing Hf and nitrogen to the surface of said silicon substrate, and forming an Hf silicate film by a CVD process, after the step of nucleation, by supplying a metal organic source containing Hf and a metal organic source containing Si to the surface of the silicon substrate. | 2008-10-02 |
20080242114 | THERMAL ANNEAL METHOD FOR A HIGH-K DIELECTRIC - A method of manufacturing a semiconductor device is provided. In one embodiment, the method provides for the formation, over a substrate, of a dielectric layer having a high dielectric constant. This dielectric layer may be exposed to a nitrogen plasma after which it may be annealed in a hydrogen containing ambient. | 2008-10-02 |
20080242115 | Semiconductor device and method for manufacturing semiconductor device - A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics. | 2008-10-02 |
20080242116 | Method for forming strained silicon nitride films and a device containing such films - A method for forming a strained SiN film and a semiconductor device containing the strained SiN film. The method includes exposing the substrate to a gas including a silicon precursor, exposing the substrate to a gas containing a nitrogen precursor activated by a plasma source at a first level of plasma power and configured to react with the silicon precursor with a first reactivity characteristic, and exposing the substrate to a gas containing the nitrogen precursor activated by the plasma source at a second level of plasma power different from the first level and configured to react with the silicon precursor with a second reactivity characteristic such that a property of the silicon nitride film formed on the substrate changes to provide the strained silicon nitride film. | 2008-10-02 |
20080242117 | APPARATUS TO REDUCE WAFER EDGE TEMPERATURE AND BREAKAGE OF WAFERS - In some embodiments radiation incident on a wafer is provided to perform an annealing process, and the wafer is cooled at an edge portion to reduce temperature and stress on the wafer. Other embodiments are described and claimed. | 2008-10-02 |
20080242118 | METHODS FOR FORMING DENSE DIELECTRIC LAYER OVER POROUS DIELECTRICS - Methods for forming a dense dielectric layer over the surface of an opening in a porous inter-layer dielectric having an ultra-low dielectric constant are disclosed. The disclosure provides methods for exposing the sidewall surface and the bottom surface of the opening to a plurality of substantially parallel ultra-violet (UV) radiation rays to form a dense dielectric layer having a substantially uniform thickness over both the sidewall surface and the bottom surface. | 2008-10-02 |
20080242119 | Bus connector with at least two cable connections for bus lines - There is described a bus connector with at least two cable connections for bus lines, with the cable connections being provided in each case for electrical connection to a bus signal line and a bus screen line of a cable, with a screen connector of the cable connection being provided for electrical contacting of the bus screen connection of the cable to the elements screening the bus connector. The screen connector is embodied as a flat screening of the cable connections and contact elements are arranged in the area of the contacting of the bus screen lines which are intended for automatic contacting of the bus screen lines with the elements of the bus connector screening it when clamped on during installation of the housing. | 2008-10-02 |
20080242120 | Right-Angle Coaxial Connector - An electrical connector and connection system are disclosed having an array of conductive coaxial pairs. Each pair consists of a cylindrical electrical conductor surrounded by a tubular electrically conductive shield with a dielectric insulator disposed there-between. A rigid connector housing contains the coaxial pairs in a fixed spaced parallel relationship. The housing has first and second interfaces relatively disposed at a right angle, and the conductors and shields each have connector pins extending from said interfaces for connection to a printed circuit board or a connector base. The coaxial pairs follow parallel curvilinear paths between the interfaces having two consecutive bends of forty-five angular degrees. | 2008-10-02 |
20080242121 | REDUCED SOCKET SIZE WITH PIN LOCATIONS ARRANGED INTO GROUPS WITH COMPRESSED PIN PITCH - In some embodiments a socket and/or a package includes a plurality of groups of pin locations including at least a first group of pin locations and a second group of pin locations. Each group of pin locations includes a standard pin pitch in a direction between pin locations of the group to allow a maximum breakout from a center of the socket and/or package to an outside of the socket and/or package. Each group of pin locations includes a minimum pin pitch in a direction orthogonal to a direction of the standard pin pitch. Other embodiments are described and claimed. | 2008-10-02 |
20080242122 | Electrical connector - An electrical connector ( | 2008-10-02 |
20080242123 | Socket for land grid array package - A land grid array socket and a microelectronic assembly including the socket. The socket comprises: a housing; an array of through-contacts on the housing; a solder ball standoff element on a PCB side of the housing; and a seating plane standoff element on a package side of the housing, the seating plane standoff element being aligned with the solder ball standoff element to form a loading force support element therewith. | 2008-10-02 |
20080242124 | BUSBAR UNIT - A busbar unit includes a busbar holder and a plurality of busbars. The busbar holder has a first surface and a second surface on both sides in an axial direction, respectively. The first surface is provided with grooves in which one or more busbars are accommodated. The busbar in the groove of the first surface is provided with a wire connector portion on the first surface. The second surface is also provided with grooves accommodating remaining busbar (s) therein. The busbar (s) in the groove of the second surface is provided with a wire connector portion on the second surface. To each wire connector portion, a conductive wire forming a coil winding of an armature of a motor is connected. | 2008-10-02 |
20080242125 | Large LGA socket and method of manufacture - An LGA interconnect device, method of making, and device for making. | 2008-10-02 |
20080242126 | CIRCUIT BOARD ASSEMBLY - A circuit board assembly includes a circuit board, at least a conductive contact and a metal shielding device. The conductive contact is extended from a lateral edge of the circuit board and is electrically connected to the circuit board. The circuit board and the conductive contact are received in the metal shielding device with the conductive contact electrically connected to the metal shielding device. The conductive contact tightly contacts with the metal shielding device by the elasticity of the conductive contact, and the circuit board assembly can remove a static using the metal shielding device and avoid the contact failure. In addition, the conductive contact can be manufactured in manufacturing of the circuit board, the man-hour and human for affixing the conduct foam is leave out and cost is decreased. | 2008-10-02 |
20080242127 | TRANSCEIVER RECEPTACLE ASSEMBLY - A receptacle assembly for a transceiver module includes a transceiver cage that is configured to receive the transceiver module. The transceiver cage is configured to be mounted proximate a cutout in a circuit board such that a portion of the transceiver cage extends through the cutout. A connector is configured to mate with the transceiver module and is disposed within the cage. The transceiver cage and the connector are configured to be mounted on the same surface of a circuit board. | 2008-10-02 |
20080242128 | Elastomeric electrical contact - An electrical contact is provided that includes an elastomeric body extending between a base portion and a mating end portion. The elastomeric body includes a ledge extending from the mating end portion to the base portion of the elastomeric body. The ledge is defined by a portion of the elastomeric body. An electrically conductive pad extends over at least a portion of the mating end portion. An electrically conductive trace is formed on a surface of the ledge. The electrically conductive trace extends from the mating end portion to the base portion of the elastomeric body. The electrically conductive trace is in electrical contact with the electrically conductive pad for electrically connecting the electrically conductive pad with an electrically conductive element engaging the base portion of the elastomeric body. | 2008-10-02 |
20080242129 | Universal two-hole electrical bond washer - The INVENTION is a single, two-hole, electrical bond washer which replaces individual single-hole flat washers that are used in the process of bonding electrical wire lugs to ground bars for protection against lightning. | 2008-10-02 |
20080242130 | METHODS AND APPARATUS FOR BATTERY CONTACT ASSEMBLY - Methods and apparatus for a batter contact assembly having a compact profile for efficient use of space and reliable battery connections. In one embodiment, the assembly is of unitary construction with hinges and engagement mechanism to facilitate installation of the assembly into a device requiring battery power. | 2008-10-02 |
20080242131 | CABLE CONNECTOR - A cable connector includes a housing and a first contact provided in the housing. The first contact includes a first engaging and pivoting unit opposed to a back surface of the cable. The cable connector also includes a second contact which is provided in the housing and which includes a second engaging and pivoting unit opposed to the back surface of the cable. The second engaging and pivoting unit has a root which is thicker than that of the first engaging and pivoting unit. The cable connector also includes a cover. The cover includes a first through hole into which the first engaging and pivoting unit is inserted, a first cam unit engaged with the first engaging and pivoting unit, a second through hole into which the second engaging and pivoting unit is inserted, and a second cam unit engaged with the second engaging and pivoting unit. | 2008-10-02 |
20080242132 | Electrical connection for high humidity and low temperature environments - A plug and socket electrical connection for environments with high humidity and low temperatures has a socket with female connections (holes with an electrical terminals), a circular recess for receiving a mating part and tabs and a plug with a male connection (electrodes), the mating part and hooks. The electrical connections are protected from moisture by a snug fit and o-rings when the socket and the plug are electrically connected and the tabs and hooks hold the socket and plug together in place. The socket and plug are disconnected by movement of a handle holding the hooks that is part of the plug and can act as a lever to help the disconnection. The handle also provides a convenient finger hold for pulling the plug away from the socket. | 2008-10-02 |
20080242133 | Adapter - An adapter for the coupling of two different electrical plugs, in particular for vehicles, comprises an electrically conductive cage open at two ends, in particular pin-like electrical contacts insertable into the cage with differing contact ends matched to the respective plug and in particular two differing insulation parts insertable into the cage and matched to the respective plug for the fixing of the electrical contacts. The cage, the electrical contacts and the insulation parts supporting them are designed such that different receptacle-like plug receivers matched to the respective plug result in the region of the two open ends of the cage. | 2008-10-02 |
20080242134 | High-Voltage Connector - A high-voltage connector is described, having a plug ( | 2008-10-02 |
20080242135 | CONNECTOR RECEPTACLE - In a connector receptacle ( | 2008-10-02 |
20080242136 | AIRTIGHT ELECTRICAL SOCKET - A water and/or airtight electrical socket for portable electronic devices includes sealing elements that are shaped like an arc, and arranged to seal only a portion of the perimeter of the socket-plug interface. When this arc element experiences pressure, it will mechanically relay the force caused by the pressure only to that section of the perimeter of the socket-plug interface that it is arranged to seal. It will not relay mechanical forces any further. This way, the mechanical effect of any extra asymmetric pressure will simply be limited to increasing the pressure of the seal in the perimeter section of that particular sealing element, thereby tightening the seal further still. This allows the socket opening to be sealed in a water- and/or airtight manner even in asymmetric pressure conditions, both when there is no plug in the socket and also when a plug is inside the socket. | 2008-10-02 |
20080242137 | SINGLE STEP OPERATION CONNECTOR ASSEMBLY - A connector assembly is presented. The assembly includes a first connector including a pilot terminal and a plurality of first terminals. Further, the assembly includes a second connector including a plurality of second terminals, where the second connector is configured to be releasably coupled with the first connector. In addition, the assembly includes a housing disposed about the second connector and in operative association with the second connector. The assembly also includes a coupling mechanism in operative association with the second connector, where the coupling mechanism is configured to aid in coupling the first connector and the second connector with use of a first force, and where the coupling mechanism includes a lever mechanism having a Clevis mechanism. The pilot terminal is configured to facilitate coupling of the first connector and the second connector. | 2008-10-02 |
20080242138 | Socket connector assembly with pick-up cap - A socket connector assembly ( | 2008-10-02 |
20080242139 | Connector and Line Connecting Method Thereof - To reduce as much as possible an outer size of a connector having an insulation-displacement type wire connection structure without deteriorating stability and reliability of connection between terminal elements and conductors. A connector ( | 2008-10-02 |
20080242140 | MALE CONNECTOR AND MATCHED FEMALE CONNECTOR THEREOF - A male connector includes a main body, a plug extending from an end of the main body, and two elastic members attached to opposite sides of the main body. An end of each of the elastic members is secured to the main body near the end thereof, and the remaining portion of each of the elastic members is cantilevered towards an opposite end of the main body. Each of the elastic members includes a locking portion attached thereto configured for engaging with a female connector. | 2008-10-02 |
20080242141 | Wire Containment Cap - A wire containment cap has twisted pair slots for routing twisted wire pairs through the wire containment cap. The twisted pair slots are provided with funnel-shaped entrances to assist in routing the twisted wire pairs from a rear end of the wire containment cap toward wire slots of the wire containment cap. The wire containment cap may be provided in shielded or unshielded versions, and is adapted for use with a communication jack assembly. | 2008-10-02 |
20080242142 | Connector - A connector includes a shell, a housing, and a plurality of terminals. The shell with a tubular shape has a first opening and a second opening. The housing includes a housing body portion, a holding portion, and a protruding portion. The housing body portion covers the second opening. The holding portion extends from the housing body portion to the first opening and holds the terminals. The protruding portion extends from a rear side of the housing body portion to the second opening side. The shell has first and second tongue portions that extend in a direction perpendicular to a fitting direction of a mating connector. Each of the first and second tongue portions is caulked in the protruding portion from an upper side and a lower side to cover the protruding portion. The second tongue portion has a board connection portion to be connected to a board. | 2008-10-02 |
20080242143 | CABLE CONNECTOR - A cable connector includes a housing, a first contact having a first contact unit opposed to a front surface of a cable and an engaging and pivoting unit opposed to a back surface of the cable, a second contact which is provided in the housing and which has a second contact unit opposed to the front surface of the cable and a wall opposed to the back surface of the cable, and a cover which is turnably supported on the engaging and pivoting unit by a through hole into which the engaging and pivoting unit is inserted and a cam unit engaged with the engaging and pivoting unit. The engaging and pivoting unit is engaged with the cam unit so that the cover can move in an inserting and releasing direction of the cable. The wall limits movement of the cover in an inserting direction of the cable. | 2008-10-02 |
20080242144 | Device for holding at least two connecting cables - The invention relates to a device ( | 2008-10-02 |
20080242145 | Connector socket module and electronic device using the same - A connector socket module having a reduced height used in a server is disclosed, the connector socket module including plural connector sockets, a relay board having a pattern of wiring electrically connected to the connector sockets provided on a front side of the relay board, a relay connector provided on a rear side of the relay board and electrically connected to the connector socket through the wiring, and a main board supporting unit extending from the rear side of relay board and supporting a main board at a prescribed height between upper and lower ends of the relay board, the main board having a main-board-side connector connected to the relay connector. | 2008-10-02 |
20080242146 | Connector substrate and speaker input terminal connection structure - In a connector substrate to which are soldered input terminals of a speaker and lead wires connected to an output terminal of a printed circuit board, the connector substrate is flat and approximately rectangular, and snap-off portions for, by being snapped off in a predetermined size, moving extreme positions of a longitudinal direction of the connector substrate, by a predetermined distance, toward an opposite extreme, are formed at either extreme of the longitudinal direction of the connector substrate. | 2008-10-02 |
20080242147 | Headset with data connector - This application is directed to a headset having an integrated data connector (e.g., a USB female connector). The headset may include an electronic device interfacing portion that may include a USB male connector and a 3.5 mm jack for engaging an electronic device. The headset may also include an acoustic portion that may include at least acoustic element (e.g., speaker) and a USB female connector. To connect the electronic device to a host device (e.g., to transfer music files or recharge the electronic device's battery), the USB connector of the electronic device interfacing portion can engage the host device. To provide audio to a user, the USB connector of the acoustic portion can engage the electronic device interfacing portion, which provides a path from the electronic device to the acoustic element for audio signals. This approach allows a user to use a single cable for connecting the electronic device to both the host device and the acoustic element. | 2008-10-02 |
20080242148 | Connector device - A disclosed plug connector is configured to be plugged into and connected to a receiving connector. The plug connector includes plural signal contact members arranged along a circumferential direction, and a cylindrical ground unit surrounding an outer peripheral side of the signal contact members. | 2008-10-02 |