40th week of 2008 patent applcation highlights part 62 |
Patent application number | Title | Published |
20080241949 | Process for preparing quetiapine fumarate - Provided is an improved synthesis of quetiapine and pharmaceutically acceptable salts. | 2008-10-02 |
20080241950 | Nucleic Acid Sequencing In Free Solution Using Protein Polymer Drag-Tags - The present invention relates to systems, compositions, and methods for nucleic acid sequencing and analysis in free-solution using protein polymer drag-tags. As such, the present invention provides protein-based molecular compositions that find use as drag-tags for use in sequencing and nucleic acid analysis methods and provides systems and methods for automated sequencing and analysis of nucleic acids in free solution. | 2008-10-02 |
20080241951 | METHOD AND APPARATUS FOR MOVING STAGE DETECTION OF SINGLE MOLECULAR EVENTS - An apparatus and method based on the apparatus is disclosed for detecting and monitoring chemical and/or bio-chemical reactions or interactions at the single molecule level, where detection and monitoring is improved by moving the viewing field of the detector in a controlled manner. The motion of the moving frame is accomplished either through software in the detector system or is accomplished by moving the reacting system. The motion is controlled and is either linear, circular or elliptical. The motion provides for improved site identification or mapping, improved event detection and monitoring, improved signal recognition and improved noise reduction. | 2008-10-02 |
20080241952 | Sensor with Holographic Multiplexed Image Display - A holographic sensor comprising a thin film polymer matrix that undergoes a change in response to a substance to be sensed, the matrix containing within its volume a set of two or more holographic recordings, each recording providing a holographic image when the sensor is illuminated, wherein the presence or appearance of each image is visible to the eye as a function of the response of the sensor to the substance to be sensed. The images provide the dynamic range of the sensor. Such a sensor can be used to provide a visible image that changes or appears to the eye in response to an analyte. | 2008-10-02 |
20080241953 | Method and Apparatus for Patterning a Bibulous Substrate - A method of patterning a bibulous substrate is disclosed. The method comprises contacting the bibulous substrate with a first surface being coated by a barrier compound, using a second surface having a predetermined pattern engraved thereon, and applying heat and pressure onto the first surface such as to pattern the bibulous substrate in a predetermined pattern. | 2008-10-02 |
20080241954 | METHODS FOR DETERMINING THE STATUS OF COPD IN HUMANS - A method of determining the status of chronic obstructive pulmonary disease (COPD) of a human that includes the steps of performing a spectral analysis of a sputum sample collected from the human; comparing the spectra produced by the analysis against a reference; and determining the status of COPD in the human based upon any determined variations. | 2008-10-02 |
20080241955 | Methods, Mixtures, Kits And Compositions Pertaining To Analyte Determination - This invention pertains to methods, mixtures, kits and compositions pertaining to analyte determination by mass spectrometry using labeling reagents that comprise a nucleophilic reactive group that reacts with a functional group of an analyte to produce a labeled analyte. The labeling reagents can be used as isobaric sets, mass differential labeling sets or in a combination of isobaric and mass differential labeling sets. | 2008-10-02 |
20080241956 | METHOD FOR DETECTING ANALYTE AND BIOCHIP - A method for detecting an analyte in a sample liquid, using a detection reagent which reacts specifically with the analyte to give structural information on the analyte, comprising the steps of:
| 2008-10-02 |
20080241957 | Sample analyzer, sample analyzing method, and computer program product - A sample analyzing method comprising: aspirating a sample from a sample container; preparing a plurality of measurement samples from the aspirated sample; sequentially measuring the plurality of prepared measurement samples; obtaining a plurality of measurement data for the respective measurement samples; and obtaining an analysis result of a predetermined item of the sample based on the plurality of measurement data, is disclosed. A sample analyzer and a computer program product are also disclosed. | 2008-10-02 |
20080241958 | Method for Determining HCG Levels in Fluid Samples - The subject invention is an immunoassay for the semi-quantitative test kit for determination of human chrionic gonadtropin (hCG) in fluid sample (such as urine) as an aid in the diagnosis of a certain stage of pregnancy. The test device includes five strips having each having a dipping end or sample ends where sample can be applied. Results are indicated by coloration of two bands across a clear area of the strips, one band being coated with a reagent such as hCG antigens and the other with a reagent such as goat/rabbit polyclonal antibody gold conjugate. The combination of color indications on the bands provides the test results. | 2008-10-02 |
20080241959 | Macrolide Compounds Containing Biotin and Photo-Affinity Group for Macrolide Target Identification - The present invention relates to new macrolide compounds represented by the general structure I, | 2008-10-02 |
20080241960 | INSULIN-LIKE GROWTH FACTOR BINDING PROTEIN - Using the proteins of the present invention, DNAs encoding the proteins, and antibodies recognizing the proteins, detection methods for diseases relating to the novel insulin-like growth factor binding proteins of the present invention, as well as diagnostic agents, preventive agents, and therapeutic agents for diseases relating to the proteins of the present invention can be provided. | 2008-10-02 |
20080241961 | DROSOPHILA G PROTEIN COUPLED RECEPTORS, NUCLEIC ACIDS, AND MEHTODS RELATED TO THE SAME - The present invention provides a | 2008-10-02 |
20080241962 | Micromachined Diagnostic Device with Controlled Flow of Fluid and Reaction - This invention relates to a micromachined microfluidics diagnostic device that comprises one or multiple assaying channels each of which is comprised a sample port, a first valve, a reaction chamber, a second valve, a fluid ejector array, a third valve, a buffer chamber, a capture zone and a waste chamber. Each of these device components are interconnected through microfluidic channels. This invention further relates to the method of operating a micromachined microfluidic diagnostic device. The flow of fluid in the microchannels is regulated through micromachined valves. The reaction of sample analytes with fluorescent tags and detection antibodies in the reaction chamber are enhanced by the micromachined active mixer. By ejecting reaction mixture onto the capture zone through micromachined fluid ejector array, the fluorescent tagged analytes bind with capturing antiodies on capture zone. The fluid ejector array further ejects buffer fluid to wash away unbound fluorescent tags. | 2008-10-02 |
20080241963 | BIOCHEMICAL LABELING MATERIALS AND MANUFACTURING METHOD THEREOF - A biochemical labeling material and manufacturing method thereof. The manufacturing method provides a plurality of nanoparticles, bonding the nanoparticles to template molecules by molecular imprinting, polymerizing the nanoparticles to form a matrix with uniformly-distributed template molecules, finally removing the template molecules from the matrix to reveal a detection group of the matrix, leaving a cavity with specific area. | 2008-10-02 |
20080241964 | MATERIAL FOR IMPROVING SENSITIVITY OF MAGNETIC SENSOR AND METHOD THEREOF - The present invention relates to a capture agent member being used in a magnetic sensor to detect the presence or concentration of a target substance in a test solution by detecting the presence or number of the magnetic marker, wherein the capture agent member contains a capture agent for capturing the target substance and a labeling agent serving as a nucleus for the magnetic marker to agglutinate, and wherein the capture agent is labeled with the labeling agent. The present invention relates to a material which improves detection sensitivity of a biosensor using a magnetic sensor while maintaining reactivity and dispersibility. In particular, according to the present invention, there can be provided a material which enables realization of high sensitivity by using a simple magnetic biosensor such as a semiconductor Hall element and a magnetoresistance effect element. | 2008-10-02 |
20080241965 | METHODS FOR VALIDATING THE PRESENCE OF AND CHARACTERIZING PROTEINS DEPOSITED ONTO AN ARRAY - A method of determining if proteins have been transferred from liquid-phase protein fractions to an array comprising staining the array with a total protein stain and imaging the array, optionally comparing the staining with a standard curve generated by staining known amounts of a known protein on the same or a similar array; a method of characterizing proteins transferred from liquid-phase protein fractions to an array including staining the array with a post-translational modification-specific (PTM-specific) stain and imaging the array and, optionally, after staining the array with a PTM-specific stain and imaging the array, washing the array, re-staining the array with a total protein stain, imaging the array, and comparing the imaging with the PTM-specific stain with the imaging with the total protein stain; stained arrays; and images of stained arrays. | 2008-10-02 |
20080241966 | Apparatuses and methods for detecting an analyte - A method and apparatus for detecting an analyte includes a sensor chamber for detecting an analyte, an analyte feed chamber, a distributor, and a controller for controlling the transport medium flow. The distributor includes an annular channel with four connections with a switchable isolating device between two connections. The controller controls the distributor for flushing the transport medium fed from the distributor to the sensor chamber without passing through the analyte feed chamber and for measuring the transport medium fed from the distributor to the sensor chamber while passing through the analyte feed chamber. | 2008-10-02 |
20080241967 | Radioimmunoassay using nanoparticle-antibody conjugates - A radioimmunoassay method for determining the quantity of an analyte of interest in a sample is disclosed. The analyte of interest may be an antigen or other chemical entity. A known antibody to the antigen or other entity is employed and is conjugated to a functionalized nanoparticle. Because of the high surface area presented by the present nanoparticle—antibody conjugates, the present radioimmunoassay method is particularly suited for the qualitative and quantitative analysis of low molecular weight chemicals. | 2008-10-02 |
20080241968 | MANUFACTURING METHOD, REMANUFACTURING METHOD AND RESHIPPING METHOD FOR A SEMICONDUCTOR MEMORY DEVICE - A manufacturing method, remanufacturing method and reshipping method for a semiconductor memory device capable of preventing the charge hold characteristic from deteriorating even if information data is repeatedly written and erased. The manufacturing method is for a semiconductor memory device having a plurality of memory cells in an FET structure formed on a semiconductor substrate, wherein each of the plurality of memory cells is to store a unit bit and hold information data. Preparing a plurality of memory cells, bits of the information data are written to the memory cells. After writing the information data bits to the memory cells, the memory cells are allowed to stand at a predetermined ambient temperature for a predetermined time. Thereafter, bits of the information data are written to the memory cells. | 2008-10-02 |
20080241969 | In-line lithography and etch system - The invention can provide a method of processing a wafer using Site-Dependent (S-D) processing sequences that can include S-D creation procedures, S-D evaluation procedures, and S-D transfer sequences. The S-D creation procedures can be performed using S-D processing elements, the S-D evaluation procedures can be performed using S-D evaluation elements, and S-D transfer sequences can be performed using site-dependent transfer subsystems. Site-dependent data can be stored in site-dependent libraries and/or databases. | 2008-10-02 |
20080241970 | Method and apparatus for performing a site-dependent dual damascene procedure - The present invention includes a method of performing a dual damascene procedure using Site-Dependent (S-D) procedures, the method including receiving a plurality of wafers and associated data by a S-D transfer subsystem coupled to a lithography-related subsystem, determining S-D wafer data for each wafer, establishing a first Dual Damascene processing sequence, determining a first set of S-D processing wafers to be processed, establishing real-time operational states for a plurality of first S-D processing elements in the lithography-related subsystem, transferring a first number of the first set of S-D processing wafers to a first number of the first S-D processing elements in the lithography-related subsystem and delaying other S-D wafers in the first set of S-D processing wafers for a first amount of time. | 2008-10-02 |
20080241971 | Method and apparatus for performing a site-dependent dual patterning procedure - The present invention includes a method of performing a double-patterning (DP) processing sequence using a plurality of Site-Dependent (S-D) procedures, the method including receiving a first set of wafers by one or more subsystems in a processing system, creating one or more first patterned layers on a first set of patterned wafers, establishing first confidence data for the first set of patterned wafers, establishing a first set of high confidence wafers, creating one or more second patterned layers on a second set of patterned wafers, establishing second confidence data for the second set of patterned wafers and establishing a second set of high confidence wafers. | 2008-10-02 |
20080241972 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE, PATTERN CORRECTION APPARATUS, AND COMPUTER-READABLE RECORDING MEDIUM - A method of manufacturing a semiconductor device includes measuring a first width of a first mask pattern formed in a photomask and a second width of a second mask pattern formed in the photomask, and deciding a temperature of heat treatment of a thickening material over a resist film based on measured results. | 2008-10-02 |
20080241973 | METHOD OF CORRECTING A MASK PATTERN AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The method of manufacturing a semiconductor device has deciding an amount of a correction of a mask pattern for a size of an active region of a semiconductor substrate, correcting the mask pattern on the basis of the decided amount of the correction, and exposing a resist film by using an exposure mask having the corrected mask pattern. | 2008-10-02 |
20080241974 | Determining photoresist parameters using optical metrology - To generate a simulated diffraction signal, one or more values of one or more photoresist parameters, which characterize behavior of photoresist when the photoresist undergoes processing steps in a wafer application, are obtained. One or more values of one or more profile parameters are derived using the one or more values, of the one or more photoresist parameters. The one or more profile parameters characterize one or more geometric features of the structure. A simulated diffraction signal is generated using the one or more values of the one or more profile parameters. The simulated diffraction signal characterizes behavior of light diffracted from the structure. The generated simulated diffraction signal is associated with the one or more values of the one or more photoresist parameters. The generated simulated diffraction signal, the one or more values of the one or more photoresist parameters, and the association between the generated simulated diffraction signal and the one or more values of the one or more photoresist parameters are stored. | 2008-10-02 |
20080241975 | Automated process control using optical metrology and photoresist parameters - To control a photolithography cluster using optical metrology, a structure is fabricated on a wafer using the photolithography cluster. A measured diffraction signal off the structure is obtained. The measured diffraction signal is compared to a simulated diffraction signal. The simulated diffraction signal is associated with one or more values of one or more photoresist parameters. The one or more photoresist parameters characterize behavior of photoresist when the photoresist undergoes processing steps in the photolithography cluster. The simulated diffraction signal was generated using one or more values of one or more profile parameters. The one or more values of the one or more profile parameters used to generate the simulated diffraction signal were derived from the one or more values of the one or more photoresist parameters associated with the simulated diffraction signal. If the measured diffraction signal and the simulated diffraction signal match, then one or more values of one or more photoresist parameters used in the photolithography cluster are determined to be the one or more values of the one or more photoresist parameters associated with the matching simulated diffraction signal. One or more process parameters or equipment settings of the photolithography cluster are adjusted based on the one or more values of the one or more photoresist parameters. | 2008-10-02 |
20080241976 | Semiconductor device production process - A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads. | 2008-10-02 |
20080241977 | Semiconductor device with electrode pad having probe mark - A semiconductor device is formed by bonding balls to a plurality of electrode pads formed on a semiconductor chip. After a wafer test is conducted by pressing a probe against the electrode pad, wire-bonding of the electrode pad to a lead is carried out so that a probe mark formed in the electrode pad during the wafer test is completely covered by a bonding ball, which forms an end of a wire connected to the lead. | 2008-10-02 |
20080241978 | LIGHT EMITTING DEVICE PROCESSES - Light-emitting devices, and related components, processes, systems and methods are disclosed. | 2008-10-02 |
20080241979 | Multi-directional light scattering LED and manufacturing method thereof - A multidirectional light scattering LED and a manufacturing method thereof are disclosed. A metal oxide is irregular disposed over a second semiconductor layer and then is removed by etching. Part of the second semiconductor layer, part of a light-emitting layer or part of the first semiconductor layer is also removed so as to form a scattering layer. A transparent conductive layer is arranged over the second semiconductor layer while further a second electrode is disposed over the transparent conductive layer. A first electrode is installed on the scattering layer. Thus light output from the LED is scattered in multi-directions. | 2008-10-02 |
20080241980 | LIQUID CRYSTAL DISPLAY - A thin film transistor array substrate including an insulating substrate, a first metallic pattern formed on the insulating substrate, and an insulating film provided on the first metallic pattern. A semiconductor pattern is provided on the insulating film, and a second metallic pattern is provided on the semiconductor pattern. The second metallic pattern is surrounded by the semiconductor pattern. | 2008-10-02 |
20080241981 | THIN FILM SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - A thin film semiconductor device is provided that includes a semiconductor thin film and a gate electrode. The semiconductor thin film has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part that is the active region overlapping with the gate electrode, a crystalline state is changed cyclically in a channel length direction, and areas each having a substantially same crystalline state traverse the channel part. | 2008-10-02 |
20080241982 | Vertical GaN-based LED and method of manufacturing the same - Provided are a vertical GaN-based LED and a method of manufacturing the same. The vertical GaN-based LED includes an n-electrode. An AlGaN layer is formed under the n-electrode. An undoped GaN layer is formed under the AlGaN layer to provide a two-dimensional electron gas layer to a junction interface of the AlGaN layer. A GaN-based LED structure includes an n-type GaN layer, an active layer, and a p-type GaN layer that are sequentially formed under the undoped GaN layer. A p-electrode is formed under the GaN-based LED structure. A conductive substrate is formed under the p-electrode. | 2008-10-02 |
20080241983 | Method of manufacturing nitride semiconductor light-emitting device - Provided is a method of manufacturing a nitride semiconductor light-emitting device including the step of contacting a surfactant material with the surface of an n-type nitride semiconductor layer or the surface of a p-type nitride semiconductor layer before the growth of an active layer, or, with a grown crystal surface during or after the growth of the active layer. According to this manufacturing method, a nitride semiconductor light-emitting device having higher light-emitting efficiency can be obtained. | 2008-10-02 |
20080241984 | METHOD FOR MANUFACTURING SEMICONDCUTOR SENSOR - A semiconductor sensor is disclosed that includes a substrate including at least a semiconductor layer. The substrate includes a weight arranging part in the vicinity of the center of the substrate, a flexible part around the weight arranging part, and supporting parts provided around the flexible part. The semiconductor sensor further includes a weight arranged on the weight arranging part. The weight is made of a material different from that of the weight arranging part and the flexible parts. | 2008-10-02 |
20080241985 | Microelectronic imaging units and methods of manufacturing microelectronic imaging units - Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes coupling a plurality of singulated imaging dies to a support member. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes forming a plurality of stand-offs on corresponding imaging dies before and/or after the imaging dies are singulated and electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member. The individual stand-offs include a portion between adjacent external contacts. | 2008-10-02 |
20080241986 | METHOD FOR FABRICATING A SILICON SOLAR CELL STRUCTURE HAVING AMORPHOUS SILICON LAYERS - Devices, solar cell structures, and methods of fabrication thereof, are disclosed. | 2008-10-02 |
20080241987 | METHOD FOR FABRICATING A SILICON SOLAR CELL STRUCTURE HAVING SILICON NITRIDE LAYERS - Devices, solar cell structures, and methods of fabrication thereof, are disclosed. | 2008-10-02 |
20080241988 | METHOD FOR FABRICATING A SILICON SOLAR CELL STRUCTURE HAVING A GALLIUM DOPED P-SILICON SUBSTRATE - Devices, solar cell structures, and methods of fabrication thereof, are disclosed. | 2008-10-02 |
20080241989 | OLED PATTERNING METHOD - A method of patterning a substrate according to several steps, including: a) mechanically locating a first masking film over the substrate; and b) segmenting the first masking film into a first masking portion and one or more first opening portions in first locations. Next, mechanically locate a first removal film over the first masking portion and first opening portions. Afterwards, one or more of the first opening portions are adhered to the first removal film. The first removal film and one or more of the first opening portions adhered to the first removal film are mechanically removed to form one or more first openings in the first masking film. Finally, materials are deposited over the substrate through the first openings in the first masking film. | 2008-10-02 |
20080241990 | METHOD FOR MANUFACTURING ORGANIC THIN FILM TRANSISTOR SUBSTRATE - A method for manufacturing an organic thin film transistor substrate comprising forming a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, defining a channel region on the gate insulating layer between a source electrode and a drain electrode, neutralizing the channel region, forming a bank insulating layer on the source electrode and the drain electrode, and forming an organic semiconductor layer in a region prepared by the bank insulating layer. | 2008-10-02 |
20080241991 | GANG FLIPPING FOR FLIP-CHIP PACKAGING - An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead frame panel includes an array of device areas, each including a plurality of leads. The method includes positioning a plurality of dice into designated positions on a carrier such that the active surfaces of the dice are facing upwards. The carrier includes a carrier frame including an associated array of carrier device areas. A lead frame panel may be positioned over the carrier such that the solder bumps on the active surfaces of the dice are adjacent and in contact with the associated leads of the associated device areas. | 2008-10-02 |
20080241992 | Method of assembling chips - A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material. | 2008-10-02 |
20080241993 | GANG FLIPPING FOR IC PACKAGING - A method of handling an IC wafer that includes a multiplicity of dice is described. Solder bumps are formed on bond pads on the active surface of the wafer. The back surface of the bumped wafer is adhered to a first mount tape. The wafer is singulated while it is still secured to the first tape to provide a multiplicity of individual dice. The active surfaces of the singulated dice are then adhered to a second tape with the first tape still adhered to the back surfaces of the dice. The first tape may then be removed. In this manner, the back surfaces of the dice may be left exposed and facing upwards with the active surfaces of the dice adhered to the second tape. The described method permits the use of a conventional die attach machine that is not designated for use as a flip-chip die attach machine. | 2008-10-02 |
20080241994 | Print Mask and Method of Manufacturing Electronic Components Using The Same - A print mask is used to form bumps on barrier metal layers of a wafer. The mask comprises a plurality of elongated perforations disposed in a linear arrangement such that paste can be applied to an object to be printed on via the perforations. Each of the perforations includes an edge disposed along the longitudinal direction, and the edge is inclined with respect to the direction perpendicular to the direction of arranging the perforations. | 2008-10-02 |
20080241995 | Adhesive Sheet For Both Dicing And Die Bonding And Semiconductor Device Manufacturing Method Using The Adhesive Sheet - An adhesive sheet for dicing and die bonding includes a base material and an adhesive layer releasably laminated on said base material, wherein said adhesive layer has a pressure sensitive adhering property at room temperature and a thermosetting property, the elastic modulus of the adhesive layer before thermosetting is 1.0×10 | 2008-10-02 |
20080241996 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes preparing a first semiconductor substrate having a first integrated circuit formed therein and including a plurality of first through substrate vias, and a second semiconductor substrate having a second integrated circuit formed therein and including a plurality of second through substrate vias, forming a solid-electrolytic layer on an upper surface of the first semiconductor substrate, mounting the second semiconductor substrate on the solid-electrolytic layer such that a lower surface of the second semiconductor substrate comes into contact with the solid-electrolytic layer, and applying a voltage between the plurality of first through substrate vias and the plurality of second through substrate vias, to form in the solid-electrolytic layer a plurality of connection electrodes, which are respectively connecting the plurality of second through substrate vias adjacent to the plurality of first through substrate vias to the plurality of first through substrate vias. | 2008-10-02 |
20080241997 | Interposer and method for producing the same and electronic device - An interposer includes a substrate made of an inorganic material; a through wiring including conductors embedded in through holes; and an upper wiring and (or) a lower wiring. The through wiring, the upper wiring and the lower wiring are respectively formed on preliminary wiring patterns that are additionally simultaneously or sequentially formed on layers made of an insulating material applied to at least wiring forming parts of the substrate, and are formed with a metal mold itself used for forming the preliminary wiring patterns or layers made of a wiring material applied by a printing operation, a plating operation or a deposition on the preliminary wiring patterns formed on the layers of the insulating material by transferring a fine structure pattern of the metal mold. | 2008-10-02 |
20080241998 | METHOD FOR FABRICATING A LOW COST INTEGRATED CIRCUIT (IC) PACKAGE - A method for fabricating a low cost integrated circuit package ( | 2008-10-02 |
20080241999 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device is manufactured by sealing a semiconductor chip, which is mounted on a prescribed support such as a lead frame, support bars, and a substrate connected with electrical wiring, in a package. Herein, individual information containing management information representing manufacturing conditions of semiconductor chips and test information representing results of testing of semiconductor chips is automatically recorded on a prescribed position of the prescribed support with respect to each of the semiconductor chips in synchronization with a die bonding process in response to the type of the package. That is, the individual information is recorded on exposed portions of outer leads, exposed portions of support bars, or the backside of the substrate, for example. This improves workability in reading and writing individual information without error, traceability to assure quality of semiconductor devices, and analysis of defects in semiconductor devices. | 2008-10-02 |
20080242000 | WAFER-LEVEL-CHIP-SCALE PACKAGE AND METHOD OF FABRICATION - A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate. | 2008-10-02 |
20080242001 | Lid Attachment Mechanism - Apparatus and methods for assembling semiconductor chips packages are provided. In one aspect, a method of manufacturing is provided that includes placing a first set of semiconductor chip package substrates in a first group of receptacles of a first processing station. Each of the first set of semiconductor chip package substrates has a first footprint. The receptacles of the first group being dimensioned to accommodate the first footprint. A second set of semiconductor chip package substrates is placed in a second group of receptacles of the first processing station. Each of the second set of semiconductor chip package substrates has a second footprint larger than the first footprint. The receptacles of the second group being dimensioned to accommodate the second footprint. A first set of lids is placed on the first set of semiconductor chip package substrates and a second group of lids is placed on the second set of semiconductor chip package substrates. | 2008-10-02 |
20080242002 | Apparatus and Methods for Cooling Semiconductor Integrated Circuit Package Structures - The present invention relates generally to apparatus and methods for cooling semiconductor integrated circuit (IC) chip package structures. More specifically, the present invention relates to apparatus and methods for thermally coupling semiconductor chips to a heat conducting device (e.g., copper thermal hat or lid) using a compliant thermally conductive material (e.g., thermal paste), wherein a thermal interface is designed to prevent/inhibit the formation of voids in the compliant thermally conductive material due to the flow of such material in and out from between the chips and the heat conducting device due to thermal cycling. | 2008-10-02 |
20080242003 | INTEGRATED CIRCUIT DEVICES WITH INTEGRAL HEAT SINKS - A method for forming integral heat sinks on back surfaces of integrated circuit devices at wafer level is described. A first metallic layer is deposited over the back surface of a wafer. A second metallic layer is deposited over the first metallic layer. Optionally, a third metallic layer is deposited over the second metallic layer. The first metallic layer, the second metallic layer, and optionally the third metallic layer form the integral heat sink for the wafer. When the wafer is diced into multiple semiconductor devices, each semiconductor device has an integral heat sink formed on its back surface that includes the first metallic layer, the second metallic layer, and optionally the third metallic layer. Optionally, each semiconductor device is connected to a lead frame via solder bumps or bonding wires to form an integrated circuit (IC) package. | 2008-10-02 |
20080242004 | INKJET PRINTED WIREBONDS, ENCAPSULANT AND SHIELDING - A method of connecting a chip to a package in a semiconductor device includes printing an encapsulant to a predetermined thickness on at least a portion of the chip and package and printing a layer of conductive material on the encapsulant in a predetermined pattern between the chip and package. The printed conductive material conforms to an upper surface of the encapsulant such that the encapsulant defines a distance from the printed conductive material to the chip and package. The method further includes printing a second layer of encapsulant over the printed conductive material curing at least the second layer of encapsulant. | 2008-10-02 |
20080242005 | Method for manufacturing semiconductor device - In the present application, is disclosed a method of manufacturing a flexible semiconductor device having an excellent reliability and tolerance to the loading of external pressure. The method includes the steps of: forming a separation layer over a substrate having an insulating surface; forming an element layer including a semiconductor element comprising a non-single crystal semiconductor layer, over the separation layer; forming an organic resin layer over the element layer; providing a fibrous body formed of an organic compound or an inorganic compound on the organic resin layer; heating the organic resin layer; and separating the element layer from the separation layer. This method allows the formation of a flexible semiconductor device having a sealing layer in which the fibrous body is impregnated with the organic resin. | 2008-10-02 |
20080242006 | METHODS OF FORMING NAND FLASH MEMORY WITH FIXED CHARGE - A string of nonvolatile memory cells connected in series includes fixed charges located between floating gates and the underlying substrate surface. Such a fixed charge affects distribution of charge carriers in an underlying portion of the substrate and thus affects threshold voltage of a device. A fixed charge layer may extend over source/drain regions also. | 2008-10-02 |
20080242007 | METHOD FOR SELECTIVELY ETCHING PORTIONS OF A LAYER OF MATERIAL BASED UPON A DENSITY OR SIZE OF SEMICONDUCTOR FEATURES LOCATED THEREUNDER - The disclosure provides a method for manufacturing a semiconductor device. The method, in one embodiment, includes forming semiconductor features ( | 2008-10-02 |
20080242008 | METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY - A method of making a monolithic, three dimensional NAND string, includes forming a select transistor, forming a first memory cell over a second memory cell, forming a first word line for the first memory cell, forming a second word line for the second memory cell, forming a bit line, forming a source line, and forming a select gate line for the select transistor. The first and the second word lines are not parallel to the bit line, and the first and the second word lines extend parallel to at least one of the source line and the select gate line. | 2008-10-02 |
20080242009 | SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure. A drain region and a source/base region are formed in the semiconductor substrate adjacent the first gate structure and a cathode region is formed in the semiconductor substrate adjacent the second gate structure. The drain region, the source/base region, and the cathode region have a second conductivity type. An anode region of the first conductivity type is formed adjacent the second gate structure in a portion of the source/base region. | 2008-10-02 |
20080242010 | At least penta-sided-channel type of finfet transistor - An at least penta-sided-channel type of FinFET transistor may include: a base; a semiconductor body formed on the base, the body being arranged in a long dimension to have source/drain regions sandwiching a channel region, at least the channel, in cross-section transverse to the long dimension, having at least five planar surfaces above the base; a gate insulator on the channel region of the body; and a gate electrode formed on the gate insulator. | 2008-10-02 |
20080242011 | Method of fabricating non-volatile memory device - A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately. | 2008-10-02 |
20080242012 | High quality silicon oxynitride transition layer for high-k/metal gate transistors - A method for fabricating a high quality silicon oxynitride layer for a high-k/metal gate transistor comprises depositing a high-k dielectric layer on a substrate, depositing a barrier layer on the high-k dielectric layer, wherein the barrier layer includes at least one of nitrogen or oxygen, depositing a capping layer on the barrier layer, and annealing the substrate at a temperature that causes at least a portion of the nitrogen and/or oxygen in the barrier layer to diffuse to an interface between the high-k dielectric layer and the substrate. The diffused nitrogen or oxygen forms a high-quality silicon oxynitride layer at the interface. The high-k dielectric layer, the barrier layer, and the capping layer may then be etched to form a gate stack for use in a high-k/metal gate transistor. The capping layer may be replaced with a metal gate electrode using a replacement metal gate process. | 2008-10-02 |
20080242013 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing such a semiconductor device having a field effect transistor with improved current driving performance (e.g., an increase of drain current) of the field effect transistor comprising the steps of ion implanting an element from the main surface to the inside of a silicon layer as a semiconductor substrate to a level shallower than the implantation depth of the impurities in the step of forming the semiconductor region before the step of ion implanting impurities from the main surface to the inside of the silicon layer as a semiconductor substrate to form the semiconductor region being aligned with the gate electrode. | 2008-10-02 |
20080242014 | METHODS FOR FABRICATING SEMICONDUCTOR SUBSTRATES WITH SILICON REGIONS HAVING DIFFERENTIAL CRYSTALLOGRAPHIC ORIENTATIONS - A method is provided for fabricating a differential semiconductor substrate. A first structure is provided which comprises a first semiconductor substrate including a first semiconductor region, and a first oxide layer overlying a surface of the first semiconductor substrate. The first semiconductor substrate has a first crystallographic orientation. A second structure is provided which includes a second semiconductor substrate comprising a first layer and a second layer, and a second oxide layer which overlies a surface of the first layer. The second semiconductor substrate has a second crystallographic orientation different than the first crystallographic orientation. The first layer includes a second semiconductor region. The first layer and the second oxide layer are removed from the second structure, and assembled to the first semiconductor substrate to form a composite structure. A bonded composite structure is then formed by exposing the composite structure to a temperature adequate to cause bonding of the first oxide layer and the second oxide layer. Portions of the bonded composite structure are removed to expose the first semiconductor region and the second semiconductor region and thereby form the differential semiconductor substrate. | 2008-10-02 |
20080242015 | Methods of Forming CMOS Integrated Circuit Devices Having Stressed NMOS and PMOS Channel Regions Therein and Circuits Formed Thereby - Methods of forming CMOS integrated circuit devices include forming at least first, second and third transistors in a semiconductor substrate and then covering the transistors with one or more electrically insulating layers that impart a net stress (tensile or compressive) to channel regions of the transistors. The covering step may include covering the first and second transistors with a first electrically insulating layer having a sufficiently high internal stress characteristic to impart a net tensile (or compressive) stress in a channel region of the first transistor and covering the second and third transistors with a second electrically insulating layer having a sufficiently high internal stress characteristic to impart a net compressive (or tensile) stress in a channel region of the third transistor. A step may then performed to selectively remove a first portion of the second electrically insulating layer extending opposite a gate electrode of the second transistor. In addition, a step may be performed to selectively remove a first portion of the first electrically insulating layer extending opposite a gate electrode of the first transistor and a second portion of the second electrically insulating layer extending opposite a gate electrode of the third transistor. | 2008-10-02 |
20080242016 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES WITH REDUCED SUSCEPTIBILITY TO LATCH-UP AND SEMICONDUCTOR DEVICE STRUCTURES FORMED BY THE METHODS - Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression. | 2008-10-02 |
20080242017 | METHOD OF MANUFACTURING SEMICONDUCTOR MOS TRANSISTOR DEVICES - A method of fabricating metal-oxide-semiconductor (MOS) transistor devices is disclosed. A semiconductor substrate is provided. A gate dielectric layer is formed. A gate electrode is stacked on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A silicon nitride spacer is formed on the liner. Using the gate electrode and the silicon nitride spacer as an implantation mask, a source/drain is implanted into the substrate. After the source/drain implant, the silicon nitride spacer is then stripped. A silicide layer is formed on the source/drain region. Subsequently, a silicon nitride cap layer is deposited. The silicon nitride cap layer has a specific stress status. | 2008-10-02 |
20080242018 | METHOD OF REDUCING CHANNELING OF ION IMPLANTS USING A SACRIFICIAL SCATTERING LAYER - Methods and devices for preventing channeling of dopants during ion implantation are provided. The method includes providing a semiconductor substrate and depositing a sacrificial scattering layer over at least a portion a surface of the substrate, wherein the sacrificial scattering layer includes an amorphous material. The method further includes ion implanting a dopant through the sacrificial scattering layer to within a depth profile in the substrate. Subsequently, the sacrificial scattering layer can be removed such that erosion of the substrate surface is less than one percent of a thickness of the sacrificial scattering layer. | 2008-10-02 |
20080242019 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device is disclosed. The method of fabricating a semiconductor device provides a semiconductor substrate. A gate dielectric layer is formed on the semiconductor substrate. A first conductive layer is formed on the gate dielectric layer, wherein the first conductive layer is an in-situ doped conductive layer. A second conductive layer is formed on the first conductive layer. The second conductive layer and the first conductive layer are patterned to form a gate electrode. | 2008-10-02 |
20080242020 | METHOD OF MANUFACTURING A MOS TRANSISTOR DEVICE - A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate and a gate structure positioned on the semiconductor substrate are prepared first. A source region and a drain region are included in the semiconductor substrate on two opposite sides of the gate structure. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Next, an inert gas treatment is performed to change a stress value of the stressed cap layer. Because the stress value of the stressed cap layer can be adjusted easily by means of the present invention, one stressed cap layer can be applied to both the N-type MOS transistor and the P-type MOS transistor. | 2008-10-02 |
20080242021 | METHOD OF FABRICATING A BOTTLE TRENCH AND A BOTTLE TRENCH CAPACITOR - A method of fabricating a bottle trench and a bottle trench capacitor. The method including: providing a substrate; forming a trench in the substrate, the trench having sidewalls and a bottom, the trench having an upper region adjacent to a top surface of the substrate and a lower region adjacent to the bottom of the trench; forming an oxidized layer of the substrate in the bottom region of the trench; and removing the oxidized layer of the substrate from the bottom region of the trench, a cross-sectional area of the lower region of the trench greater than a cross-sectional area of the upper region of the trench. | 2008-10-02 |
20080242022 | ELECTRONIC DEVICE INCLUDING DISCONTINUOUS STORAGE ELEMENTS WITHIN A DIELECTRIC LAYER AND PROCESS OF FORMING THE ELECTRONIC DEVICE - An electronic device can include a nonvolatile memory cell having DSEs within a dielectric layer. In one aspect, a process of forming the electronic device can include implanting and nucleating a first charge-storage material to form DSEs. The process can also include implanting a second charge-storage material and growing the DSEs such that the DSEs include the first and second charge-storage material. In another aspect, a process of forming the electronic device can include forming a semiconductor layer over a dielectric layer, implanting a charge-storage material, and annealing the dielectric layer. After annealing, substantially none of the charge-storage material remains within a denuded zone within the dielectric layer. In a third aspect, within a dielectric layer, a first set of DSEs can be spaced apart from a second set of DSEs, wherein substantially no DSEs lie between the first set of DSEs and the second set of DSEs. | 2008-10-02 |
20080242023 | METHOD FOR PREPARING A METAL-OXIDE-SEMICONDUCTOR TRANSISTOR - A method for preparing a Metal-Oxide-Semiconductor (MOS) transistor comprises the steps of forming a gate oxide layer on a substrate, forming a gate and a first dielectric layer on the gate oxide layer, forming a second dielectric layer on the sidewall of the gate, forming a third dielectric layer covering the first and the second dielectric layers, performing a first etching process to remove a portion of the third dielectric layer and performing a second etching process to form a spacer on the sidewall of the gate. The etching selectivity of the first etching process to the third dielectric layer and to the second dielectric layer is different from that of the second etching process such that the thickness of the second dielectric layer at the center of the substrate is smaller than the thickness of the second dielectric layer at the edge of the substrate. | 2008-10-02 |
20080242024 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device using a Fin-FET and having a contact configuration such that the GIDL is reduced while limiting an increase in contact resistance, source and drain regions of the Fin-FET are formed by solid-phase diffusion positively utilizing impurity implantation after forming of contact holes | 2008-10-02 |
20080242025 | 3-DIMENSIONAL FLASH MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - In an embodiment, a 3-dimensional flash memory device includes: a gate extending in a vertical direction on a semiconductor substrate; a charge storing layer surrounding the gate; a silicon layer surrounding the charge storing layer; a channel region vertically formed in the silicon layer; and source/drain regions vertically formed on both sides of the channel region in the silicon layer. Integration can be improved by storing data in a 3-dimensional manner; a 2-bit operation can be performed by providing transistors on both sides of the gate. | 2008-10-02 |
20080242026 | Method of manufacturing a semiconductor memory device having a floating gate - A method of manufacturing a semiconductor memory device which includes forming a conductive layer for a floating gate above a semiconductor layer intervening a gate insulating film therebetween, then, forming, over the conductive layer, a first spacer comprising a first silicon oxide material and a second spacer adjacent with the first spacer and comprising a second silicon oxide material, the second silicon oxide material having an etching rate lower than that of the first silicon oxide material, selectively removing the conductive layer by using the first and the second spacers as a mask, and removing the first spacer to expose a portion of the conductive layer. Since the etching rate for the second spacer is lower compared with the etching rate for the first spacer, the etching amount of the second spacer caused upon removal of the first spacer can be suppressed and, as a result, the productivity and the reliability of the semiconductor memory device can be improved. | 2008-10-02 |
20080242027 | Non-Volatile Memory Integrated Circuit - A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant region lines, with one line of the pair forming the source region and one line of the pair forming the drain region of each memory cell of the column. Each memory cell has a floating polysilicon storage gate. One of plural wordlines overlies each row of the memory cells. The portion of the wordline overlying each memory cells forms the control gate of the memory cell. Programming and erase operations occur by Fowler-Nordheim tunneling of electrons through a tunnel oxide layer between the floating gate and the source of the cell. | 2008-10-02 |
20080242028 | METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY - A method of making a monolithic, three dimensional NAND string including a first memory cell located over a second memory cell, includes growing a semiconductor active region of second memory cell, and epitaxially growing a semiconductor active region of the first memory cell on the semiconductor active region of the second memory cell in a different growth step from the step of growing the semiconductor active region of second memory cell. | 2008-10-02 |
20080242029 | METHOD AND STRUCTURE FOR MAKING A TOP-SIDE CONTACT TO A SUBSTRATE - A method for forming a semiconductor structure includes the following steps. A starting semiconductor substrate having a top-side surface and a back-side surface is provided. A recess is formed in the starting semiconductor substrate through the top-side of the starting semiconductor substrate. A semiconductor material is formed in the recess. A vertically conducting device is formed in and over the semiconductor material, where the starting semiconductor substrate serves as a terminal of the vertically conducting device. A non-recessed portion of the starting semiconductor substrate allows a top-side contact to be made to portions of the starting semiconductor substrate extending beneath the semiconductor material. | 2008-10-02 |
20080242030 | METHOD FOR MANUFACTURING FIN TRANSISTOR THAT PREVENTS ETCHING LOSS OF A SPIN-ON-GLASS INSULATION LAYER - A method for manufacturing a fin transistor includes forming a trench by etching a semiconductor substrate. A flowable insulation layer is filled in the trench to form a field insulation layer defining an active region. The portion of the flowable insulation layer coming into contact with a gate forming region is etched so as to protrude the gate forming region in the active region. A protective layer over the semiconductor substrate is formed to fill the portion of the etched flowable insulation layer. The portion of the protective layer formed over the active region is removed to expose the active region of the semiconductor substrate. The exposed active region of the semiconductor substrate is cleaned. The protective layer remaining on the portion of the etched flowable insulation layer is removed. Gates are formed over the protruded gate forming regions in the active region. | 2008-10-02 |
20080242031 | METHOD FOR FABRICATING P-CHANNEL FIELD-EFFECT TRANSISTOR (FET) - A method for fabrication a p-type channel FET includes forming a gate on a substrate. Then, a PAI ion implantation process is performed. Further, a pocket implantation process is conducted to form a pocket region. Thereafter, a first co-implantation process is performed to define a source/drain extension region depth profile. Then, a p-type source/drain extension region is formed. Afterwards, a second co-implantation process is performed to define a source/drain region depth profile. Thereafter, an in-situ doped epitaxy growth process is performed to form a doped semiconductor compound for serving as a p-type source/drain region. | 2008-10-02 |
20080242032 | Carbon-Doped Epitaxial SiGe - A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor gate stack, and source/drain extensions. The PMOS transistor also includes carbon-doped epitaxial SiGe source/drain regions. | 2008-10-02 |
20080242033 | Self-Aligned LDMOS Fabrication Method Integrated Deep-Sub-Micron VLSI Process, Using A Self-Aligned Lithography Etches And Implant Process - An integrated circuit includes both LDMOS devices and one or more low-power CMOS devices that are concurrently formed on a substrate using a deep sub-micron VLSI fabrication process. The LDMOS polycrystalline silicon (polysilicon) gate structure is patterned using a two-mask etching process. The first etch mask is used to define a first edge of the gate structure located away from the deep body/drain implant. The second etch mask is then used to define a second edge of the gate structure, and the second etch mask is then retained on the gate structure during subsequent formation of the deep body/drain implant. After the deep implant, shallow implants and metallization are formed to complete the LDMOS device. | 2008-10-02 |
20080242034 | METHOD OF MAKING THREE DIMENSIONAL NAND MEMORY - A method of making a monolithic, three dimensional NAND string, includes forming a semiconductor active region of a first memory cell over a semiconductor active region of a second memory cell. The semiconductor active region of the first memory cell is a first pillar having a square or rectangular cross section when viewed from above, the first pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. The semiconductor active region of the second memory cell is a second pillar having a square or rectangular cross section when viewed from above, the second pillar located under the first pillar, the second pillar being a first conductivity type semiconductor region located between second conductivity type semiconductor regions. One second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar. | 2008-10-02 |
20080242035 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n | 2008-10-02 |
20080242036 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device, includes: a) forming a first semiconductor layer on a semiconductor substrate; b) forming a second semiconductor layer on the first semiconductor layer; c) sequentially etching a part of the second semiconductor layer and a part of the first semiconductor layer so as to form a first groove exposing the first semiconductor layer; d) forming a cavity between the semiconductor substrate and the second semiconductor layer by etching the first semiconductor layer through the first groove under an etching condition in which the first semiconductor layer is more easily etched than the second semiconductor layer; e) forming an embedded oxide film in the cavity; f) etching the embedded oxide film from a lateral surface side thereof so as to form a gap between a peripheral part of the second semiconductor layer and the semiconductor substrate; and g) forming an insulating etching stopper layer in the gap. | 2008-10-02 |
20080242037 | Semiconductor device having self-aligned epitaxial source and drain extensions - A method of forming a transistor with self-aligned source and drain extensions in close proximity to a gate dielectric layer of the transistor comprises forming a gate stack on a substrate, implanting a dopant into regions of the substrate adjacent to the gate stack, wherein the dopant increases the etch rate of the substrate and defines the location of the source and drain extensions, forming a pair of spacers on laterally opposite sides of the gate stack that are disposed atop the doped regions of the substrate, etching the doped regions of the substrate and portions of the substrate subjacent to the doped regions, wherein an etch rate of the doped regions is higher than an etch rate of the portions of the substrate subjacent to the doped regions, and depositing a silicon-based material in the etched portions of the substrate. | 2008-10-02 |
20080242038 | METHODS OF FORMING A MULTILAYER CAPPING FILM TO MINIMIZE DIFFERENTIAL HEATING IN ANNEAL PROCESSES - Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting the source/drain region, forming a multilayer cap on the source/drain region, annealing the source/drain region, and removing the multilayer cap. | 2008-10-02 |
20080242039 | METHOD OF ENHANCING DOPANT ACTIVATION WITHOUT SUFFERING ADDITIONAL DOPANT DIFFUSION - A method of enhancing dopant activation without suffering additional dopant diffusion, includes forming shallow and lightly-doped source/drain extension regions in a semiconductor substrate, performing a first anneal process on the source/drain extension regions, forming deep and heavily-doped source/drain regions in the substrate adjacent to the source/drain extension regions, and performing a second anneal process on source/drain regions. The first anneal process is a flash anneal process performed for a time of between about 1 millisecond and 3 milliseconds, and the second anneal process is a rapid thermal anneal process performed for a time of between about 1 second and 30 seconds. | 2008-10-02 |
20080242040 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure comprises providing a semiconductor substrate. A feature is formed over the substrate. The feature is substantially homogeneous in a lateral direction. A first ion implantation process adapted to introduce first dopant ions into at least one portion of the substrate adjacent the feature is performed. The length of the feature in the lateral direction is reduced. After the reduction of the length of the feature, a second ion implantation process adapted to introduce second dopant ions into at least one portion of the substrate adjacent the feature is performed. The feature may be a gate electrode of a field effect transistor to be formed over the semiconductor substrate. | 2008-10-02 |
20080242041 | Selective Deposition of Germanium Spacers on Nitride - A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface. | 2008-10-02 |
20080242042 | METHOD FOR FABRICATING A CAPACITOR IN A SEMICONDUCTOR DEVICE - A method for fabricating a capacitor in a semiconductor device includes forming a sacrificial layer and a support layer on a substrate. A plurality of openings are formed by etching the support layer and the sacrificial layer. An electrode is formed in inner walls of the openings including sidewalls of the support layer patterned through etching. A portion of the patterned support layer is removed, and the sacrificial layer is also removed. | 2008-10-02 |
20080242043 | METHOD FOR CHECKING ALIGNMENT ACCURACY USING OVERLAY MARK - A method for checking the alignment accuracy using an overlay mark is provided. The overlay mark includes an inner mark and an outer mark formed on a wafer. The outer mark is formed in a lower layer on the wafer when the lower layer is patterned. The inner mark is formed within the outer mark over the lower layer when a lithography process for defining an upper layer is performed. A measurement process is conducted to obtain a first relation between each of the interior profiles of the outer marks and a second relation between each of the inner marks. Alternatively, a third relation between each of the interior profiles of the outer marks and each of the inner marks is obtained. The X-directional alignment accuracy and y-directional alignment accuracy are computed according to the first and the second relations, or the third relation. | 2008-10-02 |
20080242044 | Method for Fabricating Nonvolatile Memory Device - A method for fabricating a nonvolatile memory device includes forming a gate insulation layer, a first gate conductive layer, a first sacrificial layer, and a second sacrificial layer over a substrate, etching the first and second sacrificial layers, the first gate conductive layer, the gate insulation layer, and the substrate to form trenches, forming a first insulation layer to fill the trenches, polishing the first insulation layer using the etched second sacrificial layer as a polish stop layer, removing the second sacrificial layer, recessing the first insulation layer inside the trenches, forming a second insulation layer to fill a space produced inside the trenches by the recessing of the first insulation layer, and polishing the second insulation layer using the etched first sacrificial layer as a polish stop layer. | 2008-10-02 |
20080242045 | METHOD FOR FABRICATING TRENCH DIELECTRIC LAYER IN SEMICONDUCTOR DEVICE - A method for fabricating a trench dielectric layer in a semiconductor device is provided. A trench is formed in a semiconductor substrate and a liner nitride layer is then formed on an inner wall of the trench. A liner oxide layer formed on the liner nitride layer is nitrified in order to protect the liner nitride layer from being exposed. Subsequently, the trench is filled with one or more dielectric layers. | 2008-10-02 |
20080242046 | Method on Forming an Isolation Film or a Semiconductor Device - A method of forming an isolation film in a semiconductor device is disclosed. The disclosed method includes performing a patterning process on a predetermined region of a semiconductor substrate in which a patterned pad film is formed, forming a trench defining an inactive region and an active region, forming a liner film on the entire surface including the trench, forming an insulating film for trench burial only within the trench, stripping the remaining liner film formed except for the inside of the trench and the patterned pad film formed below the liner film, forming a sacrificial film on the entire surface, and performing a polishing process on the entire surface in which the sacrificial film is formed until the semiconductor substrate of the active region is exposed, thereby forming the isolation film having no topology difference with the semiconductor substrate of the active region. | 2008-10-02 |
20080242047 | METHOD OF FORMING ISOLATION STRUCTURE OF SEMICONDUCTOR MEMORY DEVICE - The present invention relates to a method of forming isolation layers of a semiconductor memory device. According to a method of forming isolation layers of a semiconductor memory device in accordance with an aspect of the present invention, a tunnel dielectric layer, a conductive layer for a floating gate, a buffer oxide layer, and a pad nitride layer are sequentially formed over a semiconductor substrate. A trench is formed by selectively etching the pad nitride layer, the buffer oxide layer, the conductive layer for the floating gate, the tunnel dielectric layer, and the semiconductor substrate. The trench is gap-filled by forming a dielectric layer over the entire structure including the trench. A curing process is performed using a pre-heated curing gas. A height of the isolation layers is controlled by performing a cleaning process. | 2008-10-02 |
20080242048 | METHOD FOR MANUFACTURING SOI SUBSTRATE - To easily and accurately flush a substrate surface serving an SOI area with a substrate surface serving as a bulk area, make a buried oxide film, and prevent an oxide film from being exposed on substrate surface. | 2008-10-02 |