40th week of 2008 patent applcation highlights part 20 |
Patent application number | Title | Published |
20080237744 | Semiconductor Device and Manufacturing Method Thereof - Provided is a semiconductor device and manufacturing method thereof. The semiconductor device includes a gate dielectric on a semiconductor substrate; and a gate electrode on the gate dielectric. The gate dielectric has a structure in which a buffer dielectric and a dielectric layer including a high-k material are stacked. The gate dielectric can be formed so as to reduce surface roughness between the gate dielectric and the semiconductor substrate and to improve the dielectric constant of the gate dielectric. | 2008-10-02 |
20080237745 | SRAM CELL WITH ASYMMETRICAL TRANSISTORS FOR REDUCED LEAKAGE - A method of fabricating an SRAM cell with reduced leakage is disclosed. The method comprises fabricating asymmetrical transistors in the SRAM cell. The transistors are asymmetrical in a manner that reduces the drain leakage current of the transistors. The fabrication of asymmetrical pass transistors comprises forming a dielectric region on a surface of a substrate having a first conductivity type. A gate region having a length and a width is formed on the dielectric region. Source and drain extension regions having a second conductivity type are formed in the substrate on opposite sides of the gate region. A first pocket impurity region having a first concentration and the first conductivity type is formed adjacent the source. A second pocket impurity region having a second concentration and the first conductivity type may be formed adjacent the drain. If formed, the second concentration is smaller than the first concentration, reducing the gate induced drain leakage current. | 2008-10-02 |
20080237746 | Gated diode with non-planar source region - A gated-diode semiconductor device or similar component and a method of fabricating the device. The device features a gate structure disposed on a substrate over a channel and adjacent a source and a drain. The top of the source or drain region, or both, are formed so as to be at a higher elevation, in whole or in part, than the bottom of the gate structure. This configuration may be achieved by overlaying the gate structure and substrate with a profile layer that guides a subsequent etch process to create a sloped profile. The source and drain, if both are present, may be symmetrical or asymmetrical. This configuration significantly reduces dopant encroachment and, as a consequence, reduces junction leakage. | 2008-10-02 |
20080237747 | SEMICONDUCTOR DEVICE - A semiconductor device including: a semiconductor layer; a gate insulating layer; a gate electrode; a channel region; a source region and a drain region; a guard ring region; an offset insulating layer; a first interlayer dielectric; a first shield layer formed above the first interlayer dielectric and the guard ring region and electrically connected to the guard ring region; a second interlayer dielectric; and a second shield layer formed above the second interlayer dielectric, wherein the first shield layer is provided outside of both ends of the gate electrode in a channel width direction when viewed from the top side; and wherein the second shield layer is provided in at least part of a first region and/or at least part of a second region, the first region being a region between one edge of the gate electrode and an edge of the first shield layer opposite to the edge of the gate electrode in the channel width direction when viewed from the top side, and the second region being a region between the other edge of the gate electrode and an edge of the first shield layer opposite to the other edge of the gate electrode in the channel width direction when viewed from the top side. | 2008-10-02 |
20080237748 | METHOD FOR FABRICATING HIGH COMPRESSIVE STRESS FILM AND STRAINED-SILICON TRANSISTORS - A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and ammonia to form a high compressive stress film on the surface of the gate, the spacer, and the source/drain region. Preferably, the high compressive stress film can be utilized in the fabrication of a poly stressor, a contact etch stop layer, and dual contact etch stop layers. | 2008-10-02 |
20080237749 | CMOS GATE CONDUCTOR HAVING CROSS-DIFFUSION BARRIER - A gate conductor is provided for a transistor pair including an n-type field effect transistor (“NFET”) having an NFET active semiconductor region and a p-type field effect transistor (“PFET”) having a PFET active semiconductor region, where the NFET and PFET active semiconductor regions are separated by an isolation region. An NFET gate extends in a first direction over the NFET active semiconductor region. A PFET gate extends in the first direction over the PFET active semiconductor region. A diffusion barrier is sandwiched between the NFET gate and the PFET gate. A continuous layer extends continuously in the first direction over the NFET gate and the PFET gate. The continuous layer contacts top surfaces of the NFET gate and the PFET gate and the continuous layer includes at least one of a semiconductor, a metal or a conductive compound including a metal. | 2008-10-02 |
20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 2008-10-02 |
20080237751 | CMOS Structure and method of manufacturing same - A CMOS structure includes a substrate ( | 2008-10-02 |
20080237752 | METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Disclosed is a technique for reducing the leak current by reducing contamination of metal composing a polymetal gate of a MISFET. Of a polycrystalline silicon film, a WN film, a W film, and a cap insulating film formed on a gate insulating film on a p-type well (semiconductor substrate), the cap insulating film, the W film, and the WN film are etched and the over-etching of the polycrystalline silicon film below them is performed. Then, a sidewall film is formed on sidewalls of these films. Thereafter, after etching the polycrystalline silicon film with using the sidewall film as a mask, a thermal treatment is performed in an oxidation atmosphere, by which a light oxide film is formed on the sidewall of the polycrystalline silicon film. As a result, the contamination on the gate insulating film due to the W and the W oxide can be reduced, and also, the diffusion of these materials into the semiconductor substrate (p-type well) and the resultant increase of the leak current can be prevented. | 2008-10-02 |
20080237753 | Methods of Fabricating Semiconductor Devices and Structures Thereof - Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the first spacer comprising a first material. A first liner is disposed over the first spacer and over a portion of the workpiece proximate the first spacer, the first liner comprising the first material. A second spacer is disposed over the first liner, the second spacer comprising a second material. A second liner is disposed over the second spacer, the second liner comprising the first material. | 2008-10-02 |
20080237754 | System, methods and apparatuses for nanoelectronics applied to nanorobots - A nanorobotic apparatus is described consisting of hybrid MEMS and NEMS components. The nanorobot contains sensors for situational awareness. The apparatus has nanofilament components for communications. | 2008-10-02 |
20080237755 | Seek-scan probe (SSP) memory including mechanism for track correction - An apparatus comprising a substrate having one or more anchors formed thereon; a movable platform suspended by one or more tether beams from the one or more anchors; an actuator coupled to the movable platform; and a micro-electro-mechanical (MEMS) probe having a proximal end, a distal end and a longitudinal axis extending between the proximal end and the distal end, wherein the proximal end is coupled to the movable platform and the distal end can be actuated in a direction substantially normal to a surface of the substrate. A process comprising forming one or more anchors on a substrate; suspending a movable platform by one or more tether beams coupled to the one or more anchors; coupling an actuator to the movable platform; and coupling a micro-electro-mechanical (MEMS) probe to the movable platform, the MEMS probe having a proximal end, a distal end and a longitudinal axis extending between the proximal end and the distal end, wherein the proximal end is coupled to the movable platform and the distal end can be actuated in a direction substantially normal to a surface of the substrate. | 2008-10-02 |
20080237756 | Microelectromechanical systems, and methods for encapsualting and fabricating same - There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a MEMS device, and technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging. The material that encapsulates the mechanical structures, when deposited, includes one or more of the following attributes: low tensile stress, good step coverage, maintains its integrity when subjected to subsequent processing, does not significantly and/or adversely impact the performance characteristics of the mechanical structures in the chamber (if coated with the material during deposition), and/or facilitates integration with high-performance integrated circuits. In one embodiment, the material that encapsulates the mechanical structures is, for example, silicon (polycrystalline, amorphous or porous, whether doped or undoped), silicon carbide, silicon-germanium, germanium, or gallium-arsenide. | 2008-10-02 |
20080237757 | MICRO MOVABLE DEVICE, WAFER, AND METHOD OF MANUFACTURING WAFER - A micro movable device is made by processing a material substrate of a multilayer structure including a first layer, a second layer having a finely rough region on its surface on the side of the first layer, and an intermediate layer provided between the first and the second layer. The micro movable device includes a first structure formed in the first layer and a second structure formed in the second layer. The second structure includes a portion opposing the first structure via a gap and having a finely rough region on the side of the first structure, and being relatively displaceable with respect to the first structure. | 2008-10-02 |
20080237758 | IMAGE DETECTION APPARATUS AND METHOD FOR PRODUCING THE APPARATUS - An image detection apparatus includes a substrate, a middle layer formed on the substrate, the middle layer having a quadrilateral hole, and a photoelectric conversion layer deposited on the middle layer. The curvature radius of each of the corner portions of the quadrilateral hole is greater than or equal to 2 μm. Further, the photoelectric conversion layer is made of an amorphous material. | 2008-10-02 |
20080237759 | Semiconductor device - An open portion is provided to an interlayer insulation film so as to correspond to a photoreceptor part of an optical detection device. A partition wall for surrounding the open portion ( | 2008-10-02 |
20080237760 | Substrate for Transparent Electrodes - One object of the present invention is to provide a transparent electrode substrate with an ITO film formed thereon, used for example as the transparent electrode plate in a dye sensitized solar cell, for which the electrical resistance does not increase even when exposed to high temperatures of 300° C. or higher. In order to achieve the object, the present invention provides a substrate for a transparent electrode, wherein two or more layers of different transparent conductive films are formed on a transparent substrate, and an upper layer transparent conductive film has a higher heat resistance than that of a lower layer transparent conductive film. | 2008-10-02 |
20080237761 | SYSTEM AND METHOD FOR ENHANCING LIGHT SENSITIVITY FOR BACKSIDE ILLUMINATION IMAGE SENSOR - A system and method for enhancing light sensitivity of a back-side illumination image sensor are described. An integrated circuit includes a substrate and an image sensor device comprising at least one transistor formed over a first surface of the substrate and a photosensitive region. A color filter is disposed over a second surface of the substrate opposite the first surface thereof. A micro-lens structure is disposed between the second surface of the substrate and the color filter. | 2008-10-02 |
20080237762 | Method of Fabricating Back-Illuminated Imaging Sensors Using a Bump Bonding Technique - A method for fabricating a back-illuminated semiconductor imaging device on a semiconductor-on-insulator substrate, and resulting imaging device is disclosed. The method for manufacturing the imaging device includes the steps of providing a substrate comprising an insulator layer, and an epitaxial layer substantially overlying the insulator layer; fabricating at least one imaging component at least partially overlying and extending into the epitaxial layer; forming a plurality of bond pads substantially overlying the epitaxial layer; fabricating a dielectric layer substantially overlying the epitaxial layer and the at least one imaging component; providing a handle wafer; forming a plurality of conductive trenches in the handle wafer; forming a plurality of conductive bumps on a first surface of the handle wafer substantially underlying the conductive trenches; and bonding the plurality of conductive bumps to the plurality of bond pads. | 2008-10-02 |
20080237763 | ULTRAVIOLET DETECTING DEVICE AND MANUFACTURING METHOD THEREOF, AND ULTRAVIOLET QUANTITY MEASURING APPARATUS - The present invention provides an ultraviolet detecting device which comprises a silicon semiconductor layer having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, which is formed over an insulating layer, lateral PN-junction type first and second photodiodes formed in the silicon semiconductor layer, an interlayer insulating film formed over the silicon semiconductor layer, a first filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the first photodiode and causes light lying in a wavelength range of an UV-B wave or higher to pass therethrough, and a second filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the second photodiode and allows light lying in a wavelength range of an UV-A wave or higher to pass therethrough. | 2008-10-02 |
20080237764 | SEMICONDUCTOR ELEMENT AND METHOD FOR MANUFACTURING THE SAME - A semiconductor element comprises: a semiconductor substrate; and an amorphous metal oxide film as a first film deposited on the semiconductor substrate. By providing the amorphous metal oxide film as the first film, a recess with a large aspect ratio can be filled. As a result, a void/crack-free film of excellent quality can be formed. | 2008-10-02 |
20080237765 | IMAGE SENSOR WITH THE ABILITY TO DETECT ALL COLORS AT EACH PIXEL - An image sensor with the ability to detect a different light wavelength at each pixel, due to a change of physical characteristics of material under light with different wavelength illumination. | 2008-10-02 |
20080237766 | IMAGE SENSING DEVICES INCLUDING IMAGE SENSOR CHIPS, IMAGE SENSOR PACKAGE MODULES EMPLOYING THE IMAGE SENSING DEVICES, ELECTRONIC PRODUCTS EMPLOYING THE IMAGE SENSOR PACKAGE MODULES, AND METHODS OF FABRICATING THE SAME - An image sensor package includes an image sensor chip, a handling substrate mounted on a front side of the image sensor chip and a through electrode disposed on a backside of the image sensor chip. The through electrode extends into the image sensor chip. Moreover, the image sensor chip includes a semiconductor substrate having a pixel region and a peripheral circuit region, a photoelectric transformation section disposed in the semiconductor substrate of the pixel region and a dielectric layer disposed on a front surface of the semiconductor substrate. The dielectric layer has a step region so that a top surface of the dielectric layer in the pixel region is lower than that of the dielectric layer in the peripheral circuit region. The image sensor chip further includes a conductive pad disposed on the dielectric layer in the peripheral circuit region and is electrically connected to the through electrode. | 2008-10-02 |
20080237767 | Sensor-type semiconductor device and manufacturing method thereof - A sensor-type semiconductor device and manufacturing method thereof are disclosed. The method includes providing a wafer comprising a plurality of sensor chips; forming concave grooves between the solder pads formed on the active surface of adjacent sensor chips; filling a filling material into the concave grooves and forming first conductive circuits electrically connecting the solder pads of adjacent sensor chips; mounting a light permeable body on the active surface of the wafer and thinning the non-active surface of the wafer to expose the filling material; mounting the wafer on a carrier board with second conductive circuits formed thereon corresponding in position to the filling material; forming first openings by cutting the light permeable body and the wafer to a position at which the second conductive circuits are located; forming metallic layers in the first openings by electroplating, the metallic layers electrically connecting the first and second conductive circuits of adjacent sensor chips; forming second openings by cutting the metallic layers to break the first conductive circuit connections and the second conductive circuit connections of adjacent sensor chips and meanwhile keep the first and second conductive circuits of each sensor chip still electrically connected through the metallic layers; filling a dielectric material into the second openings and removing the carrier board; and separating each of the sensor chips to form a plurality of sensor-type semiconductor devices. The invention overcomes the drawbacks of the prior art such as slanting notches formed on the non-active surface of the wafer, displacement of the notches due to the difficulty in precise alignment, as well as broken joints caused by concentrated stress generated in the slanting notches and exposed circuits. | 2008-10-02 |
20080237768 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus is provided. A solid-state imaging device chip is enclosed in a package having an optically transparent member. An adhesive layer is formed on an internal surface of the package, and a penetration hole is formed in a bottom part of the package to communicate with an open space in the package. | 2008-10-02 |
20080237769 | SEMICONDUCTOR OPTICAL SENSOR - A sensor includes a substrate provided with a circuit element forming region and a photodiode forming region, the substrate having a silicon substrate, an insulating layer on the silicon substrate, and a silicon layer on the insulating layer; a photodiode in the silicon layer; a circuit element in the silicon layer; a first interlayer insulating film formed over the silicon layer; a first light-shielding film on the first interlayer film and having an opening in the photodiode forming region; and a first inter-region light-shielding plug arranged between the two regions, for connecting the silicon substrate and the first light-shielding film. | 2008-10-02 |
20080237770 | RADIATION DETECTOR - A radiation detector that includes a charge conversion layer, a substrate, an electrode layer, an intermediary layer and wiring is provided. The substrate includes a lower electrode portion that collects charge generated by the charge conversion layer. The electrode layer includes an upper electrode portion and an extended electrode portion. The upper electrode portion is laminated on the charge conversion layer. The extended electrode portion extends from the upper electrode portion down a side face of the charge conversion layer to a region on the substrate at which the charge conversion layer is not present. The intermediary layer is formed from between the charge conversion layer and the upper electrode portion to between the extended electrode portion and the substrate. The wiring is electrically connected with the extended electrode portion at the region on the substrate at which the charge conversion layer is not present. | 2008-10-02 |
20080237771 | IMAGING SYSTEM - A viewing system configured to combine multiple spectral images of a scene, the system includes a spectral beam separator configured to split an incoming beam of radiation into a first and a second beam of radiation, the first beam of radiation including radiations substantially in a first spectral band and the second beam of radiation including radiations substantially in a second spectral band; an image intensifier configured to intensify the second beam of radiation, the image intensifier including a photocathode configured to produce a flux of photoelectrons with substantially increased efficiency when exposed to the second beam of radiation, the photocathode constructed and arranged to substantially absorb all the radiations in the second beam of radiation; a current amplifier configured to amplify the flux of photoelectrons; and a display system configured to display an image of the scene in the second spectral band based on the amplified flux of electrons simultaneously with an image of the scene in the first spectral band. | 2008-10-02 |
20080237772 | SEMICONDUCTOR DEVICE AND TEMPERATURE SENSOR STRUCTURE FOR A SEMICONDUCTOR DEVICE - A temperature sensor structure for a semiconductor device. One embodiment provides a semiconductor substrate including the semiconductor device. A dissipation region of the semiconductor device is adjacent to a main surface of the semiconductor substrate. A first layer arrangement is disposed on the main surface of the semiconductor substrate adjacent to the dissipation region of the semiconductor device. A second layer arrangement is disposed on the first layer arrangement with an insulation layer for galvanic separation therebetween. The first and second layer arrangements and the insulation layer form a layer structure on the main surface above the dissipation region. A circuit element is disposed in the second layer arrangement, the circuit element having a temperature-dependent characteristic and being coupled thermally to the dissipation region. | 2008-10-02 |
20080237773 | Integrated High Voltage Power Device Having an Edge Termination of Enhanced Effectiveness - Instabilities and related drawbacks that arise when interruptions of a perimetral high voltage ring extension implanted regions (RHV) of a main junction (P_tub | 2008-10-02 |
20080237774 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a semiconductor substrate; a first semiconductor layer of a first conductivity type provided on a major surface of the semiconductor substrate and having lower doping concentration than the semiconductor substrate; a plurality of first semiconductor column regions of the first conductivity type provided on the first semiconductor layer; | 2008-10-02 |
20080237775 | DEPLETABLE CATHODE LOW CHARGE STORAGE DIODE - An integrated circuit device comprising a diode and a method of making an integrated circuit device comprising a diode are provided. The diode can comprise an island of a first conductivity type, a first region of a second conductivity type formed in the island, and a cathode diffusion contact region doped to the second conductivity type disposed in the first region. The diode can also comprise a cathode contact electrically contacting the cathode diffusion contact region, an anode disposed in the island, an anode contact electrically contacting the anode, and a first extension region doped to the first conductivity type disposed at a surface junction between the first region and the island. | 2008-10-02 |
20080237776 | DRAM layout with vertical FETs and method of formation - DRAM cell arrays having a cell area of less than about 4 F | 2008-10-02 |
20080237777 | Completely decoupled high voltage and low voltage transistor manufacurting processes - A semiconductor wafer includes at least a partially manufactured high voltage transistor covered by a high-voltage low voltage decoupling layer and at least a partially manufactured low voltage transistor with the high-voltage low-voltage decoupling layer etched off for further performance of a low-voltage manufacturing process thereon. The high-voltage low-voltage decoupling layer comprising a high temperature oxide (HTO) oxide layer of about 30-150 Angstroms and a low-pressure chemical vapor deposition (LPCVD) nitride layer. | 2008-10-02 |
20080237778 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device having a silicon-on-insulator region and a bulk region in a same semiconductor substrate, the method includes: (a) etching the semiconductor substrate in the silicon-on-insulator region so as to form a concave; (b) forming a first semiconductor layer and subsequently a second semiconductor layer on the semiconductor substrate in the silicon-on-insulator region, so as to bury the concave; (c) etching the second semiconductor layer and the first semiconductor layer partially, so as to form a trench which exposes a side surface of the first semiconductor substrate in the silicon-on-insulator region; (d) etching the first semiconductor layer through the trench with an etching condition in which the first semiconductor layer is easier to be etched than the second semiconductor layer, so as to form a cavity between the semiconductor substrate and the second semiconductor layer in the silicon-on-insulator region; and (e) forming a buried insulating film inside the cavity. | 2008-10-02 |
20080237779 | SOI substrate and method for manufacturing SOI substrate - An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a first single crystal silicon substrate to form a second single crystal silicon substrate which has a chip size; a step (B) of forming an insulating layer on one surface of the second single crystal silicon substrate, and forming an embrittlement layer in the second single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the second single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the second single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface, are conducted. | 2008-10-02 |
20080237780 | SOI substrate and method for manufacturing SOI substrate - An SOI substrate and a manufacturing method of the SOI substrate, by which enlargement of the substrate is possible and its productivity can be increased, are provided. A step (A) of cutting a single crystal silicon substrate to form a single crystal silicon substrate which is n (n is an optional positive integer, n≧1) times as large as a size of one shot of an exposure apparatus; a step (B) of forming an insulating layer on one surface of the single crystal silicon substrate, and forming an embrittlement layer in the single crystal substrate; and a step (C) of bonding a substrate having an insulating surface and the single crystal silicon substrate with the insulating layer therebetween, and conducting heat treatment to separate the single crystal silicon substrate along the embrittlement layer, and forming a single crystal silicon thin film on the substrate having an insulating surface are conducted. | 2008-10-02 |
20080237781 | Chip-stacked semiconductor device and manufacturing method thereof - The semiconductor device according to the present invention includes a through electrode that penetrates through a silicon substrate, an isolation trench provided to penetrate through the silicon substrate to surround the through electrode, a silicon film in contact with an inner surface of the isolation trench, a silicon film in contact with an outer surface of the isolation trench, and an insulation film provided between the silicon films. According to the present invention, the silicon film within the isolation trench can be substantially regarded as a part of the silicon substrate. Therefore, even when the width of the isolation trench is increased to increase the etching rate, the width of the insulation film becoming a dead space can be made sufficiently small. Consequently, the chip area can be decreased. | 2008-10-02 |
20080237782 | Isolated rectifier diode - An isolated diode comprises a floor isolation region, a dielectric-filled trench and a sidewall region extending from a bottom of the trench at least to the floor isolation region. The floor isolation region, dielectric-filled trench and a sidewall region are comprised in one terminal (anode or cathode) of the diode and together form an isolated pocket in which the other terminal of the diode is formed. In one embodiment the terminals of the diode are separated by a second dielectric-filled trench and sidewall region. | 2008-10-02 |
20080237783 | Isolated bipolar transistor - A bipolar transistor is formed in an isolation structure comprising a floor isolation region, a dielectric filled trench above the floor isolation region and a sidewall isolation region extending downward from the bottom of the trench to the floor isolation region. This structure provides a relatively deep isolated pocket in a semiconductor substrate while limiting the depth of the trench that must be etched in the substrate. | 2008-10-02 |
20080237784 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor device formed in a semiconductor substrate wherein the semiconductor substrate has a trench for isolating elements from each other, the trench has unevenness at the bottom thereof, and an insulator is buried in the trench. | 2008-10-02 |
20080237785 | STRUCTURE OF HIGH-FREQUENCY COMPONENTS WITH LOW STRAY CAPACITANCES - A structure including at least two neighboring components, capable of operating at high frequencies, formed in a thin silicon substrate extending on a silicon support and separated therefrom by an insulating layer, the components being laterally separated by insulating regions. The silicon support has, at least in the vicinity of its portion in contact with the insulating layer, a resistivity greater than or equal to 1,000 ohms.cm. | 2008-10-02 |
20080237786 | NON-PLANAR FUSE STRUCTURE INCLUDING ANGULAR BEND AND METHOD FOR FABRICATION THEREOF - A fuse structure includes a non-planar fuse material layer typically located over and replicating a topographic feature within a substrate. The non-planar fuse material layer includes an angular bend that assists in providing a lower severance current within the non-planar fuse material layer. | 2008-10-02 |
20080237787 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention aims at offering the semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. | 2008-10-02 |
20080237788 | METHOD AND DEVICE FOR PROGRAMMING ANTI-FUSES - A device includes an anti-fuse including a first electrode that can be selectively coupled to a first voltage reference and a second electrode that can be selectively coupled to a second voltage reference. The device further includes a shunt transistor including a first current electrode coupled to the first electrode of the anti-fuse, a second current electrode coupled to the second electrode of the anti-fuse, and a control electrode. The device additionally includes control logic configured to disable the shunt transistor in response to a first program operation intended for the anti-fuse. The control logic also is configured to enable the shunt transistor in response to a second program operation not intended for the anti-fuse. | 2008-10-02 |
20080237789 | INTEGRATED CIRCUIT STUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM - Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M | 2008-10-02 |
20080237790 | Composite semiconductor device - The electrode of a thin-type capacitor is connected to the rear surface of a p-type semiconductor substrate which is brought to a ground potential, by a conductive DAF (Die Attach Film) or by a conductive adhesive, and the electrodes of the front surface of the p-type semiconductor substrate are respectively connected with and stacked on the terminals of a thin-type inductor by bumps, whereby manufacturing costs can be reduced while the occurrence of noise can be suppressed and packaging area can be made small. | 2008-10-02 |
20080237791 | Zirconium oxide based capacitor and process to manufacture the same - A capacitor structure comprises a first and a second electrode of conducting material. Between the first and second electrodes, an atomic layer deposited dielectric film is disposed, which comprises zirconium oxide and a dopant oxide. Herein, the dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, while the dielectric film comprises a dopant content of 10 atomic percent or less of the dielectric film material excluding oxygen. A process for fabricating a capacitor comprises a step of forming a bottom electrode of the capacitor. On the bottom electrode, a dielectric film comprising zirconium oxide is deposited, and a step for introducing a dopant oxide into the dielectric film performed. On the dielectric structure, a top electrode is formed. The dopant comprises an ionic radius that differs by more than 24 pm from an ionic radius of zirconium, whereas the dielectric structure deposited comprises a dopant content of 10 atomic percent or less of the deposited material excluding oxygen. | 2008-10-02 |
20080237792 | SEMICONDUCTOR CAPACITOR STRUCTURE AND LAYOUT PATTERN THEREOF - The present invention provides a metal-oxide-metal (MOM) capacitor structure having a plurality of symmetrical ring type sections. The MOM capacitor structure of the present invention does not need photomasks above standard CMOS process, and thus the process cost is cheaper. In addition, due to the semiconductor process improvement, a significantly large number of metal layers can be stacked in the MOM capacitor structure, and since the distance between the metal layers becomes smaller, the unit capacitance will be increased. | 2008-10-02 |
20080237793 | Semiconductor device having projection on lower electrode and method for forming the same - A method of forming a semiconductor device, includes forming a lower electrode including a metal and a nitrogen on a semiconductor substrate, irradiating a reducing gas to a surface of the lower electrode, and irradiating a gas containing silicon to the surface of the lower electrode to form a projection containing silicide by reacting the metal with the silicon in an island shape on the surface of the lower electrode. Then, a capacitor film is formed on the lower electrode and the projection, and an upper electrode is formed on the capacitor film. | 2008-10-02 |
20080237794 | Thin film capacitor - Disclosed is a thin film capacitor which can improve the uniformity of the capacitance while keeping a high capacitance. The thin film capacitor has a lower electrode serving as a trench forming layer where a trench pattern is to be formed, a dielectric film so provided as to cover the lower electrode, and an upper electrode laminated in order on the entire top surface of a substrate. The trench pattern is configured to have a first pattern and a second pattern separate from the first pattern. The first pattern has a plurality of protrusions provided upright at predetermined intervals, and the second pattern has a plurality of recesses provided at predetermined intervals. Trenches are each defined by the outer wall of each protrusion and the inner wall of each recess. | 2008-10-02 |
20080237795 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - There is provided a semiconductor device which includes a base insulating film formed on a semiconductor substrate, a capacitor formed on the base insulating film, an interlayer insulating film covering the capacitor, a first layer metal wiring formed on the interlayer insulating film, a single-layer first insulating film which covers the interlayer insulating film and the first layer metal wiring and has a first film thickness above the first layer metal wiring, a first capacitor protective insulating film formed on the first insulating film, a first cover insulating film which is formed on the first capacitor protective insulating film and has a second film thickness thicker than the first film thickness, above the first layer metal wiring, a third hole formed in the insulating films on the first layer metal wiring, and a fifth conductive plug formed in the third hole. | 2008-10-02 |
20080237796 | Increasing the surface area of a memory cell capacitor - Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer. | 2008-10-02 |
20080237797 | ELECTRICALLY TUNABLE RESISTOR AND RELATED METHODS - An electrically tunable resistor and related methods are disclosed. In one embodiment, the resistor includes a first resistive layer, at least one second resistive layer, and an intermediate interdiffused layer of the first resistive layer and the at least one second resistive layer. One method may include providing a first plurality of layers of different materials surrounded by at least one insulating layer, and passing a current pulse through the first plurality of layers to affect a conductivity structure of the first plurality of layers in order to obtain a first predetermined resistance value for the resistor. | 2008-10-02 |
20080237798 | MEMORY CELL AND PROCESS FOR MANUFACTURING THE SAME - A memory cell and a process for manufacturing the same are provided. In the process, a first electrode layer is formed on a conductive layer over a substrate, and then a transition metal layer is formed on the first electrode layer. After that, the transition metal layer is subjected to a plasma oxidation step to form a transition metal oxide layer as a precursor of a data storage layer, and a second electrode layer is formed on the transition metal oxide layer. A memory cell is formed after the second electrode layer, the transition metal oxide layer and the first electrode layer are patterned into a second electrode, a data storage layer and a first electrode, respectively. | 2008-10-02 |
20080237799 | SEMICONDUCTOR DEVICE CAPABLE OF DECREASING VARIATIONS IN SIZE OF METAL RESISTANCE ELEMENT - A semiconductor device is provided wherein a foundation insulating film is formed over a semiconductor substrate, a metal resistance element is formed on the foundation insulating film, and contacts are formed at both ends of the metal resistance element in a longitudinal direction of the metal resistance element and connected to the metal resistance element. The foundation insulating film comprises a single upwardly concave curved surface constituting not less than about 40 percent of an upper surface of the metal resistance element between the contacts in the longitudinal direction thereof. The curved surface of the foundation insulating film causes the metal resistance element to comprise a single upwardly concave curved surface constituting not less than about 40 percent of upper and lower surfaces of the metal resistance element between the contacts in the longitudinal direction thereof. | 2008-10-02 |
20080237800 | INTEGRATED CIRCUIT HAVING RESISTOR BETWEEN BEOL INTERCONNECT AND FEOL STRUCTURE AND RELATED METHOD - Integrated circuits (IC) and a method of fabricating an IC, where the structure of the IC incorporates a back-end-of-the-line (BEOL) thin film resistor below a first metal layer to achieve lower topography are disclosed. The resistor directly contacts any one of: a contact metal in the front-end-of-the-line (FEOL) structure; first metal layer in the BEOL interconnect; or the combination thereof, to avoid the necessity of forming contacts with differing heights or contacts over varying topography. | 2008-10-02 |
20080237801 | Semiconductor device - A semiconductor device includes a resistor element formed in a semiconductor layer of an SOI substrate (Silicon On Insulator). The semiconductor device includes a low concentration impurity area formed in the semiconductor layer as the resistor element; a high concentration impurity area formed in the semiconductor layer as a resistor element wiring portion; and a silicide layer selectively formed on the high concentration impurity area. The high concentration impurity area includes one end portion contacting with an end portion of the low concentration impurity area, and the other end portion contacting with an impurity area of another element. | 2008-10-02 |
20080237802 | STRUCTURES INCLUDING PASSIVATED GERMANIUM - A method of passivating germanium that comprises providing a germanium material and carburizing the germanium material to form a germanium carbide material. The germanium carbide material may be formed by microwave-plasma enhanced chemical vapor deposition by exposing the germanium material to a microwave generated plasma that is formed from a carbon-containing source gas and hydrogen. The source gas may be a carbon-containing gas selected from the group consisting of ethylene, acetylene, ethanol, a hydrocarbon gas having from one to ten carbon atoms per molecule, and mixtures thereof. The resulting germanium carbide material may be amorphous and hydrogenated. The germanium material may be carburized without forming a distinct boundary at an interface between the germanium material and the germanium carbide material. An intermediate semiconductor device structure and a semiconductor device structure, each of which comprises the germanium carbide material, are also disclosed. | 2008-10-02 |
20080237803 | SEMICONDUCTOR DEVICE HAVING STRUCTURE WITH FRACTIONAL DIMENSION OF THE MINIMUM DIMENSION OF A LITHOGRAPHY SYSTEM - A method for forming a semiconductor device is provided including processing a wafer having a spacer layer and a structure layer, the spacer layer is over the structure layer. The method continues including forming a first sidewall spacer from the spacer layer, forming a structure strip from the structure layer below the first sidewall spacer, forming a masking structure over and intersecting the structure strip, and forming a vertical post from the structure strip below the masking structure. | 2008-10-02 |
20080237804 | QUALITY OF A THIN LAYER THROUGH HIGH-TEMPERATURE THERMAL ANNEALING - A method for forming a structure is provided and includes implanting an atomic species into a donor substrate having an upper surface at a given depth relative to the upper surface to form an embrittlement zone in the donor substrate, the embrittlement zone defining a removable layer within the donor substrate. The method further includes assembling the upper surface of the donor substrate to a receiver substrate. Additionally, the method includes detaching the removable layer from the donor substrate at the embrittlement zone, thereby forming a detachment surface on the removable layer, by high temperature annealing. The high temperature annealing includes a temperature upgrade phase to a predetermined maximum temperature, maintaining the maximum temperature for a predetermined exposure duration, and a temperature downgrade phase. The maximum temperature and the exposure duration are selected so as to prevent the appearance of significant defects at the detachment surface. | 2008-10-02 |
20080237805 | Semiconductor Device and Method for Manufacturing Semiconductor Device - An object is to provide a semiconductor device which is not easily broken even if stressed externally and a method for manufacturing such a semiconductor device. A semiconductor device includes an element layer including a transistor in which a channel is formed in a semiconductor layer and insulating layers which are formed as an upper layer and a lower layer of the transistor respectively, and a plurality of projecting members provided at intervals of from 2 to 200 μm on a surface of the element layer. The longitudinal elastic modulus of the material for forming the plurality of projecting members is lower than that of the materials of the insulating layers. (111 words) | 2008-10-02 |
20080237806 | THROUGH-ELECTRODE AND SEMICONDUCTOR DEVICE - A three-dimensional semiconductor device is produced by laminating a plurality of semiconductor chips having through-electrodes running through semiconductor substrates, wherein each through-electrode includes an internal electrode, a ring-shaped semiconductor, and an external electrode. The internal electrode is formed using an internal conductive film and includes a plurality of pillar semiconductors, each of which is formed in a rectangular shape or a polygonal shape. The pillar semiconductors are each arranged with a prescribed distance therebetween in connection with the ring-shaped semiconductor. The internal conductive film is embedded in regions between the ring-shaped semiconductor and the pillar semiconductors and between the pillar semiconductors adjoining together. This makes it possible to form trenches having uniform depth, thus realizing a high-speed film growth with respect to the conductive film. | 2008-10-02 |
20080237807 | SEMICONDUCTOR DEVICE - A second electrode is selectively brought into contact with a semiconductor substrate. Specifically, an insulating film having opening portions is provided on the second principal surface of the semiconductor substrate, and the second electrode is provided on the insulating film. The second electrode comes into contact with the second principal surface of the semiconductor substrate through the opening portions. The total area of the opening portions is approximately the half of the total area of the second principal surface of the semiconductor substrate. Consequently, minority carriers (holes) are prevented by the insulating film from being drawn out, and thus, the loss of the minority carriers around the second electrode is decreased. Accordingly, the conductivity modulation effect is improved. Therefore, the forward voltage can be decreased even with a structure in which the impurity concentration of a p type impurity region is decreased in order to shorten a reverse recover time. | 2008-10-02 |
20080237808 | Semiconductor Device and Method of Manufacturing the Same - Disclosed is a semiconductor device in which emitter pad electrodes connected to an active region, collector and base pad electrodes are formed on a surface of a semiconductor substrate. Furthermore, on a back surface of the semiconductor substrate, a backside electrode is formed. Moreover, the emitter pad electrodes connected to a grounding potential are connected to the backside electrode through feedthrough electrodes penetrating the semiconductor substrate in a thickness direction. | 2008-10-02 |
20080237809 | METHOD OF FABRICATING HYBRID ORIENTATION SUBSTRATE AND STRUCTURE OF THE SAME - A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed. | 2008-10-02 |
20080237810 | Controlling substrate surface properties via colloidal coatings - Methods and apparatus to control surface properties via colloidal coatings are described. In one embodiment, colloidal coating may be used on a surface to enhance flow control. Other embodiments are also described. | 2008-10-02 |
20080237811 | METHOD FOR PRESERVING PROCESSING HISTORY ON A WAFER - A method for capturing process history includes performing at least a first process for forming features on a semiconducting substrate. A first cap is formed over a first region of the semiconducting substrate after performing the first process. At least a second process is performed for forming the features in a second region other than the first region while leaving the first cap in place to thereby prevent the features in the first region covered by the first cap from being exposed to the second process. A first characteristic of a first feature is measured in the first region, and a second characteristic of a second feature in the second region is measured. A wafer includes a first partially completed feature disposed in a first region. A first cap is formed above the first partially completed feature. A second partially completed feature is disposed in a second region of the wafer different than the first region. The second partially completed feature is at a later stage of completion than the first partially completed feature. | 2008-10-02 |
20080237812 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping. | 2008-10-02 |
20080237813 | CIRCUIT BOARD AND SEMICONDUCTOR DEVICE - A printed circuit board includes a source interconnect and a ground interconnect, and the circuit board has a two-dimensional geometry having a corner. Protruding portions are provided in circumferences of the source interconnect and the ground interconnect in regions except the corner in plan view, and the source interconnect and the ground interconnect are connected to a common first decoupling capacitor in each of the protruding portions. | 2008-10-02 |
20080237814 | ISOLATED SOLDER PADS - An integrated circuit package is described that includes a die and a lead frame that includes recessed regions for preventing the undesired spread of solder during reflow. The die includes a plurality of solder bumps formed on its active surface. The lead frame includes a plurality of leads, each having an associated solder pad. Each solder pad is suitably positioned adjacent and electrically contacting an associated solder bump on the die. Each lead also includes a recessed region in a region adjacent to the solder pad. The recessed region serves to isolate the surface of the solder pad from the other surfaces of the lead. In this manner, the solder of the solder bump that contacts the lead is confined to the surface of the associated solder pad. | 2008-10-02 |
20080237815 | TAPE CARRIER, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A tape carrier includes: a base film with insulating property; a wiring pattern provided on the base film within a product region, the product region being demarcated by a cutting line so as to divide the tape carrier into individual products by cutting along the tape carrier along the cut line; and a solder resist provided on the base film so as to cover the wiring pattern. The solder resist protrudes outward from within the product region. | 2008-10-02 |
20080237816 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH ENCAPSULATING FEATURES - An integrated circuit package system is provided including forming a lead frame includes forming a mold gate, providing a first surface, and providing a second surface opposite the first surface; and forming angled gate sides facing each other in the mold gate between the first surface and the second surface. | 2008-10-02 |
20080237817 | INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK SPACER STRUCTURES - An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit die over the package substrate wherein the integrated circuit die has a mount height; attaching an attachment structure having a height substantially the same as the mount height and planar dimensions predetermined to fit adjacent the integrated circuit die and over the package substrate; and attaching a heat dissipation device over the integrated circuit die and the attachment structure. | 2008-10-02 |
20080237818 | METHODS AND APPARATUS FOR MULTI-STAGE MOLDING OF INTEGRATED CIRCUIT PACKAGE - Methods and apparatus for providing an integrated circuit using a multi-stage molding process to protect wirebonds. In one embodiment, a method includes attaching a die to a leadframe having a lead finger, attaching a wirebond between the die and the leadfinger, applying a first mold material over at least a portion of the wirebond and the die and the leadfinger to form an assembly, waiting for the first mold material to at least partially cure, and applying a second mold material over the assembly. | 2008-10-02 |
20080237819 | Bipolar Carrier Wafer and Mobile Bipolar Electrostatic Wafer Arrangement - The present invention relates to a bipolar carrier wafer and a mobile, bipolar electrostatic wafer arrangement. Carrier wafers and wafer arrangements of this type can be used in particular in the field of handling technology of semiconductor wafers. The carrier wafer according to the invention serves for mounting a disc-shaped semiconductor component. It has a first surface ( | 2008-10-02 |
20080237820 | Package structure and method of manufacturing the same - A package structure including a substrate, a shielding element, a chip, a sealant layer and a semiconductor device is provided. The substrate has a first surface and a second surface opposite to the first surface. The shielding element is disposed on the first surface. The chip is disposed on the shielding element and is electrically connected to the substrate. The sealant layer is disposed on the first surface, and encapsulates the chip and the shielding element. The semiconductor device is disposed on the second surface. | 2008-10-02 |
20080237821 | Package structure and manufacturing method thereof - A package structure and a manufacturing method thereof are provided. The package structure includes a substrate, a shielding plate, a first chip, a first sealant, a second chip and a second sealant. The substrate has a lower surface and an upper surface on which the shielding plate is disposed. The first chip disposed on the shielding plate is electrically connected to the substrate. The first sealant disposed on the upper surface encapsulates the shielding plate and the first chip. The second chip disposed on the lower surface is electrically connected to the substrate. The second sealant disposed on the lower surface encapsulates the second chip. | 2008-10-02 |
20080237822 | Microelectronic die having nano-particle containing passivation layer and package including same - A microelectronic die and a package including the die. The die comprises a die substrate including a base and a die passivation layer disposed on the base. The die passivation layer includes a nanocomposite including a matrix and nanoparticles dispersed within the matrix. | 2008-10-02 |
20080237823 | Aluminum Based Bonding of Semiconductor Wafers - Aluminum or aluminum alloy on each of a pair of semiconductor wafers is thermocompression bonded. Aluminum-based seal rings or electrical interconnects between layers may be thus formed. On a MEMS device, the aluminum-based seal ring surrounds an area occupied by a movably attached microelectromechanical structure. According to a manufacturing method, wafers have an aluminum or aluminum alloy deposited thereon are etched to form an array of aluminum-based rings. The wafers are placed so as to bring the arrays of aluminum-based rings into alignment. Heat and compression bonds the rings. The wafers are singulated to separate out the individual semiconductor devices each with a bonded aluminum-based ring. | 2008-10-02 |
20080237824 | Stacked electronic component package having single-sided film spacer - A method of fabricating a stacked electronic component package includes placing a single-sided film spacer on an upper surface of a lower electronic component inward of bond pad with a pickup tool. After being adhered to the upper surface of the lower electronic component, the pickup tool is retracted from the single-sided film spacer. An upper surface of a film, e.g., an organic film, of the single-sided film spacer is nonadhesive. Accordingly, the single-sided film spacer does not stick to the pickup tool during retraction of the pickup tool from the single-sided film spacer. | 2008-10-02 |
20080237825 | STACKED INTEGRATED CIRCUIT PACKAGE SYSTEM WITH CONDUCTIVE SPACER - A stacked integrated circuit package system is provided including providing a first device and a second device with the first device, the second device, or a combination thereof having an integrated circuit die; forming a conductive spacer structure over the first device with the conductive spacer structure having a spacer filler around a conductive element; mounting the second device over the conductive spacer structure and the first device; and encapsulating the first device, the second device, and the conductive spacer structure. | 2008-10-02 |
20080237826 | Method for protecting encapsulated sensor structures using stack packaging - A method of protecting a micro-mechanical sensor structure embedded in a micro-mechanical sensor chip, in which the micro-mechanical sensor structure is fabricated with a protective membrane, the micro-mechanical sensor chip is arranged so that a surface of the protective membrane faces toward a second chip, and the micro-mechanical sensor chip is secured to the second chip. | 2008-10-02 |
20080237827 | Integrated circuit with flexible planer leads - A microelectronic device including a microelectronic circuit and at least one planar flexible lead. These planar flexible leads are adapted to bend and flex during mechanical stress allow direct mounting of the device to a member, and withstand extreme thermal cycling, such as −197° C. to +150° C. such as encountered in space. | 2008-10-02 |
20080237828 | SEMICONDUCTOR DEVICE PACKAGE WITH DIE RECEIVING THROUGH-HOLE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE-SURFACES FOR WLP AND METHOD OF THE SAME - The present invention discloses a structure of package comprising a substrate with at least one die receiving through holes, a conductive connecting through holes structure and a contact pads on both side of substrate. At least one die is disposed within the die receiving through holes. A first material is formed under the die and second material is formed filled in the gap between the die and sidewall of the die receiving though holes. Dielectric layers are formed on the surface of both side of the die and the substrate. Redistribution layers (RDL) are formed on the both sides and coupled to the contact pads. A protection bases are formed over the RDLs. | 2008-10-02 |
20080237829 | High current lead electrode for semiconductor device - A semiconductor package that includes a lead frame riveted to pillars electrically connect to an electrode of a semiconductor die. | 2008-10-02 |
20080237830 | Semiconductor device - There is provided a semiconductor device whose cost is low and whose case is restrained from breaking. In the semiconductor device having a semiconductor sensor chip, a signal processing circuit for processing signals output from the semiconductor sensor chip and a hollow case for mounting the semiconductor sensor chip and the signal processing circuit therein, the case is constructed by bonding a concave bottom member whose one end is opened with a plate-like lid member that covers the opening of the bottom member. Then, the bottom and lid members are both made of a semiconductor material and are bonded by means of anode bonding or metal bonding for example. | 2008-10-02 |
20080237831 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed according to the present invention, the package structure includes: a carrier board having a first surface, a second surface, and at least an opening penetrating the first and second surfaces, the first and second surfaces each having electrically connecting pads; a semiconductor component received in the opening, the semiconductor component has a first active surface and a second active surface, and each of the first and second active surfaces has a plurality of electrode pads; a plurality of first conductive elements electrically connected to the electrically connecting pads of the first and second surfaces of the carrier board with the electrode pads of the first and second active surfaces of the semiconductor component; and a molding material formed on a portion of the first surface of the carrier board, the first active surface of the semiconductor component, a portion of the second surface of the carrier board, and the second active surface of the semiconductor component, and adapted to cover the first conductive elements; thereby forming a module structure for electrical connection with other modules or stacked devices, and further enhancing electrical functions. | 2008-10-02 |
20080237832 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed, including a carrier board having a first and an opposing second surfaces and formed with at least an opening penetrating the first and second surfaces, wherein a plurality of electrically connecting pads are formed on the first and second surfaces of the carrier board, respectively; a semiconductor component disposed in the opening, the semiconductor component having a first and a second active surfaces each with a plurality of electrode pads being formed thereon; a third semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a fourth semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component, thereby providing a modularized structure for electrically connecting with other modules or stack devices and enhancing electrical functionality. | 2008-10-02 |
20080237833 | MULTI-CHIP SEMICONDUCTOR PACKAGE STRUCTURE - A multi-chip semiconductor package structure is disclosed according to the present invention. The package structure includes: a carrier board having a first surface, a second surface, and at least one opening penetrating the first and second surfaces, the first and second surfaces each being formed with a plurality of electrically connecting pads thereon; a semiconductor component received in the opening and having first and second active surfaces, the first and second active surfaces each being formed with a plurality of electrode pads thereon; a plurality of first conductive elements electrically connected to the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component; a semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads electrically connected to the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a molding material formed on a portion of the second surface of the carrier board and the second active surface of the semiconductor component to cover the first conductive elements. The present invention provides a modularized structure capable of electrically connecting to other modules or stacked devices as well as enhancing electrical performance. | 2008-10-02 |
20080237834 | CHIP PACKAGING STRUCTURE AND CHIP PACKAGING PROCESS - A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost. | 2008-10-02 |
20080237835 | NON-UNIFORM FEEDTHROUGH AND LEAD CONFIGURATION FOR A TRANSISTOR OUTLINE PACKAGE - A transistor outline package having a feedthrough via and lead configuration that maximizes the amount of usable area on a header of the package is disclosed. In one embodiment, the package includes a header having an interior surface that includes a first and second lead assembly. The first lead assembly includes two vias having a first diameter, with each first via being positioned along a first pin circle imaginarily defined on the interior surface of the header. Each first via also includes first leads received therein. The second lead assembly includes four vias having a second diameter each, with each second via being positioned along a second pin circle that has a diameter greater than that of the first pin circle. Each second via includes second leads received therein. This configuration increases usable area on the header interior surface between the leads, enabling relatively larger submounts to be placed thereon. | 2008-10-02 |
20080237836 | SEMICONDUCTOR CHIP EMBEDDING STRUCTURE - A semiconductor chip embedding structure is disclosed, including a carrier board having a first and an opposed second surfaces and formed with at least a through hole; a semiconductor chip received in the through hole, the chip having an active surface and an inactive surface opposite to one another, wherein the active surface has a plurality of electrode pads, a passivation layer is formed on the active surface with the electrode pads exposed from the passivation layer, and metal pads are formed on surfaces of the electrode pads; a buffer layer formed on the first surface of the carrier board and on surfaces of the passivation layer and the metal pads; a first dielectric layer formed on the buffer layer; and a first circuit layer formed on the first dielectric layer and electrically connected with the metal pads of the chip via first conductive structures formed in the buffer layer and the first dielectric layer, wherein the CTE (Coefficient of Thermal Expansion) of the buffer layer is between the CTE of the semiconductor chip and the CTE of the dielectric layer. Thereby, the buffer layer can reduce the stress on the interface between the dielectric layer and the semiconductor chip. | 2008-10-02 |
20080237837 | Integrated Circuit Arrangement - An integrated circuit arrangement including a nonplanar substrate on which an integrated circuit is formed on at least one side, wherein the side of the substrate a which has the integrated circuit is arranged on a carrier and the carrier is produced from a chemically resistant material. | 2008-10-02 |
20080237838 | Semiconductor device - The semiconductor device includes a plurality of semiconductor chips, and a circuit substrate having a substantially rectangular outer shape. The semiconductor device is an MCM having an MCM packaging structure in which the plurality of semiconductor chips are juxtaposed on the semiconductor chip mounting surface of the circuit substrate, and the semiconductor chip mounting surface is covered by a sealing resin along an outer edge of the circuit substrate so that the plurality of semiconductor chips are sealed. The thickness of the semiconductor chip to be mounted so as to traverse a center line has a thicker thickness in a direction perpendicular to the semiconductor chip mounting surface than the thickness of any of the other semiconductor chips which is mounted on the semiconductor chip mounting surface, the center line being defined an intersection of (i) a longitudinal cross section which divides the semiconductor chip mounting surface into two in a longitudinal direction of the semiconductor chip mounting surface and (ii) a transverse cross section which divides the semiconductor chip mounting surface into two in a transverse direction of the semiconductor chip mounting surface. This enables to suppress the warpage generated in the semiconductor device, and to reduce inadequate connection occurred due to the warpage in the semiconductor device. | 2008-10-02 |
20080237839 | Semiconductor apparatus and method of manufacturing same - A semiconductor apparatus and a method of manufacturing same can simplify the manufacturing process and prevent a decrease in production yield without decreasing in sensor sensitivity. A semiconductor apparatus includes a package having a first region having a first thickness, a second region having a second thickness greater than the first thickness, the second region being surrounded by the first region, a third region having a third thickness greater than the second thickness, the third region being surrounded by the second region, and at least one connection pad electrically provided in the third region and connected to an external of the package; a sensor chip having a first weight section, a fixed section surrounding the first weight section and being separated from the first weight section, and a beam section having an elasticity and connecting the first weight section to the fixed section, the fixed section being positioned at the second region of the package; and a second weight section separated from the fixed section and the beam section and connected to the first weight section via an adhesive layer. | 2008-10-02 |
20080237840 | Flexible circuit electronic package with standoffs - A flexible circuit electronic package including a heat sink, a flexible circuit having a semiconductor chip positioned thereon and electrically coupled thereto, and a quantity of heat shrunk adhesive securing the flexible circuit to the heat sink such that the flexible circuit is planar. This package is then adapted for being positioned on and electrically coupled to a circuitized substrate such as a printed circuit board. A method of making this package is also provided. | 2008-10-02 |
20080237841 | Microelectronic package, method of manufacturing same, and system including same - A microelectronic package includes a substrate ( | 2008-10-02 |
20080237842 | Thermally conductive molding compounds for heat dissipation in semiconductor packages - Methods and apparatus relating to thermally conductive molding compounds are described. In one embodiment, a molding compound may include thermally conductive particles to form a thermally conductive path in the molding compound (e.g., for improved heat dissipation through the molding compound). Other embodiments are also described. | 2008-10-02 |
20080237843 | Microelectronic package including thermally conductive sealant between heat spreader and substrate - A microelectronic package. The package includes a substrate; a die mounted onto the substrate; an integrated heat spreader mounted onto the substrate, and thermally coupled to a backside of the die; and a sealant material bonding the integrated heat spreader to the substrate, the sealant material having a bulk thermal conductivity above about 1 W/m/° C. and a modulus of elasticity lower than a modulus of elasticity of solder. | 2008-10-02 |