39th week of 2012 patent applcation highlights part 44 |
Patent application number | Title | Published |
20120244608 | Composite sensor assemblies for single use bioreactors - A composite sensor assembly for monitoring bio-processes which is suitable for use with a polymeric bioprocess vessel or with downstream equipment, and comprises:
| 2012-09-27 |
20120244609 | Composite sensor assemblies for single use bioreactors - A composite sensor assembly for monitoring bio-processes which is suitable for use with a polymeric bioprocess vessel or with downstream equipment, and comprises:
| 2012-09-27 |
20120244610 | PHOTO-DAMAGE APPARATUS FOR SORTING PARTICLES - A system and apparatus for sorting a mixture of stained particles in a fluid flow path, including stained particles. The system can include a pulsed electromagnetic radiation source for exciting fluorescence emissions from the stained particles, a photodetector for detecting the fluorescence emissions from the stained particles, a processor for classifying the stained particles; and a photo-damaging laser for damaging selected particles in the flow path. | 2012-09-27 |
20120244611 | VERMICOMPOSTING DEVICE - A vermicomposting device for vermicomposting organic material, comprises a casing including an annular hollow body member defining an internal cavity, a head member mounted to an upper end portion of the body member and a base member removably attached to a lower end portion of the body member, and a plurality of composting trays removably disposed within the internal cavity in a stacked relationship. Each of the composting trays is an open top tray including a circular perforated bottom wall surrounded by an annular side wall upwardly extending from the perforated bottom wall. The base member includes a support portion and a drip bucket disposed under the composting trays to receive and collect any liquid byproduct from the vermicomposting process. The head member is movable relative to the body member so as to provide an access to the internal cavity of the body member. | 2012-09-27 |
20120244612 | COMPOSTER - In a rotary composter having a horizontally elongated rotatable cylindrical drum, material is fed from a hopper into the drum through an opening in a stationary end plate having an annular marginal area which overlaps, in sealing relationship, an annular intake end wall extending inward from the internal wall of the drum from a location adjacent to an intake end of the drum. At an exit end of the drum material passes through a central opening in an annular exit end wall and falls by gravity onto a cylindrical screen which is fixed to, and rotates with, the exit end wall. The annular end walls are in axial register with external trunnions on the drum which ride on pairs of supporting rollers. The exit end rollers allow for axial expansion of the drum. The interior wall the drum is lined with a rubber. | 2012-09-27 |
20120244613 | HUMAN MICRORNAS AND METHODS FOR INHIBITING SAME - The invention relates to isolated DNA or RNA molecules comprising at least ten contiguous bases having a sequence in a microRNA shown in SEQ ID NOs: 1-94; 281-374; 467-481; 497-522; or 549, except that up to thirty percent of the bases may be wobble bases, and up to 10% of the contiguous bases may be non-complementary. The invention further relates to modified single stranded microRNA molecules, isolated single stranded anti-microRNA molecules and isolated microRNP molecules. In another embodiment, the invention relates to a method for inhibiting microRNP activity in a cell. | 2012-09-27 |
20120244614 | METHOD FOR CULTURING MYCOPLASMA CONTAMINATION-FREE CELLS AND METHOD FOR REMOVING MYCOPLASMA CONTAMINATION OF CELLS - Provided is a method for culturing cells, which prevents the possibility of mycoplasma contamination by culturing the cells using biomass extract obtained by culturing a strain with amphidinol productivity, preferably a strain such as | 2012-09-27 |
20120244615 | ISOLATED A-TYPE FHF N-TERMINAL DOMAIN PEPTIDES AND METHODS OF USE - Isolated peptides are provided that are effective in inducing long-term inactivation of voltage-gated sodium channels (VGSCs) in mammalian cells. Such peptides are useful in reducing the action potentials of these excitable cells, for example, neurons, myocytes, and tonic muscle cells, in mammals in need thereof. | 2012-09-27 |
20120244616 | METHOD OF OOCYTE CRYOPRESERVATION USING ANTIFREEZE PROTEIN - Disclosed is a method for cryopreserving an oocyte by adding an antifreeze protein to a cryopreservation liquid (equilibrium solution, vitrification solution). The disclosed cryopreservation method of an oocyte minimizes damage to the oocyte, which increases the survival rate of the oocyte after freezing and thawing of the oocyte, and improves a fertilization rate, and a blastocyst development ratio of the oocyte. | 2012-09-27 |
20120244617 | MESH ENCLOSED TISSUE CONSTRUCTS - Described is a scaffold that is strong enough to resist forces that exist inside a body, while possessing biocompatible surfaces. The scaffold is formed of a layer of mesh (e.g., Stainless Steel or Nitinol) that is tightly enclosed by a multi-layer biological matrix. The biological matrix can include three layers, such a first layer (smooth muscle cells) formed directly on the metal mesh, a second layer (fibroblast/myofibroblast cells) formed on the first layer, and a third layer (endothelial cells) formed on the second layer. The scaffold can be formed to operate as a variety of tissues, such as a heart valve or a vascular graft. For example, the mesh and corresponding biological matrix can be formed as leaflets, such that the scaffold is operable as a tissue heart valve. | 2012-09-27 |
20120244618 | METHODS AND SYSTEMS FOR IDENTIFYING MICRO-RNA TARGETS AND SYNTHESIZING NOVEL MICRO-RNAS AND USES OF THE SAME - Method of identifying a microRNA-recognition element and of generating microRNAs are disclosed. System and computer programs for performing such methods are disclosed. Recombinant nucleic acid molecule comprising a heterologous coding sequences and one or more MREs are also disclosed as are isolated nucleic acid molecule comprising one or more MRE sequences and being free of a coding sequence operably linked to regulatory elements. MicroRNA generated by a methods of the invention and the usr of the microRNAs to downregulate gene expression are disclosed. | 2012-09-27 |
20120244619 | COMPOSITION FOR PROMOTING DIFFERENTIATION OF PLURIPOTENT STEM CELLS INTO CARDIAC MUSCLE CELLS WHICH COMPRISES NITROVIN - The present invention provides a composition for promoting differentiation of pluripotent stem cells into cardiac muscle cells which comprises nitrovin, a method for inducing differentiation of pluripotent stem cells into cardiac muscle cells by using nitrovin and a method for preparing cardiac muscle cells by using nitrovin. | 2012-09-27 |
20120244620 | COMPOSITIONS AND METHODS FOR INDUCING THE ACTIVATION OF IMMATURE MONOCYTIC DENDRITIC CELLS - The present invention provides methods for inducing the maturation of immature dendritic cells (DC) and for activating those cells without the use of a dendritic cell maturation agent. The activated DC can be used for inducing an antigen specific T cell response. Methods of the invention can also comprise the addition of a directional maturation agent, such as interferon gamma, to induce a Th-1 and/or Th-2 bias in the response obtained. The present invention also provides dendritic cell populations useful for activating and for inducing antigen specific T cells. Similarly, activated antigen specific T cell populations, and methods of making the same are provided. | 2012-09-27 |
20120244621 | TUMOR-SPECIFIC BACTERIAL PROMOTER ELEMENTS - The invention relates to bacterial promoter elements which constitute or which are comprised in promoter regions and which confer tumour specificity to the promoter region activity, resulting in transcription of a transgene, which can be a heterologous or a homologous gene, which transgene is functionally arranged downstream of the promoter region at presence of a host bacterium in tumour tissue, while essentially conferring inactivity of the promoter region and no transcription at presence of the host bacterium in non-tumour tissue. Accordingly, the invention relates to bacterial promoter regions containing these tumour specific promoter elements. | 2012-09-27 |
20120244622 | REGULATED GENE EXPRESSION SYSTEMS AND CONSTRUCTS THEREOF - Compositions and methods for nitrogen sensitive regulation of expression of a transcribable nucleic acid molecule. One aspect provides a nitrogen-sensitive expression system that includes a transcription factor region comprising an NtcA binding site and a core promoter region comprising a RuBisCo promoter or a variant or a functional fragment thereof. Another aspect provides a method of transforming a host cell with an expression system. Also provided are expression cassettes, transformed host cells, and kits. | 2012-09-27 |
20120244623 | TAMPER EVIDENT INDICATING DEVICES - A variety of indicators, e.g., time, temperature, time-temperature, freeze, thaw and sterilization are reported and used for monitoring quality of perishables. However, these indicators are tamperable, e.g., an indicator can be opened, removed, repositioned, exchanged or replaced. Disclosed are tamper evident time, temperature, time-temperature, freeze, thaw, sterilization and like indicating devices. If an indicator is tampered, it will be either destroyed or will provide a visual indication or a message, such as “VOID” or “TAMPERED”. | 2012-09-27 |
20120244624 | ANALYZING METHOD AND SYSTEM FOR TEST STRIPS - An exemplary test strip reading and analyzing system includes a test strip unit, a mobile device and a remote computing apparatus. The test strip unit includes at least one tested-object reacting region. The mobile device includes an image capture module for capturing a test-strip image of the test strip unit and a transmission module electrically coupled to the image capture module. The remote computing apparatus, installed with a test strip analyzing system, is for analyzing the test-strip image and accordingly generating an test report. The test-strip image captured by the image capture module is transmitted to the remote computing apparatus through the transmission module; and the test report generated by the remote computing apparatus is consequently transmitted to the mobile device. | 2012-09-27 |
20120244625 | Reductive Amination and Analysis of Carbohydrates Using 2-Picoline Borane as Reducing Agent - The invention provides the use of 2-picoline borane (2-PB) for the reductive amination of carbohydrates, especially glycans from book plasma, wherein the concentration of 2-PB is less than the concentration of NaBH(OAc) | 2012-09-27 |
20120244626 | NANOHYBRID NITROGEN MONOXIDE DETECTING SENSOR AND A PRODUCTION METHOD THEREFOR - The present invention provides a nanohybrid type nitrogen monoxide detecting sensor and a production method therefor in which the nanohybrid type nitrogen monoxide detecting sensor includes a fluorescent semiconducting quantum dot and a transition metal compound. | 2012-09-27 |
20120244627 | Methods for Quantifying Vitamin D Metabolites by Mass Spectrometry - Provided are methods of detecting the presence or amount of a dihydroxyvitamin D metabolite in a sample using mass spectrometry. The methods generally comprise associating an amine with a dihydroxyvitamin D metabolite in a sample, ionizing the adduct, and detecting the amount of the ion to determine the presence or amount of the vitamin D metabolite in the sample. | 2012-09-27 |
20120244628 | LIQUID ANALYSIS SYSTEM - A liquid analysis system for a photometric determination of an analyte in a liquid sample includes an analyzer comprising a photometer, an RFID parameter reading device and an identifier reading device, and a cuvette package comprising an RFID parameter transponder and a plurality of test cuvettes of one batch. Each test cuvette comprises a reagent. Batch identification and batch-specific reagent data are stored in the RFID parameter transponder. Each test cuvette comprises a batch-specific identifier including a batch identification. The batch identification is configured to be read by the identifier reading device. | 2012-09-27 |
20120244630 | MULTIPLEXED ANALYTE CONCENTRATION MEASUREMENT - Disclosed is a method of multiplexed concentration measurement of one or more analytes in a sample by means of electrical impedance measurements, the method comprises the steps of : providing the sample; providing a plurality of subsets of particles with capture molecules specific for at least one of the analytes, where the particles in each subset are distinguishable from the particles in the other subsets; mixing the sample with the subsets of particles, wherein the method further comprises the steps of: measure the change in the electrical impedance measurement, when the particles pass one or more sets of electrodes; determining the concentration of the one or more analytes by analyzing the electrical measurement change associated with the particles passing by the electrodes, where the concentration of the one or more analytes are determined based on a change in a property of the respective particles. | 2012-09-27 |
20120244631 | Apparatus and Method for Determining Microscale Interactions Based on Compressive Sensors such as Crystal Structures - Techniques for determining values for a metric of microscale interactions include determining a mesoscale metric for a plurality of mesoscale interaction types, wherein a value of the mesoscale metric for each mesoscale interaction type is based on a corresponding function of values of the microscale metric for the plurality of the microscale interaction types. A plurality of observations that indicate the values of the mesoscale metric are determined for the plurality of mesoscale interaction types. Values of the microscale metric are determined for the plurality of microscale interaction types based on the plurality of observations and the corresponding functions and compressed sensing. | 2012-09-27 |
20120244632 | STEROL GLUCOSIDE TOXINS - The invention relates to the identification of sterol glucoside toxins, and provides methods for detecting and detoxifying the compounds, as well as therapeutic methods for treating subjects exposed to such toxins. In alternative embodiments, the toxins may for example include beta-sitostrol-beta-D-glucoside (5-cholesten-24b-ethyl-3b-ol-D-glucoside) or cholesterol glucoside (5-cholesten-3b-ol-3b-D-glucoside). | 2012-09-27 |
20120244633 | LIGHT-EMITTING INTRA-CAVITY INTERFEROMETRIC SENSORS - Light-emitting intra-cavity interferometric (ICI) optical sensors based on channel waveguide structures which include an internal light emitting material and a functionalized region. In some embodiments, the waveguides are made of a sol-gel which incorporates the light emitting material. In some embodiments, the waveguide structure includes an ICI resonator backbone and the ICI sensor is a laser sensor. In some embodiments, the resonator backbone has an interferometric Y-branch shape. In some embodiments, the resonator backbone has a Mach Zehnder interferometer shape. In some embodiments, an ICI laser sensor has an interferometric arrayed waveguide grating shape. In some embodiments, an ICI sensor may be remotely optically pumped and remotely read. | 2012-09-27 |
20120244634 | METHOD FOR DETECTION OF BASIC PEPTIDE AND REAGENT FOR DETECTION OF BASIC PEPTIDE - The present invention provides a method for detection of a basic peptide by mixing a sample suspected to contain the basic peptide and a reagent containing denatured albumin and detecting turbidness due to a complex of the basic peptide and denatured albumin. | 2012-09-27 |
20120244635 | NANOCHANNEL ARRAYS AND NEAR-FIELD ILLUMINATION DEVICES FOR POLYMER ANALYSIS AND RELATED METHODS - Provided are devices and methods for polymer analysis, in which labeled polymers are translocated along nanochannels that have illuminated detection regions within. As a labeled polymer translocates along the nanochannel and the labels pass over the illuminated detection regions, the labels become detectable (e.g., where different labels fluoresce in response to different wavelengths present at different illumination regions), and the user generates a spatial map of the location of the various labels along the length of the polymer. The location of the labels is then correlated to one or more structural characteristics of the polymer. | 2012-09-27 |
20120244636 | INCORPORATION OF METHYL LYSINE INTO POLYPEPTIDES - The invention relates to A method of making a polypeptide comprising at least one N | 2012-09-27 |
20120244637 | METHOD AND SYSTEM FOR INTERACTION ANALYSIS - A method of determining one or more interaction parameters for the interaction between an analyte and a ligand using a biosensor, which comprises the steps of: A: providing a sensor surface having the ligand immobilized thereto, B: contacting the sensor surface with a control analyte, C: registering the sensor response from binding of the control analyte to binding sites of the ligand, D: determining the control saturation response (R | 2012-09-27 |
20120244638 | METHOD AND SYSTEM FOR BINDING BEHAVIOR ANALYSIS - A method of evaluating an interaction parameter for the interaction between a plurality of analytes and a ligand using a biosensor, which comprises the steps of:
| 2012-09-27 |
20120244639 | METHOD OF MANUFACTURING MAGNETIC MEMORY - According to one embodiment, a method of manufacturing a magnetic memory, the method includes forming a first magnetic layer having a variable magnetization, forming a tunnel barrier layer on the first magnetic layer, forming a second magnetic layer on the tunnel barrier layer, the second magnetic layer having an invariable magnetization, forming a hard mask layer as a mask on the second magnetic layer, patterning the second magnetic layer by using the mask of the hard mask layer, and executing a GCIB-irradiation by using the mask of the hard mask layer, after the patterning. | 2012-09-27 |
20120244640 | METHOD OF MANUFACTURING MULTILAYER FILM - According to one embodiment, a method of manufacturing a multilayer film, the method includes forming a first layer, forming a second layer on the first layer, and transcribing a crystal information of one of the first and second layers to the other one of the first and second layers by executing a GCIB-irradiation to the second layer. | 2012-09-27 |
20120244641 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The device includes a magnetoresistance effect element using magnetic material containing at least one of cobalt, iron, and nickel. Forming the element includes forming a stacked body above a semiconductor substrate. The stacked body includes layers. The layers includes the magnetic material. Forming the element further includes processing the stacked body in a vacuum atmosphere by plasma etching using a first gas containing chlorine. Forming the element further includes subjecting the stacked body to a gas treatment using a second gas containing an amino group while holding the stacked body in the vacuum atmosphere. | 2012-09-27 |
20120244642 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method for manufacturing a semiconductor device including a semiconductor substrate having transistors formed thereon, a first interlayer insulating film formed above the semiconductor substrate and the transistors, a ferroelectric capacitor formed above the first interlayer insulating film, a second interlayer insulating film formed above the first interlayer insulating film and the ferroelectric capacitor, a first metal wiring formed on the second interlayer insulating film, and a protection film formed on an upper surface of the wiring but not on a side surface of the wiring. | 2012-09-27 |
20120244643 | Light-Emitting Device and Manufacturing Method Thereof - An EL light-emitting element in which a lower electrode layer, an EL layer, and an upper electrode layer are stacked is formed on a substrate, and a wiring is formed on a counter substrate. Further, the substrate and the counter substrate are bonded so that the wiring is in physical contact with the upper electrode layer of the EL element. Accordingly, the wiring can serve as an auxiliary wiring for increasing conductivity of the upper electrode layer. With such an auxiliary wiring, a potential drop due to the resistance of the upper electrode layer can be suppressed even in the light-emitting device whose light-emitting portion is large. | 2012-09-27 |
20120244644 | System and Method for Increasing Productivity of Organic Light Emitting Diode Material Screening - A system and method of increasing productivity of OLED material screening includes providing a substrate that includes an organic semiconductor, processing regions on the substrate by combinatorially varying parameters associated with the OLED device production on the substrate, performing a first characterization test on the processed regions on the substrate to generate first results, processing regions on the substrate in a combinatorial manner by varying parameters associated with the OLED device production on the substrate based on the first results of the first characterization test, performing a second characterization test on the processed regions on the substrate to generate second results, and determining whether the substrate meets a predetermined quality threshold based on the second results. | 2012-09-27 |
20120244645 | ELECTROSTATIC POST EXPOSURE BAKE APPARATUS AND METHOD - An Electrostatic Post Exposure Bake (EPEB) subsystem comprising an Electrostatic Bake Plate (EBP) configured in a processing chamber in an EPEB subsystem, wherein the EPEB wafer comprises an exposed masking layer having unexposed regions and exposed regions therein and the EPEB wafer is developed using the EBP. | 2012-09-27 |
20120244646 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND ADJUSTING APPARATUS - According to embodiments, there is provided a manufacturing method of a semiconductor device includes forming a semiconductor thin film on a substrate; processing the thin film to a predetermined shape; executing an ion implantation process on the thin film processed to the predetermined shape; executing an anneal treatment on the thin film on which the ion implantation process has been executed to create a resistor element; and adjusting both or any one of a process condition of the ion implantation process and a treatment condition of the anneal treatment based on at least any one of a film forming condition and a film formation result of the forming and a film process result of the processing. | 2012-09-27 |
20120244647 | Pick-Up Method of Die Bonder and Die Bonder - The present invention provides a die bonder capable of stripping a die without fail, or a highly reliable die bonder or pick-up method using the die bonder. | 2012-09-27 |
20120244648 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To improve the reliability in an electric inspection of a semiconductor device. When a movable pedestal | 2012-09-27 |
20120244649 | POLISHING METHOD, POLISHING APPARATUS AND POLISHING TOOL - A polishing method and a polishing apparatus particularly suitable for finishing a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that a surface of a substrate of a compound semiconductor containing an element of Ga can be flattened with high surface accuracy within a practical processing time. In the presence of water ( | 2012-09-27 |
20120244650 | Air-Stable Ink for Scalable, High-Throughput Layer Deposition - A method for producing and depositing air-stable, easily decomposable, vulcanized ink on any of a wide range of substrates is disclosed. The ink enables high-volume production of optoelectronic and/or electronic devices using scalable production methods, such as roll-to-roll transfer, fast rolling processes, and the like. | 2012-09-27 |
20120244651 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE - A method for manufacturing light emitting diodes includes steps: providing a substrate having an upper conductive layer and a lower conductive layer formed on a top face and bottom face thereof; dividing each of the upper conductive layer and the lower conductive layer into first areas and second areas; defining cavities in the substrate through the first areas of the upper conductive layer to expose the lower conductive layer; forming conductive posts within the substrate; forming an overlaying layer to connect the first areas of the upper and lower conductive layers; mounting chips on the overlaying layer within the cavities and electrically connecting each chip with an adjacent first area and post; forming an encapsulant on the substrate to cover the chips; and cutting the substrate into individual packages. | 2012-09-27 |
20120244652 | METHODS OF FABRICATING LIGHT EMITTING DIODE DEVICES - An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor. | 2012-09-27 |
20120244653 | METHOD FOR PRODUCING GROUP III NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT - A reflective film including Ag of an Ag alloy is patterned in a uniform thickness without decreasing reflectivity. The reflective film is formed on the entire surface of a first insulating film by sputtering, vacuum deposition or the like, and a barrier metal film having a given pattern is formed on the reflective film by a lift-off method. The reflective film is wet etched using a silver etching liquid. The barrier metal film is not wet etched by the silver etching liquid, and therefore functions as a mask, and the reflective film in a region on which the barrier metal film has been formed remains not etched. As a result, the reflective film having a desired patter can uniformly be formed on the first insulating film. | 2012-09-27 |
20120244654 | ENHANCED PLANARITY IN GaN EDGE EMITTING LASERS - A GaN edge emitting laser is provided comprising a semi-polar GaN substrate, an active region, N-side and P-side waveguiding layers, and N-type and P-type cladding layers. The GaN substrate defines a 20 | 2012-09-27 |
20120244655 | BACKGRIND PROCESS FOR INTEGRATED CIRCUIT WAFERS - An integrated circuit is formed by coating a top surface of a wafer that has been processed through all integrated circuit chip manufacturing steps prior to backgrind with photoresist, applying backgrind tape over a top surface of the photoresist, backgrinding a back surface of the wafer to a specified thickness, removing the backgrind tape from the top surface of the photoresist, and removing the photoresist. The surface of the integrated circuit and any devices that may be bonded to the surface of the integrated circuit are protected by the photoresist layer during removal of the backgrind tape. | 2012-09-27 |
20120244656 | METHOD AND APPARATUS FOR PRODUCING SOLAR CELL - Disclosed herein are a method and an apparatus for producing a solar cell. The method includes: (a) preparing a rear contact solar cell substrate having electrode patterns formed on a rear surface thereof; (b) performing scribing on a front surface of the substrate on which the electrode patterns are not formed, by using laser; and (c) cutting the substrate in each cell along the scribing so as to form the solar cell. Further, an apparatus for producing a solar cell is operated by the method for producing a solar cell. | 2012-09-27 |
20120244657 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device according to an embodiment, an epitaxial semiconductor layer is epitaxially grown on a semiconductor substrate, a photoelectric converting portion is formed on the epitaxial semiconductor layer, a wiring layer is formed on the epitaxial semiconductor layer after forming the photoelectric converting portion, a support substrate is bonded onto the wiring layer, and the semiconductor substrate is etched from an opposite surface side to a side for the bonding after the bonding. In the method for manufacturing a semiconductor device, an amorphous Si layer is formed on the opposite surface side of the epitaxial semiconductor layer after the etching and an antireflection film and a color filter are formed on the amorphous Si layer in sequence. | 2012-09-27 |
20120244658 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device including an oxide semiconductor, which has stable electric characteristics and high reliability, is provided. In a method for manufacturing a transistor including an oxide semiconductor film, an implantation step where rare gas ions are implanted to the oxide semiconductor film is performed, and the oxide semiconductor film to which rare gas ions are implanted is subjected to a heating step under reduced pressure, in a nitrogen atmosphere, or in a rare gas atmosphere, whereby hydrogen or water contained in the oxide semiconductor film to which rare gas ions are implanted is released; thus, the oxide semiconductor film is highly purified. | 2012-09-27 |
20120244659 | METHOD FOR FORMING OXIDE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for forming an oxide semiconductor film having favorable semiconductor characteristics is provided. In addition, a method for manufacturing a semiconductor device having favorable electric characteristics, with use of the oxide semiconductor film is provided. A method for forming an oxide semiconductor film including the steps of forming an oxide semiconductor film, forming a hydrogen permeable film over and in contact with the oxide semiconductor film, forming a hydrogen capture film over and in contact with the hydrogen permeable film, and releasing hydrogen from the oxide semiconductor film by performing heat treatment. Further, in a method for manufacturing a semiconductor device, the method for forming an oxide semiconductor film is used. | 2012-09-27 |
20120244660 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere. | 2012-09-27 |
20120244661 | Method of Fabricating Semiconductor Die with Through-Hole Via on Saw Streets and Through-Hole Via in Active Area of Die - A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. Metal vias are also formed through the contact pads on the active area of the die. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. Repassivation layers are formed between the RDL for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The vias through the saw streets and vias through the active area of the die, as well as the RDL, provide electrical interconnect to the adjacent die. | 2012-09-27 |
20120244662 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a manufacturing method thereof are disclosed. In accordance with an embodiment of the present invention, the single-layer board on chip package substrate includes an insulator, a circuit pattern and a flip-chip bonding pad, which are formed on an upper surface of the insulator, a conductive bump, which is in contact with a lower surface of the circuit pattern and penetrates through the insulator, a solder resist layer, which is formed on the upper surface of the insulator such that at least a portion of the flip-chip bonding pad is exposed, and a flip-chip bonding bump, which is formed on an upper surface of the flip-chip bonding pad in order to make a flip-chip connection with an electronic component. | 2012-09-27 |
20120244663 | SEMICONDUCTOR DEVICE CHIP MOUNTING METHOD - A semiconductor device chip has a plurality of projecting electrodes mounted on a wiring board or wafer having electrodes respectively corresponding to the projecting electrodes of the semiconductor device chip. An insulator is applied to the front side of the semiconductor device wafer where the projecting electrodes are formed, to fill any spaces between adjacent electrodes with the insulator. The front side of the wafer covered with the insulator is planarized to expose the end surfaces of the projecting electrodes, and the wafer is divided along division lines to obtain a plurality of individual semiconductor device chips. Each chip is mounted on the wiring board or the wafer with an anisotropic conductor interposed between the projecting electrodes of each chip and the electrodes of the wiring board or the wafer to thereby respectively connect the projecting electrodes and the electrodes through the anisotropic conductor. | 2012-09-27 |
20120244664 | REDUCING WARPAGE FOR FAN-OUT WAFER LEVEL PACKAGING - Fan-out wafer level packaging includes an integrated circuit having a top surface, a bottom surface, a plurality of side surfaces, and a bond pad defined on the top surface. A layer of encapsulant substantially surrounds the side surfaces of the integrated circuit, the layer of encapsulant having a height substantially equal to a height of the integrated circuit. A bump is spaced apart from the integrated circuit, and a redistribution layer electrically couples the bond pad of the integrated circuit to the bump. | 2012-09-27 |
20120244665 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes: forming a first layer including crystals by processing a surface of a first electrode of a semiconductor element; forming a second layer including crystals by processing a surface of a second electrode of a mounting member on which the semiconductor element is mounted; reducing a first oxide film present over or in the first layer and a second oxide film present over or in the second layer at a first temperature, the first temperature being lower than a second temperature at which a first metal included in the first electrode diffuses in a solid state and being lower than a third temperature at which a second metal included in the second electrode diffuses in a solid state; and bonding the first layer and the second layer to each other by solid-phase diffusion. | 2012-09-27 |
20120244666 | PRINTED SUBSTRATE MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD - Solder bumps are formed on a plurality of electrode parts of a printed substrate and a semiconductor chip is loaded on the printed substrate via the plurality of solder bumps. In this case, a thermoplastic film is prepared as an underfill that covers a surface of the printed substrate on which the solder bumps are formed. In the film, parts corresponding to the solder bumps are removed and a peripheral edge of a part on which the semiconductor chip will be loaded has a protruded form. After the printed substrate has been covered with the film, the film is bonded onto the board and the semiconductor chip is loaded on the printed substrate and carried into a reflow furnace. In the reflow furnace, heat and pressure are applied to fuse the solder bumps. | 2012-09-27 |
20120244667 | PRECURSOR COMPOSITION FOR OXIDE SEMICONDUCTOR AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - Provided is a precursor composition for an oxide semiconductor. The precursor composition for the oxide semiconductor includes a metal complex compound formed by a metal ion and an organic ligand, wherein the precursor composition is represented by the following Formula 1. | 2012-09-27 |
20120244668 | SEMICONDUCTOR DEVICES WITH LAYOUT CONTROLLED CHANNEL AND ASSOCIATED PROCESSES OF MANUFACTURING - The present technology is directed generally to processes of forming semiconductor devices (e.g., JFET devices). The semiconductor device comprises a gate region, a source region, a drain region and a channel region having a channel size. The channel size is controlled by adjusting a layout width of the gate region. | 2012-09-27 |
20120244669 | Method of Manufacturing Semiconductor Device Having Metal Gates - The present invention provides a method of manufacturing semiconductor device having metal gates. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench. Then, a first metal layer is formed in the first trench. The second sacrifice gate is removed to form a second trench. Next, a second metal layer is formed in the first trench and the second trench. Lastly, a third metal layer is formed on the second metal layer wherein the third metal layer is filled into the first trench and the second trench. | 2012-09-27 |
20120244670 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES - A substrate including an NMOS transistor region and a PMOS transistor region is prepared. A silicon-germanium layer is formed on the PMOS transistor region. Nitrogen atoms are injected in an upper portion of the silicon-germanium layer. A first gate dielectric layer is formed on the NMOS transistor region and the PMOS transistor region. The nitrogen atoms are injected into the upper portion of the silicon-germanium layer before forming the first gate dielectric layer. | 2012-09-27 |
20120244671 | Unitary Floating-Gate Electrode with Both N-Type and P-Type Gates - An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes n-type and p-type doped portions serving as gate electrodes of n-channel and p-channel MOS transistors, respectively; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad. An opening at the surface of the analog floating-gate electrode, at the location at which n-type and p-type doped portions of the floating gate electrode abut, allow formation of silicide at that location, shorting the p-n junction. | 2012-09-27 |
20120244672 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can form a plurality of grooves extending in a first direction on a semiconductor substrate. The method can form an insulating layer on the inner face of the groove and on the top face of the semiconductor substrate. The method can deposit a first conductive layer on the insulating layer so as to fill in the groove. The method can deposit a second conductive layer on the first conductive layer. The method can form a hard mask in a region including part of a region immediately above the groove on the second conductive layer. The method can form a columnar body including the hard mask and the second conductive layer by etching the second conductive layer using the hard mask as a mask. | 2012-09-27 |
20120244673 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include selectively implanting an impurity into a underlying layer containing silicon using a mask to form a boron-added region and an etched region. The boron-added region contains boron, and a boron concentration of the etched region is lower than a boron concentration in the boron added region. The method can include forming a pair of holes reaching the etched region in the stacked body including a plurality of layers of electrode layers. The method can include forming a depression part connected to a lower end of each of the pair of holes in the underlying layer by removing the etched region through the holes using an etching solution. | 2012-09-27 |
20120244674 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES - A method of fabricating a semiconductor device includes providing a semiconductor substrate including a channel region, forming a gate electrode structure on the channel region of the semiconductor substrate, forming a first trench in the semiconductor substrate, and forming a second trench in the semiconductor device. The first trench may include a first tip that protrudes toward the channel. The second trench may be an enlargement of the first trench and may include a second tip that also protrudes toward the channel region. In some examples, the second tip may protrude further towards the channel region than the first tip. | 2012-09-27 |
20120244675 | METHOD FOR FORMING METAL GATE - A method for forming a metal gate is provided. First, a dummy material is formed to completely cover a substrate. Second, a dopant is selectively implanted into the dummy material. Then, some of the dummy material is removed to expose part of the substrate and to form a dummy gate including a dopant region disposed between a first region and a second region. Later an interlayer dielectric layer is formed to surround the dummy gate. Next, a selective etching step is carried out to remove the first region to form a recess without substantially removing the dopant region. Afterwards, the recess is filled with a material set to form a metal gate. | 2012-09-27 |
20120244676 | SEMICONDUCTURE STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE THAT PROVIDES TWO INDIVIDUAL RESISTORS OR A CAPACITOR - A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow. | 2012-09-27 |
20120244677 | METHOD AND APPARATUS FOR SELECTIVELY REMOVING ANTI-STICTION COATING - The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask. | 2012-09-27 |
20120244678 | SEMICONDUCTOR DEVICE WAFER BONDING METHOD - A semiconductor device wafer bonding method bonds a first semiconductor device wafer having a plurality of semiconductor devices with a plurality of projecting electrodes to a second semiconductor device wafer having a plurality of electrodes respectively corresponding to the projecting electrodes of the first semiconductor device wafer. An insulator is applied and fills the spacing between adjacent projecting electrodes. The first semiconductor device wafer is planarized to expose the end surfaces of the projecting electrodes, and the first semiconductor device wafer is bonded to the second semiconductor device wafer with an anisotropic conductor interposed between the projecting electrodes of the first semiconductor device wafer and the electrodes of the second semiconductor device wafer, to thereby respectively connect the electrodes through the anisotropic conductor. | 2012-09-27 |
20120244679 | METHOD FOR PRODUCING BONDED WAFER - The present invention is directed to a method for producing a bonded wafer, the method in which heat treatment for flattening the surface of a thin film is performed on a bonded wafer made by the ion implantation delamination method in an atmosphere containing hydrogen or hydrogen chloride, wherein the surface of a susceptor on which the bonded wafer is to be placed, the susceptor used at the time of flattening heat treatment, is coated with a silicon film in advance. As a result, a method for producing a bonded wafer is provided, the method by which a bonded wafer having a thin film with good film thickness uniformity can be obtained even when heat treatment for flattening the surface of a thin film of a bonded wafer after delamination is performed in the ion implantation delamination method. | 2012-09-27 |
20120244680 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device comprises the steps of forming a film on a main face of a semiconductor substrate having a plurality of device forming regions for forming semiconductor devices, the film having a coefficient of thermal expansion different from that of the semiconductor substrate and including a cutout on a region between the plurality of device forming regions; forming the semiconductor devices in the respective device forming regions by using the film; and dividing the semiconductor substrate into the respective device forming regions. | 2012-09-27 |
20120244681 | SEMICONDUCTOR DIE SINGULATION METHOD - In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer. | 2012-09-27 |
20120244682 | WAFER DIVIDING METHOD - In a wafer dividing method, a wafer is held by a chuck table of a laser beam processing apparatus. A modified layer is formed by radiating a laser beam having a wavelength that transmits the laser beam through the wafer, while adjusting the beam convergence point to a position inside of the wafer, so as to form a pair of modified layers the interval of which is greater than the width of a cutting edge of a cutting blade and smaller than the width of planned dividing lines, on the back side of the wafer at both sides of each of the planned dividing lines. The wafer is adhered to a dicing tape and divided into individual devices by cutting along the dividing lines. | 2012-09-27 |
20120244683 | MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT - A manufacturing method of a semiconductor element comprises the steps of (a) preparing a growth substrate, (b) forming a semiconductor layer on the growth substrate, (c) dividing the semiconductor layer into a plurality of elements while leaving at least a part of the semiconductor layer between each element to form a sacrificial layer around each element, (d) forming a metal layer on the semiconductor layer, (e) bonding a supporting substrate to the semiconductor layer via the metal layer, and (f) removing the growth substrate from the semiconductor layer by irradiating a laser whose area of irradiation covers each element within an outline of the sacrificial layer of each element. | 2012-09-27 |
20120244684 | FILM-FORMING APPARATUS AND METHOD - A film-forming apparatus and method is provided that includes a reflector and insulator capable of suppressing the thermal degradation of components in close proximity to the heater in a film-forming apparatus. In a film-forming apparatus the reflector is used in combination with insulator. Specifically, in a film-forming apparatus a reflector is disposed below a heater with the insulator placed below the reflector. The insulator absorbs the radiant heat from the heater thus suppressing an excessive rise in temperature around the heater, it is therefore possible to prevent thermal degradation of components in close proximity of the heater. For example, when the temperature of a semiconductor substrate is 1650° C., the temperature of the quartz heater base maybe about 1000° C. This is lower than the softening point temperature of the quartz heater base, preventing deformation of the heater base. | 2012-09-27 |
20120244685 | Manufacturing Apparatus and Method for Semiconductor Device - A semiconductor manufacturing apparatus includes: a plurality of reaction chambers into which wafers are introduced and deposition process is performed; a material gas supply mechanism that includes a plurality of material gas supply lines that respectively supply a material gas to the plurality of reaction chambers and a flow rate control mechanism that controls a flow rate of the marital gas in the material gas supply lines; a carrier gas supply mechanism that includes a plurality of carrier gas supply lines that respectively supplies a carrier gas into the plurality of reaction chambers; and a material gas switching mechanism that intermittently opens and closes the plurality of material gas supply lines respectively so that at least one of the plurality of material gas supply lines comes to be in an opened state at a same time, and sequentially switches the reaction chamber to which the material gas is supplied. | 2012-09-27 |
20120244686 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - An exemplary method for fabricating a semiconductor device includes the steps (a) growing a p-type gallium nitride-based compound semiconductor layer in a heated atmosphere; (b) cooling the p-type gallium nitride-based compound semiconductor layer; (c) forming three or more well layers before the step (a); and (d) forming an n-type semiconductor layer on a substrate before the step (c), wherein the step (c) includes growing each of the well layers to a thickness of 5 nm or more with the supply of the hydrogen gas to the reaction chamber cut off, and wherein the step (a) includes supplying hydrogen gas to the reaction chamber, and wherein the step (b) includes cooling the p-type gallium nitride-based compound semiconductor layer with the supply of the hydrogen gas to the reaction chamber cut off. | 2012-09-27 |
20120244687 | METHOD OF MANUFACTURING A BASE SUBSTRATE FOR A SEMI-CONDUCTOR ON INSULATOR TYPE SUBSTRATE - A method and system are provided for manufacturing a base substrate that is used in manufacturing semi-conductor on insulator type substrate. The base substrate may be manufactured by providing a silicon substrate having an electrical resistivity above 500 Ohm·cm; cleaning the silicon substrate so as to remove native oxide and dopants from a surface thereof; forming, on the silicon substrate, a layer of dielectric material; and forming, on the layer of dielectric material, a layer of poly-crystalline silicon. These actions are implemented successively in an enclosure. | 2012-09-27 |
20120244688 | SELECTIVE EPITAXIAL FORMATION OF SEMICONDUCTIVE FILMS - Epitaxial layers are selectively formed in semiconductor windows by a cyclical process of repeated blanket deposition and selective etching. The blanket deposition phases leave non-epitaxial material over insulating regions, such as field oxide, and the selective etch phases preferentially remove non-epitaxial material while deposited epitaxial material builds up cycle-by-cycle. Quality of the epitaxial material improves relative to selective processes where no deposition occurs on insulators. Use of a germanium catalyst during the etch phases of the process aid etch rates and facilitate economical maintenance of isothermal and/or isobaric conditions throughout the cycles. Throughput and quality are improved by use of trisilane, formation of amorphous material over the insulating regions and minimizing the thickness ratio of amorphous:epitaxial material in each deposition phase. | 2012-09-27 |
20120244689 | SCHOTTKY DIODE WITH CONTROL GATE FOR OPTIMIZATION OF THE ON STATE RESISTANCE, THE REVERSE LEAKAGE, AND THE REVERSE BREAKDOWN - A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode. | 2012-09-27 |
20120244690 | ION IMPLANTED RESIST STRIP WITH SUPERACID - According to certain embodiments, a resist is placed over the surface of a semiconductor structure, wherein the resist covers a portion of the semiconductor structure. Dopants are implanted into the semiconductor structure using an ion implantation beam in regions of the semiconductor structure not covered by the resist. Due to exposure to the ion implantation beam, at least a portion of the resist is converted by exposure to the ion beam to contain an inorganic carbonized material. The semiconductor structure with resist is contacted with a superacid composition containing a superacid species to remove the resist containing inorganic carbonized materials from the semiconductor structure. | 2012-09-27 |
20120244691 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts. | 2012-09-27 |
20120244692 | INTEGRATED SHADOW MASK/CARRIER FOR PATTERN ION IMPLANTATION - An improved, lower cost method of processing substrates, such as to create solar cells is disclosed. In addition, a modified substrate carrier is disclosed. The carriers typically used to carry the substrates are modified so as to serve as shadow masks for a patterned implant. In some embodiments, various patterns can be created using the carriers such that different process steps can be performed on the substrate by changing the carrier or the position with the carrier. In addition, since the alignment of the substrate to the carrier is critical, the carrier may contain alignment features to insure that the substrate is positioned properly on the carrier. In some embodiments, gravity is used to hold the substrate on the carrier, and therefore, the ions are directed so that the ion beam travels upward toward the bottom side of the carrier. | 2012-09-27 |
20120244693 | METHOD FOR PATTERNING A FULL METAL GATE STRUCTURE - A method of patterning a gate structure on a substrate is described. The method includes preparing a metal gate structure on a substrate, wherein the metal gate structure includes a high dielectric constant (high-k) layer, a first gate layer formed on the high-k layer, and a second gate layer formed on the first gate layer, and wherein the first gate layer comprises one or more metal-containing layers. The method further includes preparing a mask layer with a pattern overlying the metal gate structure, transferring the pattern to the second gate layer, transferring the pattern to the first gate layer, and transferring the pattern in the first gate layer to the high-k layer, and prior to the transferring of the pattern to the high-k layer, passivating an exposed surface of the first gate layer using a nitrogen-containing and/or carbon-containing environment to reduce under-cutting of the first gate layer relative to the second gate layer, wherein the passivating is performed separately from or in addition to the transferring of the pattern to the first gate layer. | 2012-09-27 |
20120244694 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a manufacturing method of semiconductor integrated circuit, which is effective when applied to a processing technique for a gate electrode or the like. In the patterning of a gate stack film having a high-k gate insulating film and a metal electrode film in a memory region, etching for a cut region between adjacent gate electrodes is performed first using a first resist film and, after the first resist film that is no longer needed is removed, etching for a line and space pattern is performed using a second resist film. | 2012-09-27 |
20120244695 | METHOD FOR FABRICATING FLASH MEMORY DEVICE AND FLOATING GATE THEREIN - A method for fabricating a floating gate in a flash memory device includes providing a substrate, forming a first-type ion doped floating gate layer on the substrate, forming a first patterned photoresist layer on the first-type ion doped floating gate layer, dry etching the first patterned photoresist layer, wherein a dimension of the pattern of the first photoresist layer after the dry etching process is smaller than a dimension of the pattern before the dry etching process. The method further includes forming a dual-doped floating gate layer by implanting second-type ions into the first-type ion doped floating gate layer by using the first photoresist layer as a mask, wherein the first-type ions and the second-type ions have opposite charges. A flash memory device thus fabricated has a small CD and a dual-doped floating gate that provide high programming efficiency. | 2012-09-27 |
20120244696 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is disclosed. The method includes forming a third film so as to cover a second pattern, a second mask pattern, and a first film; etching back the third film to form a first sidewall line pattern along a sidewall of the second pattern and to form a first sidewall mask pattern along a sidewall of the second mask pattern; forming a third mask pattern comprising a resist film so as to cover the second mask pattern and the first sidewall mask pattern; and selectively removing the second pattern using the third mask pattern as a mask and thereafter removing the third mask pattern. | 2012-09-27 |
20120244697 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device that improves the heat cycle resistance and power cycle resistance of a power module. An electrode member in which copper posts are formed in a plurality of perforations cut in a support made of a ceramic material is soldered onto a side of an IGBT where an emitter electrode is formed. By soldering the copper posts onto the electrode, heat generated in the IGBT is transferred to the electrode member and is radiated. In addition, even if a material of which the IGBT is made and copper differ in thermal expansivity, stress on a soldered interface is reduced and distortion is reduced. This suppresses the appearance of a crack. As a result, the heat cycle resistance and power cycle resistance of a power module can be improved. | 2012-09-27 |
20120244698 | METHODS FOR FORMING COPPER DIFFUSION BARRIERS FOR SEMICONDUCTOR INTERCONNECT STRUCTURES - Embodiments of methods for forming Cu diffusion barriers for semiconductor interconnect structures are provided. The method includes oxidizing an exposed outer portion of a copper line that is disposed along a dielectric substrate to form a copper oxide layer. An oxide reducing metal is deposited onto the copper oxide layer. The copper oxide layer is reduced with at least a portion of the oxide reducing metal that oxidizes to form a metal oxide barrier layer. A dielectric cap is deposited over the metal oxide barrier layer. | 2012-09-27 |
20120244699 | ATOMIC LAYER DEPOSITION OF TUNGSTEN MATERIALS - Embodiments of the invention provide a method for depositing tungsten-containing materials. In one embodiment, a method includes forming a tungsten nucleation layer over an underlayer disposed on the substrate while sequentially providing a tungsten precursor and a reducing gas into a process chamber during an atomic layer deposition (ALD) process and depositing a tungsten bulk layer over the tungsten nucleation layer, wherein the reducing gas contains hydrogen gas and a hydride compound (e.g., diborane) and has a hydrogen/hydride flow rate ratio of about 500:1 or greater. In some examples, the method includes flowing the hydrogen gas into the process chamber at a flow rate within a range from about 1 slm to about 20 slm and flowing a mixture of the hydride compound and a carrier gas into the process chamber at a flow rate within a range from about 50 sccm to about 500 sccm. | 2012-09-27 |
20120244700 | METHODS FOR FABRICATING SEMICONDUCTOR DEVICES INCLUDING METAL SILICIDE - Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a metal silicide in an upper portion of a gate electrode structure and in an active semiconductor region laterally adjacent to the gate electrode structure. A first portion of the metal silicide formed in the upper portion of the gate electrode structure is removed. | 2012-09-27 |
20120244701 | METHOD FOR FORMING NISI FILM, METHOD FOR FORMING SILICIDE FILM, METHOD FOR FORMING METAL FILM FOR USE IN SILICIDE-ANNEALING, APPARATUS FOR VACUUM PROCESSING AND FILM-FORMING APPARATUS - The method for the formation of a silicide film herein provided comprises the steps of forming an Ni film on the surface of a substrate mainly composed of Si and then heat-treating the resulting Ni film to thus form an NiSi film as an upper layer of the substrate, wherein, prior to the heat-treatment for the formation of the NiSi film, the Ni film is subjected to a preannealing treatment using H | 2012-09-27 |
20120244702 | METHOD FOR PRINTING A SUBSTRATE - Embodiments of the present invention generally relate to methods of printing MWT solar cells. The methods include positioning the non-light-receiving side of a solar cell substrate on a support. The solar cell substrate has a plurality of holes formed therethrough. The plurality of holes are then metalized. Metalizing the holes includes applying a first silver-containing paste within the holes, or depositing the first silver-containing paste on the interior surface of the holes. The first silver-containing paste is in electrical communication with the front surface and the back surface of the substrate. Then, a plurality of collection fingers are formed on the front surface of the substrate using a second silver-containing paste. The substrate may then be flipped, and one or more printing processes may be performed on the non-light-receiving side of the substrate. | 2012-09-27 |
20120244703 | TRAY FOR CVD AND METHOD FOR FORMING FILM USING SAME - A tray for film formation by a CVD method includes a tray main body ( | 2012-09-27 |
20120244704 | METHOD FOR REMOVING OXIDES - A method for removing native oxides from a substrate surface is provided. In one embodiment, the method comprises positioning a substrate having an oxide layer into a processing chamber, exposing the substrate to a gas mixture while forming a volatile film on the substrate and maintaining the substrate at a temperature below 65° C., heating the substrate to a temperature of at least about 75° C. to sublimate the volatile film and remove the oxide layer, and depositing a first layer on the substrate after heating the substrate. | 2012-09-27 |
20120244705 | POST-TUNGSTEN CMP CLEANING SOLUTION AND METHOD OF USING THE SAME - A post-W CMP cleaning solution consists of carboxylic acid and deionized water. The carboxylic acid may be selected from the group consisting of (1) monocarboxylic acids; (2) dicarboxylic acids; (3) tricarboxylic acids; (4) polycarboxylic acids; (5) hydroxycarboxylic acids; (6) salts of the above-described carboxylic acids; and (7) any combination thereof. The post-W CMP cleaning solution can work well without adding any other chemical additives such as surfactants, corrosion inhibitors, pH adjusting agents or chelating agents. | 2012-09-27 |
20120244706 | CHEMICAL MECHANICAL POLISHING METHOD - A chemical mechanical polishing method includes providing a device layer having a surface to be polished, polishing the surface using an alkaline grinding slurry, removing a residual layer that is been formed on the polished surface using an acid buffer, forming a passivation layer covering the polished surface of the device layer after the residual layer has been removed, and cleaning the passivation layer using deionized water. A semiconductor device thus fabricated has surfaces with excellent flatness, good manufacturing yield and long-term reliability. | 2012-09-27 |
20120244707 | METHOD OF CORRECTING MASK PATTERN, COMPUTER PROGRAM PRODUCT, MASK PATTERN CORRECTING APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In the method of correcting a mask pattern according to the embodiments, a mask pattern correction amount for a reference flare value is calculated as a reference mask correction amount, for every type of patterns within the layout, and a change amount of the mask pattern correction amount corresponding to the change amount of the flare value is calculated as the change amount information. A mask pattern corresponding to the flare value of the pattern is created based on the reference mask correction amount and the change amount information corresponding to the pattern, extracted from the information having the pattern, the reference mask correction amount, and the change amount information correlated with each other, and based on a difference between the flare value of the pattern and the reference flare value. | 2012-09-27 |
20120244708 | Methods Of Patterning Materials - Some embodiments include methods of forming openings. For instance, a construction may have a material over a plurality of electrically conductive lines. A plurality of annular features may be formed over the material, with the annular features crossing the lines. A patterned mask may be formed over the annular features, with the patterned mask leaving segments of the annular features exposed through a window in the patterned mask. The exposed segments of the annular features may define a plurality of openings, and such openings may be transferred into the material to form openings extending to the electrically conductive lines. | 2012-09-27 |