38th week of 2010 patent applcation highlights part 43 |
Patent application number | Title | Published |
20100240162 | MANUFACTURING METHOD OF LIGHT EMITTING DIODE INCLUDING CURRENT SPREADING LAYER - Provided is a method of manufacturing a light emitting diode using a nitride semiconductor, which including the steps of: forming n- and p-type current spreading layers using a hetero-junction structure; forming trenches by dry-etching the n- and p-type current spreading layers; forming an n-type metal electrode layer in the trench of the n-type current spreading layer; forming a p-type metal electrode layer in the trench of the p-type current spreading layer; and forming a transparent electrode layer on the p-type metal electrode layer, thereby improving current spreading characteristics as compared with the conventional method of manufacturing the light emitting diode, and enhancing operating characteristics of the light emitting diode. | 2010-09-23 |
20100240163 | SUBSTRATE WITH MULTIPLE ENCAPSULATED PRESSURES - A method of forming a device with multiple encapsulated pressures is disclosed herein. In accordance with one embodiment of the present invention, there is provided a method of forming a device with multiple encapsulated pressures, including providing a substrate, forming a functional layer on top of a surface of the substrate, the functional layer including a first device portion at a first location, and a second device portion at a second location adjacent to the first location, encapsulating the functional layer, forming at least one diffusion resistant layer above the encapsulated functional layer at a location above the first location and not above the second location, modifying an environment adjacent the at least one diffusion resistant layer, and diffusing a gas into the second location as a result of the modified environment. | 2010-09-23 |
20100240164 | RADIATION DETECTOR MANUFACTURING METHOD - A coating film is formed by applying, on a tentative support, a dispersion solution in which at least an inorganic semiconductor particle and a binder are dispersed. Then, a radiation photoconductive layer is formed by subjecting the coating film to thermal compression, and the radiation photoconductive layer is joined to an active matrix layer in which multiple switching elements are arranged. This allows the radiation photoconductive layer to generate a charge in response to radiation of an electromagnetic wave representing image information and to be arranged such that the charge is read out by the active matrix layer. | 2010-09-23 |
20100240165 | METHOD FOR MANUFACTURING SOLAR CELL - A manufacturing method of a polycrystalline solar cell is disclosed. A polycrystalline silicon solar cell in accordance with the present invention performs crystallization-annealing amorphous silicon with a metal catalyst so as to reduce a crystallization temperature. The manufacturing method of a solar cell in accordance with the present invention includes the steps of (a) forming a first amorphous silicon layer on a substrate; (b) forming a second amorphous silicon layer on the first amorphous silicon layer; (c) forming a metal layer on the second amorphous silicon layer; (d) performing crystallization-annealing the second amorphous silicon layer; and (e) forming a third amorphous silicon layer on a resulting crystalline silicon layer of the step (d). | 2010-09-23 |
20100240166 | MANUFACTURE METHOD FOR PHOTOVOLTAIC MODULE - The invention permits a plurality of strips of resin adhesive film having a desired width and unwound from a single feeding reel to be simultaneously pasted on a solar cell. For this purpose, the invention comprises the steps of: unwinding a resin adhesive film sheet from a reel on which the resin adhesive film sheet is wound; splitting the unwound resin adhesive film into two or more film strips in correspondence to lengths of wiring material to bond; pasting the strips of resin adhesive film on an electrode of the solar cell; and placing the individual lengths of wiring material on the electrode of the solar cell having the plural strips of resin adhesive film pasted thereon and thermally setting the resin adhesive film by heating so as to fix together the electrode of the solar cell and the wiring material. | 2010-09-23 |
20100240167 | Quantum confinement solar cell fabricated by atomic layer deposition - The current invention provides a method of fabricating quantum confinement (QC) in a solar cell that includes using atomic layer deposition (ALD) for providing at least one QC structure embedded into an intrinsic region of a p-i-n diode in the solar cell, where optical and electrical properties of the confinement structure are adjusted according to at least one dimension of the confinement structure. The QC structures can include quantum wells, quantum wires, quantum tubes, and quantum dots. | 2010-09-23 |
20100240168 | PORTABLE OPTICAL DETECTION CHIP AND MANUFACTURING METHOD THEREOF - A portable optical detection chip comprises a substrate, a plurality of avalanche-type photosensitive device modules and a plurality of plane mirrors. The plurality of avalanche-type photosensitive device modules are formed on the substrate, and each of them comprises a plurality of avalanche-type photosensitive devices and a plurality of lenses. Each of the lenses is stacked on one of the avalanche-type photosensitive devices. The plurality of plane mirrors are disposed between the avalanche-type photosensitive device modules. That is, the avalanche-type photosensitive device modules are separated from each other by the plane mirrors. | 2010-09-23 |
20100240169 | METHOD TO MAKE ELECTRICAL CONTACT TO A BONDED FACE OF A PHOTOVOLTAIC CELL - A photovoltaic cell is formed by bonding a donor body to a receiver element and cleaving a thin lamina from the donor body. Electrical contact is made to the bonded surface of the lamina through vias formed in the lamina. In some embodiments the emitter exists only at the bonded surface or only at the cleaved surface face; the emitter does not wrap through the vias between the surfaces. Wiring contacting each of the two surfaces is formed only at the cleaved face, and one set of wiring contacts the bonded surface through conductive material formed in the vias, insulated from the via sidewalls. | 2010-09-23 |
20100240170 | METHOD OF FABRICATING SOLAR CELL - A method of fabricating a solar cell is provided. A dopant material layer is deposited on a front surface of a semiconductor substrate and an over-depositing dopant layer is also formed on a back surface of the semiconductor substrate, wherein dopants of the dopant material layer diffuse into the front surface of the semiconductor substrate to form a doping layer and dopants of the over-depositing dopant layer diffuse into the back surface of the semiconductor substrate to form a doping residual layer during said depositing process. The dopant material layer and the over-depositing dopant layer are removed. An anti-reflective layer is formed on the doping layer. After the doping residual layer on the semiconductor substrate is removed to expose the back surface of the semiconductor substrate, a passivation layer is formed on the exposed back surface of the semiconductor substrate. Then, a first electrode and a second electrode are formed. | 2010-09-23 |
20100240171 | Method of Fabricating a Multijunction Solar Cell with a Phosphorus-Containing Nucleation Layer - A multijunction solar cell is fabricated according to an embodiment by providing a substrate, depositing a nucleation first layer over and directly in contact with the substrate, depositing a second layer containing an arsenic dopant over the nucleation layer and depositing a sequence of layers over the second layer forming at least one solar subcell. The nucleation layer serves as a diffusion barrier to the arsenic dopant such that diffusion of the arsenic dopant into the substrate is limited in depth by the nucleation layer. | 2010-09-23 |
20100240172 | METHODS OF MAKING AN EMITTER HAVING A DESIRED DOPANT PROFILE - A method for obtaining a desired dopant profile of an emitter for a solar cell which includes depositing a first amorphous silicon layer having a first doping level over an upper surface of the crystalline silicon substrate, depositing a second amorphous silicon layer having a second doping level on the first amorphous silicon layer, and heating the crystalline silicon substrate and the first and second amorphous silicon layers to a temperature sufficient to cause solid phase epitaxial crystallization of the first and second amorphous silicon layers, such that the first and second amorphous silicon layers, after heating, have the same grain structure and crystal orientation as the underlying crystalline silicon substrate | 2010-09-23 |
20100240173 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - The manufacturing method of the present invention includes steps of selectively forming a photocatalyst material or a material including an amino group by discharging a composition including the photocatalyst material or the material including an amino group; immersing the photocatalyst material or the material including an amino group in a solution including a plating catalyst material so as to adsorb or deposit the plating catalyst material onto the photocatalyst material or the material including an amino group; and immersing the plating catalyst material in a plating solution including a metal material so as to form a metal film on a surface of the photocatalyst material or the material including an amino group adsorbing or depositing the plating catalyst material, thereby manufacturing a semiconductor device. The pH of the solution including the plating catalyst material is adjusted in a range of 3 to 6. | 2010-09-23 |
20100240174 | Via Using Zn or Zn Alloys and Its Making Method, 3D Chip Stack Packages Using Thereof - Disclosed are via, a method for formation of via using zinc and zinc alloys, and a process for fabrication of three-dimensional multiple chip stack packages by using the same. In lamination of three-dimensional chips, the chips with reduced defects are rapidly formed by the steps of: punching each of the chips to form a via hole used for a circuit wiring between the chips; depositing a seed layer on an inside of the via hole; forming a plated layer inside the via hole by using Zn and Zn alloys through an electroplating process; removing oxide film from surface of the plated layer; and heat treating the via hole at a temperature of more than melting point of the Zn and Zn alloys. Particularly, the chip having Zn via formed according to the present invention has an advantage of simultaneously overcoming problems in establishment of processing parameters caused by Cu via (e.g., plating mode, current density, influence of additives, pore formation, etc.), problems in successive processes caused by Sn (and other low melting point metals) via (e.g., soldering, chip stack, etc.) and difficulty in mechanical reliability of the process. Additionally, when stacking multiple chips with various functions in the three-dimensional chip stack package, the package can be simply fabricated by controlling contents of constitutional elements in Zn alloy via which has specific thermal properties (such as melting point, thermal expansion coefficient, etc.) suitable for processing temperature of each of the chips. | 2010-09-23 |
20100240175 | METHOD FOR MAKING A STACKED PACKAGE SEMICONDUCTOR MODULE HAVING PACKAGES STACKED IN A CAVITY IN THE MODULE SUBSTRATE - A stacked die chip scale package, in which a stacked die assembly is mounted within a cavity in a module substrate. In some embodiments certain of the die are stacked on a front side of a stacked die assembly substrate, and the stacked die assembly substrate is inverted in the cavity and the substrate is electrically interconnected to a front side of the module substrate; others of the die are stacked on the back side of the stacked die assembly substrate, and are interconnected by wire bonds to the front side of the module substrate. In some embodiments, the cavity is covered by a heat sink, and the stacked die assembly is mounted onto the heat sink. Also, methods for making the module are provided. | 2010-09-23 |
20100240176 | ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE, METHODS OF MANUFACTURING THE SAME, CIRCUIT BOARD, AND ELECTRONIC INSTRUMENT - The present invention is a method of manufacturing a semiconductor device, by forming a wiring on or above a wafer so that the wiring is electrically connected to a first electrode disposed on a first surface of the wafer, forming a first resin layer on or above the wafer such that the wiring is disposed between the wafer and the first resin layer, forming an opening in the first resin layer such that the opening overlaps the wiring, forming a conductive member in the opening such that the conductive member being electrically connected to the wiring, forming a second electrode on the conductive member such that the second electrode is electrically connected to the wiring via the conductive member, and separating the wafer into individual elements after the forming of the first resin layer. | 2010-09-23 |
20100240177 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes, forming an isolation region defining a first region and a second region, injecting a first impurity of a first conductivity type into the first region and the second region, forming a first gate insulating film and a first gate electrode over the first region, forming a second gate insulating film and a second gate electrode over the second region, forming a first mask layer over a first portion of the second region to expose a second portion of the second region and the first region, and injecting a second impurity of the first conductivity type into the semiconductor substrate from a direction diagonal to a surface of the semiconductor substrate. | 2010-09-23 |
20100240178 | SEMICONDUCTOR DEVICE WITH IMPROVED SHORT CHANNEL EFFECT OF A PMOS AND STABILIZED CURRENT OF AN NMOS AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area. | 2010-09-23 |
20100240179 | Methods of manufacturing capacitor structures and methods of manufacturing semiconductor devices using the same - A capacitor structure includes a plurality of lower electrodes on a substrate, the lower electrodes having planar top surfaces and being arranged in a first direction to define a lower electrode column, a plurality of lower electrode columns being arranged in a second direction perpendicular to the first direction to define a lower electrode matrix, a plurality of supports on upper sidewalls of at least two adjacent lower electrodes, a dielectric layer on the lower electrodes and the supports, and an upper electrode on the dielectric layer. | 2010-09-23 |
20100240180 | Methods of Manufacturing Semiconductor Devices Having Low Resistance Buried Gate Structures - In a method of manufacturing a semiconductor device, a recess is formed in an active region of a substrate. A gate insulation layer is formed in the first recess. A barrier layer is formed on the gate insulation layer. A preliminary nucleation layer having a first resistance is formed on the barrier layer. The preliminary nucleation layer is converted into a nucleation layer having a second resistance substantially smaller than the first resistance. A conductive layer is formed on the nucleation layer. The conductive layer, the nucleation layer, the barrier layer and the gate insulation layer are partially etched to form a buried gate structure including a gate insulation layer pattern, a barrier layer pattern, a nucleation layer pattern and a conductive layer pattern. | 2010-09-23 |
20100240181 | Method for Forming Single-Level Electrically Erasable and Programmable Read Only Memory Operated in Environment with High/Low-Voltage - First of all, a semiconductor substrate is provided, and then a first/second wells with a first conductivity are formed therein so as to individually form a first part of the floating gate of single-level EEPROM and a low-voltage device thereon, wherein the first and the second wells are used to separate the high-voltage device, and the depth of the first well is the same as the second well. Furthermore, the high-voltage device and the second part of the floating gate of single-level EEPROM are individually formed on the semiconductor substrate between the first and the second wells, and the control gate of the floating gate of single-level EEPROM is formed in the third well located under the second part of the floating gate of single-level EEPROM, wherein the high-voltage device can be operated in the opposite electric field about 18V, such as −6V˜12V, −12V˜6V, −9V˜9V etc. | 2010-09-23 |
20100240182 | Spacer Patterns Using Assist Layer For High Density Semiconductor Devices - High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers. | 2010-09-23 |
20100240183 | METHOD OF MANUFACTURING POWER SEMICONDUCTOR DEVICE - A mask layer having a plurality of openings is formed on the first layer. A second layer having a second conductivity type different from the first conductivity type is formed on the first layer by introducing impurities using the mask layer. A third layer having the first conductivity type is formed on the second layer by introducing impurities using the mask layer. A trench extending through the second layer and the third layer to the first layer is formed by carrying out etching using an etching mask including at least the mask layer. A gate insulation film covering a sidewall of the trench is formed. A trench gate filling the trench is formed on the gate insulation film. | 2010-09-23 |
20100240184 | METHOD OF FORMING BURIED GATE ELECTRODE - A method of forming a buried gate electrode prevents voids from being formed in a silicide layer of the gate electrode. The method begins by forming a trench in a semiconductor substrate, forming a conformal gate oxide layer on the semiconductor in which the trench has been formed, forming a first gate electrode layer on the gate oxide layer, forming a silicon layer on the first gate electrode layer to fill the trench. Then, a portion of the first gate electrode layer is removed to form a recess which exposed a portion of a lateral surface of the silicon layer. A metal layer is then formed on the semiconductor substrate including on the silicon layer. Next, the semiconductor substrate is annealed while the lateral surface of the silicon layer is exposed to form a metal silicide layer on the silicon layer. | 2010-09-23 |
20100240185 | Semiconductor device and method of manufacturing the same - A method of manufacturing a semiconductor device includes: forming a trench for forming buried type wires by etching a substrate; forming first and second oxidation layers on a bottom of the trench and a wall of the trench, respectively; removing a part of the first oxidation layer and the entire second oxidation layer; and forming the buried type wires on the wall of the trench by performing a silicide process on the wall of the trench from which the second oxidation layer is removed. As a result, the buried type wires are insulated from each other. | 2010-09-23 |
20100240186 | Dual-SiGe Epitaxy for MOS Devices - A semiconductor includes a semiconductor substrate, a gate stack on the semiconductor substrate, and a stressor having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor includes a first stressor region and a second stressor region on the first stressor region, wherein the second stressor region extends laterally closer to a channel region underlying the gate stack than the first stressor region. | 2010-09-23 |
20100240187 | INTEGRATED SEMICONDUCTOR STRUCTURE INCLUDING A HETEROJUNCTION BIPOLAR TRANSISTOR AND A SCHOTTKY DIODE - An integrated semiconductor structure includes a heterojunction bipolar transistor and a Schottky diode. The structure has a substrate, the heterojunction bipolar transistor overlying and contacting the substrate, wherein the heterojunction bipolar transistor includes a transistor collector layer, and a Schottky diode overlying the substrate and overlying the transistor collector layer. The Schottky diode includes a Schottky diode barrier layer structure that desirably is not of the same material, doping, and thickness as the transistor collector layer. | 2010-09-23 |
20100240188 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer. | 2010-09-23 |
20100240189 | Methods of Fabricating Semiconductor Devices - Methods of fabricating semiconductor devices are provided including forming a dielectric interlayer on a substrate, the dielectric interlayer defining an opening therein. A metal pattern is formed in the opening. An oxidization process is performed on the metal pattern to form a conductive metal oxide pattern, and the conductive metal oxide pattern is planarized. Related semiconductor devices are also provided. | 2010-09-23 |
20100240190 | METHOD FOR FABRICATING DEEP TRENCH CAPACITOR - A method for fabricating the deep trench capacitor is described as follows. A substrate of a first conductivity type is provided, which includes a deep band region of a second conductivity type therein. A deep trench is formed in the substrate and through the deep band region. A collar oxide is then formed in an upper portion of the trench, wherein at least a portion of the deep band region is exposed. A bottom electrode, a capacitor dielectric layer and a top electrode are formed in the trench sequentially. | 2010-09-23 |
20100240191 | METHOD OF FORMING SEMICONDUCTOR DEVICE HAVING A CAPACITOR - A method of forming a semiconductor device includes forming a lower electrode layer on a substrate, forming a surface oxide layer on the lower electrode layer, partially removing the lower electrode layer to form a lower electrode, removing the surface oxide layer to expose the lower electrode, forming a capacitor dielectric layer on the lower electrode, and forming an upper electrode on the capacitor dielectric layer. | 2010-09-23 |
20100240192 | ALIGNMENT MARK, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND MASK SET - An alignment mark formed by using a first mask used in forming a same memory cell pattern on a substrate and formed together with the memory cell pattern includes: a first pattern for position detection used for alignment in forming a first wiring pattern; and a first irregular reflection prevention mark that suppresses, when a position detection signal is irradiated as alignment in forming a second wiring pattern further on an upper layer side than the first wiring pattern, irregular reflection of a position detection signal from a second pattern for position detection formed further in a lower layer than the first pattern for position detection. | 2010-09-23 |
20100240193 | METHODS OF FABRICATING FLASH MEMORY DEVICES INCLUDING SUBSTANTIALLY UNIFORM TUNNEL OXIDE LAYERS - A method of forming a flash memory device in a memory cell region of a substrate includes forming a first insulating layer on the substrate, forming a first conductive layer on the first insulating layer, forming trench isolation regions in the substrate extending through the first conductive layer and the first insulating layer to define an active region in the memory cell region between the trench isolation regions, and selectively removing the first conductive layer and the first insulating layer from the memory cell region of the substrate to expose a surface of the active region between the trench isolation regions. | 2010-09-23 |
20100240194 | Method of fabricating semiconductor device - A method of fabricating a semiconductor device, the method including sequentially forming a pad oxide layer and a nitride layer on a substrate; etching the nitride layer, the pad oxide layer, and the substrate to form a trench; forming a sidewall oxide layer on a sidewall and a bottom of the trench; forming a oxide layer liner including nitrogen on the sidewall oxide layer; and forming a gap fill layer on the oxide layer liner | 2010-09-23 |
20100240195 | FABRICATION METHOD FOR DEVICE STRUCTURE HAVING TRANSPARENT DIELECTRIC SUBSTRATE - A semiconductor device has a transparent dielectric substrate such as a sapphire substrate. To enable fabrication equipment to detect the presence of the substrate optically, the back surface of the substrate is coated with a triple-layer light-reflecting film, preferably a film in which a silicon oxide or silicon nitride layer is sandwiched between polycrystalline silicon layers. This structure provides high reflectance with a combined film thickness of less than half a micrometer. | 2010-09-23 |
20100240196 | ADHESIVE, ADHESIVE SHEET, MULTI-LAYERED ADHESIVE SHEET, AND PRODUCTION METHOD FOR AN ELECTRONIC PART - A multi-layered adhesive sheet includes a substrate film, an adhesive layer formed by coating an adhesive having a specific composition onto the substrate film, and a die attachment film laminated on the adhesive layer. The multi-layered adhesive sheet employing an adhesive having this specific composition is superior in retention of a die chip during dicing of a silicon wafer, the multi-layered adhesive sheet is less likely to come off a ring frame during the dicing of the silicon wafer, and it allows for the die attachment film and the adhesive layer to be easily peeled apart during a pick-up operation of a die chip. | 2010-09-23 |
20100240197 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND RELATED FABRICATION METHOD - Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. The semiconductor device includes a semiconductor substrate having a cell region and a peripheral region, a cell active region formed in the cell region, and a peripheral active region formed in the peripheral region, wherein the cell active region and the peripheral active region are defined by isolation regions. The semiconductor device further includes a first gate stack formed on the cell active region, a second gate stack formed on the peripheral active region, a cell epitaxial layer formed on an exposed portion of the cell active region, and a peripheral epitaxial layer formed on an exposed portion of the peripheral active region, wherein the height of the peripheral epitaxial layer is greater than the height of the cell epitaxial layer. | 2010-09-23 |
20100240198 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes growing an AlN layer by MOVPE in which a nitrogen-source flow ratio at a far side from a substrate is set lower than that at a near side, the nitrogen-source flow ratio being a ratio of a flow rate of a nitrogen source to a total flow rate of growth gas; and growing a GaN-based semiconductor layer on the AlN layer by MOVPE. | 2010-09-23 |
20100240199 | Scalable Light-Induced Metallic to Semiconducting Conversion of Carbon Nanotubes and Applications to Field-Effect Transistor Devices - Among others, techniques are described for forming nanotubes. In one aspect, a method includes forming a base layer of a transition metal on a substrate. The method also includes heating the substrate with the base layer in a mixture of gases to grow nanotubes on the base layer. | 2010-09-23 |
20100240200 | SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD - A substrate processing system includes a processing chamber that performs a preset process on a plurality of substrates in a batch-type manner; a substrate mounting table, installed within the processing chamber, configured to mount the plurality of substrates on a concentric circle and configured to be rotatable forward and backward; substrate accommodation units configured to accommodate the plurality of substrates in multi-stages in a vertical direction; substrate holders and configured to transfer the substrates between the substrate accommodation units and the processing chamber; elevating mechanisms configured to move the substrate accommodation units up and down. Unprocessed substrates are mounted on the substrate mounting table while the substrate mounting table is being rotated in one direction. After the completion of the processing of the substrates, unloading of processed substrates and loading of new unprocessed substrates are performed while the substrate mounting table is rotated in the another direction. | 2010-09-23 |
20100240201 | IMPLANTATION OF MULTIPLE SPECIES TO ADDRESS COPPER RELIABILITY - A first species and a second species are implanted into a conductor of a substrate, which may be copper. The first species and second species may be implanted sequentially or at least partly simultaneously. Diffusion of the first species within the conductor of the substrate is prevented by the presence of the second species. In one particular example, the first species is silicon and the second species is nitrogen, although other combinations are possible. | 2010-09-23 |
20100240202 | SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD THEREOF - The present invention provides a semiconductor apparatus for improving a switching speed and a withstand voltage, and a manufacturing method of the semiconductor apparatus. The semiconductor apparatus of the invention including a first conductive type semiconductor substrate, a first conductive type first semiconductor region with an impurity concentration lower than that of the semiconductor substrate and formed on a first principal surface of the semiconductor substrate, a second conductive type second semiconductor region formed in a surface region of the first semiconductor region and which forms a PN junction with the first semiconductor region, a contact region including a part of the first semiconductor region and a part of the second semiconductor region, an insulating layer having an opening part through which at least the contact region are exposed, a first electrode formed so as to be in contact with at least the contact region and a second electrode formed on a second principal surface of the semiconductor substrate, wherein the second semiconductor region, viewed from a direction perpendicular to the first principal surface includes a first region in which a plurality of islands of the second semiconductor are aligned with intervals and a second region which connects each end of the islands of the first region each other. | 2010-09-23 |
20100240203 | SILICON-BASED VISIBLE AND NEAR-INFRARED OPTOELECTRIC DEVICES - In one aspect, the present invention provides a silicon photodetector having a surface layer that is doped with sulfur inclusions with an average concentration in a range of about 0.5 atom percent to about 1.5 atom percent. The surface layer forms a diode junction with an underlying portion of the substrate. A plurality of electrical contacts allow application of a reverse bias voltage to the junction in order to facilitate generation of an electrical signal, e.g., a photocurrent, in response to irradiation of the surface layer. The photodetector exhibits a responsivity greater than about 1 A/W for incident wavelengths in a range of about 250 nm to about 1050 nm, and a responsivity greater than about 0.1 A/W for longer wavelengths, e.g., up to about 3.5 microns. | 2010-09-23 |
20100240204 | METHODS FOR FORMING METAL GATE TRANSISTORS - A method for cleaning a diffusion barrier over a gate dielectric of a metal-gate transistor over a substrate is provided. The method includes cleaning the diffusion barrier with a first solution including at least one surfactant. The amount of the surfactant of the first solution is about a critical micelle concentration (CMC) or more. The diffusion barrier is cleaned with a second solution. The second solution has a physical force to remove particles over the diffusion barrier. The second solution is substantially free from interacting with the diffusion barrier. | 2010-09-23 |
20100240205 | METHODS OF FABRICATING THREE-DIMENSIONAL NONVOLATILE MEMORY DEVICES USING EXPANSIONS - Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers. | 2010-09-23 |
20100240206 | METHOD OF ANNEALING A DIELECTRIC LAYER - A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer. | 2010-09-23 |
20100240207 | METHODS OF MANUFACTURING CHARGE TRAP TYPE MEMORY DEVICES - Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process. | 2010-09-23 |
20100240208 | FLOATING GATE HAVING MULTIPLE CHARGE STORING LAYERS, METHOD OF FABRICATING THE FLOATING GATE, NON-VOLATILE MEMORY DEVICE USING THE SAME, AND FABRICATING METHOD THEREOF - Provided is a floating gate having multiple charge storage layers, a non-volatile memory device using the same, and a method of fabricating the floating gate and the non-volatile memory device, in which the multiple charge storage layers using metallic/semiconducting nano-particles is formed to thereby enhance a charge storage capacity of the memory device. The floating gate includes a polymer electrolytic film which is deposited on a tunneling oxide film, and is formed of at least one stage in which at least one thin film is deposited on each stage, and at least one metal nano-particle layer which is self-assembled on the upper surface of each stage of the polymer electrolytic film and on which a number of nano-particles for trapping charges are formed. The floating gate is made by self-assembling the nano-particles on the polymer electrolytic film, and thus can be fabricated without undergoing a heat treatment process at high temperature. | 2010-09-23 |
20100240209 | SEMICONDUCTOR DEVICES INCLUDING HYDROGEN IMPLANTATION LAYERS AND METHODS OF FORMING THE SAME - Provided are semiconductor devices and methods of forming the same. The semiconductor devices include a substrate further including a hydrogen implantation layer and a gate structure formed on the hydrogen implantation layer to include a first insulating layer, a charge storage layer, a second insulating layer and a conductive layer. | 2010-09-23 |
20100240210 | STRAPPING CONTACT FOR CHARGE PROTECTION - A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area. | 2010-09-23 |
20100240211 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device. | 2010-09-23 |
20100240212 | Method of manufacturing a semiconductor device - A semiconductor device manufacturing method includes a process for filling holes in a dielectric film with tungsten. The process deposits tungsten in the holes, partially etches the deposited tungsten, and then deposits additional tungsten in the holes. Voids that may be left by the first tungsten deposition step are made accessible by openings formed in the etching step, and are then filled in by the second tungsten deposition step. Tungsten hexafluoride may be used as both a deposition source gas and an etching gas, providing a simple and inexpensive process that is suitable for high-volume production. | 2010-09-23 |
20100240213 | Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device on a semiconductor substrate, includes the steps of forming a first metal film on a front surface of the semiconductor substrate; forming a second metal film on the surface of the first metal film; activating a surface of the second metal film to provide an activated surface; and forming a plated film on the activated surface by a wet plating method in a plating bath that includes a reducing agent that is oxidized during plating and that has a rate of oxidation, wherein the second metal film is a metal film mainly composed of a first substance that enhances the rate of oxidation of the reducing agent in the plating bath. Wet plating is preferably an electroless process. | 2010-09-23 |
20100240214 | METHOD OF FORMING MULTI METAL LAYERS THIN FILM ON WAFER - A method of forming the multi metal layers thin film has Ti sputtered on top surface of a substrate by PVD first. Then, Ti is transformed into TiN via CVD. Thus, by skipping the extra process steps of wafer cleaning and surface treating, the method not only solves the stress problems between two different metal layers but also improves the cycle time and particle performance for the production without any yield impact. | 2010-09-23 |
20100240215 | Multi-Sacrificial Layer and Method - MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode. | 2010-09-23 |
20100240216 | FILM FORMATION METHOD AND APPARATUS UTILIZING PLASMA CVD - A film formation method to form a predetermined thin film on a target substrate includes first and second steps alternately performed each at least once. The first step is arranged to generate first plasma within a process chamber that accommodates the substrate while supplying a compound gas containing a component of the thin film and a reducing gas into the process chamber. The second step is arranged to generate second plasma within the process chamber while supplying the reducing gas into the process chamber, subsequently to the first step. | 2010-09-23 |
20100240217 | SUBSTRATE PROCESSING METHOD - A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas. | 2010-09-23 |
20100240218 | SUBSTRATE ETCHING METHOD AND SYSTEM - The etching method includes etching the silicon oxide film by supplying a halogen-containing gas and a basic gas to the substrate so that the silicon oxide film is chemically reacted with the halogen-containing gas and the basic gas to generate a condensation layer; etching silicon by supplying a silicon etching gas, which includes at least one selected from the group consisting of an F | 2010-09-23 |
20100240219 | Method of treating a semiconductor substrate - A method of treating a semiconductor substrate has forming convex patterns over the semiconductor substrate by dry etching, cleaning and modifying a surface of the convex patterns by using chemical, forming a hydrophobic functional surface on the modified surface of the convex patterns, after forming the hydrophobic functional surface, rinsing the semiconductor substrate by using water, drying the semiconductor substrate, and removing the hydrophobic functional group from the hydrophobic functional surface of the convex patterns. | 2010-09-23 |
20100240220 | PROCESS FOR STRIPPING PHOTORESIST AND REMOVING DIELECTRIC LINER - A process of stripping a patterned photoresist layer and removing a dielectric liner includes performing an oxygen-containing plasma dry etch process and performing a fluorine-containing plasma dry etch process in the same reaction chamber at a process temperature less than 120° C. | 2010-09-23 |
20100240221 | Methods of Forming Patterns for Semiconductor Devices - Provided are methods of forming patterns of semiconductor devices, whereby patterns having various widths may be simultaneously formed, and a pattern density may be doubled by a double patterning process in a portion of the semiconductor device. A dual mask layer is formed on a substrate. A variable mask layer is formed on the dual mask layer. A first photoresist pattern having a first thickness and a first width in the first region, and a second photoresist pattern having a second thickness greater than the first thickness and a second width wider than the first width in the second region are formed on the variable mask layer. A first mask pattern and a first variable mask pattern are formed in the first region, and a second mask pattern and a second variable mask pattern are formed in the second region, by sequentially etching the variable mask layer and the dual mask layer by using, as etch masks, the first photoresist pattern and the second photoresist pattern. First spacers covering side walls of the first mask pattern and second spacers covering side walls of the second mask pattern are formed. The first mask pattern is removed, and then the substrate is etched in the first region and the second region by using the first spacers as an etch mask in the first region, and the second mask pattern and the second spacers as an etch mask in the second region. | 2010-09-23 |
20100240222 | WAFER FIXTURE FOR WET PROCESS APPLICATIONS - The present invention is a wafer fixture comprising a housing body, a thrust plate, a flexure clamp, gaskets, flexure pins on an inner circumference of the housing body, locking grooves on an outer circumference of the flexure clamp, and a handle. A wafer may be placed between the gaskets of the housing body and the thrust plate. The flexure clamp may be placed over the thrust plate and secured to the housing body by rotating the flexure clamp such that locking grooves of the fixture plate mate with the flexure pins on the inner circumference of the housing body. The present invention in yet another embodiment is a wafer etch tool comprising a housing, a flexure clamp, and means for securing a wafer between the housing and the flexure clamp upon rotation of the flexure clamp within the housing. | 2010-09-23 |
20100240223 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, comprising: loading a wafer to be subjected to film formation to a chamber; supporting the wafer to be spaced from a film formation position of the wafer; preliminarily heating the wafer while rotating a rotating member for rotating the wafer through a supporting member during the film formation at a predetermined rotational speed under a state of the wafer to be spaced from the film formation position; placing the wafer on the supporting member in the film formation position; and heating the wafer at a predetermined temperature and supplying a process gas onto the wafer while rotating the wafer. | 2010-09-23 |
20100240224 | MULTI-ZONE SEMICONDUCTOR FURNACE - A semiconductor furnace suitable for chemical vapor deposition processing of wafers. The furnace includes a thermal reaction chamber having a top, a bottom, a sidewall, and an internal cavity for removably holding a batch of vertically stacked wafers. A heating system is provided that includes a plurality of heaters arranged and operative to heat the chamber. The heating system includes at least one top heater; at least one bottom heater, and a plurality of sidewall heaters spaced along the height of the reaction chamber to control temperature variations within in the chamber and promote uniform film deposit thickness on the wafers. | 2010-09-23 |
20100240225 | MICROWAVE PLASMA PROCESSING APPARATUS, MICROWAVE PLASMA PROCESSING METHOD, AND MICROWAVE-TRANSMISSIVE PLATE - Disclosed is a microwave plasma processing apparatus ( | 2010-09-23 |
20100240226 | METHOD AND APPARATUS FOR THERMAL TREATMENT OF SEMICONDUCTOR WORKPIECES - The present invention provides an apparatus and method for rapid and uniform thermal treatment of semiconductor workpieces in two closely arranged thermal treatment chambers with a retractable door between them. The retractable door moves in between two thermal treatment chambers during heating or cooling process, and additional heating and cooling sources are provided for double-side thermal treatment of the semiconductor workpiece. | 2010-09-23 |
20100240227 | ACTIVATING DOPANTS USING MULTIPLE CONSECUTIVE MILLISECOND-RANGE ANNEALS - A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds. | 2010-09-23 |
20100240228 | LINEAR MOTION ELECTRICAL CONNECTOR ASSEMBLY - A linear motion electrical connector includes an outer component having a bore defined by an inner surface and a cylinder within the bore. The cylinder has an outer surface. An annular groove is formed on one of the outer surface of the cylinder or the inner surface of the outer component. The annular groove has an axial length. A conductive spring is fit within the annular groove and provides electrical contact between the outer component and the cylinder. The conductive helical spring is adapted to roll along the axial length of the annular groove to maintain electrical contact when the cylinder is translated relative to the outer component. | 2010-09-23 |
20100240229 | SLIDING WINDOW MAGNETIC ELECTRICAL CONNECTOR - An electrical connector for supplying electrical power from a fixed member to a movable member that moves with respect to the fixed member, the movable member bearing an electrical load. The electrical connector has a first connector part fixed to the fixed member and connected to a source of electrical power. A second connector part is fixed to the movable member and is connected to the electrical load. The first connector part and second connector part are movable into electrical engagement when the movable member is moved adjacent the fixed member. The first connector part has a first housing, a movable enclosure in the housing, having first external electrical contacts, and a movable carriage bearing second electrical contacts. The movable carriage has first magnets or magnet attractive components, the second contacts being movable with the carriage by a first magnetic force into electrical engagement with the first contacts and being retracted away from the first contacts by a second force. The second connector part has a second housing and second magnets or magnet attractive components and has third electrical contacts for electrically engaging with the first contacts. The first magnetic force is generated when the first and second connector parts are disposed adjacent each other by the interaction of the first magnets or magnet attractive components and the second magnets or magnetic attractive components thereby to move the movable carriage to allow the first and second contacts to come into electrical engagement. When the second connector part is moved away from the first connector part, the first magnetic force ceases to act on the movable carriage and the movable carriage is retracted by the second force whereby the first contacts are electrically disengaged from the second contacts and the first contacts are disconnected from the source of electrical power. The movable enclosure has a limited range of motion in at least two directions defining its contact surface thereby to facilitate alignment of the first and third contacts. | 2010-09-23 |
20100240230 | POWER PLUG - The present invention relates to a power plug, comprises: a magnetic conductive ring; a grounding insulation supporting ring; a grounding ring connection seat, a grounding connection sheet is extended from one end of the grounding ring connection seat; a power insulation supporting ring; a power ring connection seat, a power connection sheet is extended from one end of the power ring connection seat; an insulation supporting ring; an identifying connection seat; an insulation retaining ring and a cable housing. The identifying connection seat and the power ring connection seat and the grounding ring connection seat are assembled in a manner of a ring being provided on other rings therefore a 360 degree nondirectional power plug is obtained. | 2010-09-23 |
20100240231 | CONNECTOR AND DEVICE INCLUDING THE SAME - A connector includes, a frame section which has an inner space defined by side walls and a bottom portion, a plurality of pins protruding from the bottom portion in the inner space, a cover which has a magnet and a plurality of holes, where the cover is movable along the pins in the inner space between a first position and a second position that the pins are electrically connected, a detection unit that output a detection signal, an electromagnet provided at a position on the bottom portion opposing the magnet, and a control unit that controls a moving of the cover between the first position and the second position by bringing the electromagnet in a normal ON state or in an OFF state or a reverse ON state. | 2010-09-23 |
20100240232 | ELECTRICAL CONNECTING DEVICE - The present invention discloses an electrical connecting device adapted to receive a chip unit. The electrical connecting device includes an insulation base, a terminal set, a circuit board, a cover and a driving mechanism. The insulation base is formed with a terminal area and a first pierced hole. The terminal set is disposed correspondingly in the terminal area. The circuit board is disposed under the insulation base. The circuit board is formed with a pad area, which is disposed correspondingly to and under the terminal area for the terminal set to be soldered on. The circuit board is formed with a through hole corresponding to the first pierced hole. The cover is horizontally and slidably covering the insulation base. The driving mechanism at least has a metal bushing covered into the first pierced hole and the through hole. The driving mechanism further has a cam, which has a driven portion extending to form a first cylinder into the first pierced hole. The first cylinder is jointed into the metal bushing correspondingly. A second cylinder which is off-centered with respect to the first cylinder is formed between the driven portion and the first cylinder and entering the second pierced hole. | 2010-09-23 |
20100240233 | ELECTRICAL CONNECTOR HAVING RIBBED GROUND PLATE - An electrical connector includes a dielectric housing, a plurality of electrical signal contacts carried by the dielectric housing, and a ground plate carried by the dielectric housing. The electrical signal contacts are arranged along a first plane, wherein the signal contacts define signal pairs such that a respective gap is disposed between adjacent signal pairs. The signal contacts further define respective mating and mounting ends. The ground plate includes a ground plate body oriented in a second plane that is substantially parallel to the first plane and offset from the first plane. The ground plate body defines first and second opposed surfaces. The ground plate includes at least one rib that defines first and second opposed surfaces, wherein the first surface of the rib projects from the first surface of the ground plate body in a direction toward the gap, and the second surface is recessed into the second surface of the ground plate body. The ground plate further includes a plurality of mating ends and mounting ends extending from the ground plate body and disposed in the first plane so as to be aligned with the respective mating ends and mounting ends of the electrical signal contacts. | 2010-09-23 |
20100240234 | Internal bus bar and an electrical interconnection means therefor - An electrified framework system for bringing power and/or signal to electrically powered devices is provided. The system includes at least one longitudinally extending electrified bus bar. The bus bar has a housing which includes a pair of conductors positioned therein. Each conductor has a mating surface which provides a continuous conductive path for attachment of devices. The system also includes a means to bring electricity to the conductors without interfering with the mating surface of the conductors and thereby creating an unavailable point for electrical connection. | 2010-09-23 |
20100240235 | ELECTRONIC DEVICE - This invention provides an electronic device capable of being connected with an external device. The electronic device includes a first connecting port, an adapting element, and a casing. The first connecting port is disposed at the casing. The adapting element has a second connecting port and a connector. The size of the second connecting port is greater than that of the first connecting port. The casing has a containing space for containing the adapting element. When the electronic device is connected with the external device, the adapting element is separated from the containing space, the connector is connected with the first connecting port, and the second connecting port is connected with the external device. | 2010-09-23 |
20100240236 | PORTABLE COMPUTER UNIVERSAL SERIAL BUS DEVICE WITH AN EXTENDABLE CONNECTOR SECURED BY MULTIPLE LOCKING MECHANISMS - An apparatus for use within an electrical devices is disclosed. The apparatus comprises a casing having an upper body and a lower body, the casing including a tab disposed on a surface thereof and an adjustable base having a plurality of tab cavities adjacent to the tab. The tab engagingly couples to one of the plurality of tab cavities to secure the adjustable base. The apparatus also includes a connector system coupled to the adjustable base. | 2010-09-23 |
20100240237 | Electrical additional module for a service device, combination of the additional module with the service device, as will as an additional module set - Service devices are used in the field of automation and normally form interfaces between programmable logic controllers (PLC) and the installations or installation components to be controlled. Service devices such as these generally have a multiplicity of electrical interfaces for additional modules, with the additional modules being connected via control lines to the PLC, to further service devices or to installation components. An electrical additional module for a service device, a combination of the additional module with the service device, and an additional module set having various additional modules which allow easier fitting and removal of the additional modules in the service device are disclosed. In at least one embodiment, an electrical additional module is proposed, having an appliance interface for fitting the additional module to a service device, with the service device having a stepped holding geometry with at least two steps on each of which a contact device is arranged for holding an electrical opposing contact device, with the appliance interface having step sections which are designed to be complementary to the at least two steps and on which in each case one of the electrical opposing contact device is arranged in order to make contact with the associated contact device, and with the at least two step sections being rigidly connected to one another when the additional module is not fitted. | 2010-09-23 |
20100240238 | CONNECTOR TERMINAL PROTECTION CAP AND HARNESS ASSEMBLY - An object of the present invention is to provide a connector terminal protection cap for a harness and a harness assembly that are capable of protecting connector terminals provided on one end of a harness and that does not come off easily during transfer or transport but can be easily removed at an assembly site. Provided are a connector terminal protection cap that is made of plastic and is attached to a connector provided on one end of a harness to protect connector terminals, the connector terminal protection cap including a cap main body that has an opening at one end thereof that serves as a mating portion to be fitted to a connector main body and a cap-shaped cylinder portion that is formed integrally with and continuously from the mating portion to cover an outer circumference of the terminals, and a pair of pawl members and that are provided at opposing positions on an outer circumference of the mating portion of the cap main body, anchoring to the connector main body, thereby attaching the cap main body to the connector main body in a freely attachable/detachable manner. | 2010-09-23 |
20100240239 | Electronic Device with Hidden I/O Interface Module - An electronic device with a hidden I/O interface module is disclosed. The electronic device includes a container and a surface with an opening, container and the opening communicate with each other. The container includes a first position and a second position. The electronic device also includes an I/O connection unit, a pivot module and a cover. The I/O connection unit is disposed at the container, electrically connected to the electronic device and includes a connecting surface. The pivot module is connected to the I/O connection unit. The cover is connected to the pivot module. When the cover is shut, it covers the container and makes the I/O connection unit located at the first position. When the cover is open, it drives the pivot module to drive the I/O connection unit to move to the second position to make the connecting surface of the I/O connection unit aligned with the surface. | 2010-09-23 |
20100240240 | FLEXIBLE CONNECTOR FOR IMPLANTABLE ELECTRICAL STIMULATION LEAD - In some embodiments, an apparatus includes an electrical connector having a side wall defining a lumen and an elongate opening. The lumen is configured to receive at least a conductive portion of an electronic implant. The elongate opening divides the side wall into a first portion and a second portion. The first portion of the side wall is configured to move relative to the second portion of the side wall between a first position and a second position. The first portion of the side wall is electrically conductive and includes a protrusion. The protrusion is configured to contact the conductive portion of the electronic implant such that the conductive portion of the electronic implant is electrically coupled to the first portion of the side wall when the first portion of the side wall is in the second position. | 2010-09-23 |
20100240241 | APPARATUS, MOUNTING STRUCTURE, INSERTING AND PULLING JIG, AND FIXING METHOD - An apparatus includes a first substrate, a first connector disposed on a top face of the first substrate, a to-be-fixed member disposed on a back face of the first substrate, a second substrate disposed facing the first substrate, a second connector disposed on the second substrate and connected to the first connector, and a fixing module disposed on the second substrate and pivoting a locking arm using a rotating shaft, wherein the to-be-fixed member is pushed by a pushing portion provided at a tip of the locking arm when the locking arm is at a first position. | 2010-09-23 |
20100240242 | PLUG FOR PHOTOVOLTAIC CONNECTOR CABLE - The invention relates to a plug connector ( | 2010-09-23 |
20100240243 | ELECTRICAL CONNECTOR ASSEMBLY WTH IMPROVED LATCHING MECHANISM - An electrical connector assembly ( | 2010-09-23 |
20100240244 | MULTI-PORT CABLE CONNECTOR WITH TWO-STAGE RETENTION CLIPS - A device of and method for making a multi-port cable connector is disclosed. The device comprises a connector housing having a plurality of orifices and a clip receiving portion extending into each orifice, each orifice being adapted to receive a corresponding cable connector therein and each clip receiving portion including, at least one grooved engagement surface disposed in a sidewall of the clip receiving portion and defining a first stage, and at least one second grooved engagement surface disposed below the at least one first grooved engagement surface in a sidewall of the clip receiving portion and defining a second stage; and comprises a plurality of retention clips adapted to slide between the first stage and the second stage in a corresponding clip receiving portion, each retention clip including a pair of engagement arms having a notched engagement surface for alternately engaging the pair of first engagement surfaces and the pair of second engagement surfaces. | 2010-09-23 |
20100240245 | Jacket Sleeve with Grippable Tabs for a Cable Connector - A jacket sleeve with grippable tabs provides protection to exposed portions of cable that are connected to an electrical connection. The jacket sleeve can be made as part of the electrical connector or may be connected subsequent to its creation through the use of glues or other adhesives. The jacket sleeve can be made of a material that is more pliable than the electrical connector, making it easier for a lineperson to place the sleeve over an exposed portion of cable. The jacket sleeve can include holes or slots either in the sleeve or in tabs that are attached to the sleeve. A lineperson can place one or more fingers into each hole or slot in order to get a better grip on the sleeve and pull the sleeve over the exposed portion of cable with less slippage and effort on the part of the lineperson. | 2010-09-23 |
20100240246 | CONNECTOR ASSEMBLY WITH A LIGHT INDICATIVE OF A CONNECTOR STATUS - A connector assembly includes a housing, a light source located within the housing, and a cover element covering at least a portion of a mating face of the housing. The housing includes a connector that is arranged to electrically mate with a peripheral connector proximate to the mating face of the housing. The light source generates light directed toward the mating face of the housing to indicate a status of the connector. The cover element includes a light transmissive area that is positioned to receive the light generated by the light source and transmit the light outward from the mating face in order to indicate the status of the connector. | 2010-09-23 |
20100240247 | THREE-DIMENSIONAL CONNECTOR FOR A COORDINATE INPUT DEVICE - A three-dimensional connector, which is used by a coordinate input device of a touch pad has a flat conductor cable with an end being connected to the touch pad and another end having multiple conductive lines. Each of the conductive lines is attached with a vertical guiding conductor pin. The guide conductor pin has a head section to press-fit with the flat conductor cable, and extends through a support to transmit electronic signals in a direction perpendicular to said flat conductor cable. | 2010-09-23 |
20100240248 | THREE-DIMENSIONAL CONNECTOR FOR A COORDINATE INPUT DEVICE - A three-dimensional connector, which is used by a coordinate input device of a touch pad, has a flat conductor cable with an end being connected to the touch pad and another end forming a soldered conductive contact head perpendicular to the flat conductor cable to pass through a support to shorten a length of said conductor cable and enhance electro-conductibility of the connector. | 2010-09-23 |
20100240249 | ELECTRICAL WIRING SYSTEM - An electrical wiring system for use in an AC electrical power distribution circuit including a plurality of AC electric power transmitting wires having termination ends disposed within a device box. The system includes a plug connector device configured to terminate the plurality of AC electric power transmitting wires. The system additionally includes an electrical wiring device including at least one AC electric circuit element and at least one electrical interface operatively coupled to the at least one circuit element. The electrical wiring device also includes a receptacle, wherein the receptacle is configured to receive the plug connector device such that electrical continuity is established between the AC electric circuit element and the plurality of AC electric power transmitting wires when the plug connector device is inserted into the receptacle. | 2010-09-23 |
20100240250 | WALL PLATE ASSEMBLY WITH INTEGRAL UNIVERSAL SERIAL BUS MODULE - A wall plate assembly including a wall plate with an integrated USB module. The assembly includes a USB connector and printed circuit board formed together on the wall plate as an integral whole. By placing USB extender circuitry directly on the printed circuit board, rather than in a separate housing, the present assembly can maintain its bus-powered attributes without the bulk of a separate extender housing. A quick-connect coupling enables fast electrical connection and disconnection with a complementary quick-connect coupling on a USB wire. | 2010-09-23 |
20100240251 | METHODS AND SYSTEMS FOR POSITIONING CONNECTORS TO MINIMIZE ALIEN CROSSTALK - The present invention relates to methods and systems for minimizing alien crosstalk between connectors. Specifically, the methods and systems relate to isolation and compensation techniques for minimizing alien crosstalk between connectors for use with high-speed data cabling. A frame can be configured to receive a number of connectors. Shield structures may be positioned to isolate at least a subset of the connectors from one another. The connectors can be positioned to move at least a subset of the connectors away from alignment with a common plane. A signal compensator may be configured to adjust a data signal to compensate for alien crosstalk. The connectors are configured to efficiently and accurately propagate high-speed data signals by, among other functions, minimizing alien crosstalk. | 2010-09-23 |
20100240252 | Electrical Connector - The electrical connector includes an insulating housing, for receiving at least one electrical contact terminal connected to a cable, wherein at least one terminal accommodating chamber is formed, said insulating housing including a front face intended to mate with a counterpart connector, and a rear wall provided with a rear slot for introducing each terminal in the respective chamber. It further including a sealing deformable material facing the rear wall, and press for pressing the sealing deformable material against the rear wall. The press comprises a flap connected to the housing so as to be able to rotate between an open position in which access to the rear slot is allowed, and a closed position in which the flap presses the sealing deformable material against the rear wall, so that the sealing deformable material deforms in order to sealingly close the rear slot and come into contact with the cable when it is inserted. | 2010-09-23 |
20100240253 | Connector Assemblies for Implantable Medical Electrical Systems - A device connector assembly includes a plurality of electrical contacts and a sealing member including a corresponding plurality of apertures; each electrical contact extends within a corresponding aperture of the plurality of apertures such that each contact is accessible for coupling with a corresponding connector element of a lead connector. The lead connector elements protrude from a first side of an insulative substrate of the lead connector, and may be coupled to the contacts of the device connector assembly by aligning each connector element with the corresponding aperture of the sealing member, and applying a force to a second side of the insulative substrate, opposite the first side, in order to press each connector element into engagement with the corresponding contact. | 2010-09-23 |
20100240254 | PLUG-IN CONNECTOR COMPRISING A MODIFIED INSULATOR DUCT FOR SHIELDING ELECTROMAGNETIC RADIATION - A plug-in connector ( | 2010-09-23 |
20100240255 | ELECTRICAL CONNECTOR WITH IMPROVED MOUNTING PORTION - An electrical connector ( | 2010-09-23 |
20100240256 | INTERCONNECTING MODULAR HEADERS AND HEADER ASSEMBLIES THEREOF - Interconnecting modular connectors or headers have flexible tongue and groove structures for forming a variety of header assembly configurations. The interconnecting modular headers can have locking structures in addition to the tongue and groove mating structures for permanently interlocking the modular headers together. The sidewalls of each modular connector can be parallel to each other and disposed at supplementary angles with respect to the rear wall of the housing. The top wall of each modular connector can have a portion wall extending inwardly from each sidewall at an angle of greater than ninety degrees and each portion wall can have an upwardly extending wall that joins the portion walls to a ceiling. The portion walls can join with the upwardly extending walls to form a T-shape corner. The upwardly extending walls can join with the ceiling equally at an angle of greater than ninety degrees. | 2010-09-23 |
20100240257 | CONNECTOR WITH PROJECTING FUNCTION - A connector with projecting function is electrically connected to a circuit board of an electronic device and includes a casing, a base, a rear cover, a projecting module and an electrical connector. The base has a first port and a second port. The projecting module is provided in the first port. The electrical connector is provided in the second port. The casing and the rear cover are assembled outside the base. When the connector is combined with the electronic device, a plurality of electrical-conductive terminals of the connector is configured to transmit image signals of the electronic device to a circuit board of the connector. Then, a control circuit and an image processing chip of the projecting module can process the image signals to project the processed images onto an external screen. | 2010-09-23 |
20100240258 | Connector - The present invention relates to a connector. The connector includes: a housing; a plurality of the terminals arranged thereon for electrically contacting with a board; a pair of arms extending from two ends of the housing, respectively; a first projection and a second projection formed on each of the arms; and a metal member arranged along the length direction of each of the arms, having a hold-down portion and a first recess for engaging with the first projection with a first buffer space existing therebetween. The metal member is spaced from the second projection by a second buffer space. When the hold-down portion is soldered to a board, the first projection or the second projection may remedy overwarp of the board or the housing. | 2010-09-23 |
20100240259 | AUDIO JACK WITH POGO PINS FOR CONDUCTIVE CONTACTS - An audio jack can allow electrical connections between an audio plug and an electronic device. The audio jack can include a series of pogo pins operative to extend into an audio jack cavity to provide conductive contacts for an audio plug placed within the audio jack. When an audio plug is inserted in the audio jack, the deflectable tips of each pogo pin can deflect and contact audio plug contact portions or regions. The end of the pogo pins opposite the deflectable tips can be coupled to an appropriate electronic device component, such as a printed circuit board, flex circuit, cable, or any other suitable component to provide a conductive path for signals between the audio plug and the electronic device. | 2010-09-23 |
20100240260 | EARPHONE JACK DEVICE AND PORTABLE ELECTRONIC DEVICE EMPLOYING THE SAME - A portable electronic device includes an earphone jack device for connecting a plug of an earphone and a main circuit board. The main circuit board includes an audio signal processor module connected to the earphone jack device, an MSM module connected to the audio signal processor module, and a PMIC module connected to the earphone jack device. The MSM module generates a first bias voltage inputted into the audio signal processor module to actuate the audio signal processor module to play audio signals, and the PMIC module generates a second bias voltage inputted to the earphone jack device to actuate the earphone connected to the earphone jack device. | 2010-09-23 |
20100240261 | AUDIO SIGNAL SWITCHER - An audio signal switcher includes a jack switcher and a plug switcher. The jack switcher includes at least two audio jacks and a first USB port. The first USB port includes a first data pin, a second data pin, a power pin, and a ground pin. Each of the audio jacks includes a left track segment, a right track segment, and a ground segment, which are electrically isolated coupled to at least three pins of the first USB port. The plug switcher includes an audio plug and a second USB port. The second USB port also includes a data pin, a second data pin, a power pin, and a ground pin. The audio plug also includes a left track segment, a right track segment, and a ground segment, which are electrically isolated coupled to at least three pins of the second USB port. | 2010-09-23 |