38th week of 2013 patent applcation highlights part 75 |
Patent application number | Title | Published |
20130246693 | FLASH-AWARE STORAGE OPTIMIZED FOR MOBILE AND EMBEDDED DBMS ON NAND FLASH MEMORY - Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates. | 2013-09-19 |
20130246694 | Multilevel Memory Bus System For Solid-State Mass Storage - The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these. | 2013-09-19 |
20130246695 | INTEGRATED CIRCUIT DEVICE, SIGNAL PROCESSING SYSTEM AND METHOD FOR PREFETCHING LINES OF DATA THEREFOR - An integrated circuit device comprising at least one prefetching module for prefetching lines of data from at least one memory element. The prefetching module is configured to determine a position of a requested block of data within a respective line of data of the at least one memory element, determine a number of subsequent lines of data to prefetch, based at least partly on the determined position of the requested block of data within the respective line of data of the at least one memory element, and cause the prefetching of n successive lines of data from the at least one memory element. | 2013-09-19 |
20130246696 | System and Method for Implementing a Low-Cost CPU Cache Using a Single SRAM - One embodiment of the present invention relates to a CPU cache system that stores tag information and cached data in the same SRAM. The system includes an SRAM memory device, a lookup buffer, and a cache controller. The SRAM memory device includes a cache data section and a cache tag section. The cache data section includes data entries and the tag section includes tag entries associated with the data entries. The tag entries include memory addresses that correspond to the data entries. The lookup buffer includes lookup entries associated with at least a portion of the data entries. The number of lookup entries is less than the number of tag entries. The cache controller is configured to perform a speculative read of the cache data section and a cache check of the lookup buffer simultaneously or in a single cycle. | 2013-09-19 |
20130246697 | Organizing Data in a Hybrid Memory for Search Operations - Methods, systems, and computer readable storage medium embodiments for configuring a lookup table, such as an access control list (ACL) for a network device are disclosed. Aspects of these embodiments include storing a plurality of data entries in a memory, each of the stored plurality of data entries including a header part and a body part, and encoding each of a plurality of bit-sequences in the header part of a stored data entry from the plurality of data entries to indicate a bit comparing action associated with a respective bit sequence in the body part of the stored data entry. Other embodiments include searching a lookup table in a network device. | 2013-09-19 |
20130246698 | Hybrid Memory for Search Operations - Methods, systems, and computer readable storage medium embodiments for configuring a lookup table for a network device are disclosed. Aspects in these embodiments include generating a decision tree based upon bit representations of respective data entries from a plurality of data entries where one or more of the plurality of data entries are represented at respective nodes of the decision tree, storing a first bit pattern corresponding to a selected node from the decision tree in a content addressable memory (CAM) at a location associated with an index, and storing one or more second bit patterns at an address in a second memory. The one or more second hit patterns correspond to the one or more data entries represented at the selected node, and the address is associated with the index. Embodiments also include searching a lookup table in a network device. | 2013-09-19 |
20130246699 | FINDING THE LENGTH OF A SET OF CHARACTER DATA HAVING A TERMINATION CHARACTER - The length of character data having a termination character is determined. The character data for which the length is to be determined is loaded, in parallel, within one or more vector registers. An instruction is used that loads data in a vector register to a specified boundary, and provides a way to determine the number of characters loaded, using, for instance, another instruction. Further, an instruction is used to find the index of the first termination character, e.g., the first zero or null character. This instruction searches the data in parallel for the termination character. By using these instructions, the length of the character data is determined using only one branch instruction. | 2013-09-19 |
20130246700 | DEVICE TYPE OVERRIDE - A backup system override may be specified to allow a backup system to access a backup created on an old storage device. For example, an archival backup may be accessed long after the storage device that created the backup has been decommissioned. The file history information in the backup may specify a storage device no longer accessible by the backup system. An override in the backup system allows the backup system to access the backup with the file history information through a different storage device than the storage device that created the backup. The different storage device may have a different name and/or be of a different type than the original storage device that created the backup. The override may also allow access to command scripts and links in the backup. | 2013-09-19 |
20130246701 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR WRITING MULTIPLE FILES SIMULTANEOUSLY TO A TAPE MEDIA - In one embodiment, a method includes storing data received from at least two data sources in a buffer, writing the data from the at least two data sources to regions in a first wrap of a tape on a data-source basis in a first predetermined order, the regions in the first wrap being previously allocated to the at least two data sources, moving a head to a second wrap of the tape when an end of the first wrap of the tape is reached, and writing the data from the at least two data sources to regions in the second wrap in a second predetermined order, the second predetermined order being a reverse order relative to the first predetermined order, the regions in the second wrap being previously allocated to the at least two data sources. The first and second wraps have first and second predetermined lengths, respectively. | 2013-09-19 |
20130246702 | STORAGE CONTROL DEVICE, STORAGE CONTROL METHOD, AND RECORDING MEDIUM - A storage control device includes a memory configured to store a program; and a processor configured to execute a process based on the program. The process includes: writing additional data into an area reserved for allocation in a disk, detecting a volume of the data and the additional data written into the disk as a used amount of the disk, calculating an amount of increase or decrease in a current used amount of the disk with respect to the used amount of the disk previously detected, calculating a changed volume on the basis of a ratio between the amount of increase or decrease in the used amount of the disk and a volume of the area reserved for allocation, and allocating the area reserved for allocation to the disk so that the area reserved for allocation corresponding to the calculated changed volume is continued in the disk. | 2013-09-19 |
20130246703 | SHINGLED MAGNETIC RECORDING DISK DRIVE WITH INTER-BAND DISK CACHE AND MINIMIZATION OF THE EFFECT OF FAR TRACK ERASURE ON ADJACENT DATA BANDS - A shingled magnetic recording hard disk drive that uses writeable cache tracks in the inter-band gaps between the annular data bands minimizes the effect of far track erasure (FTE) in the boundary regions of annular data bands caused by writing to the cache tracks. Based on the relative FTE effect for all the tracks in a range of tracks of the cache track being written, a count increment (CI) table or a cumulative count increment (CCI) table is maintained. For every writing to a cache track, a count for each track in an adjacent boundary region, or a cumulative count for each adjacent boundary region, is increased. When the count value for a track, or the cumulative count for a boundary region, reaches a predetermined threshold the data is read from that band and rewritten to the same band. | 2013-09-19 |
20130246704 | SYSTEMS AND METHODS FOR OPTIMIZING WRITE ACCESSES IN A STORAGE ARRAY - A method may include storing data in one or more first-type stripes spanning a plurality of N storage resources and having N−1 data strips for storing the data and a parity strip for storing parity information for the data stored to the particular first-type stripe and each of the plurality of storage resources includes one of a data strip or a parity strip of the particular first-type stripe if the data to be stored exceeds a threshold size. If the data to be stored does not exceed a threshold size, the method may include storing the data in a second-type stripe and a third-type stripe each spanning N storage resources, such that each stripe comprises N−1 data strips for storing the data and a metadata strip for storing address information for the corresponding second-type strip or third-type strip. | 2013-09-19 |
20130246705 | BALANCING LOGICAL UNITS IN STORAGE SYSTEMS - Techniques for generating a recommended change to balance a storage system are described in various implementations. A method that implements the techniques may include analyzing a storage system that includes a plurality of logical unit numbers (LUNs) that support asymmetric logical unit access (ALUA) to determine a current state of the storage system, wherein the current state includes LUN distribution information and system performance information. The method may also include evaluating the current state to determine whether the current state is unbalanced based on the LUN distribution information and the system performance information, and in response to determining that the current state is unbalanced, generating a recommended change to balance the storage system. | 2013-09-19 |
20130246706 | STORAGE APPARATUS AND PROGRAM UPDATE METHOD - A storage apparatus and program update method for reducing tediousness and complications of drive inventory management. | 2013-09-19 |
20130246707 | TWO STAGE CHECKSUMMED RAID STORAGE MODEL - A method for writing a logical data block to storage. The method includes receiving a request to write a logical data block to a storage pool, allocating a number of physical log blocks in a RAID log and a parity block for the logical data block, and writing the logical data block and the parity block to the physical log blocks. The number of the physical log blocks are less than a number of disks storing the RAID log. The method further includes allocating space in a physical slab block in a RAID slab for the logical data block, copying data including the logical data block to the space in the physical slab block, and updating, in the RAID slab, a check-sum corresponding to the physical slab block and a parity block that includes the data stripe having the physical slab block based on the data copied. | 2013-09-19 |
20130246708 | FILTERING PRE-FETCH REQUESTS TO REDUCE PRE-FETCHING OVERHEAD - The disclosed embodiments provide a system that filters pre-fetch requests to reduce pre-fetching overhead. During operation, the system executes an instruction that involves a memory reference that is directed to a cache line in a cache. Upon determining that the memory reference will miss in the cache, the system determines whether the instruction frequently leads to cache misses. If so, the system issues a pre-fetch request for one or more additional cache lines. Otherwise, no pre-fetch request is sent. Filtering pre-fetch requests based on instructions' likelihood to miss reduces pre-fetching overhead while preserving the performance benefits of pre-fetching. | 2013-09-19 |
20130246709 | TRANSLATION ADDRESS CACHE FOR A MICROPROCESSOR - Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version. | 2013-09-19 |
20130246710 | STORAGE SYSTEM AND DATA MANAGEMENT METHOD - A storage system is provided with a plurality of physical storage devices, a cache memory, a control device that is coupled to the plurality of physical storage devices and the cache memory, and a buffer part. The buffer part is a storage region that is formed by using at least a part of a storage region of the plurality of physical storage devices and that is configured to temporarily store at least one target data element that is to be transmitted to a predetermined target. The control device stores a target data element into a cache region that has been allocated to a buffer region (that is a part of the cache memory and that is a storage region of a write destination of the target data element for the buffer part). The control device transmits the target data element from the cache memory. In the case in which a new target data element is generated, the control device executes a control in such a manner that the new target data element has a high tendency to be stored for a buffer region in which the transmitted target data element has been stored and to which a cache region has been allocated. | 2013-09-19 |
20130246711 | System and Method for Implementing a Hierarchical Data Storage System - A system and method for efficiently storing data both on-site and off-site in a cloud storage system. Data read and write requests are received by a cloud data storage system. The cloud storage system has at least three data storage layers. A first high-speed layer, a second efficient storage layer, and a third off-site storage layer. The first high-speed layer stores data in raw data blocks. The second efficient storage layer divides data blocks from the first layer into data slices and eliminates duplicate data slices. The third layer stores data slices at an off-site location. | 2013-09-19 |
20130246712 | Methods And Apparatuses For Efficient Load Processing Using Buffers - Various embodiments of the invention concern methods and apparatuses for power and time efficient load handling. A compiler may identify producer loads, consumer reuse loads, consumer forwarded loads, and producer/consumer hybrid loads. Based on this identification, performance of the load may be efficiently directed to a load value buffer, store buffer, data cache, or elsewhere. Consequently, accesses to cache are reduced, through direct loading from load value buffers and store buffers, thereby efficiently processing the loads. | 2013-09-19 |
20130246713 | CONDITIONAL WRITE PROCESSING FOR A CACHE STRUCTURE OF A COUPLING FACILITY - A method for managing a cache structure of a coupling facility includes receiving a conditional write command from a computing system and determining whether data associated with the conditional write command is part of a working set of data of the cache structure. If the data associated with the conditional write command is part of the working set of data of the cache structure the conditional write command is processed as an unconditional write command. If the data associated with the conditional write command is not part of the working set of data of the cache structure a conditional write failure notification is transmitted to the computing system. | 2013-09-19 |
20130246714 | SYSTEM AND METHOD FOR SUPPORTING BUFFER ALLOCATION IN A SHARED MEMORY QUEUE - A system and method can support buffer allocation in a shared memory queue. The shared memory queue can be associated with a shared memory, to which one or more communication peers are attached. One or more processes can travel through a plurality of memory blocks in the shared memory, and can allocate one or more message buffers in the shared memory mutual exclusively. The allocated message buffers can be used to contain one or more messages for the one or more communication peers. Furthermore, a said process can allocate the message buffers based on an atomic operation on the memory block at the instruction level. | 2013-09-19 |
20130246715 | COMMUNICATION APPARATUS, LOAD DISTRIBUTION METHOD, AND RECORDING MEDIUM - A first communication apparatus includes a first central processing core; and a first memory. The first communication apparatus executes load distribution based on a first load amount of the first communication apparatus and a second load amount of a second communication apparatus that includes a second central processing core and a second memory. The first communication apparatus executes first load distribution when the first communication apparatus and the second communication apparatus perform wireless communication. The first communication apparatus executes second load distribution when the first communication apparatus and the second communication apparatus perform wired communication. | 2013-09-19 |
20130246716 | MEMORY SYSTEM AND DATA WRITING METHOD - According to one embodiment, when a controller writes update data in a second memory to a first memory which is nonvolatile and a difference between a size of a page and a size of the update data is equal to or greater than a size of a cluster, the controller configured to generate write data by adding, to the update data, data which has the size of the cluster, store an update content of management information corresponding to the update data and an update content storage position indicating a storage position of the update content of the management information in the first memory, and write the generated write data to a block in writing of the first memory. | 2013-09-19 |
20130246717 | INFORMATION PROCESSING SYSTEM - An information processing system includes: CPUs; storage devices; switches; dummy storage devices which are with respective storage devices and each of which sends, when receiving an identifying information request, its own identifying information back to a sender of the identifying information request; and dummy CPUs which are associated with respective CPUs and each of which tries to, when receiving an instruction for acquiring identifying information from a dummy storage device, acquire the identifying information of the dummy storage device by transmitting the identifying information request, and sends the identifying information as response information back to a sender device of the acquiring instruction. | 2013-09-19 |
20130246718 | CONTROL DEVICE AND CONTROL METHOD FOR CONTROL DEVICE - A control device includes a storage to store correspondence information indicating a correspondence between each of memories and each of information processing devices; and a processor to execute an operation including: detecting a first memory from among the memories, the first memory being a memory whose access frequency exceeds a predetermined access frequency or is relatively high, and a second memory being a memory whose access frequency is lower than or equal to a predetermined access frequency, changing the correspondence information so that an information processing device corresponding to the first memory changes from a first information processing device to a second information processing device corresponding to the second memory, and notifying a management device of the changed correspondence information, and outputting data read from the first memory to the management device via the second information processing device. | 2013-09-19 |
20130246719 | PARTITION-FREE MULTI-SOCKET MEMORY SYSTEM ARCHITECTURE - A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock. | 2013-09-19 |
20130246720 | Providing Reliability Metrics For Decoding Data In Non-Volatile Storage - A set of reliability metrics is provided for use by an iterative probabilistic decoding process for non-volatile storage. A plurality of sense operations are performed on at least one set of non-volatile storage elements which are programmed to a plurality of programming states. A set of reliability metrics such as logarithmic likelihood ratios is provided based on the sense operations. The set of reliability metrics is can be used by an iterative probabilistic decoding process in determining a programming state of at least one non-volatile storage element based on at least one subsequent sense operation involving the at least one non-volatile storage element. The plurality of sense operations can be performed at different ages (e.g., number of program/erase cycles) of the at least one set of non-volatile storage elements and the set of reliability metrics can be based on an average over the different ages. | 2013-09-19 |
20130246721 | CONTROLLER, DATA STORAGE DEVICE, AND COMPUTER PROGRAM PRODUCT - According to an embodiment, a controller includes a write control unit configured to make a control that converts data requested to be written by an external device into pieces of cluster data with a size of a cluster of a storage medium, compresses each piece of cluster data, determines a corresponding physical address of a write destination in the storage medium according to a predetermined rule, and writes the compressed pieces of cluster data to the storage medium using the physical address of the write destination. The write control unit also makes a control that writes a correspondence between the physical address and a corresponding logical address to a storage unit. The controller also includes a read control unit configured to a control that reads a piece of cluster data from the storage medium using an acquired physical address, and decompresses the read piece of cluster data. | 2013-09-19 |
20130246722 | STORAGE SYSTEM HAVING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE WITH NONVOLATILE SEMICONDUCTOR MEMORY - A storage system coupled to a host has a nonvolatile semiconductor storage device that includes a nonvolatile semiconductor memory configured by a plurality of pages, and a storage controller coupled to the semiconductor storage device. In the case where data stored in the plurality of pages become unnecessary, with this plurality of pages being the basis of a region of a logical volume based on the nonvolatile semiconductor storage device, the storage controller transmits, to the nonvolatile semiconductor storage device, an unnecessary reduction request for reducing the number of pages that are the basis of the region having the unnecessary data stored therein. On the basis of the unnecessary reduction request, the nonvolatile semiconductor storage device invalidates the plurality of pages that are the basis of the region having the unnecessary data stored therein. | 2013-09-19 |
20130246723 | Efficient Loading of Data into Memory of a Computing System - The method comprises receiving mapping information from a data storage system. The mapping information associates a first data chunk stored in the data storage system with a unique identifier to support deployment of a first virtual machine on a host computing system. Once the mapping information is received, the mapping information is utilized to determine whether any copies of the first data chunk have already been loaded into a memory of the host computing system in association with deployment of the first virtual machine or a second virtual machine on the host computing system. If no copies of the first data chunk have already been loaded into the memory, the first data chunk is retrieved from the data storage system, loaded into the memory, and utilized to deploy the first virtual machine on the host computing system. | 2013-09-19 |
20130246724 | BACKUP DEVICE, METHOD OF BACKUP, AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN PROGRAM FOR BACKUP - A backup device that generates a backup volume of an object volume, the backup device includes: a first storage device that stores data of the backup volume; and a processor that generates, upon receipt of an instruction of generating the backup volume, the backup volume by copying data of the object volume into a first region of the first storage device, moves the data of the backup volume, the data being stored in the first region of the first storage device, to a second region of the first storage device, the second region being subordinate to the first region, and releases, upon receipt of an instruction of generating the backup volume under a state where the data of the backup volume is stored in the second region, the data of the backup volume from the second region. | 2013-09-19 |
20130246725 | RECORDING MEDIUM, BACKUP CONTROL METHOD, AND INFORMATION PROCESSING DEVICE - A program causes a computer to execute a control process that includes: issuing, in accordance with a module in an environment, an instruction for causing a process of another program operating on the environment and utilizing a first storage region to stop an updating operation; notifying, to a process of another module in another environment from which each real storage device is recognizable, first/second virtual identification information for identifying, in a virtual storage device(s) recognized in the former environment, the first/second storage regions; acquiring, in accordance with the latter module by using the above information and a relation between the real and virtual storage devices, first/second real identification information for identifying, in the real storage device(s), the first/second storage regions; and based on the first/second real identification information and in accordance with the latter module, issuing an instruction for backing up data from the first to the second storage region. | 2013-09-19 |
20130246726 | METHOD AND DEVICE FOR A MEMORY SYSTEM - A method for the writing and reading of semi-structured data objects into a memory system is disclosed. The writing method comprises transforming the semi-structured data object into a first data stream, allocating a first storage area for the semi-structured data object in the memory system, writing the first data stream to the allocated first storage area, and creating at least one data object locator indicative of the commencement of the allocated first storage area; and updating the inode to reflect the new storage area of the updated object locator. | 2013-09-19 |
20130246727 | ELECTRONIC CIRCUIT AND ARBITRATION METHOD - An electronic circuit including, a plurality of memory masters that access a memory, and an arbitration circuit that arbitrates between the plurality of memory masters requesting access to the memory. The arbitration circuit performs the following processing, when one of the plurality of memory masters has succeeded in accessing the memory, priority of the one memory master is decreased, and priority of the other one of the plurality of masters is increased, for each of the plurality of memory masters, a correction value to be applied to the priority is determined according to the number of accesses made to the memory during a certain past period, and permission to access the memory is granted to a memory master selected from along the plurality of memory masters according to the priority corrected by adding the correction value. | 2013-09-19 |
20130246728 | INFORMATION PROCESSING APPARATUS - A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted. | 2013-09-19 |
20130246729 | Method for Managing a Memory of a Computer System, Memory Management Unit and Computer System - A method for managing a memory of a computer system, a memory management unit and a computer system are provided. The method includes: receiving an allocation request sent by a user process; allocating the memory for the user process according to the allocation request and setting an offline flag for the memory; receiving a locking request sent by the user process; locking the memory according to the locking request and the offline flag of the memory; and taking the memory offline according to the offline flag of the memory. The computer system includes at least one memory and a memory management unit according to an embodiment of the present invention. Thus, through the interaction between a kernel and the user process and setting an offline mode for the memory, the memory locked by the user process is taken offline. | 2013-09-19 |
20130246730 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR WRITING THEREIN - According to one embodiment, a semiconductor memory device includes a plurality of blocks in a memory cell, each of the blocks acting as an erasure unit of data, the block including a plurality of pages, each of the pages including a plurality of memory cell transistors, each of the memory cell transistors being configured to be an erasure state or a first retention state based on a threshold voltage of the memory cell transistor, and a controller searching data in the block with respect to, writing a first flag denoting effective into a prescribed page of the block with the erasure state, and writing the first flag denoting non-effective into a prescribed page of the block with the first retention state, reading out the prescribed page of the block with the first retention state, and determining that the block is writable when the first flag denotes effective. | 2013-09-19 |
20130246731 | DISTRIBUTED GRAPH STORAGE SYSTEM - In a method of implementing a graph storage system, the graph storage system is stored on a plurality of computing systems. A global address space is provided for distributed graph storage. The global address space is managed with graph allocators, in which a graph allocator allocates space from a block of the distributed global memory in order to store a plurality of graphs. | 2013-09-19 |
20130246732 | METHOD OF PROGRAMMING MEMORY CELLS AND READING DATA, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME - A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells. | 2013-09-19 |
20130246733 | PARALLEL PROCESSING DEVICE - A parallel processing device includes a processing sequence management unit that reads commands of the command corresponding to a parallel processing start bit to the command corresponding to a parallel processing completion bit from a sequence command storage in sequence to make the sequence command storage output the commands to a first address management unit and a second address management unit, the first address management unit refers to the sequence commands read from the sequence command storage in order from the head to find the command that a first processing execution unit executes, and then instructs the first processing execution unit to execute the command, and the second address management unit refers to the sequence commands read from the sequence command storage in order from the head to find the command that a second processing execution unit executes, and then instructs the second processing execution unit to execute the command. | 2013-09-19 |
20130246734 | Adaptive Address Mapping with Dynamic Runtime Memory Mapping Selection - A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel. | 2013-09-19 |
20130246735 | RECONFIGURABLE PROCESSOR BASED ON MINI-CORES, SCHEDULE APPARATUS, AND METHOD THEREOF - A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration. | 2013-09-19 |
20130246736 | PROCESSOR, ELECTRONIC CONTROL UNIT AND GENERATING PROGRAM - A processor in which plural cores perform respective programs includes: a first own core execution point acquiring part configured to acquire first code block information if a first core executes an execution history recording instruction described at an execution history recording point in the program, the first code block information indicating, with a single address, a series of instructions executed by the first core; a first other core execution point acquiring part configured to acquire first execution address information of an instruction, the instruction being executed by a second core, if the first core executes the execution history recording instruction; and a first execution point information recording part configured to record the first code block information and the first execution address information in a shared memory in time series such that they are associated with each other. | 2013-09-19 |
20130246737 | SIMD Compare Instruction Using Permute Logic for Distributed Register Files - Mechanisms, in a data processing system comprising a single instruction multiple data (SIMD) processor, for performing a data dependency check operation on vector element values of at least two input vector registers are provided. Two calls to a simd-check instruction are performed, one with input vector registers having a first order and one with the input vector registers having a different order. The simd-check instruction performs comparisons to determine if any data dependencies are present. Results of the two calls to the simd-check instruction are obtained and used to determine if any data dependencies are present in the at least two input vector registers. Based on the results, the SIMD processor may perform various operations. | 2013-09-19 |
20130246738 | INSTRUCTION TO LOAD DATA UP TO A SPECIFIED MEMORY BOUNDARY INDICATED BY THE INSTRUCTION - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary. | 2013-09-19 |
20130246739 | COPYING CHARACTER DATA HAVING A TERMINATION CHARACTER FROM ONE MEMORY LOCATION TO ANOTHER - Copying characters of a set of terminated character data from one memory location to another memory location using parallel processing and without causing unwarranted exceptions. The character data to be copied is loaded within one or more vector registers. In particular, in one embodiment, an instruction (e.g., a Vector Load to block Boundary instruction) is used that loads data in parallel in a vector register to a specified boundary, and provides a way to determine the number of characters loaded. To determine the number of characters loaded (a count), another instruction (e.g., a Load Count to Block Boundary instruction) is used. Further, an instruction (e.g., a Vector Find Element Not Equal instruction) is used to find the index of the first delimiter character, i.e., the first termination character, such as a zero or null character within the character data. This instruction checks a plurality of bytes of data in parallel. | 2013-09-19 |
20130246740 | INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor. | 2013-09-19 |
20130246741 | RUN-TIME INSTRUMENTATION DIRECTED SAMPLING - Embodiments of the invention relate to implementing run-time instrumentation directed sampling. An aspect of the invention includes fetching a run-time instrumentation next (RINEXT) instruction from an instruction stream. The instruction stream includes the RINEXT instruction followed by a next sequential instruction (NSI) in program order. The method further includes executing the RINEXT instruction by a processor. The executing includes determining whether a current run-time instrumentation state enables setting a sample point for reporting run-time instrumentation information during program execution. Based on the current run-time instrumentation state enabling setting the sample point, the NSI is a sample instruction for causing a run-time instrumentation event. Based on executing the NSI sample instruction, the run-time instrumentation event causes recording of run-time instrumentation information into a run-time instrumentation program buffer as a reporting group. | 2013-09-19 |
20130246742 | RUN-TIME-INSTRUMENTATION CONTROLS EMIT INSTRUCTION - Embodiments of the invention relate to executing a run-time-instrumentation EMIT (RIEMIT) instruction. A processor is configured to capture the run-time-instrumentation information of a stream of instructions. The RIEMIT instruction is fetched and executed. It is determined if the current run-time-instrumentation controls are configured to permit capturing and storing of run-time-instrumentation information in a run-time-instrumentation program buffer. If the controls are configured to store run-time-instrumentation instructions, then a RIEMIT instruction specified value is stored as an emit record of a reporting group in the run-time-instrumentation program buffer. | 2013-09-19 |
20130246743 | DETERMINING THE STATUS OF RUN-TIME-INSTRUMENTATION CONTROLS - The invention relates to determining the status of run-time-instrumentation controls. The status is determined by executing a test run-time-instrumentation controls (TRIC) instruction. The TRIC instruction executed in either a supervisor state or a lesser-privileged state. The TRIC instruction determines whether the run-time-instrumentation controls have changed. The run-time-instrumentation controls are set to an initial value using a privileged load run-time-instrumentation controls (LRIC) instruction. The TRIC instruction is fetched and executed. If the TRIC instruction is enabled, then it is determined if the initial value set by the run-time-instrumentation controls has been changed. If the initial value set by the run-time-instrumentation controls has been changed, then a condition code is set to a first value. | 2013-09-19 |
20130246744 | MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control. | 2013-09-19 |
20130246745 | VECTOR PROCESSOR AND VECTOR PROCESSOR PROCESSING METHOD - A vector processor includes an instruction fetching unit configured to acquire an instruction, a decoding/issuing unit configured to decode the instruction and issuing the instruction, an operation group configured to include a plurality of operation units and a register configured to store the element data column, wherein the plurality of operation units include a first operation unit processes a first type instruction and a second operation unit processes a second type instruction and the first type instruction; and when a plurality of divided instructions, for which the element data of an instruction to be issued has been divided, are processed by the second operation unit, in a case where the second type instruction is not present, the decoding/issuing unit issues the divided instructions, and in a case where the second type instruction is present, the decoding/issuing unit issues the instruction to be issued without performing division. | 2013-09-19 |
20130246746 | RUN-TIME INSTRUMENTATION DIRECTED SAMPLING - Embodiments of the invention relate to implementing run-time instrumentation directed sampling. An aspect of the invention includes a method for implementing run-time instrumentation directed sampling. The method includes fetching a run-time instrumentation next (RINEXT) instruction from an instruction stream. The instruction stream includes the RINEXT instruction followed by a next sequential instruction (NSI) in program order. The method further includes executing the RINEXT instruction by a processor. The executing includes determining whether a current run-time instrumentation state enables setting a sample point for reporting run-time instrumentation information during program execution. Based on the current run-time instrumentation state enabling setting the sample point, the NSI is a sample instruction for causing a run-time instrumentation event. Based on executing the NSI sample instruction, the run-time instrumentation event causes recording of run-time instrumentation information into a run-time instrumentation program buffer as a reporting group. | 2013-09-19 |
20130246747 | RUN-TIME-INSTRUMENTATION CONTROLS EMIT INSTRUCTION - Embodiments of the invention relate to executing a run-time-instrumentation EMIT (RIEMIT) instruction. A processor is configured to capture the run-time-instrumentation information of a stream of instructions. The RIEMIT instruction is fetched and executed. It is determined if the current run-time-instrumentation controls are configured to permit capturing and storing of run-time-instrumentation information in a run-time-instrumentation program buffer. If the controls are configured to store run-time-instrumentation instructions, then a RIEMIT instruction specified value is stored as an emit record of a reporting group in the run-time-instrumentation program buffer. | 2013-09-19 |
20130246748 | DETERMINING THE STATUS OF RUN-TIME-INSTRUMENTATION CONTROLS - The invention relates to determining the status of run-time-instrumentation controls. The status is determined by executing a test run-time-instrumentation controls (TRIC) instruction. The TRIC instruction is executed in either a supervisor state or a lesser-privileged state. The TRIC instruction determines whether the run-time-instrumentation controls have changed. The run-time-instrumentation controls are set to an initial value using a privileged load run-time-instrumentation controls (LRIC) instruction. The TRIC instruction is fetched and executed. If the TRIC instruction is enabled, then it is determined if the initial value set by the run-time-instrumentation controls has been changed. If the initial value set by the run-time-instrumentation controls has been changed, then a condition code is set to a first value. | 2013-09-19 |
20130246749 | DATA PROCESSOR TO PROCESS DATA - A data processor includes a first register file including registers, a second register file including resisters, a number of which is larger than that of the registers of the first register file, an instruction decoder and an operation unit. The instruction decoder decodes an instruction described in first and second instruction formats. The first instruction format includes a first register-addressing field for designating the first register file. The second instruction format includes a second register-addressing field for designating the second register file, a size of which is larger than that of the first register-addressing field. The operation unit executes an instruction described in the first and second instruction formats using operand data stored in the first and second register files, respectively, based on the instruction decoder, and executes operations in parallel, a number of which is determined by a certain field included in the second instruction format. | 2013-09-19 |
20130246750 | CONFIGURABLE PIPELINE BASED ON ERROR DETECTION MODE IN A DATA PROCESSING SYSTEM - A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected. | 2013-09-19 |
20130246751 | VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 2013-09-19 |
20130246752 | VECTOR FIND ELEMENT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 2013-09-19 |
20130246753 | VECTOR STRING RANGE COMPARE - Processing of character data is facilitated. A Vector String Range Compare instruction is provided that compares each element of a vector with a range of values based on a set of controls to determine if there is a match. An index associated with the matched element or a mask representing the matched element is stored in a target vector register. Further, the same instruction, the Vector String Range Compare instruction, also searches a selected vector for null elements, also referred to as zero elements. | 2013-09-19 |
20130246754 | RUN-TIME INSTRUMENTATION INDIRECT SAMPLING BY ADDRESS - Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by address. An aspect of the invention includes reading sample-point addresses from a sample-point address array, and comparing, by a processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor. A sample point is recognized upon execution of the instruction associated with the address matching one of the sample-point addresses. Run-time instrumentation information is obtained from the sample point. The run-time instrumentation information is stored in a run-time instrumentation program buffer as a reporting group. | 2013-09-19 |
20130246755 | RUN-TIME INSTRUMENTATION REPORTING - Embodiments of the invention relate to run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records. | 2013-09-19 |
20130246756 | HARDWARE PROTOCOL STACK - Disclosed is a hardware protocol stack, where header information of analysis-subjected protocol is stored in a register unit, comparison is made whether information recorded in the header of inputted frame mutually matches header information stored in the register unit, and data is extracted as a result of the comparison. | 2013-09-19 |
20130246757 | VECTOR FIND ELEMENT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Equal instruction is provided that compares data of multiple vectors for equality and provides an indication of equality, if equality exists. An index associated with the equal element is stored in a target vector register. Further, the same instruction, the Find Element Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 2013-09-19 |
20130246758 | VECTOR STRING RANGE COMPARE - Processing of character data is facilitated. A Vector String Range Compare instruction is provided that compares each element of a vector with a range of values based on a set of controls to determine if there is a match. An index associated with the matched element or a mask representing the matched element is stored in a target vector register. Further, the same instruction, the Vector String Range Compare instruction, also searches a selected vector for null elements, also referred to as zero elements. | 2013-09-19 |
20130246759 | VECTOR FIND ELEMENT NOT EQUAL INSTRUCTION - Processing of character data is facilitated. A Find Element Not Equal instruction is provided that compares data of multiple vectors for inequality and provides an indication of inequality, if inequality exists. An index associated with the unequal element is stored in a target vector register. Further, the same instruction, the Find Element Not Equal instruction, also searches a selected vector for null elements, also referred to as zero elements. A result of the instruction is dependent on whether the null search is provided, or just the compare. | 2013-09-19 |
20130246760 | CONDITIONAL IMMEDIATE VALUE LOADING INSTRUCTIONS - A data processor comprising a plurality of registers, and instruction execution circuitry having an associated instruction set, wherein the instruction set includes an instruction specifying at least a mask operand, a register operand and an immediate value operand, and the instruction execution circuitry, in response to an instance of the instruction, determines a Boolean value based on the mask operand and sets a respective one of a plurality of registers specified by the register operand of the instance to a value of the immediate value operand if the Boolean value is true. The instruction execution circuitry, in response to the instance of the instruction, may set the respective one of the plurality of registers specified by the register operand of the instance to zero if the Boolean value is false. | 2013-09-19 |
20130246761 | REGISTER SHARING IN AN EXTENDED PROCESSOR ARCHITECTURE - Systems and methods are disclosed for sharing one or more registers in an extended processor architecture. The method comprises executing a first thread and a second thread on a processor core supported by an extended register file, wherein one or more registers in the extended register file are accessible by said first and second threads; loading first data for use by the first thread into a first set of physical registers mapped to a first set of logical registers associated with the first thread; and providing the first data for use by the second thread by maintaining the first data in the first set of physical registers and mapping set first set of physical registers to a second set of logical registers associated with the second thread. | 2013-09-19 |
20130246762 | INSTRUCTION TO LOAD DATA UP TO A DYNAMICALLY DETERMINED MEMORY BOUNDARY - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary is dynamically determined based on a specified type of boundary and one or more characteristics of the processor executing the instruction, such as cache line size or page size used by the processor. | 2013-09-19 |
20130246763 | INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY - A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined. | 2013-09-19 |
20130246764 | INSTRUCTION TO LOAD DATA UP TO A SPECIFIED MEMORY BOUNDARY INDICATED BY THE INSTRUCTION - A Load to Block Boundary instruction is provided that loads a variable number of bytes of data into a register while ensuring that a specified memory boundary is not crossed. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary. | 2013-09-19 |
20130246765 | DATA PROCESSOR - For efficient issue of a superscalar instruction a circuit is employed which retrieves an instruction of each instruction code type other than a prefix based on a determination result of decoders for determining instruction code type, adds the immediately preceding instruction to the retrieved instruction, and outputs the resultant. When an instruction of a target code type is detected in a plurality of instruction units to be searched, the circuit outputs the detected instruction code and the immediately preceding instruction other than the target code type as prefix code candidates. When an instruction of a target code type cannot be detected at the rear end of the instruction units, the circuit outputs the instruction at the rear end as a prefix code candidate. When an instruction of a target code type is detected at the head in the instruction code search, the circuit outputs the instruction code at the head. | 2013-09-19 |
20130246766 | TRANSFORMING NON-CONTIGUOUS INSTRUCTION SPECIFIERS TO CONTIGUOUS INSTRUCTION SPECIFIERS - Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture. | 2013-09-19 |
20130246767 | INSTRUCTION TO COMPUTE THE DISTANCE TO A SPECIFIED MEMORY BOUNDARY - A Load Count to Block Boundary instruction is provided that provides a distance from a specified memory address to a specified memory boundary. The memory boundary is a boundary that is not to be crossed in loading data. The boundary may be specified a number of ways, including, but not limited to, a variable value in the instruction text, a fixed instruction text value encoded in the opcode, or a register based boundary; or it may be dynamically determined. | 2013-09-19 |
20130246768 | TRANSFORMING NON-CONTIGUOUS INSTRUCTION SPECIFIERS TO CONTIGUOUS INSTRUCTION SPECIFIERS - Emulation of instructions that include non-contiguous specifiers is facilitated. A non-contiguous specifier specifies a resource of an instruction, such as a register, using multiple fields of the instruction. For example, multiple fields of the instruction (e.g., two fields) include bits that together designate a particular register to be used by the instruction. Non-contiguous specifiers of instructions defined in one computer system architecture are transformed to contiguous specifiers usable by instructions defined in another computer system architecture. The instructions defined in the another computer system architecture emulate the instructions defined for the one computer system architecture. | 2013-09-19 |
20130246769 | RUN-TIME INSTRUMENTATION MONITORING FOR PROCESSOR CHARACTERISTIC CHANGES - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 2013-09-19 |
20130246770 | CONTROLLING OPERATION OF A RUN-TIME INSTRUMENTATION FACILITY FROM A LESSER-PRIVILEGED STATE - Embodiments of the invention relate to enabling and disabling execution of a run-time instrumentation facility. An instruction for execution by the processor in a lesser privileged state is fetched by the processor. It is determined, by the processor, that the run-time instrumentation facility permits execution of the instruction in the lesser-privileged state and that controls associated with the run-time instrumentation facility are valid. The run-time instrumentation facility is disabled based on the instruction being a run-time instrumentation facility off (RIOFF) instruction. The disabling includes updating a bit in a program status word (PSW) of the processor to indicate that run-time instrumentation data should not be captured by the processor. The run-time instrumentation facility is enabled based on the instruction being a run-time instrumentation facility on (RION) instruction. The enabling includes updating the bit in the PSW to indicate that run-time instrumentation data should be captured by the processor. | 2013-09-19 |
20130246771 | RUN-TIME INSTRUMENTATION MONITORING OF PROCESSOR CHARACTERISTICS - Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor. | 2013-09-19 |
20130246772 | RUN-TIME INSTRUMENTATION INDIRECT SAMPLING BY INSTRUCTION OPERATION CODE - Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by instruction operation code. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by instruction operation code. The method includes reading sample-point instruction operation codes from a sample-point instruction array, and comparing, by a processor, the sample-point instruction operation codes to an operation code of an instruction from an instruction stream executing on the processor. The method also includes recognizing a sample point upon execution of the instruction with the operation code matching one of the sample-point instruction operation codes. The run-time instrumentation information is obtained from the sample point. The method further includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group. | 2013-09-19 |
20130246773 | HARDWARE BASED RUN-TIME INSTRUMENTATION FACILITY FOR MANAGED RUN-TIMES - Embodiments of the invention relate to performing run-time instrumentation. Run-time instrumentation is captured, by a processor, based on an instruction stream of instructions of an application program executing on the processor. The capturing includes storing the run-time instrumentation data in a collection buffer of the processor. A run-time instrumentation sample point trigger is detected by the processor. Contents of the collection buffer are copied into a program buffer as a reporting group based on detecting the run-time instrumentation sample point trigger. The program buffer is located in main storage in an address space that is accessible by the application program. | 2013-09-19 |
20130246774 | RUN-TIME INSTRUMENTATION SAMPLING IN TRANSACTIONAL-EXECUTION MODE - Embodiments of the invention relate to implementing run-time instrumentation indirect sampling by address. An aspect of the invention includes a method for implementing run-time instrumentation indirect sampling by address. The method includes reading sample-point addresses from a sample-point address array, and comparing, by a processor, the sample-point addresses to an address associated with an instruction from an instruction stream executing on the processor. The method further includes recognizing a sample point upon execution of the instruction associated with the address matching one of the sample-point addresses. Run-time instrumentation information is obtained from the sample point. The method also includes storing the run-time instrumentation information in a run-time instrumentation program buffer as a reporting group. | 2013-09-19 |
20130246775 | RUN-TIME INSTRUMENTATION SAMPLING IN TRANSACTIONAL-EXECUTION MODE - Embodiments of the invention relate to implementing run-time instrumentation sampling in transactional-execution mode. An aspect of the invention includes a method for implementing run-time instrumentation sampling in transactional-execution mode. The method includes determining, by a processor, that the processor is configured to execute instructions of an instruction stream in a transactional-execution mode, the instructions defining a transaction. The method also includes interlocking completion of storage operations of the instructions to prevent instruction-directed storage until completion of the transaction. The method further includes recognizing a sample point during execution of the instructions while in the transactional-execution mode. The method additionally includes run-time-instrumentation-directed storing, upon successful completion of the transaction, run-time instrumentation information obtained at the sample point. | 2013-09-19 |
20130246776 | RUN-TIME INSTRUMENTATION REPORTING - Embodiments of the invention relate to run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records. | 2013-09-19 |
20130246777 | INFORMATION PROCESSOR AND RECORDING MEDIUM - A computer-readable recording medium has a program recorded therein. The program includes a pre-certified file to be authenticated, an authentication information file, and a default configuration file. The program is subjected to authentication based on the comparison of authentication information generated from the file to be authenticated and the authentication information of the authentication information file when the program is installed in an information processor. The program instructs a central processing unit to execute: when a configuration file of a predetermined filename exists in the information processor, registering configuration data written in the configuration file with a first storage area different from a second storage area in which the program is stored; determining whether the configuration data are stored in the first storage area; and when it is determined that the configuration data are stored in the first storage area, reflecting the configuration data in the operation of the program. | 2013-09-19 |
20130246778 | DYNAMICALLY SCALABLE APPLICATION INFRASTRUCTURE - The invention relates to a method for processing information in an apparatus having one or more interfaces to one or more peripheral components, said method comprising obtaining information about resources of the one or more peripheral components from at least one peripheral component, forming a policy basing at least partly on the information about the resources of the at least one peripheral component, forming a cost function basing at least partly on the information about the resources of the at least one peripheral component, determining an entry combination of the resources forming the cost function such that the entry combination is at least in part compliant with the policy and changing configuration of the apparatus to at least partly comply with the determined entry combination. | 2013-09-19 |
20130246779 | Calling Firmware Runtime Services of Basic Input Output System - Approaches for calling firmware runtime services of a basic input/output system. A special globally unique identifier and a name are sent to PURE virtual variable stores by an operating system. The PURE virtual variable stores identify the special globally unique identifier and the name, for example, by checking in the PURE virtual variable stores to ascertain if the special identifier and the name correspond to a firmware runtime service of the basic input/output system. A corresponding firmware runtime service of the basic input/output system is called. The firmware runtime service of the basic input output system then executes. | 2013-09-19 |
20130246780 | Instrumenting Configuration and System Settings - Described are systems and methods for instrumenting configuration and system settings based on targeting configuration settings at dynamically populated groups, groups with varied membership, and objects defined in a class. The systems and methods provide for attributing a configuration setting or policy to one or more objects and then targeting the object at one or more scopes. | 2013-09-19 |
20130246781 | MULTI-CORE SYSTEM ENERGY CONSUMPTION OPTIMIZATION - Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the computer system by measuring performance levels and energy usages of the system component under a range of energy settings and utilization rates of the system component. A utilization rate of the system component can be determined based on prediction factors including the execution of a first set of instructions on the computer system. The system component can be configured to execute a second set of instructions after the first set of instructions by selecting an energy setting from the range of energy settings for operating the system component. The energy setting can be selected based on the energy usage benchmark and the determined utilization rate. | 2013-09-19 |
20130246782 | UTILIZING SIGNATURES TO DISCOVER AND MANAGE DERELICT ASSETS OF AN INFORMATION TECHNOLOGY ENVIRONMENT - A set of asset signatures can be analyzed. Each asset signature can be associated with an asset. Derelict assets can be discovered based on the asset signatures. The asset can represent a fundamental structural unit of an information technology (IT) environment. A multi-stage screening process can be performed to discover derelict assets. In a first stage, assets having a normal state are able to be changed to a suspect state based on results of analyzing the corresponding asset signature. In a second stage, assets having a suspect state are able to be selectively changed in state to a normal state or to a derelict state. An asset management system record can be maintained for each of the set of assets. Each record of the asset management system can be a configuration item (CI), which indicates whether each of the set of assets is in a normal state, a suspect state, or a derelict state. The asset management system can periodically reclaim resources consumed by derelict assets. | 2013-09-19 |
20130246783 | GENERATING PROTOCOL-SPECIFIC KEYS FOR A MIXED COMMUNICATION NETWORK - Security keys are typically needed to communicate with various network communication protocols of a mixed communication network. Herein, a protocol-specific key for a particular network communication protocol is generated based upon a result of a hash operation that includes a network key associated with the mixed communication network and information corresponding to the particular network communication protocol. Interoperability of multiple devices in the mixed communication network is made possible when the multiple devices generate (i.e. derive) protocol-specific keys using the same network key and common information corresponding to particular network communication protocols. | 2013-09-19 |
20130246784 | WIRELESS ACCESS POINT SECURITY FOR MULTI-HOP NETWORKS - Security in wireless communication networks that employ relay stations to facilitate communications between base stations and mobile stations is enhanced. In one embodiment, resource information provided to one or more relay stations from a base station or another relay station is encrypted prior to being delivered to the one or more relay stations. Only authorized relay stations are allocated an appropriate key necessary to decrypt the resource information. As such, only appropriate relay stations are able to access and use the resource information to effect communications directly or indirectly between the base stations and the mobile stations. In certain embodiments, the resource information is delivered between the various base and relay stations using either unicast or multicast delivery techniques. | 2013-09-19 |
20130246785 | METHOD FOR SECURING MESSAGES - There is provided a method for secure communications. The method comprises obtaining a broadcast message, computing a signature for said broadcast message using a private key, and sending a transmission to a communication device. The private key is associated with a certificate and the transmission comprises the signature. | 2013-09-19 |
20130246786 | CLIENT DEVICE AND LOCAL STATION WITH DIGITAL RIGHTS MANAGEMENT AND METHODS FOR USE THEREWITH - A current version certificate is stored that includes a corresponding current version identifier. A current instance certificate is received from the certificate authority, wherein the current instance certificate includes the current version identifier of the current version certificate and a current instance public key corresponding to the current instance private key. The current instance certificate is sent to a local station, during a registration with the local station. A request is generated and sent to the local station. First encrypted data is received from the local station, wherein the first encrypted data includes a content key that is encrypted via the current instance public key. | 2013-09-19 |
20130246787 | MESSAGE STORAGE AND TRANSFER SYSTEM - An electronic content exchange system includes a communications medium and at least two storage media. Each storage media includes an interface configured to send and receive messages, a memory storing a current content, a respective unique identifier, and a log of content transfers; and a controller. The controller receives a content transfer message including at least a message content to be transferred, and executes a Transfer-in process to increase the current content by the message content to be transferred and record information of the transfer in the log. The controller receives, via the interface, a content transfer request message including at least a message content to be transferred, and executes a Transfer-out process to generate and send a content transfer message including the message content to be transferred, decreasing the current content by the message content to be transferred; and recording information of the transfer in the log. | 2013-09-19 |
20130246788 | Efficient Delivery of Structured Data Items - A configurable device and a method associated with the device is described, the device including. a cryptographic engine, a seed receiver operative to receive a seed, a part seed generator operative to receive a part number, and the seed from the seed receiver, and to generate a part seed based, at least in part, on the seed and the part number, a part generator operative to receive the part seed produced by the part seed generator to produce a crypto data item part based, at least in part, on the part seed, and a cryptosystem integrator operative to integrate the produced crypto data item part into the cryptographic engine, thereby producing a crypto product wherein the cryptographic engine uses the produced crypto product as an auxiliary input into a crypto graphic algorithm used to protect the digital content. Related methods, systems, and apparatus is also described. | 2013-09-19 |
20130246789 | METHOD OF SECURING TRANSMISSION DATA - A method is provided for securing transmission data between an upload device and a download device. The upload device is configured to generate a first matrix, a second matrix and a re-encryption vector, to encrypt a plaintext data file using the first matrix to obtain a ciphertext data file, to transmit the ciphertext data file and the re-encryption vector to a server, and to transmit the second matrix to the download device. The server is configured to re-encrypt the ciphertext data file using the re-encryption vector to obtain a re-encrypted data file that can be decrypted using the second matrix to obtain a decrypted data file, and to allow the download device to download the re-encrypted data file therefrom. | 2013-09-19 |
20130246790 | STORAGE METHOD, SYSTEM AND APPARATUS - The present invention discloses a storage method, system and apparatus. The method comprises: encrypting data with a storage key to obtain encrypted data; encrypting the storage key with two different encryption methods to generate a personal key and a data key, respectively, wherein the personal key can be decrypted with a key from the user who owns the data to obtain the storage key, and the data key can be decrypted with the unencrypted data to obtain the storage key; saving the encrypted data, personal key and data key in a server. The technical scheme of the present invention can prevent saving duplicate files while ensuring that the unencrypted data cannot be accessed by any other users and storage service providers. | 2013-09-19 |
20130246791 | PRIVACY-PRESERVING PUBLISH-SUBSCRIBE PROTOCOL IN A CLOUD-ASSISTED BROADCAST MODEL - A method and system for providing privacy in a publish-subscribe protocol is provided. A server receives from a third party a topic-based key associated with a tree structure having a pseudonym of a topic as a root and at least one client as a leaf. The server encrypts a key associated with a conditional oblivious transfer protocol using the topic-based key. The server encrypts an item with the key associated with the conditional oblivious transfer protocol. The server transmits the encrypted key and the encrypted item to a plurality of clients. The encrypted item is decryptable by the at least one client with the key associated with the conditional oblivious transfer protocol when the key associated with the conditional oblivious transfer protocol is decryptable with an interest-based key associated with a tree structure having a pseudonym of an interest as a root and the at least one client as a leaf. | 2013-09-19 |
20130246792 | KEY CENTRIC IDENTITY - Aspects of the disclosure provide a method. The method includes generating an identification based on a public key of an asymmetric key pair for a device, including the identification into an information unit to identify the device as a source of the information unit and transmitting the information unit. | 2013-09-19 |