38th week of 2013 patent applcation highlights part 34 |
Patent application number | Title | Published |
20130242585 | LIGHT MODULE OF A LIGHTING DEVICE OF A MOTOR VEHICLE - A light module of a lighting device comprises one passing-light sub-module for production of a dimmed-light distribution below a horizontal “light/dark” boundary, one high-beam sub-module for production of a light distribution above the boundary, a common projection-lens system for production of an overall light distribution, and one element deflecting a course of light beams of the sub-module(s) before it falls on the system. To realize the smallest system and a reduction of non-homogeneities in the overall light distribution in a region of the boundary, a majority of the light beams of the high-beam sub-module falls on a common segment of the system as a majority of the light beams of the passing-light sub-module, a smaller portion of the light beams of the high-beam sub-module falls on another segment of the system, and the system exhibits a deflector that deflects at least a portion of the light beams falling on the other segment downward. | 2013-09-19 |
20130242586 | VEHICLE EXTERIOR MIRROR SYSTEM WITH LIGHT MODULE - A lighted exterior rearview mirror system for a vehicle includes a lighted exterior rearview mirror assembly and a light module disposed thereat. The light module includes a plurality of illumination sources operable to emit light in a generally forwardly direction with respect to the vehicle. The light module includes at least one turn signal indicator illumination source that, at least responsive to an activation of a turn signal by the driver of the equipped vehicle, is operable to emit light in a generally sidewardly and/or rearwardly direction with respect to the vehicle. The light module includes a light piping element and the turn signal indicator illumination source is disposed at an inboard end of the light piping element and the light piping element guides light emanating from the turn signal indicator illumination source along the light piping element and out an outboard end of the light piping element. | 2013-09-19 |
20130242587 | OUTER CASING FOR VEHICLE LAMP, VEHICLE LAMP AND MANUFACTURING METHOD FOR THE SAME - An outer casing for vehicle lamps, a vehicle lamp and a manufacturing method for the outer casing and the vehicle lamp can include an outer lens having a rib located at a peripheral portion thereof and a casing having a supporting portion located so as to face the rib formed in a ring shape. The rib of the lens can include an end portion formed in a convex shape in a width direction thereof in accordance with a light energy distribution of a laser welder, and can be attached to the casing with confidence by utilizing the energy distribution. Thus, the vehicle lamp using the outer casing can incorporate various lamps with an airtight structure and an adequate mechanical strength while preventing misalignment between the outer lens and the casing, and the manufacturing method can provide the outer casing using similar manufacture equipment as compared with conventional methods. | 2013-09-19 |
20130242588 | LIGHTING DEVICE - A lighting device includes a housing having first and second housing parts to define a receiving space. The housing parts are inwardly recessed and converge into marginal regions, respectively. Arranged in the receiving space is a light conductor. A plastic film strip is arranged between edges of the housing parts and is transparent for light emitted by the light conductor, with the emitted light being projected into one end face of the film strip and extracted from another end face of the film strip. The film strip is sized to terminate flush with the housing parts. | 2013-09-19 |
20130242589 | VEHICLE HEADLAMP - The present invention provides a semiconductor-type light source | 2013-09-19 |
20130242590 | VEHICLE HEADLIGHT - An arrangement of headlight lenses for a vehicle headlight, each headlight lens having a monolithic body of transparent material, which monolithic body includes at least one light entry face, a light passage section and at least one optically operative light exit face. | 2013-09-19 |
20130242591 | DISPLAY SCREEN - The invention relates to a display screen comprising: a housing forming an enclosure; a display surface on the front face of the housing; a printed circuit board arranged inside the housing; and at least one light-emitting diode that forms a back-lighting source for the display surface and is arranged on a face of the printed circuit board. The display screen is characterised in that the printed circuit board is a single-face printed circuit board, the display screen comprises a thermoconductive plate arranged against the face of the printed circuit board opposite the one carrying the at least one light-emitting diode, and the display screen also comprises a second double-face printed circuit board that has a smaller surface than the single-face printed circuit board, is connected to said single-face printed circuit board by at least one electrical connection, and carries at least one element for controlling the back-lighting of the display surface. | 2013-09-19 |
20130242592 | HEAT CONDUCTING LAMP BASE AND LED LAMP INCLUDING THE SAME - A heat conducting lamp base ( | 2013-09-19 |
20130242593 | Sighting Device with Selectable Pin Lighting - A selective light assembly for a sighting device associated with an archer bow or the like has a plurality of light collectors, such as optical fibers, that serve as sight points. An artificial light source is adapted for projecting radiant energy in a direction toward the light collectors and a base member is operatively associated with the light source. The base member has at least one window adapted for alignment with at least one of the light collectors. At least one of the light source and base member is adjustable between first and second positions, such that the radiant energy projects through the base member and onto first and second light collectors for selectively illuminating a sight dot associated with one of the light collectors. | 2013-09-19 |
20130242594 | LIGHT EMITTING DEVICE - A light emitting device capable of adjusting height difference between the light emitters and optical waveguides individually and easily with high accuracy is realized. The light emitting device comprises multiple light emitters; an optical multiplexer comprising the openings of multiple optical waveguides at the incidence end for light from the multiple light emitters and the opening of an optical waveguide combining said multiple optical waveguides at the light exit end; and multiple drivers driving said multiple light emitters, respectively, along the tilt direction of a surface tilted at a given angle with respect to the surface on which said optical waveguides are formed, wherein said light emitters are provided at an angle that makes the central axes of light from said light emitters in the light emission direction parallel to the surface on which said optical waveguides are formed. | 2013-09-19 |
20130242595 | SOLID STATE LIGHT SOURCE WITH HYBRID OPTICAL AND ELECTRICAL INTENSITY CONTROL - A solid state illumination system is provided as a replacement for conventional arc light, metal halide and Xenon light sources for applications in microscopy, fluorescence microscopy, and endoscopy. The illumination system includes hybrid optical and electrical control of output intensity in which the light output of one or more of the light sources is attenuated optically such that it is not necessary to reduce the electrical drive power/current of the LEDs at a level where the spectral power distribution is variable. One or more fixed, selectable, or variable neutral density filters is interposed in the output beam of one or more sources to achieve optical attenuation of the light output. The hybrid optical and electrical control of output intensity allows greater dynamic range of intensity to be achieved than could be achieved with electrical control of the LEDs alone while maintaining the desired spectral power distribution. | 2013-09-19 |
20130242596 | FRONTLIGHT UNIT FOR ENHANCING ILLUMINATION OF A REFLECTIVE DISPLAY - The frontlight illumination system is intended for enhancing illumination of a reflective display having pixels arranged in a matrix pattern and using monochromatic laser lights as light sources. The unit contains a network of light-distributing planar ridge waveguides with holograms arranged in a matrix pattern that corresponds to the matrix pattern of the reflective display. The light-distributing holograms of the system are formed on opposite sides of each core of respective light-distributing planar ridge waveguides. Neighboring holograms located on opposite sides of the core are combined into pairs and are arranged on each core in positions at which they interact with a predetermined phase shift that doubles the intensity of light directed to the reflective display and extinguishes light directed to the external surface. | 2013-09-19 |
20130242597 | ILLUMINATION APPARATUS - An illumination apparatus, comprising at least one light emitting source embedded in a waveguide material is disclosed. The waveguide material is capable of propagating light generated by light emitting source(s), such that at least a portion of the light is diffused within the waveguide material and exits through at least a portion of its surface. | 2013-09-19 |
20130242598 | OPTICAL SHEET, BACKLIGHT UNIT USING THE SAME AND METHOD FOR PRODUCING THE SAME - Provided is an optical sheet capable of exhibiting superior optical function, and a high-quality backlight unit using the same. The optical sheet includes a transparent substrate layer, and an optical function layer having a plurality of fibers protruding from one surface side of the substrate layer. The optical function layer preferably includes an adhesive portion joining the plurality of fibers to the substrate layer. The adhesive portion is preferably laminated entirely on the one surface side of the substrate layer. The adhesive portion is preferably formed from acryl emulsion adhesives. The refractive index of the fiber is preferably no less than 1.3 and no greater than 1.8. The density of the fiber per unit area in the plane direction of the substrate layer is preferably no less than 100 fibers/cm | 2013-09-19 |
20130242599 | Lighting Device Comprising A Light Guide And A Support - A lighting device ( | 2013-09-19 |
20130242600 | Backlight Structures and Backlight Assemblies for Electronic Device Displays - An electronic device may have a liquid crystal display with backlight structures. The backlight structures may produce backlight that passes through the display layers in the display. The display layers may include a layer of liquid crystal material interposed between a color filter layer and a thin-film transistor layer. The backlight structures may include a light guide plate. A plurality of light-emitting diodes mounted on a flexible printed circuit may be coupled to an edge of the light guide plate. The flexible printed circuit may be curled into a spring element to bias the light-emitting diodes against the edge of the light guide plate. A plurality of gaps may be formed in the flexible printed circuit and may be used to separate and mechanically decouple adjacent light-emitting diodes. Individual light-emitting diodes may independently register to the light guide plate to maximize optical efficiency in the display. | 2013-09-19 |
20130242601 | LIGHT GUIDE AND KEYBOARD BACKLIGHT - A backlit system comprises a base panel, a plurality of keys disposed on the base panel, a substantially planar light guide panel disposed between the base panel and the plurality of keys, at least one light source disposed on the light guide panel, and at least one light management feature disposed on the light guide panel. The at least one light management feature is configured to at least partially reflect incident light within the light guide panel. | 2013-09-19 |
20130242602 | LIGHT GUIDE PLATE AND BACKLIGHT MODULE - A light guide plate and a backlight module are described. The light guide plate includes a main body and a plurality of stripe microstructures. The main body includes a light incidence surface, a light-emitting surface and a light reflective surface. The light-emitting surface is opposite to the light reflective surface, and the light incidence surface is connected between the light-emitting surface and the light reflective surface. The light-emitting surface includes a microstructure region adjacent to the light incidence surface. The stripe microstructures are arranged in the microstructure region, and parallel to a normal line of the light incidence surface. | 2013-09-19 |
20130242603 | LIGHTING DEVICE - A lighting device includes a housing having first and second housing parts to define a first receiving space there between, and a third housing part arranged on the second housing part to define an open gap. The third housing part defines with the second housing part a second receiving space in which a first light conductor is arranged. A plastic film strip is arranged between edges of the first and second housing parts and is transparent for light emitted by the first light conductor, with the emitted light being projected into one end face of the film strip and extracted from another end face of the film strip. The film strip is sized to terminate flush with the first and second housing parts. Arranged in the second receiving space is a second light conductor which emits light through the gap. | 2013-09-19 |
20130242604 | LIGHT UNIT - A light unit is provided. The light unit includes a PCB mounted with a plurality of LEDs, and a light guide member having a plurality of reception grooves piercing therethrough and receiving the LEDs, wherein the light guide member includes one surface and the other surface opposite to the one surface, and the one surface of the light guide member is further coated with the resin material. The reception grooves are formed in the light guide member and are filled with a fluid resin material, thus preventing the damage to the LED caused by the difference between the thermal expansion rates of the components such as the light guide member, the reflection film and the PCB. | 2013-09-19 |
20130242605 | OPTICAL DIFFUSING FILM AND A LIQUID CRYSTAL DISPLAY BACKLIGHT USING THE SAME - An optical diffusing film and a LCD backlight using the same are provided. The optical diffusing film comprises a transparent substrate made of an optically transparent material with a refractive index of 1.4 to 1.8, and a diffusing coating with a refractive index of 1.4 to 1.7 disposed on an upper surface of the transparent substrate, wherein diffusing particles with a refractive index of 1.4 to 1.7 are distributed in the diffusing coating, and the diffusing particles are in close contact with each other, the diffusing coating has a thickness of ½ to ⅔ of the largest particle size of the diffusing particles, and the coating density of the diffusing particles is 10 | 2013-09-19 |
20130242606 | PLANE ILLUMINATION APPARATUS AND BACKLIGHT APPARATUS - A plane illumination apparatus has an optical device, an irradiation unit to irradiate the coherent light beams to the optical device. The irradiation unit makes the coherent light beams scan the surface of the optical device by changing propagation directions of the coherent light beams, the light guide plate comprises a light take-out portion specific zone to take out coherent light beams to outside while making coherent light beams propagate between a first end face on which coherent light beams from the optical device are incident and a second end face that is provided to face the first end face, and the specific zone is provided inside the light take-out portion or along the first end face, or along the second end face. | 2013-09-19 |
20130242607 | BACKLIGHT MODULE - A backlight module is provided. The backlight module includes a light source and a group of replaceable optical elements. The light source emits a first light. The replaceable optical elements receive the first light and backlight light is then excited, wherein the replaceable optical elements include a first replaceable optical element and a second replaceable optical element. The first replaceable optical element has a first phosphor. The first phosphor can be excited by light and emits second light. The second replaceable optical element has a second phosphor. The second phosphor can be excited by light and emits third light. | 2013-09-19 |
20130242608 | Assembled Mold Frame and Backlight Module Comprising Same - The present invention provides an assembled mold frame and a backlight module including the mold frame. The assembled mold frame includes two opposite first side frames, two opposite second side frames, and four L-shaped connection frames connecting between the first side frames and the second side frames. The first and second side frames are of a linear form. Each first side frame includes a single first side frame unit or a plurality of interconnected first side frame units. Each second side frame includes a single second side frame unit or a plurality of interconnected second side frame units. Each connection frame has two ends that are respectively mating and jointed to one of the first side frame units and one of the second side frame units. The four connection frames, the two first side frames, and the two second side frames are sequentially jointed to form an enclosed rectangular frame. | 2013-09-19 |
20130242609 | SURFACE LIGHT SOURCE DEVICE - A surface light source device in which an optical sheet and light guide plate can be firmly fixed at low cost. The surface light source device has a light source, a frame that includes an accommodation part and at least a part of the accommodation part is surrounded by a sidewall, a light guide plate accommodated in the accommodation part, at least one optical sheet stacked on the light guide plate. A part of the light guide plate and a part of the optical sheet are fixed to the frame by filling a gap between a part of an outer surface of the light guide plate and an inner surface of the sidewall with an adhesive resin. | 2013-09-19 |
20130242610 | LIGHT GUIDE BODY, LIGHTING DEVICE HAVING LIGHT GUIDE BODY, AND DISPLAY DEVICE - A light guiding element has a first principal surface, a second principal surface which opposes the first principal surface, a first lateral surface which intersects with the first principal surface and the second principal surface, and a second lateral surface which opposes the first lateral surface. The light guiding element allows light incoming from the first lateral surface to propagate between the first principal surface and the second principal surface. The light guiding element includes a portion in which a refractive index varies substantially continuously from the first principal surface toward the second principal surface. | 2013-09-19 |
20130242611 | Side-Edge Backlight Module - The present invention provides a side-edge backlight module, which includes a backlight source that emits blue light, a light guide board, and a fluorescent powder layer. The light guide board includes a light incidence surface. The backlight source is set corresponding to the light incidence surface and is arranged at one side of the light guide board. The fluorescent powder layer is mounted by a bonding layer to the light incidence surface of the light guide board. The bonding layer has an end face that is in contact engagement with the fluorescent powder layer and includes a smooth continuous curved surface. The fluorescent powder layer is set along the curved surface. The fluorescent powder layer is excited by the blue light emitting from the backlight source to generate white light. The white light transmits through the bonding layer to enter the light guide board. | 2013-09-19 |
20130242612 | LIGHT GUIDE PANEL AND BACKLIGHT UNIT HAVING THE SAME - A light guide panel (LGP) is provided, which includes a front surface, a rear surface, and four edge surfaces, in which rays of light emitted from light sources are introduced through at least one of the four edge surfaces, a plurality of lenticular patterns formed on one of the front surface and the rear surface, and a plurality of light emitting patterns which induce the rays of light emitted from the light sources toward the front surface. The plurality of light emitting patterns are integrally formed with the plurality of lenticular patterns. | 2013-09-19 |
20130242613 | SURFACE LIGHT SOURCE DEVICE - A variation in luminance is reduced near a light source without decreasing intensity of a light exit pattern. A light source is disposed and a light exit pattern is formed. The light exit pattern reflects light guided in a light guide plate and outputs the light. In inclined angles of tangents of the light exit patterns in a section passing through a center axis of the light exit pattern, a largest inclined angle of the tangent is defined as a maximum inclined angle of the light exit pattern. At this time, in the light exit pattern provided in the light guide plate, the maximum inclined angle is decreased with increasing distance from a light incident surface in a region near the light incident surface, and the maximum inclined angle is decreased or kept constant with increasing distance from the light incident surface in a region distant from the region near the light incident surface. | 2013-09-19 |
20130242614 | SURFACE LIGHT SOURCE DEVICE - A surface light source device has a point light source disposed opposite a light incident surface of a light guide plate. The light guide plate includes a light introduction part, and a light guide plate body having a thickness smaller than a maximum thickness of the light introduction part. The light introduction part includes an inclined surface inclined from a surface in a portion having a thickness larger than the thickness of the light guide plate body toward an end of the surface of the light guide plate body. The light guide plate body has a light exit pattern for reflecting the light in the light guide plate body to output the light from a light exit surface. In a region close to the point light source of the light guide plate body, the thickness of the light guide plate body increases gradually with distance from the point light source. | 2013-09-19 |
20130242615 | Water-Proof Light-Emitting Decoration Building Block - A water-proof light-emitting decoration building block is connected to the top or bottom end of connected conventional light-emitting basic interlocking bricks and includes a light-transmittable brick, multiple first one-way conductive members and multiple second one-way conductive members. The brick has a top end and a bottom end, one of the top and bottom ends has a water-proof decoration portion and the other end has multiple connection portions. Each of the first one-way conductive members has a conductive rod. The conductive rods of the first one-way conductive members and the second one-way conductive members are respectively located in the connection portions. The water-proof light-emitting decoration building blocks can be connected to the top or bottom end of assembled basic light-emitting interlocking bricks to obtain water-proof and light-emitting features. | 2013-09-19 |
20130242616 | POWER INVERTER FOR FEEDING ELECTRIC ENERGY FROM A DC POWER GENERATOR INTO AN AC GRID WITH TWO POWER LINES - A power inverter includes two input terminals, two output terminals and a resonant converter that includes a high frequency transformer having a primary winding and a secondary winding, at least one high frequency switched semiconductor power switch that connects one end of the primary winding of the high frequency transformer to one of the input terminals to provide a current path through the primary winding to the other one of the input terminals. The power inverter further includes a resonant series circuit having an inductance and a capacitance, and a high frequency rectifier that rectifies a current through the secondary winding, two output lines, and an output converter connected between the output lines of the high frequency rectifier and the two output terminals. | 2013-09-19 |
20130242617 | H-BRIDGE MICRO INVERTER GRID-CONNECTED DEVICE - An H-bridge micro inverter grid-connected device is invented to solve the problem that failure of any photovoltaic panel on the existing solar photovoltaic system cascade can cause efficiency reduction of the whole photovoltaic panel module. The H-bridge micro inverter grid-connected device comprises a single-chip microcomputer controller, a CPLD controller, a MOSFET full-bridge circuit, a high-frequency transformer, a half-bridge rectifying circuit, an SCR full-bridge circuit and a filter circuit, wherein the MOSFET full-bridge circuit is in the full-bridge type, the high-frequency transformer is a single-phase transformer with a central tap, and the SCR full-bridge circuit is applied. The integral structure above is characterized by the decreasing number of components, the reduction of power switches, and the simplification of the control circuits and driving circuits, so as to decrease the number of full-control switch components, improve the system reliability and reduce the system costs. | 2013-09-19 |
20130242618 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The AlGaN/GaN HEMT includes, on an SiC substrate, a laminated compound semiconductor structure and a gate electrode formed on the laminated compound semiconductor structure, wherein a p-type impurity (Mg) and oxygen (O) localize in a lower region of the laminated compound semiconductor structure aligned with the gate electrode, to such a depth as to cause part of a two-dimensional electron gas generated in the laminated compound semiconductor structure to disappear. | 2013-09-19 |
20130242619 | RESET VOLTAGE CIRCUIT FOR A FORWARD POWER CONVERTER - An example method includes controlling a duty ratio of a switch to regulate an output of a forward power converter and storing a first voltage. The first voltage is equal to an input voltage of the forward power converter when the input voltage is at a steady-state value. The method also includes resetting a transformer of the forward power converter when the switch is in an OFF state by setting a voltage across a primary winding of the transformer to the stored first voltage in response to a drop in the input voltage to below the steady-state value. Further included in the method is increasing the duty cycle of the switch to greater than fifty (50) percent in response to the drop in the input voltage to maintain regulation at the output of the forward power converter. | 2013-09-19 |
20130242620 | POWER SUPPLY APPARATUS DRIVING CIRCUIT, POWER SUPPLY APPARATUS DRIVING INTEGRATED CIRCUIT, AND POWER SUPPLY APPARATUS - In a power supply apparatus driving circuit, at startup, an input voltage of a switching power supply is used as a driving power supply, and loss generated in a starting circuit is reduced. The starting circuit and the driving circuit are configured as a single driver. A control IC generates a switching control signal to control a first switching element and a second switching element. A driving circuit in a high breakdown voltage driver IC generates gate drive voltage signals for the first switching element and the second switching element based on the switching control signal inputted from the control IC. A starting circuit supplies the partial voltage of a voltage inputted to a starting power supply terminal, to each of the driving circuit in the high breakdown voltage driver IC and the control IC that is externally provided, and shuts off a switching element after startup. | 2013-09-19 |
20130242621 | PHASE-SHIFTING A SYNCHRONIZATION SIGNAL TO REDUCE ELECTROMAGNETIC INTERFERENCE - A power supply with reduced electromagnetic interference (EMI) is described. This power supply includes cascaded stages with switched-mode power-supply circuits that are switched synchronously during operation by switching signals that have a common fundamental frequency. EMI associated with the power supply is reduced by establishing a phase shift between the switching signals in at least two of the stages. | 2013-09-19 |
20130242622 | METHOD AND APPARATUS FOR STARTING UP - Aspects of the disclosure provide a method. The method includes receiving an input voltage rectified from an alternating current (AC) power supply, detecting a time duration that the input voltage is between a first threshold voltage and a second threshold voltage, determining a line voltage of the AC power supply based on the time duration, and regulating a time for turning on a switch to transfer energy via a transformer based on the detected line voltage. | 2013-09-19 |
20130242623 | POWER CONVERTER AND INTEGRATED DC CHOKE THEREFOR - A power conversion system with multiple parallel connected motor drives including a plurality of rectifiers and a corresponding inverters connected by windings of a single common mode choke. | 2013-09-19 |
20130242624 | POWER MODULE AND POWER CONVERSION APPARATUS - A power module, which is connected to a power source, includes a rectifying unit, a filtering unit and an inverter. The rectifying unit has three legs. The filtering unit is connected to the rectifying unit, and the inverter is connected to the filtering unit. One of the three legs has two switching elements connected in series, and another one of the three legs has two rectifying elements connected in series. In addition, a power conversion apparatus including the power module is also disclosed. | 2013-09-19 |
20130242625 | Adaptive Bipolar Junction Transistor Gain Detection - A power converter that controls a collector current of a bipolar junction transistor (BJT) by controlling the base current to the BJT after having determined the gain of the BJT. A gain detection block determines a gain of the BJT during a first mode. A current calculation block generates a current setting for the base current based on the gain of the BJT determined by the gain detection block during a second mode distinct from the first mode. In some embodiments, the power converter may be included in a LED lamp system. | 2013-09-19 |
20130242626 | DISCHARGE CIRCUITS FOR EMI FILTERS CAPACITORS AND METHODS THEREOF - A discharge circuit for an EMI filter capacitor, wherein the EMI filter capacitor is coupled between input terminals of a switching converter. The discharge circuit has a detecting circuit and a current source. The detecting circuit is configured to detect whether an electrical source is coupled to the input terminals of the switching converter. The current source is coupled between the input terminals of the switching converter and a power supply capacitor, and is configured to provide a power supply voltage across the power supply capacitor. When the electrical source is uncoupled from the input terminals of the switching converter, the EMI filter capacitor is discharged by the current source. | 2013-09-19 |
20130242627 | MONOLITHIC HIGH VOLTAGE MULTIPLIER - High voltage diode-connected gallium nitride high electron mobility transistor structures or Schottky diodes are employed in a network including high-k dielectric capacitors in a solid state, monolithic voltage multiplier. A superjunction formed by vertical p/n junctions in gallium nitride facilitates operation of the high electron mobility transistor structures and Schottky diodes. A design structure for designing, testing or manufacturing an integrated circuit is tangibly embodied in a machine-readable medium and includes elements of a solid state voltage multiplier. | 2013-09-19 |
20130242628 | SOLAR POWER CONDITIONER - A solar power conditioner includes: a synchronous controller; and electric power converters connected in series with each other and arranged at panel groups, respectively. Each electric power converter executes a MPPT control for tracking a maximum power point of an output electric power of the panel group, and converts a voltage and a current of the output electric power of the panel group. The synchronous controller synchronously controls the electric power converters to superimpose converted voltages in series, the converted voltages outputting from the electric power converters, so that the electric power converters output a predetermined pseudo sine wave voltage or a predetermined alternating current voltage. | 2013-09-19 |
20130242629 | ON-TIME COMPENSATION FOR SWITCHING POWER CONVERTERS - An improved discontinuous current mode (DCM) switching power converter that compensates for the effect of dead time. The dead time of the switching power converter is measured during a switching cycle and a baseline on-time for a switch of the switching power converter is determined. The dead time and baseline on-time are used in calculating the desired on-time of the switch during a subsequent switching cycle of the power converter. The desired switch on-time regulates the output voltage to a desired voltage level. The desired switch on-time also maintains the average input current to the power converter in proportion to the input voltage, thereby improving the power factor of the switching power. | 2013-09-19 |
20130242630 | SWITCHING POWER SUPPLY DEVICE - A switching power supply device includes: a chopper circuit that adjusts a DC voltage input through a reactor to a desired DC voltage by performing an on/off operation of a switching element; an inverter circuit that converts an output of the chopper circuit into a desired AC voltage; a first capacitor that is provided on a side of the inverter circuit relative to the switching element; a second capacitor that is provided on a side of the inverter circuit relative to the switching element; and a resistor that is in a resonant loop formed by three constituent elements that are the first capacitor, the second capacitor, and a wiring inductance between the chopper circuit and the inverter circuit, where the resistor is connected in series to the second capacitor and inserted between the DC bus-bars. | 2013-09-19 |
20130242631 | POWER CONVERTER APPARATUS - A power converter apparatus includes a first substrate and a second substrate closely arranged to face each other, switching elements mounted on respective mounting surfaces of the first and second substrates, a primary and a secondary bus bars extending between the first and second substrates, an output terminal electrically connected to the primary bus bar, and two input terminals provided on the second substrate. The direction in which current flows into the first substrate and the direction in which current flows into the second substrate via the input and the output terminals are opposite to each other, and the direction in which the current flows into the primary bus bar and a direction in which the current flows into the secondary bus bar are opposite to each other. | 2013-09-19 |
20130242632 | CONTENT ADDRESSABLE MEMORY SYSTEM - There is a need to highly integrate a circuit area of content addressable memory (CAM) and ensure faster operation thereof. | 2013-09-19 |
20130242633 | Apparatus for ROM Cells - A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the first second-level contact shifts in a first direction with reference to the first first-level contact. The ROM cell further comprises a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is aligned with the first first-level contact and a second second-level formed on the second first-level contact, wherein the second second-level contact shifts in a second direction with reference to the second first-level contact, and wherein the first direction is opposite to the second direction. | 2013-09-19 |
20130242634 | SHIFT REGISTER MEMORY AND DRIVING METHOD THEREOF - A shift register memory according to the present embodiment includes a magnetic pillar including a plurality of magnetic layers and a plurality of nonmagnetic layers provided between the magnetic layers adjacent to each other. A stress application part applies a stress to the magnetic pillar. A magnetic-field application part applies a static magnetic field to the magnetic pillar. The stress application part applies the stress to the magnetic pillar in order to transfer magnetization states of the magnetic layers in a stacking direction of the magnetic layers. | 2013-09-19 |
20130242635 | SEMICONDUCTOR MEMORY DEVICE INCLUDING SENSING VERIFICATION UNIT - A semiconductor memory device includes a memory cell array configured to store data including a verification code; a sensing unit configured to sense the stored data including the verification code; and a verification unit configured to determine whether the sensing unit is able to sense the stored data based on a sensing condition, wherein the verification unit is configured to determine whether the sensing unit is able to sense the stored data based on the sensing condition and a value of the verification code sensed by the sensing unit. | 2013-09-19 |
20130242636 | ELECTROMECHANICAL INTEGRATED MEMORY ELEMENT AND ELECTRONIC MEMORY COMPRISING THE SAME - An electromechanical memory element includes a fixed body and a deformable element attached to the fixed body. An actuator causes a deformation of the deformable element from a first position (associated with a first logic state) to a second position (associated with a second logic state) where a mobile element makes contact with a fixed element. A programming circuit then causes a weld to be formed between the mobile element and the fixed element. The memory element is thus capable of associating the first and second positions with two different logic states. The weld may be selectively dissolved to return the deformable element back to the first position. | 2013-09-19 |
20130242637 | Memelectronic Device - A memelectronic device may have a first and a second electrode spaced apart by a plurality of materials. A first material may have a memory characteristic exhibited by the first material maintaining a magnitude of an electrically controlled physical property after discontinuing an electrical stimulus on the first material. A second material may have an auxiliary characteristic. | 2013-09-19 |
20130242638 | RESISTANCE-CHANGE TYPE NON-VOLATILE SEMICONDUCTOR MEMORY - A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line. | 2013-09-19 |
20130242639 | MEMORY DEVICE AND DRIVING METHOD THEREOF - Even in a circuit which always needs power supply, with a structure in which power supply is stopped in a period which does not need power supply, power consumption at the time of writing data to a memory device included in the circuit is reduced. A volatile memory portion and a nonvolatile memory portion are provided in the memory device included in the circuit which always needs power supply. As a memory element for storing data stored in the volatile memory portion which is included in the nonvolatile memory portion, a variable resistance memory element whose resistance value can be varied depending on voltage applied between both end terminals thereof is used. | 2013-09-19 |
20130242640 | Methods and Systems for Resistive Change Memory Cell Restoration - A resistive change memory device includes a first conductive line, a second conductive line, and a resistive change memory cell that includes a resistive memory element coupled between the first conductive line and the second conductive line. The resistive change memory device also includes control circuitry to apply, via the first conductive line and the second conductive line, a first biasing condition to the resistive change memory cell for a reset operation and a second biasing condition to the resistive change memory cell for a restore operation. The restore operation is performed to counteract a decrease in resistance of the resistive memory element for a reset state of the resistive change memory cell. At least one of a voltage, current, and duration of the second biasing condition is greater than a corresponding voltage, current, or duration of the first biasing condition. | 2013-09-19 |
20130242641 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a plurality of variable resistance memory cells; a plurality of bit lines each of which is connected to one end of each of the plurality of variable resistance memory cells; a common source line that is connected to the other ends of the plurality of variable resistance memory cells in common; a source line driver that supplies a potential to the common source line; and a controller that variably controls a current supplied to the common source line by the source line driver. | 2013-09-19 |
20130242642 | VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT WRITING METHOD - A variable resistance nonvolatile memory element writing method according to the present disclosure includes: (a) changing a variable resistance layer to a low resistance state by applying, to a second electrode, a first voltage which is negative with respect to a first electrode; and (b) changing the variable resistance layer to a high resistance state. Step (b) includes: (i) applying, to the second electrode, a second voltage which is positive with respect to the first electrode; and (ii) changing the variable resistance layer to the high resistance state by applying, to the second electrode, a third voltage, which is negative with respect to the first electrode and is smaller than the absolute value of a threshold voltage for changing the variable resistance layer from the high resistance state to the low resistance state, after the positive second voltage is applied in step (i). | 2013-09-19 |
20130242643 | SEMICONDUCTOR MEMORY DEVICE INCLUDING POWER DECOUPLING CAPACITOR - A semiconductor memory device includes a power decoupling capacitor (PDC) for preventing effective capacitance reduction during a high frequency operation. The semiconductor memory device includes the PDC to which a cell capacitor type decoupling capacitor is connected in series. The PDC includes a metal conductive layer electrically connected in parallel to a conductive layer formed on the same level as a bit line of a cell array region, wherein a plurality of decoupling capacitors in a first group and a plurality of decoupling capacitors in a second group are respectively connected to each other in parallel in a peripheral circuit region, and a storage electrode of the first group and a storage electrode of the second group are electrically connected to each other in series through the conductive layer. | 2013-09-19 |
20130242644 | MEMORY CELL AND MEMORY ARRAY - A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters. | 2013-09-19 |
20130242645 | Memory Cell - Memory cells are described with cross-coupled inverters including unidirectional gate conductors. Gate conductors for access transistors may also be aligned with a long axis of the inverter gate conductor. Contacts of one inverter in a cross-coupled pair may be aligned with a long axis of the other inverter's gate conductor. Separately formed rectangular active regions may be orthogonal to the gate conductors across pull up, pull down and access transistors. Separate active regions may be formed such that active regions associated with an access transistor and/or a pull up transistor are noncontiguous with, and narrower than, an active region associated with a pull down transistor of the inverter. The major components of 6T SRAM, and similar, memory cell topologies may be formed essentially from an array of rectangular lines, including unidirectional gate conductors and contacts, and unidirectional rectangular active regions crossing gate conductors of the inverters and access transistors. | 2013-09-19 |
20130242646 | MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) DIE INCLUDING AN INTEGRATED MAGNETIC SECURITY STRUCTURE - An MRAM die may include a first write line, a second write line, an MRAM cell disposed between the first write line and the second write line, and a magnetic security structure adjacent to the MRAM cell. The magnetic security structure may include a permanent magnetic layer and a soft magnetic layer. | 2013-09-19 |
20130242647 | MAGNETIC MEMORY - A magnetic memory according to an embodiment includes: a magnetic layer including a plurality of magnetic domains and a plurality of domain walls, and extending in a direction; a pinning layer formed with nonmagnetic phases and magnetic phases, extending in an extending direction of the magnetic layer and being located adjacent to the magnetic layer; an electrode layer located on the opposite side of the pinning layer from the magnetic layer; an insulating layer located between the pinning layer and the electrode layer; a current introducing unit flowing a shift current to the magnetic layer, the shift current causing the domain walls to shift; a write unit writing information into the magnetic layer; a read unit reading information from the magnetic layer; and a voltage generating unit generating a voltage to be applied between the pinning layer and the electrode layer. | 2013-09-19 |
20130242648 | APPROACH FOR PHASE CHANGE MEMORY CELLS TARGETING DIFFERENT DEVICE SPECIFICATIONS - A memory chip and methods of fabricating a memory device with different programming performance and retention characteristics on a single wafer. One method includes depositing a first bounded area of phase change material on the wafer and depositing a second bounded area of phase change material on the wafer. The method includes modifying the chemical composition of a switching volume of the first bounded area of phase change material. The method includes forming a first memory cell in the first bounded area of phase change material with a modified switching volume of phase change material and a second memory cell in the second bounded area of phase change material with an unmodified switching volume of phase change material such that the first memory cell has a first retention property and the second memory cell has a second retention property. The first retention property is different from the second retention property. | 2013-09-19 |
20130242649 | METHOD, SYSTEM, AND DEVICE FOR STORAGE CELL, SUCH AS FOR MEMORY - Embodiments disclosed herein may relate to forming an interface between a selector transistor and a phase change material storage cell in a memory device. | 2013-09-19 |
20130242650 | SET PULSE FOR PHASE CHANGE MEMORY PROGRAMMING - A memory device and method for programming the memory device, including a method for a melting phase change memory cell by applying an electronic signal at a first value and subsequently decreasing the signal value. The phase change memory cell can be substantially crystallized after the decrease in signal value. | 2013-09-19 |
20130242651 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second conductive layers function as a second electrode of the first capacitor. The first conductive layers and the second conductive layers are arranged alternately in the direction substantially perpendicular to a semiconductor substrate. A control circuit is configured to control a voltage applied to each of first conductive layers and the second conductive layers according to voltages of gates of a plurality of memory transistors, thereby changing a capacitance of the first capacitor. | 2013-09-19 |
20130242652 | Enhanced Multilevel Memory - Subject matter disclosed herein relates to semiconductor memories and, more particularly, to multilevel non-volatile or volatile memories. | 2013-09-19 |
20130242653 | FLASH MULTI-LEVEL THRESHOLD DISTRIBUTION SCHEME - A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages. | 2013-09-19 |
20130242654 | MEMORY DEVICES INCLUDING VERTICAL PILLARS AND METHODS OF MANUFACTURING AND OPERATING THE SAME - In a semiconductor device and a method of forming such a device, the semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers is provided on the substrate. A plurality of gate patterns is provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel, the vertical channel being in contact with the substrate at a contact region that comprises a semiconducting region. | 2013-09-19 |
20130242655 | Techniques for Accessing Column Selecting Shift Register with Skipped Entries in Non-Volatile Memories - Techniques are present for locating an initial physical location in a looping shift register with random skips on each loop. Here the shift register is for accessing columns in a non-volatile memory, where defective columns of the array are skipped. A look-up table provides for the initial skip of each loop, providing the number of skips from preceding loop to provide a physical address is close to the actual physical address. A new structure of shift registers then enables an automatic shift mode within the loop. The new structure has an additional register and logic gates that count how many skipped entry before the current pointer and shift the current pointer accordingly. | 2013-09-19 |
20130242656 | HOST EQUIPMENT, MEMORY CONTROLER, AND MEMORY DEVICE - A memory controller includes a processor that includes a monitoring module, a control module, and a parity generating module. The monitoring module receives a data sequence and checks the data sequence for a designated pattern. The control module determines page size of data sequences that include the designated pattern and arranges an idle area for each page based on the total data quantity and the size of the data sequence, where the data quantity of the data stored in each page is uniform. The parity generating module generates the extended parity in the idle area based on a portion of the data stored in each page and the management information of the page. In each page, the control module stores a portion of the data and the extended parity in the idle area. | 2013-09-19 |
20130242657 | USE OF EMERGING NON-VOLATILE MEMORY ELEMENTS WITH FLASH MEMORY - Memory devices and methods of operating memory devices are provided, such as those that involve a memory architecture that replaces typical static and/or dynamic components with emerging non-volatile memory (NV) elements. The emerging NV memory elements can replace conventional latches, can serve as a high speed interface between a flash memory array and external devices and can also be used as high performance cache memory for a flash memory array. | 2013-09-19 |
20130242658 | SYSTEM AND METHOD FOR ACCESSING AND STORING INTERLEAVED DATA - A flash storage system includes a data buffer configured to receive and store a data block having data portions. The system further includes flash storage devices having storage blocks interleaved among the flash storage devices and a controller coupled to the data buffer and the flash storage devices. The controller is configured to initiate data transfers for writing the data portions of the data block asynchronously into the storage blocks, where the data transfers for writing the data portions of the data block asynchronously into the storage blocks include reading the data portions of the data block from the data buffer serially and writing the data portions of the data block into the storage blocks in parallel. | 2013-09-19 |
20130242659 | SPLIT-GATE TYPE NONVOLATILE MEMORY DEVICE, SEMICONDUCTOR DEVICE HAVING SPLIT-TYPE NONVOLATILE MEMORY DEVICE EMBEDDED THEREIN, AND METHODS OF FORMING THE SAME - A split-gate type nonvolatile memory device includes a semiconductor substrate having a first conductivity type, a deep well having a second conductivity type in the semiconductor substrate, a pocket well having the first conductivity type in the deep well, a source line region having the second conductivity type in the pocket well, an erase gate on the source line region, and a first floating gate and a first control gate stacked sequentially on the pocket well on a side of the erase gate. The pocket well is electrically isolated from the substrate by the deep well, so that a negative voltage applied to the pocket well may not adversely affect operation of other devices formed on the substrate. | 2013-09-19 |
20130242660 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, in a write control unit that performs writing on a selected memory cell connected to a selected word line by making to apply a program voltage to the selected word line while making to apply an intermediate voltage to unselected word lines, an isolation voltage is controlled to be applied to any word line of the unselected word lines at a time of applying the program voltage and the isolation voltage is controlled to increase before the intermediate voltage is removed after applying the program voltage. | 2013-09-19 |
20130242661 | NON-VOLATILE STORAGE WITH READ PROCESS THAT REDUCES DISTURB - A apparatus and process for reading data from non-volatile storage includes applying a read compare signal to a selected data memory cell of a NAND string, applying a first set of one or more read pass voltages to unselected data memory cells at both ends of the NAND string and applying a second set of one or more read pass voltages to unselected data memory cells between both ends of the NAND string and on both sides of the selected data memory cell. The second set of one or more read pass voltages are all higher than the first set of one or more read pass voltages. | 2013-09-19 |
20130242662 | METHOD FOR DRIVING A NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A method for driving a nonvolatile semiconductor memory device is provided. The nonvolatile semiconductor memory device has source/drain diffusion layers spaced from each other in a surface portion of a semiconductor substrate, a laminated insulating film formed on a channel between the source/drain diffusion layers and including a charge storage layer, and a gate electrode formed on the laminated insulating film, the nonvolatile semiconductor memory device changing its data memory state by injection of charges into the charge storage layer. The method includes, before injecting charges to change the data memory state into the charge storage layer: injecting charges having a polarity identical to that of the charges to be injected; and further injecting charges having a polarity opposite to that of the injected charges. | 2013-09-19 |
20130242663 | PROGRAMMING INHIBIT METHOD OF NONVOLATILE MEMORY APPARATUS FOR REDUCING LEAKAGE CURRENT - The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage. | 2013-09-19 |
20130242664 | INTERFACE CIRCUIT - According to an embodiment, an interface circuit is provided with an output buffer which generates an output waveform on the basis of the ON/OFF operation of a transistor and a driver circuit which drives the transistor and is capable of independently changing a turn-ON speed and a turn-OFF speed of the transistor. | 2013-09-19 |
20130242665 | Method and Apparatus for Shortened Erase Operation - A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures. | 2013-09-19 |
20130242666 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A first non-selected word line including a word line adjacent to a selected word line is applied with a first write pass voltage. Furthermore, a second non-selected word line which is a non-selected word line excluding the first non-selected word line is applied with a second write pass voltage smaller than a program voltage. A control circuit, in the write operation, raises the first write pass voltage toward a first target value by executing a voltage raising operation having a first voltage rise width, X times, and raises the second write pass voltage toward a second target value by executing a voltage raising operation having a second voltage rise width, Y times. The first voltage rise width is larger than the second voltage rise width, and X times is fewer than Y times. | 2013-09-19 |
20130242667 | NON-VOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME - Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. | 2013-09-19 |
20130242668 | FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING SAME - A flash memory device includes a memory cell array made up of memory cells arranged in rows and columns. A first page of data is programmed in selected memory cells of the memory cell array, and a second page of data is subsequently programmed in the selected memory cells. The first page of data is programmed using a program voltage having a first start value, and the second page of data is programmed using a program voltage having a second start value determined by a programming characteristic of the selected memory cells. | 2013-09-19 |
20130242669 | END-OF-LIFE RELIABILITY FOR NON-VOLATILE MEMORY CELLS - A memory chip includes a memory array and a two-dimensional sensing system. The array includes a multiplicity of memory cells connected in rows by word lines and in columns by bit lines. The sensing system moves a read point two-dimensionally within a two-dimensional read space as the two-dimensional read space shrinks and shifts over the life of the chip. | 2013-09-19 |
20130242670 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes a semiconductor layer, a first insulating film formed on the semiconductor layer, a charge storage layer formed on the first insulating film and having fine metal grains, a second insulating film formed on the charge storage layer, and a gate electrode formed on the second insulating film. During a write operation, a differential voltage is applied across the gate electrode and the semiconductor layer to place the gate electrode at a lower voltage than the semiconductor layer and cause a positive electric charge to be stored in the charge storage layer. | 2013-09-19 |
20130242671 | VOLTAGE REGULATOR FOR BIASING A NAND MEMORY DEVICE - Disclosed herein is a device that includes an amplifier, a first transistor coupled between the first power supply line and the internal node and including a gate terminal supplied with a bias voltage, a second transistor coupled between the internal node and the second power supply line and including a gate terminal coupled to the output terminal of the amplifier, a third transistor coupled between the first power supply line and the output node and including a gate terminal coupled to the internal node, a divider configured to produce a first discharge path from the output node to the second power supply line to establish the feedback voltage to the amplifier, and a first switch circuit supplied with a first signal and coupled between the output node and the internal node. | 2013-09-19 |
20130242672 | Non-volatile Memory Device And A Method Of Operating Same - An array of non-volatile memory cells in a semiconductor substrate of a first conductivity type. Each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate, with a channel region therebetween. A word line overlies one portion of the channel region, is adjacent to the first region, and has little or no overlap with the first region. A floating gate overlies another portion of the channel region, and is adjacent to the first portion and the second region. A coupling gate overlies the floating gate. An erase gate overlies the second region. A bit line is connected to the first region. A negative charge pump circuit generates a negative voltage. A control circuit generates a plurality of control signals in response to receiving a command signal, and applies the negative voltage to the word line of unselected memory cells. | 2013-09-19 |
20130242673 | TECHNIQUES FOR ACCESSING MEMORY CELLS - Techniques for accessing memory cells are disclosed. In one particular embodiment, the techniques may be realized as an apparatus providing voltage to a high impedance node of a memory cell. The apparatus may comprise a precharge switch coupled to a first voltage source node, a precharge capacitor coupled to the precharge switch, and a switch matrix coupled to the precharge capacitor, a second voltage source node, and the high impedance node of the memory cell. The precharge switch may be configured to decouple the precharge capacitor from the first voltage source node, and the switch matrix may be configured to decouple the second voltage source node from the high impedance node of the memory cell and to couple the precharge capacitor to the high impedance node of the memory cell. | 2013-09-19 |
20130242674 | SEMICONDUCTOR DEVICE, METHOD FOR CONTROLLING THE SAME, AND SEMICONDUCTOR SYSTEM - The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized. | 2013-09-19 |
20130242675 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A three-dimensional nonvolatile memory device comprises a plurality of cell strings arranged perpendicular to a substrate. The nonvolatile memory device is programmed by identifying a selected word line and a plurality of unselected word lines connected to at least one of the cell stings, and sequentially applying a negative voltage and a pass voltage to the selected and unselected word lines, and then applying a program voltage to the selected word line while continuing to apply the pass voltage to the unselected word lines. | 2013-09-19 |
20130242676 | FAST-SWITCHING WORD LINE DRIVER - A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level. | 2013-09-19 |
20130242677 | Methods and Apparatus for Designing and Constructing Multi-port Memory Circuits with Voltage Assist - To handle multiple concurrent memory requests, a dual-port six transistor (6T) SRAM bit cell is proposed. The dual-port 6T SRAM cell uses independent word lines and bit lines such that the true side and the false side of the bit cell may be accessed independently. Single-ended reads allow the memory system to handle two independent read operations concurrently. Single-ended writes are enabled by adjusting the V | 2013-09-19 |
20130242678 | SIGNAL TRACKING IN WRITE OPERATIONS OF MEMORY CELLS - In a method, a first edge of a first tracking signal in a first direction of a memory array is generated. A first edge of a second tracking signal in a second direction of the memory array is generated. A first edge of a write-timing control signal is generated based on a slower edge of the first edge the first tracking signal and of the first edge of the second tracking signal. The first edge of the write-timing control signal is used to generate a second edge of the second tracking signal. | 2013-09-19 |
20130242679 | SEMICONDUCTOR MEMORY DEVICE FOR CONTROLLING WRITE RECOVERY TIME - A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal. | 2013-09-19 |
20130242680 | MEMORY MODULES - A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit. | 2013-09-19 |
20130242681 | METHODS AND APPARATUS FOR REDUCING PROGRAMMING TIME OF A MEMORY CELL - A method is provided for programming a memory cell having a first terminal coupled to a word line and a second terminal coupled to a bit line. During a first predetermined time interval, the word line is switched from a first standby voltage to a first voltage, the bit line is switched from a second standby voltage to a predetermined voltage, and a voltage drop across the first and second terminals is a safe voltage that does not program the memory cell. During a second predetermined time interval, the word line is switched from the first voltage to a second voltage, and a voltage drop across the first and second terminals is a programming voltage that is sufficient to program the memory cell. Numerous other aspects are provided. | 2013-09-19 |
20130242682 | MEMORY DEVICE POWER CONTROL - The apparatus described herein may comprise a first set of transistors, including a first transistor and a second transistor, and a second set of transistors, including a third transistor and a fourth transistor. Gates of the first and second transistors may be coupled to a first signal and a second signal, respectively, each indicating whether a corresponding one of a first supply voltage and a second supply voltage reaches a first threshold voltage or a second threshold voltage to power on a first circuit or a second circuit of a memory device. Gates of the third and fourth transistors may be coupled to a first inverted version of the first signal and a second inverted version of the second signal, respectively. An outcome signal of the second set of transistors may indicate a power-on state of the memory device responsive to power states of the first and second signals. | 2013-09-19 |
20130242683 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITORS FOR STABILIZING OPERATION VOLTAGE - Disclosed herein is a device that includes first and second memory cell arrays each including a plurality of memory cells, a first power supply line supplying a first voltage to the first memory cell array, a second power supply line supplying the first voltage to the second memory cell array, and a first capacitive element. The first capacitive element is electrically connected to the first power supply line and is electrically disconnected from the second power supply line when the first memory cell array is activated and the second memory cell array is deactivated. The first capacitive element is electrically connected to the second power supply line and is electrically disconnected from the first power supply line when the second memory cell array is activated and the first memory cell array is deactivated. | 2013-09-19 |
20130242684 | SEMICONDUCTOR STORAGE DEVICE AND DRIVING METHOD THEREOF - A semiconductor storage device according to the present embodiment includes local word lines and bit lines intersecting the local word lines. Each memory segment includes nonvolatile memory cells. Each memory segment corresponds to a plurality of the local word lines. A sense amplifier corresponds to a plurality of the bit lines. A global word line corresponds to a plurality of the local word lines, and is commonly driven in the memory segments. A decoder is connected between the global word line and the local word lines corresponding to the global word line, and selectively drives a certain local word line from the local word lines. A segment controller is provided in each memory segment, and selects one of the memory segments to be driven. An input/output part outputs read data from the memory segments or receives write data to the memory segments. | 2013-09-19 |