37th week of 2014 patent applcation highlights part 81 |
Patent application number | Title | Published |
20140258574 | Two-Wire Serial Interface and Protocol - In a serial transmission method using a two-wire serial interface, a master device transmits a first synchronous serial signal via the two-wire serial interface to wake-up a slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface. The asynchronous data signal directly controls a function of the slave device. | 2014-09-11 |
20140258575 | MASTER-SLAVE DETECTION METHOD AND MASTER-SLAVE DETECTION CIRCUIT - A master-slave detection method includes: every single time period, utilizing a random manner for determining whether a first device is used to transmit a specific pulse signal to a second device; every single time period, utilizing a random manner for determining whether the second device is used to transmit the specific pulse signal to the first device; when the first device receives at least one portion of the specific pulse signal earlier than the second device, setting the first device as a master device, stopping the master device from sending the specific pulse signal and utilizing the master device to start transmitting a specific sequence; and setting the second device as a slave device when the second device receives the specific sequence. The at least one portion of the specific pulse signal includes continuous single pulses. | 2014-09-11 |
20140258576 | COMMUNICATION DEVICE, COMMUNICATION METHOD, AND COMMUNICATION SYSTEM - A slave device ( | 2014-09-11 |
20140258577 | Wire Level Virtualization Over PCI-Express - A network element (NE) comprising a processor configured to receive a resource request via a Peripheral Component Interconnect (PCI) Express (PCI-e) network from a first device, wherein the first device is external to the NE, and query an access control list to determine whether the first device has permission to access a resource. The disclosure also includes an apparatus comprising a memory comprising instructions, and a processor configured to execute the instructions by allocating a resource of a shared device for use by an external device over a PCI-e network by updating a resource allocation table. | 2014-09-11 |
20140258578 | Supporting Multiple Channels Of A Single Interface - In one embodiment, the present invention includes a method for receiving a request for a transaction from a first agent in a fabric and obtaining an address, a requester identifier, a tag, and a traffic class of the transaction, and determining a channel of a target agent to receive the transaction based on at least two of the address, the requester identifier, the tag, and the traffic class. Based on this channel determination, the transaction can be sent to the channel of the target agent. Other embodiments are described and claimed. | 2014-09-11 |
20140258579 | MULTIPLE PATH LOAD DISTRIBUTION FOR HOST COMMUNICATION WITH A TAPE STORAGE DEVICE - A multiple port host communicates with multiple tape drives by requesting information associated with a particular tape. Information of availability status of a plurality of host ports is provided. Traversing all host initiator ports finds a host port with no or the least traffic load for a tape reservation request. A host port's traffic load calculation uses instant and the updated historical traffic as primary and secondary factors. Every host port's traffic load is updated for every read/write command, and is used for path selection of reservation requests. The instant load is relatively sensitive but will be zero under light load. The historical load is aware of the light load though it is not sensitive enough when a burst I/O occurs. With the traffic load calculated from instant and historical loads, the distribution of tape tasks is spread evenly among host initiator ports under light load and burst I/O scenarios. | 2014-09-11 |
20140258580 | MOTOR CONTROL APPARATUS AND MOTOR CONTROL METHOD - A motor control apparatus includes: a driving control unit that performs driving control of a motor in accordance with a drive command; an interrupt control unit that starts and executes interrupt processing for performing the driving control at an interrupt cycle; a first processing unit that executes same first processing every time the interrupt processing starts; and a second processing unit that selects and executes a different piece of processing from second processing every time the interrupt processing starts. The interrupt control unit executes at least one piece of the first processing before executing the second processing in the interrupt processing. | 2014-09-11 |
20140258581 | Method and Device for Serial Data Transmission Having a Flexible Message Size and a Variable bit Length - A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the transmitted messages having a logical structure according to CAN standard ISO 11898-1, the logical structure encompassing a start-of-frame bit, arbitration field, control field, data field, CRC field, acknowledge field, and end-of-frame sequence, the control field encompassing a data length code having an information item regarding the data field length. When a first marker (EDL) is present, the control field of the messages, divergently from the CAN standard ISO 11898-1, encompasses more than six bits; when the first marker (EDL) is present, the control field of the message is expanded to include at least one further bit (ESI); and the further bit (ESI) or one of the further bits causes an information item regarding the “error passive” state of the bus subscriber to be integrated into transmitted messages. | 2014-09-11 |
20140258582 | SEMICONDUCTOR DEVICE WITH VIAS ON A BRIDGE CONNECTING TWO BUSES - A semiconductor device comprises conductive buses and conductive bridges. A respective conductive bridge is conductively coupled to at least two portions of at least one of the conductive buses. At least N plus one (N+1) vias are coupled between every one of the conductive bridges and a respective feature in an integrated circuit when: (1) a width of the respective conductive bridge is less than a width of each of the at least two portions of the at least one of the conductive buses to which the respective conductive bridge is coupled, and (2) a distance along the respective conductive bridge and at least one of the vias is less than a critical distance. N is a number of conductive couplings between the respective one of the conductive bridges and the at least one of the conductive buses. | 2014-09-11 |
20140258583 | Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric - In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed. | 2014-09-11 |
20140258584 | BUS RELAY APPARATUS, INTEGRATED CIRCUIT APPARATUS, CABLE, CONNECTOR, ELECTRONIC APPLIANCE, AND BUS RELAY METHOD - A bus relay apparatus includes: an upstream port unit to which a USB host is connected; a downstream port unit to which a USB device is connected; an upstream port control unit; a downstream port control unit; and a relay unit configured to relay a packet transferred between the upstream port unit and the downstream port unit. In the bus relay apparatus, the downstream port unit reproduces a bus status detected by the upstream port unit and transmits the bus status, and the upstream port unit reproduces a bus status detected by the downstream port unit and transmits the bus status. | 2014-09-11 |
20140258585 | DATA PATH DIFFERENTIATOR FOR PRE-EMPHASIS REQUIREMENT DETERMINATION OR SLOT IDENTIFICATION - An apparatus and method is disclosed for generating path length information for two (usually redundant) receive paths in a receiving device such as a server blade so that the proper amount of equalization and/or pre-emphasis may be applied to receiver and driver circuits in the server blade. In one embodiment, the path length information comprises a longer or shorter path determination, and may also include a estimation of the slot location. In another embodiment, the path length information comprises a representation of the length of two receive paths. The path length information generating circuit is connected to the two receive inputs of the receiving device though high impedance elements, and the path length information may be utilized by hardware or a processor to set the equalization or pre-emphasis in the receiver and/or driver. | 2014-09-11 |
20140258586 | METHODS AND SYSTEMS FOR REDUCING THE AMOUNT OF TIME AND COMPUTING RESOURCES THAT ARE REQUIRED TO PERFORM A HARDWARE TABLE WALK (HWTW) - A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions. | 2014-09-11 |
20140258587 | SELF RECOVERY IN A SOLID STATE DRIVE - An apparatus having a nonvolatile memory and a controller. The memory stores information in multiple pages. The information includes data units and headers. Each data unit is associated with a respective identifier in an address space of the apparatus and a respective location in the memory, has a respective header having the respective identifier, and is associated with a respective time stamp. Multiple headers include ones of the time stamps. The controller is configured to (i) read information stored in the pages, (ii) determine an order in which the data units were written based on the time stamps, (iii) locate based on the order (a) each last-written occurrence of the respective identifiers and (b) the respective locations of the data units associated with the last-written occurrences, and (iv) rebuild a map of the controller according to the respective locations of each last-written occurrence of each respective identifier. | 2014-09-11 |
20140258588 | METHODS, DEVICES AND SYSTEMS FOR TWO STAGE POWER-ON MAP REBUILD WITH FREE SPACE ACCOUNTING IN A SOLID STATE DRIVE - A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands. | 2014-09-11 |
20140258589 | RANDOM NUMBER GENERATION - A system for random number generation may include non-volatile memory, and a random number stored on the non-volatile memory. The system may also include a key linked to the random number. The system may further include a computer-apparatus designed to use the random number based upon the key. | 2014-09-11 |
20140258590 | Enhanced Dynamic Read Process with Single-Level Cell Segmentation - A dynamic read case designation is determined for each of multiple wordline regions, respectively, of each of a number of single-level cell logic groups within a computer memory. The dynamic read case designation for any given one of the multiple wordline regions specifies a wordline read voltage to be used in reading memory cells of each wordline within the given one of the multiple wordline regions. The number of single-level cell logic groups are folded into a multi-level cell block. The folding includes reading the memory cells of each wordline of each of the multiple wordline regions of each of the number of single-level cell logic groups using a wordline read voltage corresponding to the dynamic read case designation, as determined for the wordline region within which the read memory cells reside. | 2014-09-11 |
20140258591 | DATA STORAGE AND RETRIEVAL IN A HYBRID DRIVE - A data storage device includes a magnetic storage device and a non-volatile solid-state memory device. The addressable space of the non-volatile solid-state storage device is partitioned into a plurality of equal sized segments and the addressable space of a command to read or write data to the data storage device is partitioned into a number of equal sized sets of contiguous addresses, such that each set of contiguous addresses has the same size as a segment of the addressable space of the non-volatile solid-state storage device. Storage can be allocated in the non-volatile solid-state device for selected sets of the contiguous addresses by mapping each selected set to a specific segment of the addressable space of the non-volatile solid-state device. | 2014-09-11 |
20140258592 | WRITE PROTECTION DATA STRUCTURE - A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses. | 2014-09-11 |
20140258593 | APPROXIMATE MULTI-LEVEL CELL MEMORY OPERATIONS - The present technology relaxes the precision (or full data-correctness-guarantees) requirements in memory operations, such as writing or reading, of MLC memories so that an application may write and read a digital data value as an approximate value. Types of MLCs include Flash MLC and MLC Phase Change Memory (PCM) as well as other resistive technologies. Many software applications may not need the accuracy or precision typically used to store and read data values. For example, an application may render an image on a relatively low resolution display and may not need an accurate data value for each pixel. By relaxing the precision or correctness requirements is a memory operation, MLC memories may have increased performance, lifetime, density, and/or energy efficiency. | 2014-09-11 |
20140258594 | RANDOM NUMBER GENERATION - A system for random number generation may include non-volatile memory, and a random number stored on the non-volatile memory. The system may also include a key linked to the random number. The system may further include a computer-apparatus designed to use the random number based upon the key. | 2014-09-11 |
20140258595 | SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM FOR DYNAMIC CACHE SHARING IN A FLASH-BASED CACHING SOLUTION SUPPORTING VIRTUAL MACHINES - A cache controller implemented in O/S kernel, driver and application levels within a guest virtual machine dynamically allocates a cache store to virtual machines for improved responsiveness to changing demands of virtual machines. A single cache device or a group of cache devices are provisioned as multiple logical devices and exposed to a resource allocator. A core caching algorithm executes in the guest virtual machine. As new virtual machines are added under the management of the virtual machine monitor, existing virtual machines are prompted to relinquish a portion of the cache store allocated for use by the respective existing machines. The relinquished cache is allocated to the new machine. Similarly, if a virtual machine is shutdown or migrated to a new host system, the cache capacity allocated to the virtual machine is redistributed among the remaining virtual machines being managed by the virtual machine monitor. | 2014-09-11 |
20140258596 | MEMORY CONTROLLER AND MEMORY SYSTEM - A memory controller having a plurality of channels according to an embodiment of the present invention includes: a valid page information management unit that manages, for each of the channel, identification information of a valid page; a write buffer that stores data to be written to the memory; a garbage collection control unit that executes a garbage collection process; and a channel controller capable of executing multi-plane read. The garbage collection control unit controls multi-plane read of the channel controller based on the identification information to level a total number of valid pages read from each of the channel. | 2014-09-11 |
20140258597 | MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - An operating method is for a memory device which controls a nonvolatile memory. The operating method includes managing a program depth bit map indicating an upper page program state of each of a plurality of word lines of the nonvolatile memory in response to an external write request, and outputting one of a plurality of different read commands to the nonvolatile memory based on information of the program depth bit map corresponding to a word line to be accessed in response to an external read request. | 2014-09-11 |
20140258598 | SCALABLE STORAGE DEVICES - Techniques using scalable storage devices represent a plurality of host-accessible storage devices as a single logical interface, conceptually aggregating storage implemented by the devices. A primary agent of the devices accepts storage requests from the host using a host-interface protocol, processing the requests internally and/or forwarding the requests as sub-requests to secondary agents of the storage devices using a peer-to-peer protocol. The secondary agents accept and process the sub-requests, and report sub-status information for each of the sub-requests to the primary agent and/or the host. The primary agent optionally accumulates the sub-statuses into an overall status for providing to the host. Peer-to-peer communication between the agents is optionally used to communicate redundancy information during host accesses and/or failure recoveries. Various failure recovery techniques reallocate storage, reassign agents, recover data via redundancy information, or any combination thereof. | 2014-09-11 |
20140258599 | WRITE PROTECTION DATA STRUCTURE - A data storage device includes a write protection data structure that includes a first set of entries corresponding to a first set of ranges of memory addresses. A first indication stored in an entry, in the first set of entries, corresponds to an absence of write-protected data between a lowest address of the range of addresses corresponding to the entry and a highest address of a memory. A second indication stored in the entry corresponds to write-protected data within the range of addresses. The data storage device also includes a write protection map that includes a second set of entries corresponding to a second set of ranges of the memory addresses. The device is configured to locate, in the write protection data structure, an entry corresponding to a range of memory addresses. | 2014-09-11 |
20140258600 | PRE-LOADING DATA - A device includes a non-volatile memory configured to store software to facilitate normal functions of the device, a first processing section including a data processor configured to execute the software when the device is in a normal mode, and load the software into a working memory in response to a trigger, and a second processing section coupled to a clock for maintaining a time, the second processing section configured to handle background processes when the device is in a low-power mode and initiate the trigger in response to the time of the clock preceding a user-set time by a preset advance interval, the pre-set advance interval taking into account a length of time to load the software into the working memory, wherein the working memory includes a volatile memory configured to store the software, and wherein in the low-power mode, the volatile memory receives insufficient power to store the software. | 2014-09-11 |
20140258601 | Memory Controller Supporting Nonvolatile Physical Memory - A memory system includes nonvolatile physical memory, such as flash memory, that exhibits a wear mechanism asymmetrically associated with write operations. A relatively small cache of volatile memory reduces the number of writes, and wear-leveling memory access methods distribute writes evenly over the nonvolatile memory. | 2014-09-11 |
20140258602 | SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS - A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area. | 2014-09-11 |
20140258603 | ASYMMETRIC MEMORY MIGRATION IN HYBRID MAIN MEMORY - Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component. | 2014-09-11 |
20140258604 | NON-VOLATILE STORAGE MODULE HAVING MAGNETIC RANDOM ACCESS MEMORY (MRAM) WITH A BUFFER WINDOW - A block storage system includes a host and comprises a block storage module that is coupled to the host. The block storage module includes a MRAM array and a bridge controller buffer coupled to communicate with the MRAM array. The MRAM array includes a buffer widow that is moveable within the MRAM array to allow contents of the MRAM array to be read by the host through the bridge controller buffer even when the capacity of the bridge controller buffer is less than the size of the data being read from the MRAM array. | 2014-09-11 |
20140258605 | MEMORY IMBALANCE PREDICTION BASED CACHE MANAGEMENT - Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed. | 2014-09-11 |
20140258606 | STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND STORAGE CONTROL METHOD - A storage control device includes: a partial unit buffer configured to hold at least one data assigned to a partial unit, in which the partial unit is one of a plurality of partial units that are each a division of a write unit for a memory; and a request generation section configured to generate, upon indication of a busy state in the memory for any of the partial units, a write request for the write unit of the memory when the holding of the data assigned to that partial unit is possible in the partial unit buffer. | 2014-09-11 |
20140258607 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device and a method of operating the same are provided. The semiconductor memory device includes a buffer that inputs a first signal and outputs a first delay signal, a command decoder that outputs a second signal, a mask pulse signal generator that inputs the first delay signal and the second signal and generates a mask pulse signal, and a signal reshaper that inputs the first delay signal, the second signal and the mask pulse signal and reshapes the first delay signal or the second signal. | 2014-09-11 |
20140258608 | Storage Controller Cache Synchronization Method and Apparatus - A method for a pair of redundant storage controllers to ensure reliable cached write data transfers to storage device logical volumes is provided. The method includes maintaining metadata including a first number identifying which controller currently owns the volume, a second number identifying which controller previously owned the volume, a third number identifying which controller is a preferred owner of the volume, and an indication if the volume is write protected. The method also includes determining if all volumes currently owned by the controller are write protected. If all volumes currently owned by the controller are write protected, then the method includes verifying that the second controller is working and transferring cache data from the second controller to the first controller. If all volumes currently owned by the first controller are not write protected, then the method includes updating the second number and placing all volumes online. | 2014-09-11 |
20140258609 | QUALITY OF SERVICE CONTROL METHOD FOR STORAGE SYSTEM - A method and a system for controlling quality of service of a storage system, and a storage system. The method includes: collecting information about processing capabilities of the hard disks in the storage system and obtaining processing capabilities of the hard disks according to the information about processing capabilities; dividing a cache into multiple cache tiers according to the processing capabilities of the hard disks; and writing, for a cache tier in which dirty data reaches a preset threshold, data in the cache tier into at least one hard disk corresponding to the cache tier. The method avoids a phenomenon of preempting page resources in the cache. | 2014-09-11 |
20140258610 | RAID Cache Memory System with Volume Windows - The invention may be embodied in a cache memory volume windows data storage system to enable cache memory rebuilds in response to power-on-reset (POR) events. To handle POR events occurring while a flush from the cache memory to the permanent memory is taking place, the storage controller maintains duplicate copy of a volume window bitmap and a volume mark register while a portion of the cache memory unavailable due to the flush event. The second copy of the volume bit map and volume mark register concatenation are used to account for the case where a POR event occurs while the flush is in process. The firmware uses the peer drives and the applicable cache rebuild protocol (e.g., RAID) to rebuild the data for all volume windows that contain data that may have become corrupted due to a POR event occurring during cache memory flush events are in progress. | 2014-09-11 |
20140258611 | SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit. | 2014-09-11 |
20140258612 | Mirrored data storage with improved data reliability - A plurality of arrays of storage devices, each providing dual storage device redundancy, is provided. The plurality of arrays of storage devices includes a plurality of mirrored sets of primary storage devices, each including an even number of at least two or more primary storage devices. Each of the mirrored sets of primary storage devices stores a first and a second copy of data. The plurality of arrays of storage devices also includes a secondary storage device, which is a single physical storage device that stores a third copy of the data stored on each of the plurality of mirrored sets of primary storage devices. The secondary storage device has at least the capacity to store the data stored on the plurality of mirrored sets of primary storage devices. Dual storage device redundancy preserves data if data cannot be read from one or two physical storage devices in any array. | 2014-09-11 |
20140258613 | VOLUME CHANGE FLAGS FOR INCREMENTAL SNAPSHOTS OF STORED DATA - Methods and structure are provided for tracking changes to a logical volume over time. One exemplary embodiment is a backup system for a Redundant Array of Independent Disks (RAID) storage system. The backup system includes a backup storage device that includes Copy-On-Write snapshots of a logical volume of the storage system. The backup system also includes a backup controller. The backup controller is able to maintain flags for the logical volume that indicate whether extents at the logical volume have been modified since a previous snapshot was created, and to move the flags from the logical volume to a new Copy-On-Write snapshot of the volume when the new Copy-On-Write snapshot is created. This preserves information describing which extents of the logical volume changed between the creation of the new snapshot and the previous snapshot. | 2014-09-11 |
20140258614 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell array having a plurality of memory cells, each memory cell configured to store plural bits of data, and a controller. The controller is configured to execute a write operation on the memory cells such that user data are written in at least one of the plural bits of data and prescribed data are written in the remaining bits of the plural bits of data. As a result, the number of bits of user data stored in the memory cells is less than the number of plural bits of data that each memory cell is configured to store. | 2014-09-11 |
20140258615 | STORAGE CONTROL APPARATUS AND STORAGE SYSTEM COMPRISING MULTIPLE STORAGE CONTROL APPARATUSES - A storage system has multiple disk controller (DKC) units that are coupled to one another in accordance with a coupling mode that satisfies the following (a1) through (a3): (a1) | 2014-09-11 |
20140258616 | METHOD AND SYSTEM FOR HETEROGENEOUS DATA VOLUME - A method and system is disclosed for providing a heterogeneous data storage comprising a plurality of storage devices of different types with respect to device vendor, model, capacity, performance and/or function. The present invention employs data access mechanisms specific to the type of underlying storage and the type of data to be stored or retrieved, and provides for integrated remote mirroring, disaster recovery and hierarchical storage management (HSM), as well as improved I/O performance and life expectancy of storage disks. A method of writing to and reading from heterogeneous data volume is also disclosed. | 2014-09-11 |
20140258617 | STORAGE APPARATUS AND STORAGE AREA ARRANGEMENT METHOD - This storage apparatus for providing a dynamically expandable virtual volume to a host system to access the virtual volume comprises an allocation unit for configuring a group with a plurality of disks for providing a storage area to be allocated to the virtual volume, and allocating the storage area respectively from a plurality of the groups to the virtual volume; and a storage area arrangement unit for rearranging the storage area in each of the groups being used by the virtual volume to become optimal among each of the groups based on external operation. | 2014-09-11 |
20140258618 | MULTI LATENCY CONFIGURABLE CACHE - Described herein are technologies for optimizing different cache configurations of a size-configurable cache. One configuration includes a base cache portion and a removable cache portion, each with different latencies. The latency of the base cache portion is modified to correspond to the latency of the removable portion. | 2014-09-11 |
20140258619 | APPARATUSES AND METHODS FOR A MEMORY DIE ARCHITECTURE - Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command. | 2014-09-11 |
20140258620 | METHOD, APPARATUS, SYSTEM FOR HANDLING ADDRESS CONFLICTS IN A DISTRIBUTED MEMORY FABRIC ARCHITECTURE - Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and Input/Output (I/O) agents in a computer system are serviced concurrently through use of a distributed memory fabric architecture employing parallel pipelines while maintaining memory coherency for cachelines associated with the caching agents and enforcing memory access ordering for memory access requests originating from I/O agents. | 2014-09-11 |
20140258621 | NON-DATA INCLUSIVE COHERENT (NIC) DIRECTORY FOR CACHE - Embodiments relate to a non-data inclusive coherent (NIC) directory for a symmetric multiprocessor (SMP) of a computer. An aspect includes determining a first eviction entry of a highest-level cache in a multilevel caching structure of the first processor node of the SMP. Another aspect includes determining that the NIC directory is not full. Another aspect includes determining that the first eviction entry of the highest-level cache is owned by a lower-level cache in the multilevel caching structure. Another aspect includes, based on the NIC directory not being full and based on the first eviction entry of the highest-level cache being owned by the lower-level cache, installing an address of the first eviction entry of the highest-level cache in a first new entry in the NIC directory. Another aspect includes invalidating the first eviction entry in the highest-level cache. | 2014-09-11 |
20140258622 | PREFETCHING OF DATA AND INSTRUCTIONS IN A DATA PROCESSING APPARATUS - A data processing apparatus includes a processor and a hierarchical data storage system, including a memory and a cache, for storing the data and the instructions in storage locations identified by physical addresses. The apparatus includes address translation circuitry for mapping the virtual addresses to the physical addresses and load store circuitry receiving access requests from the processor. The store circuitry accesses the translation circuitry to identify physical addresses that correspond to virtual addresses of the received data access requests, and to access the corresponding physical addresses in the hierarchical data storage system. Preload circuitry receives preload requests from the processor indicating virtual addresses storage locations that are to be preloaded. Prefetch circuitry monitors at least some of the accesses performed by the load store circuitry and predicts addresses to be accessed subsequently, and transmits the predicted addresses to the preload circuitry as preload requests. | 2014-09-11 |
20140258623 | MECHANISM FOR COPYING DATA IN MEMORY - An improved mechanism for copying data in memory is described which uses aliasing. In an embodiment, data is accessed from a first location in a memory and stored in a cache line associated with a second, different location in the memory. In response to a subsequent request for data from the second location in the memory, the cache returns the data stored in the cache line associated with the second location in the memory. The method may be implemented using additional hardware logic in the cache which is arranged to receive an aliasing request from a processor which identifies both the first and second locations in memory and triggers the accessing of data from the first location for storing in a cache line associated with the second location. | 2014-09-11 |
20140258624 | Apparatus and Method for Operating a Processor with an Operation Cache - A processor includes a computation engine to produce a computed value for a set of operands. A cache stores the set of operands and the computed value. The cache is configured to selectively identify a match and a miss for a new set of operands. In the event of a match the computed value is supplied by the cache and a computation engine operation is aborted. In the event of a miss a new computed value for the new set of operands is computed by the computation engine and is stored in the cache. | 2014-09-11 |
20140258625 | Data processing method and apparatus - Embodiments of the present invention provide a data processing method and apparatus. According to the embodiments of the present invention, when it is found that a data hash value in a currently received data stream exceeds a preset first threshold, a part or all of data in the data stream is not deduplicated, and is directly stored, so as to prevent the data in the data stream from being dispersedly stored into a plurality of storage areas; instead, the part or all of the data is stored into a storage area in a centralized manner, so that a deduplication rate is effectively improved on the whole, particularly in a scenario of large data storage amount. | 2014-09-11 |
20140258626 | ELECTRONIC DEVICES HAVING SEMICONDUCTOR MEMORY UNIT - An electronic device includes: a variable resistance element having a first electrode, a variable resistance layer, and a second electrode which are sequentially stacked therein; a spacer formed on the sidewall of the variable resistance element; and a conductive line covering the variable resistance element including the spacer. | 2014-09-11 |
20140258627 | MIGRATION OF DATA TO REGISTER FILE CACHE - Methods and migration units for use in out-of-order processors for migrating data to register file caches associated with functional units of the processor to satisfy register read operations. The migration unit receives register read operations to be executed for a particular functional unit. The migration unit reviews entries in a register renaming table to determine if the particular functional unit has recently accessed the source register and thus is likely to comprise an entry for the source register in its register file cache. In particular, the register renaming table comprises entries for physical registers that indicate what functional units have accessed the physical register. If the particular functional unit has not accessed the particular physical register the migration unit migrates data to the register file cache associated with the particular functional unit. | 2014-09-11 |
20140258628 | SYSTEM, METHOD AND COMPUTER-READABLE MEDIUM FOR MANAGING A CACHE STORE TO ACHIEVE IMPROVED CACHE RAMP-UP ACROSS SYSTEM REBOOTS - A cache controller having a cache store and associated with a storage system maintains information stored in the cache store across a reboot of the cache controller. The cache controller communicates with a host computer system and a data storage system. The cache controller partitions the cache memory to include a metadata portion and log portion. A separate portion is used for cached data elements. The cache controller maintains a copy of the metadata in a separate memory accessible to the host computer system. Data is written to the cache store when the metadata log reaches its capacity. Upon a reboot, metadata is copied back to the host computer system and the metadata log is traversed to copy additional changes in the cache that have not been saved to the data storage system. | 2014-09-11 |
20140258629 | SPECIFIC PREFETCH ALGORITHM FOR A CHIP HAVING A PARENT CORE AND A SCOUT CORE - Embodiments relate to a method, system, and computer program product for prefetching data on a chip having at least one scout core and a parent core. The method includes saving a prefetch code start address by the parent core. The prefetch code start address indicates where a prefetch code is stored. The prefetch code is specifically configured for monitoring the parent core based on a specific application being executed by the parent core. The method includes sending a broadcast interrupt signal by the parent core to the at least one scout core. The broadcast interrupt signal being sent based on the prefetch code start address being saved. The method includes monitoring the parent core by the prefetch code executed by at least one scout core. The scout core executes the prefetch code based on receiving the broadcast interrupt signal. | 2014-09-11 |
20140258630 | PREFETCHING FOR MULTIPLE PARENT CORES IN A MULTI-CORE CHIP - Embodiments relate to a method, system, and computer program product for prefetching data on a chip. The chip has at least one scout core, multiple parent cores that cooperate together to execute various tasks, and a shared cache that is common between the scout core and the multiple parent cores. An aspect of the embodiments includes monitoring the multiple parent cores by the at least one scout core through the shared cache for a shared cache access occurring in a base parent core. The method includes saving a fetch address by the at least one scout core based on the shared cache access occurring. The fetch address indicates a location of a specific line of cache requested by the base parent core. | 2014-09-11 |
20140258631 | Allocating Enclosure Cache In A Computing System - Allocating enclosure cache in a computing system that includes an enclosure and a plurality of enclosure attached servers, including: receiving, by the enclosure, memory access information from each of the plurality of enclosure attached servers; determining, by the enclosure in dependence upon the memory access information, an amount of enclosure cache to allocate as shared cache that can be accessed by two or more of the enclosure attached servers; and determining, by the enclosure in dependence upon the memory access information, an amount of enclosure cache to allocate to each enclosure attached server for exclusive use by the enclosure attached server. | 2014-09-11 |
20140258632 | Sharing Cache In A Computing System - Sharing cache in a computing system that includes a plurality of enclosure attached servers, including: identifying, by an enclosure, a first enclosure attached server that is not meeting a first predetermined performance threshold; identifying, by the enclosure, a second enclosure attached server that is meeting a second predetermined performance threshold; blocking, by the enclosure, access to a predetermined amount of cache on the second enclosure attached server by the second enclosure attached server; determining, by the enclosure, whether the second enclosure attached server is meeting the second predetermined performance threshold; responsive to determining that the second enclosure attached server is meeting the second predetermined performance threshold, lending, by the enclosure, the predetermined amount of cache on the second enclosure attached server to the first enclosure attached server. | 2014-09-11 |
20140258633 | Sharing Cache In A Computing System - Sharing cache in a computing system that includes a plurality of enclosure attached servers, including: identifying, by an enclosure, a first enclosure attached server that is not meeting a first predetermined performance threshold; identifying, by the enclosure, a second enclosure attached server that is meeting a second predetermined performance threshold; blocking, by the enclosure, access to a predetermined amount of cache on the second enclosure attached server by the second enclosure attached server; determining, by the enclosure, whether the second enclosure attached server is meeting the second predetermined performance threshold; responsive to determining that the second enclosure attached server is meeting the second predetermined performance threshold, lending, by the enclosure, the predetermined amount of cache on the second enclosure attached server to the first enclosure attached server. | 2014-09-11 |
20140258634 | Allocating Enclosure Cache In A Computing System - Allocating enclosure cache in a computing system that includes an enclosure and a plurality of enclosure attached servers, including: receiving, by the enclosure, memory access information from each of the plurality of enclosure attached servers; determining, by the enclosure in dependence upon the memory access information, an amount of enclosure cache to allocate as shared cache that can be accessed by two or more of the enclosure attached servers; and determining, by the enclosure in dependence upon the memory access information, an amount of enclosure cache to allocate to each enclosure attached server for exclusive use by the enclosure attached server. | 2014-09-11 |
20140258635 | INVALIDATING ENTRIES IN A NON-COHERENT CACHE - Techniques are provided for performing an invalidate operation in a non-coherent cache. In response to receiving an invalidate instruction, a cache unit only invalidates cache entries that are associated with invalidation data. In this way, a separate invalidate instruction is not required for each cache entry that is to be invalidated. Also, cache entries that are not to be invalidated remain unaffected by the invalidate operation. A cache entry may be associated with invalidation data if an address of the corresponding data item is in a particular set of addresses. The particular set of addresses may have been specified as a result of an invalidation instruction specified in code that is executing on a processor that is coupled to the cache. | 2014-09-11 |
20140258636 | CRITICAL-WORD-FIRST ORDERING OF CACHE MEMORY FILLS TO ACCELERATE CACHE MEMORY ACCESSES, AND RELATED PROCESSOR-BASED SYSTEMS AND METHODS - Critical-word-first reordering of cache fills to accelerate cache memory accesses, and related processor-based systems and methods are disclosed. In this regard in one embodiment, a cache memory is provided. The cache memory comprises a data array comprising a cache line, which comprises a plurality of data entry blocks configured to store a plurality of data entries. The cache memory also comprises cache line ordering logic configured to critical-word-first order the plurality of data entries into the cache line during a cache fill, and to store a cache line ordering index that is associated with the cache line and that indicates the critical-word-first ordering of the plurality of data entries in the cache line. The cache memory also comprises cache access logic configured to access each of the plurality of data entries in the cache line based on the cache line ordering index for the cache line. | 2014-09-11 |
20140258637 | FLUSHING ENTRIES IN A NON-COHERENT CACHE - Techniques are provided for performing a flush operation in a non-coherent cache. In response to determining to perform a flush operation, a cache unit flushes certain data items. The flush operation may be performed in response to a lapse of a particular amount of time, such as a number of cycles, or an explicit flush instruction that does not indicate any cache entry or data item. The cache unit may store change data that indicates which entry stores a data item that has been modified but not yet been flushed. The change data may be used to identify the entries that need to be flushed. In one technique, a dirty cache entry that is associated with one or more relatively recent changes is not flushed during a flush operation. | 2014-09-11 |
20140258638 | Method and apparatus for efficient read cache operation - A method for providing efficient use of a read cache by a storage controller is provided. The method includes the storage controller receiving a read request from a host computer and determining if a host stream size is larger than a read cache size. The host stream size is a current cumulative size of all read requests in the host stream. If the host stream size is larger than the read cache size then migrating data to a first area of the read cache containing data that has been in the read cache for the longest time. If the host stream size is not larger than the read cache size then migrating data to a second area of the read cache containing data that has been in the read cache for the shortest time. The host stream is a consecutive group of sequential read requests from the host computer. | 2014-09-11 |
20140258639 | CLIENT SPATIAL LOCALITY THROUGH THE USE OF VIRTUAL REQUEST TRACKERS - A memory request optimizer includes a memory tracker for receiving a read request from client devices and for determining whether the request address matches any of the virtual request trackers. If the request address does not match any virtual request tracker, an allocation logic allocates a next available virtual request tracker to track the request address. When the request address matches a virtual request tracker, a prefetch logic increments a current tracker match count for the virtual request tracker and determines whether a linear history of tracker match counts indicates a prefetch of a next request data is appropriate based on one or more predetermined criteria. If the linear history indicates the prefetch is appropriate, the prefetch logic obtains the next request data at an address equal to the request address plus a preconfigured request offset from the memory sub-system and stores the next request data in a cache. | 2014-09-11 |
20140258640 | PREFETCHING FOR A PARENT CORE IN A MULTI-CORE CHIP - Embodiments of the invention relate to prefetching data on a chip having at least one scout core, at least one parent core, and a shared cache that is common between the at least one scout core and the at least one parent core. A prefetch code is executed by the scout core for monitoring the parent core. The prefetch code executes independently from the parent core. The scout core determines that at least one specified data pattern has occurred in the parent core based on monitoring the parent core. A prefetch request is sent from the scout core to the shared cache. The prefetch request is sent based on the at least one specified pattern being detected by the scout core. A data set indicated by the prefetch request is sent to the parent core by the shared cache. | 2014-09-11 |
20140258641 | COMMUNICATING PREFETCHERS IN A MICROPROCESSOR - A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern. | 2014-09-11 |
20140258642 | DYNAMIC PRIORITIZATION OF CACHE ACCESS - Some embodiments of the inventive subject matter are directed to operations that include determining that an access request to a computer memory results in a cache miss. In some examples, the operations further include determining an amount of cache resources used to service additional cache misses that occurred within a period prior to the cache miss. Furthermore, in some examples, the operations further include servicing the access request to the computer memory based, at least in part, on the amount of the cache resources used to service the additional cache misses within the period prior to the cache miss. | 2014-09-11 |
20140258643 | METHOD AND SYSTEM FOR MAINTAINING RELEASE CONSISTENCY IN SHARED MEMORY PROGRAMMING - A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory. | 2014-09-11 |
20140258644 | TRANSACTIONAL MEMORY THAT PERFORMS AN ATOMIC METERING COMMAND - A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit. | 2014-09-11 |
20140258645 | System and Method for Implementing Reader-Writer Locks Using Hardware Transactional Memory - Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource. | 2014-09-11 |
20140258646 | FORMING A CHARACTERIZATION PARAMETER OF A RESISTIVE MEMORY ELEMENT - An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed. | 2014-09-11 |
20140258647 | RECORDING MEDIUM STORING PERFORMANCE EVALUATION ASSISTANCE PROGRAM, PERFORMANCE EVALUATION ASSISTANCE APPARATUS, AND PERFORMANCE EVALUATION ASSISTANCE METHOD - A characteristic amount for a data redundancy method of a storage apparatus, a characteristic amount for performance of a storage device, a phase change multiplicity, which is a multiplicity at a boundary between a low load and a high load, and the number of read requests per unit time are calculated by using redundancy method information of the storage apparatus, the number of storage devices of the storage apparatus, a used ratio of a used storage area, a ratio of read requests to requests, an average data amount of data read in response to a read request, the number of requests per unit time, and a constant decided based on a processing time for a write request in the storage apparatus and a type of a storage device, and a predicted value of an average response time to a read request is calculated by using the calculated values. | 2014-09-11 |
20140258648 | OVERWRITING PART OF COMPRESSED DATA WITHOUT DECOMPRESSING ON-DISK COMPRESSED DATA - Overwriting part of compressed data without decompressing on-disk compressed data is includes by receiving a write request for a block of data in a compression group from a client, wherein the compression group comprises a group of data blocks that is compressed, wherein the block of data is uncompressed. The storage server partially overwrites the compression group, wherein the compression group remains compressed while the partial overwriting is performed. The storage server determines whether the partially overwritten compression group including the uncompressed block of data should be compressed. The storage server defers compression of the partially overwritten compression group if the partially overwritten compression group should not be compressed. The storage server compresses the partially overwritten compression group if the partially overwritten compression group should be compressed. | 2014-09-11 |
20140258649 | CONTROL OF PAGE ACCESS IN MEMORY - The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters. | 2014-09-11 |
20140258650 | MANAGING OPERATIONS ON STORED DATA UNITS - A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform two or more operations with respect to data units. The operations include: a second read operation, different from the first read operation, that retrieves a data unit to be read based at least in part on an address of a data block containing the data unit to be read, and a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit. | 2014-09-11 |
20140258651 | MANAGING OPERATIONS ON STORED DATA UNITS - A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, and configured to store, for at least some of the data blocks, corresponding historical information about prior removal of one or more data units from that data block, the removal affecting at least some addresses of data units in that data block. The system is configured to perform at least one operation that accesses at least a first data unit stored in a first data block according to address information interpreted based on any stored historical information corresponding to the first data block. | 2014-09-11 |
20140258652 | MANAGING OPERATIONS ON STORED DATA UNITS - A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block. | 2014-09-11 |
20140258653 | INTEGRATING DATA FROM SYMMETRIC AND ASYMMETRIC MEMORY - Data stored within symmetric and asymmetric memory components of main memory is integrated by identifying a first data as having access characteristics suitable for storing in an asymmetric memory component. The first data is included among a collection of data to be written to the asymmetric memory component. An amount of data is identified within the collection of data to be written to the asymmetric memory component. The amount of data is compared within the collection of data to a volume threshold to determine whether a block write to the asymmetric memory component is justified by the amount of data. If justified, the collection of data is loaded to the asymmetric memory component. | 2014-09-11 |
20140258654 | STORAGE SYSTEM - For the purpose of suppressing decrease of a deduplication rate in a storage system, a storage system according to the present invention includes: a data buffer; a dividing unit configured to generate divided data by dividing data inputted into the data buffer; and a storage processing unit configured to store the divided data into a storage device while eliminating duplicate storage. The dividing unit is configured to generate the divided data by dividing the data inputted into the data buffer by a preset division standard based on the content of the data and also divide, by the division standard, connected data that residual data being left without being divided by the division standard and continuing data continuing to the residual data and being inputted in the data buffer are connected. | 2014-09-11 |
20140258655 | METHOD FOR DE-DUPLICATING DATA AND APPARATUS THEREFOR - Disclosed are a method for data de-duplication and an apparatus for the same. The method may comprise obtaining access property of data based on input request or output request for the data, determining de-duplication unit of the data based on the access property, and performing de-duplication on the data based on the de-duplication unit. Thus, data de-duplication rate may be determined adaptively based on input/output characteristics of data. Also, data de-duplication may be performed based on the determined data de-duplication rate so as to provide low input/output latency. | 2014-09-11 |
20140258656 | Lock-Free Object Recycling - Methods, program products, and systems for lock-free object recycling are described. In some implementations, a system can provide a type-neutral wrapper for a first data object. Upon receiving an indicator that the first data object is no longer used, the system can store the first data object and the type-neutral wrapper in a lock-free data structure. Upon receiving a request to create a second data object, the system can fetch the type-neutral wrapper and the first data object from the lock-free data structure without using a lock. The system can then return the first data object as a response to the request. | 2014-09-11 |
20140258657 | SYSTEM AND METHOD FOR MANAGING STORAGE SYSTEM SNAPSHOTS - A method of managing snapshots on a storage system includes a storage controller (1) receiving a request to store a first snapshot associated with a first volume among a plurality of volumes on the storage system and (2) determining if an assigned snapshot reserve space remaining associated with the first volume is less than an amount of space that is required to store the first snapshot. In response to the assigned snapshot reserve space remaining being less than the amount of space required, borrowing snapshot reserve space from at least one of an unused assigned space or an unused unassigned space within the storage system and storing at least a portion of the first snapshot to the borrowed snapshot reserve space. | 2014-09-11 |
20140258658 | REDUCING DATA LOSS IN A COMPUTING STORAGE ENVIRONMENT - For reducing data loss by a processor device in a computing storage environment, data blocks are prioritized for creating an N number of additional secondary copies of data using a vulnerability factor for identifying those of the data blocks having a probability of failure. The data blocks include at least a primary copy and a secondary copy of the data. | 2014-09-11 |
20140258659 | PROTECTION OF FORMER PRIMARY VOLUMES IN A SYNCHRONOUS REPLICATION RELATIONSHIP - An aspect includes protecting a former primary volume in a synchronous replication relationship. A swap between a primary volume at a first site and a secondary volume at a second site is initiated such that the secondary volume becomes a new primary volume and the primary volume becomes the former primary volume. A fenced state is set as active for the former primary volume. The former primary volume is configured as a fenced volume based on the fenced state being active. Read and write access to the fenced volume is blocked while the fenced state is active. | 2014-09-11 |
20140258660 | HAREWARE-SUPPORTED MEMORY TEMPORAL COPY - Providing a snapshot of a physical memory region as of a specified time includes: sending, from a first processor to a second processor, a request to generate a snapshot of the physical memory region as of the specified time; and generating, using the second processor, the snapshot of the physical memory region based at least in part on a known state of the physical memory region and log information about update activity of the physical memory region. | 2014-09-11 |
20140258661 | Backup method and computer system thereof - A backup method for a computer system includes a backup module, a storage device, a south bridge circuit and a serial-advanced-technology-attachment to universal-serial-bus (SATA-to-USB) transmission line. The backup method includes when the computer system is operated in a turned off status, determining whether the backup module is coupled to a stable voltage source; when the backup module is coupled to the stable voltage source, determining a voltage level of a detection point; and when the voltage level of the detection point is a low level, initiating a backup operation of the backup module to read a plurality of data in the storage device via the SATA-to-USB transmission line. | 2014-09-11 |
20140258662 | METHOD FOR CREATING CONSISTENT BACKUP IMAGE OF A STORAGE VOLUME WITHOUT REQUIRING A SNAPSHOT - Method for creating a consistent image, on a destination volume, of a target volume that remains in production use while the image is being created, without requiring the use of a snapshot. | 2014-09-11 |
20140258663 | METHOD AND APPARATUS FOR PREVENTING UNAUTHORIZED ACCESS TO CONTENTS OF A REGISTER UNDER CERTAIN CONDITIONS WHEN PERFORMING A HARDWARE TABLE WALK (HWTW) - A security apparatus and method are provided for performing a security algorithm that prevents unauthorized access to contents of a physical address (PA) that have been loaded into a storage element of the computer system as a result of performing a prediction algorithm during a hardware table walk that uses a predictor to predict a PA based on a virtual address (VA). When the predictor is enabled, it might be possible for a person with knowledge of the system to configure the predictor to cause contents stored at a PA of a secure portion of the main memory to be loaded into a register in the TLB. In this way, a person who should not have access to contents stored in secure portions of the main memory could indirectly gain unauthorized access to those contents. The apparatus and method prevent such unauthorized access to the contents by masking the contents under certain conditions. | 2014-09-11 |
20140258664 | METHOD AND APPARATUSES FOR READING DATA - A method of reading data includes setting first addresses defining a full image and second addresses defining a blocking region included in the full image and not reading blocking region data corresponding to the blocking region among image data corresponding to the full image using the first addresses and the second addresses. | 2014-09-11 |
20140258665 | STORAGE DEVICE, DATA PROCESSING DEVICE, REGISTRATION METHOD, ADN RECORDING MEDIUM - A storage device includes a switching unit which switches an access destination in a storage area between a first storage area and a second storage area in response to an access request from a host device; and a nonvolatile storage medium which stores a first host device information used to identify the host device in the second storage area, and a software module executed by a CPU provided in the host device, the software module comprising causing an authority grant unit which transmits a control signal for switching the access destination to the first storage area to the switching unit of the storage device, when the acquired first and second host device information are compared to find that the first and second host device information match with each other. | 2014-09-11 |
20140258666 | MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING READ DATA - Embodiments of the present invention provide memory systems having a plurality of memory devices sharing an interface for the transmission of read data. A controller can identify consecutive read requests sent to different memory devices. To avoid data contention on the interface, for example, the controller can be configured to delay the time until read data corresponding to the second read request is placed on the interface. | 2014-09-11 |
20140258667 | Apparatus and Method for Memory Operation Bonding - A processor is configured to evaluate memory operation bonding criteria to selectively identify memory operation bonding opportunities within a memory access plan. Memory operations are combined in response to the memory operation bonding opportunities to form a revised memory access plan with accelerated memory access. | 2014-09-11 |
20140258668 | Systems and Methods for Managing Storage Space in Hybrid Data Storage Systems - The present invention relates to systems and methods for managing storage space in hybrid data storage systems. Specifically, the systems and methods of the present invention intelligently allocate data to solid state drives or other relatively high performance drives, and other data storage, such as, for example, hard drives or other like drives, based on data source, data type, data function or other like parameters. The intelligent allocation between at least one solid state drive, or other relatively high performance drive, and at least one other drive type allows for greater system performance through efficient use storage space. Specifically, the present invention adaptively uses the fastest necessary connected storage options in a hybrid data storage set to maintain maximum performance while most efficiently using minimum rewrites of data. Moreover, the allocation of data to storage in a hybrid data storage system may be controlled automatically or may be specifically set by a user thereof. | 2014-09-11 |
20140258669 | MEMORY MANAGEMENT METHOD, MEMORY MANAGEMENT APPARATUS AND NUMA SYSTEM - Embodiments of the present invention provide a memory management method, a memory management apparatus and a NUMA system. The memory management method includes: determining, according to a memory demand information which includes memory demand information sent by a processor, whether a memory controller meeting the memory demand information exists in a local processing node which the processor; and if exists, determining, in the memory controller meeting the memory demand information, a memory management area meeting the memory demand information, and allocating the memory management area meeting the memory demand information to the processor. Therefore, the memory controller and the memory management area do not need to be determined in a processing node that does not meet the requirements, which can rapidly find a storing area meeting the requirements, and improve the memory allocation efficiency. | 2014-09-11 |
20140258670 | SYSTEM AND METHOD FOR EFFICIENT SWAP SPACE ALLOCATION IN A VIRTUALIZED ENVIRONMENT - A technique for efficient swap space management creates a swap reservation file using thick provisioning to accommodate a maximum amount of memory reclamation from a set of one or more associated virtual machines (VMs). A VM swap file is created for each VM using thin provisioning. When a new block is needed to accommodate page swaps to a given VM swap file, a block is removed from the swap reservation file and a block is added to the VM swap file, thereby maintaining a net zero difference in overall swap storage. The removed block and the added block may be the same storage block if a block move operation is supported by a file system implementing the swap reservation file and VM swap files. The technique also accommodates swap space management of resource pools. | 2014-09-11 |
20140258671 | Heuristic Journal Reservations - Example apparatus and methods reserve space in a journal using an observation based approach instead of a fixed sized approach or a worst case scenario approach. One example method receives a request to allocate space in a journal to support a file system transaction. The example method reserves an amount of space in the journal based on a pre-existing reservation size estimate. Unlike conventional systems, the estimate is not based on a worst-case scenario. The example method observes the actual amount of storage used in the journal by the file system transaction and then selectively automatically adjusts the pre-existing reservation size estimate. The estimate may slowly shrink if no overflows are encountered but may quickly grow if an overflow is detected. | 2014-09-11 |
20140258672 | DEMAND DETERMINATION FOR DATA BLOCKS - The positioning a block of data within a storage hierarchy. For the given block of data, demand statistics are accumulated for each of multiple time periods by evaluating input/output operations on the block of data during the time period and assigning a resulting demand value to the time period for that time period. This is done for multiple time periods so that the accumulated demand for a given point of time may be calculated using the assigned demand values for the previous time periods. The accumulated demand may then be used to determine a level in the storage hierarchy that the block of data should be placed. This allows for the more in-demand memory blocks to be placed in higher in the storage hierarchy. Thus, the principles described herein allow for efficient use of computing resources. | 2014-09-11 |
20140258673 | APPARATUS AND METHOD FOR PROCESSING DATA IN TERMINAL - An apparatus and a method for processing data in a terminal are provided. The method includes when a specific program including a specific extension is stored, identifying addresses representing a position of specific data having the specific extension in an entire storage space, initializing the specific program based on the identified addresses, and generating an address table based on the identified addresses, and storing the generated address table. | 2014-09-11 |