37th week of 2008 patent applcation highlights part 21 |
Patent application number | Title | Published |
20080218205 | Timing Exact Design Conversions from FPGA to ASIC - A device having a design conversion from a field programmable gate array (FPGA) to an application specific integrated circuit (ASIC), comprising: a user configurable element in the FPGA replaced by a mask configurable element in the ASIC, wherein the FPGA and the ASIC have identical die size and identical transistor layouts. | 2008-09-11 |
20080218206 | FIELD PROGRAMMABLE GATE ARRAY LONG LINE ROUTING NETWORK - A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set of programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines. | 2008-09-11 |
20080218207 | SYNCHRONOUS FIRST-IN/FIRST-OUT BLOCK MEMORY FOR A FIELD PROGRAMMABLE GATE ARRAY - The present invention comprises a field programmable gate array that has a plurality of dedicated first-in/first-out memory logic components. The field programmable gate array includes a plurality of synchronous random access memory blocks that are coupled to a plurality of dedicated first-in/first-out memory logic components and a plurality of random access memory clusters that are programmably coupled to the plurality of dedicated first-in/first-out memory logic components and to the plurality of synchronous random access memory blocks. | 2008-09-11 |
20080218208 | PROGRAMMABLE LOGIC DEVICE HAVING LOGIC ARRAY BLOCK INTERCONNECT LINES THAT CAN INTERCONNECT LOGIC ELEMENTS IN DIFFERENT LOGIC BLOCKS - A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the LABs include a predetermined number of logic elements, one or more control signals distributed among the predetermined number of logic elements in the LAB, and LAB lines spanning between logic elements in different LABs in the array. In various embodiments, the LAB lines are arranged in a staggered pattern with a predetermined pitch between the lines. In other embodiments, the control signals of adjacent LABs can overlap, allowing control signals to be routed to the logic elements of adjacent LABs. | 2008-09-11 |
20080218209 | Device for Controlling Terminal State, Method Thereof, and Device for Transmitting Paging Message - The present invention relates to a device for controlling a state of a terminal with respect to mobility management, and a method thereof. The state of the terminal includes a disconnected state and a connected state, the connected state includes an active state and an idle state, and the active state includes an active sub-state and a standby sub-state. The terminal in the active state updates location information for each cell, and the terminal in the idle state updates the location information for each radio access network registration area including a plurality of cells. The terminal in the active sub-state performs a handover when leaving a current cell. The terminal in the standby sub-state determines a quality of service (QoS) of packet data, and performs the handover or is set to be in the idle state according to the determined QoS. | 2008-09-11 |
20080218210 | INTEGRATED NANOTUBE AND FIELD EFFECT SWITCHING DEVICES - Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit. | 2008-09-11 |
20080218211 | High-speed buffer circuit, system and method - A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation. | 2008-09-11 |
20080218212 | LOW TO HIGH VOLTAGE CONVERSION OUTPUT DRIVER - A low to high voltage conversion output driver. The low to high voltage conversion output driver has an output coupled to a first fixed voltage via a load device and comprises a current source, a low voltage transistor, and a high voltage transistor. The current source has one end coupled to a second fixed voltage. The low voltage transistor has a first terminal coupled to the other end of the current source, a second terminal receiving a low voltage data signal, and a third terminal. The high voltage transistor has a first terminal coupled to the third terminal of the low voltage transistor, a second terminal coupled to a bias source, and a third terminal coupled to the output. | 2008-09-11 |
20080218213 | BIDIRECTIONAL LEVEL SHIFT CIRCUIT AND BIDIRECTIONAL BUS SYSTEM - A plurality of transistors are connected between an I | 2008-09-11 |
20080218214 | SEMICONDUCTOR OUTPUT CIRCUIT, EXTERNAL OUTPUT SIGNAL GENERATION METHOD, AND SEMICONDUCTOR DEVICE - A semiconductor output circuit, an external output signal generation method and a semiconductor device that suppress variation in an external output signal caused by a decrease in power supply voltage. An output section changes electric potential of an external output signal EB according to a change in electric potential of an internal input signal A from ground to VDD or from VDD to the ground. A differential section outputs an output signal corresponding to the external output signal EB and a predetermined reference signal VREF. The differential section functions as a voltage follower so that the electric potential of the external output signal EB will correspond to the predetermined reference signal VREF. As a result, variation in output voltage VOL at a low voltage side of the external output signal EB is suppressed. | 2008-09-11 |
20080218215 | Advanced Repeater Utilizing Signal Distribution Delay - An advanced repeater utilizing signal distribution delay. In accordance with a first embodiment of the present invention, such an advanced repeater circuit comprises an output stage for driving an output signal line responsive to an input signal and a feedback loop coupled to said output signal line for changing state of said output stage subsequent to a delay after a transition of said output signal. The delay is due to transmission line effects of said output signal line. | 2008-09-11 |
20080218216 | Metastable-resistant phase comparing circuit - A phase comparing circuit includes a first storage circuit for reading an external clock signal based on a control clock signal; first and second inverters for inverting a signal from the first storage circuit based respectively on first and second threshold levels; third and fourth inverters for inverting respective signals output from the first and second inverters; a delay circuit for delaying the control clock signal by a specific time; a coincidence control circuit for setting the delayed control clock signal to be active when the signals from the third and fourth inverters coincide with each other, and setting it to be inactive when the signals from the third and fourth inverters do not coincide with each other; and a second storage circuit for reading a signal output form the first storage circuit when the delayed control clock signal is active, and outputting the read signal as the control signal. | 2008-09-11 |
20080218217 | Semiconductor integrated circuit device - High precision of various feedback systems represented by a PLL circuit and the like is realized. For example, in a charge pump circuit in the PLL circuit, a first to a third PMOS transistors connected in series in three stages are provided between a power source voltage and an output node, and a first to a third NMOS transistors connected in series in three stages are provided between a ground voltage and the output node. And, the second PMOS transistor and the second NMOS transistor are driven ON when establishing conductivity between the power source voltage or the ground voltage and the output node by a first pulse signal, and the first PMOS transistor and the third NMOS transistor are driven OFF when the conductivity is shut down by a second pulse signal. Accordingly, the conduction time can be set by time difference between one edge of the first pulse signal and one edge of the second pulse signal, and therefore, short conduction time can be set, as a result, a charge amount of the charge pump circuit can be controlled precisely. | 2008-09-11 |
20080218218 | POTENTIAL COMPARATOR AND TEST APPARATUS - The potential comparator includes input wires 3 and 4 that input a differential signal output from a test object | 2008-09-11 |
20080218219 | COMPARATOR AND IMAGE DISPLAY SYSTEM - A comparator for comparing a reference signal with a data signal includes a voltage boosting circuit, a first logic inverting circuit and a second logic inverting circuit. The voltage boosting circuit receives the reference signal to hold a voltage difference during a first time, and receives the data signal to generate a comparing signal according to the data signal and the voltage difference during a second time. The first logic inverting circuit is electrically connected to the voltage boosting circuit, outputs an initial signal to the voltage boosting circuit to hold the voltage difference during the first time, and inverts the comparing signal to output a first voltage signal during the second time. The second logic inverting circuit is electrically connected to the first logic inverting circuit during the second time, and inverts the first voltage signal to output a second voltage signal fed back to hold the comparing signal. | 2008-09-11 |
20080218220 | Signal converting apparatus - A signal converting apparatus includes the following elements. A converting section converts an input signal into output signals on the basis of the values of reference parameters, serving as references of a plurality of parameters for signal conversion, and the values of newly proposed parameters. An evaluation input receiving section receives an evaluation input indicating the selection of either the output signal based on the values of the reference parameters or the output signal based on the values of the newly proposed parameters. A parameter updating section linearly changes the values of the newly proposed parameters when the evaluation input indicates the selection of the output signal based on the values of the newly proposed parameters, and nonlinearly changes the values of the reference and newly proposed parameters when the evaluation input indicates the selection of the output signal based on the values of the reference parameters. | 2008-09-11 |
20080218221 | ANALOG SOURCE DRIVING APPARATUS - An analog source driving apparatus including an operational amplifier, a first resistor, a second resistor, a variable gain unit and a source driver is provided. A constant gain amplifier is composed with the operational amplifier, the first resistor, and the second resistor, wherein the first resistor is coupled between the inverse input terminal of the operational amplifier and the ground, and the second resistor is coupled between the inverse input terminal and the output terminal of the operational amplifier. The variable gain unit is coupled to an analog signal and the non-inverse input terminal of the operational amplifier for adjusting the analog signal to avoid affecting the zero point position and pole position of the system. Accordingly, the analog source driving apparatus can provide a stable driving output. | 2008-09-11 |
20080218222 | Circuit and method for current-mode output driver with pre-emphasis - An output driver circuit including a pre-driver stage that receives a first data signal, the pre-driver stage including a plurality of first differential pairs that perform current subtraction to output a second data signal based on the first data signal, and an output driver stage electrically coupled to the pre-driver stage that receives the second data signal from the pre-driver stage, the output driver stage including a plurality of second differential pairs that transmit an output signal along transmission lines. | 2008-09-11 |
20080218223 | POWER ON DETECTION CIRCUIT - A power on detection circuit for accurately detecting an input voltage with a simple circuit structure and reduced current consumption includes a voltage conversion circuit, which converts input voltage into current, and a latch circuit, which holds the power on detection signal. The voltage conversion circuit supplies output current to a current source and a capacitor via a connection node. The current source generates a flow of current that is proportional to the absolute temperature. When the output current of the voltage conversion circuit becomes greater than the current of the current source, the capacitor is charged and the voltage at the connection node is pulled up. A latching circuit is activated in accordance with the voltage at the connection node to output a power on detection signal. | 2008-09-11 |
20080218224 | SEMICONDUCTOR INTEGRATED CIRCUIT - The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed. | 2008-09-11 |
20080218225 | Semiconductor Device and Communication Control Method - The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B. The controller controls in such way that the core B can receive only the data arriving prior to the setup of the clock signal clkB. The controller stores the history on a communication status between cores. | 2008-09-11 |
20080218226 | CIRCUITS AND APPARATUS TO IMPLEMENT DIGITAL PHASE LOCKED LOOPS - Circuits and apparatus to implement digital phase locked loops are disclosed. A disclosed example digital phase locked loop circuit comprises a phase detector to detect a phase difference between a reference signal and a feedback signal, a time digitizer to convert the phase difference to a digital value, and an adder to add an offset to the digital value, the offset selected to reduce a digital phase locked loop dead zone | 2008-09-11 |
20080218227 | SEMICONDUCTOR MEMORY APPARATUS - In order to provide a semiconductor memory apparatus which can adjust the locked loop circuit such as a DLL in detail after producing the semiconductor memory apparatus, and moreover, which can adjust the locked loop circuit by using a measuring apparatus which has a low testing frequency, an exclusive-OR circuit generates an adjusting clock signal TCLK obtained by multiplying a frequency of a pair of test clock signals which respectively have a phase difference. A DLL circuit inputs the adjusting clock signal TCLK in place to an external clock signal CLK. The counter circuit counts the control clock signal CCLK outputted from the DLL circuit for a predetermined time. A comparator compares a counted value to an expected value and outputs a comparison result. A phase adjusting circuit outputs an adjusting signal to a delay circuit inside the DLL circuit based on the comparison result outputted from the comparator, and adjusts a phase of the control clock signal CCLK outputted from the DLL circuit. | 2008-09-11 |
20080218228 | Symmetrical Time/Voltage Conversion Circuit - The invention relates to a time/voltage conversion circuit, comprising two simple time/voltage converters (CTT | 2008-09-11 |
20080218229 | ADJUSTMENT OF PLL BANDWIDTH FOR JITTER CONTROL USING FEEDBACK CIRCUITRY - Jitter method and control circuit for a circuit block in a transceiver system having a phase lock loop circuit which includes an oscillator, a charge pump connected to the oscillator to add or subtract charge to or from said oscillator, and a low pass filter connected to said charge pump are provided. Circuitry is connected to the output of the oscillator and the input of the charge pump to control the amount of charge added to or subtracted from the charge pump to control the bandwidth output by the oscillator and thereby reduce jitter in the phase lock circuit. | 2008-09-11 |
20080218230 | CLOCK TEST APPARATUS AND METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A clock test apparatus for a semiconductor integrated circuit includes a delay unit configured to delay an internal clock signal. A comparison unit compares the phase of an output signal of the delay unit with the phase of a reference clock signal. A phase discrimination unit receives a test mode signal, the reference clock signal, and an output signal of the comparison unit, thereby outputting a discrimination signal. | 2008-09-11 |
20080218231 | MULTIPLE OUTPUT TIME-TO-DIGITAL CONVERTER - A differential line compensation apparatus, semiconductor chip and system are disclosed. | 2008-09-11 |
20080218232 | TIMING CONTROLLER, DISPLAY DEVICE INCLUDING TIMING CONTROLLER, AND SIGNAL GENERATION METHOD USED BY DISPLAY DEVICE - A display device includes a timing controller and a display unit. The timing controller receives an external clock signal, reads signal generation information, and generates and outputs an internal clock signal based on the read signal generation information. The display unit receives the internal clock signal and displays an image. When the internal clock signal is abnormal, the timing controller rereads the signal generation information and generates and outputs the internal clock signal based on the reread signal generation information. | 2008-09-11 |
20080218233 | Master-slave type flip-flop circuit and latch circuit - A clock input circuit | 2008-09-11 |
20080218234 | LOW POWER FLIP-FLOP CIRCUIT - A flip-flop circuit having low power consumption includes a sensing circuit, and a clock generating circuit. The flip-flop is leading edge triggered and operates on an internally generated pseudo clock signal. The sensing circuit senses a change in an input signal and an output signal of the flip-flop. The clock generating circuit generates a pseudo clock signal with a sharp rise and fall based upon an external clock signal. | 2008-09-11 |
20080218235 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH FLIP-FLOP CIRCUITS MOUNTED THEREON - A plurality of flip-flop circuits, having different circuit configurations, which perform an identical digital signal processing are mixed on a single semiconductor substrate. A first flip-flop circuit among the plurality of flip-flop circuits receives a clock signal supplied from outside the flip-flop circuits, through at least two stage inverters, and operates with clock signals outputted from the inverters. A second flip-flop circuit receives the clock signal supplied from outside the flip-flop circuits through at least one inverter having a less number of stages than the number of stages of the inverter contained in the first flip-flop circuit, and operates with at least one of the clock signal and a clock signal outputted from the inverter. | 2008-09-11 |
20080218236 | DELAY CIRCUIT - A delay circuit ( | 2008-09-11 |
20080218237 | MULTI-LEVEL MULTI-PIN DIFFERENTIAL INTERFACE - A digital interface system that includes a first circuit that transmits a set of voltage levels and a second circuit that receives the set of voltage levels and generates a set of voltage differential levels based on the set of voltage levels. The set of voltage differential levels corresponds to a first predetermined value. Each of the voltage levels is different from another of the voltage levels. | 2008-09-11 |
20080218238 | Input signal detecting circuit - An input signal detecting circuit includes a plurality of comparators configured to output a plurality of differential output signals in response to a differential input signal, respectively; and a differential exclusive OR circuit configured to output an exclusive OR resultant signal from the plurality of differential output signals outputted from the plurality of comparators. In at least one of the plurality of comparators, a DC operation voltage is changed in response to a control signal supplied to the comparator. | 2008-09-11 |
20080218239 | Interface circuit and signal output adjusting method - The problem to be solved by of this claimed application is solved by providing an interface circuit and a signal output adjusting method that are capable of adjusting amplitude of a transmission-side signal by taking attenuation of a transmission path into consideration. In a transmission-side circuit part of an interface circuit | 2008-09-11 |
20080218240 | CURRENT CONTROL CIRCUIT USED FOR VOLTAGE BOOSTER CIRCUIT - When a low level voltage is inputted to an input terminal IN, a transistor EF | 2008-09-11 |
20080218241 | DIFFERENTIAL OUTPUT CIRCUIT WITH REDUCED DIFFERENTIAL OUTPUT VARIATION - In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on. | 2008-09-11 |
20080218242 | OUTPUT SIGNAL SWITCHING DEVICE - An output signal switching device includes a switching unit connected to a base board and a detection resistor. The voltage of the detection resistor is set to be constant by a resistor. The expansion board includes the detection resistor. When being connected to the expansion board, the switching unit interrupts a signal inputted to the switching unit from the base board. | 2008-09-11 |
20080218243 | SEMICONDUCTOR SWITCHING CIRCUIT AND SEMICONDUCTOR INTEGRATED-DEVICE - There is provided a switching circuit including, a semiconductor switching circuit comprising, a transistor, a first electrode of the transistor being connected to an electrical source via a load, a second electrode of the transistor being connected to a standard potential, a driving circuit outputting a signal to a control electrode of the transistor on a basis of a potential in the first electrode of the transistor so as to turn on and off the transistor, the driving circuit turning on when an input voltage applied from an input terminal being a first voltage higher than a threshold voltage of the transistor, the driving circuit turning off when the input voltage being a second voltage lower than the threshold voltage of the transistor. | 2008-09-11 |
20080218244 | Analog switch - An analog switch comprises a first transistor, a second transistor, the drain and the source thereof being connected between said first input terminal and a second output terminal whereto said second signal is output and the gate thereof being grounded or connected to a supply voltage node, a third transistor, the drain and the source thereof being connected between a second input terminal whereto said second signal is input and said second output terminal and said third transistor being turned on and off by a control signal provided to the gate thereof; and a fourth transistor, the drain and the source thereof being connected between said second input terminal and said first output terminal and the gate thereof being grounded or connected to a supply voltage node. | 2008-09-11 |
20080218245 | SOLID-STATE SWITCH - A solid state switch that employs a controller driven input and MOSFET power switching devices is disclosed. The controller can test for a short-circuit on the load side of the MOSFET power switching devices before putting the switch in a sustained conductive state. | 2008-09-11 |
20080218246 | RELAY CONNECTOR UNIT AND ELECTRONIC DEVICE CONTROL SYSTEM - A relay connector unit for communicating an electronic control unit with a plurality of electronic devices includes: a first connecting unit connected to the electronic control unit; a second connecting unit having a plurality of circuits connected to the electronic devices respectively; and a transferring unit connected to the first connecting unit and the second connecting unit. The transferring unit transmits first information received by the first connecting unit from the electronic control unit to at least one of the electronic devices through a corresponding circuit, on the basis of circuit identifying data included in first information, the circuit identifying data indicating the corresponding circuit to be transferred to or from. The transferring unit appends the circuit identifying data to second information received from one of the electronic devices through the corresponding circuit to transmit the second information to the electronic control unit through the first connecting unit. | 2008-09-11 |
20080218247 | METHOD FOR AUTOMATICALLY ADJUSTING ELECTRICAL FUSE PROGRAMMING VOLTAGE - The present invention provides a circuit for determining the optimal gate voltage for programming transistors. The determination of the optimal voltage compensates for the variations in the programming current due to process variations in manufacturing or due to ambient conditions. By applying the optimal gate voltage thus determined to the programming transistors of electrical fuses, the optimal level of current is passed through the electrical fuses to enable high yielding and reliable electrical fuse programming. | 2008-09-11 |
20080218248 | Circuit for Adjusting Reference Voltage Using Fuse Trimming - A binary bidirectional trimming circuit is disclosed. The trimming circuit includes: a first resistor set having 4 resistors in parallel connected and a first fuse bridged two ends thereto provide one trimming step; a second resistor set having 2 resistors in series connected and a second fuse bridged two ends thereto provide eight trimming steps; a third resistor set having 2 resistors in parallel connected and a third fuse bridged two ends thereto provide two trimming steps; a fourth resistor set having 1 resistor and a fourth fuse bridged two ends thereto provide four trimming steps; a first loading resistor; and a second loading resistor. The first resistor set, second resistor set, first loading resistor, third resistor set, the fourth resistor set, and the second loading resistor are in series connected. The output terminal is located at the nodes of the third resistor set and the first loading resistor so that the trimming steps provided by the third resistor set and the fourth resistor set are opposite to that of the first resistor set and the second resistor set. | 2008-09-11 |
20080218249 | Semiconductor device and trimming method therefor - Provided is a semiconductor device including a divisional resistor having a fuse, and a divisional resistor for measuring relative accuracy which is obtained by eliminating the fuse from the divisional resistor having the fuse. Characteristic values of the divisional resistor for measuring relative accuracy are measured so as to obtain trimming data, and then the divisional resistor having the fuse is trimmed, to thereby obtain a semiconductor device with highly precise characteristics. | 2008-09-11 |
20080218250 | CHARGE PUMP CIRCUIT - In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate −VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes −VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation. The positive electric potential generating charge pump circuit performs the normal operation, because the electric potential of the P-type semiconductor substrate is −VDD. After the output electric potential HV of the positive electric potential generating charge pump circuit reaches 2VDD, the negative electric potential generating charge pump circuit is put into a second operation mode (inverting HV). | 2008-09-11 |
20080218251 | Plasma television set and power supply circuit - A plasma television set includes a detection disabling circuit including a dividing resistance having one of two ends to which a constant voltage is supplied from an outside of the sustain voltage generation circuit and the other end which is grounded, the dividing resistance having a dividing point, and a diode having an anode connected to the dividing point of the second dividing resistance and a cathode connected to a dividing point of another dividing resistance, and a substitute voltage stop circuit including a resistance to which the predetermined starting voltage is supplied, an electrolytic capacitor having a positive electrode connected to the resistance and a negative electrode grounded, and a transistor having a base connected to the positive electrode of the electrolytic capacitor, an emitter grounded and a collector connected to the dividing point of the second dividing resistance. | 2008-09-11 |
20080218252 | VOLTAGE REGULATOR OUTPUTTING POSITIVE AND NEGATIVE VOLTAGES WITH THE SAME OFFSETS - A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit. | 2008-09-11 |
20080218253 | LOW POWER VOLTAGE REFERENCE - A voltage reference includes a first cell configured to receive a first proportional to absolute temperature (PTAT) current and a second cell configured to receive a second PTAT current. The first cell includes a diode-connected stack of insulated-gate field-effect transistors (IGFETs). The diode-connected stack of IGFETs includes a first transistor that is configured to be biased in a triode weak inversion region. The second cell includes a diode-connected stack of IGFETs and a serially coupled resistor. A magnitude of the second PTAT current is based on a drain-to-source voltage of the first transistor and a value of the serially coupled resistor. The voltage reference provides a reference voltage at a reference node of the second cell based on the second PTAT current. | 2008-09-11 |
20080218254 | Reduced jitter amplification methods and apparatuses - Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier. | 2008-09-11 |
20080218255 | Filter Characteristic Adjusting Apparatus and Filter Characteristic Adjusting Method - There is provided a filter characteristic adjusting apparatus and a filter characteristic adjusting method which can avoid an increase in circuit scale of the filter characteristic adjusting apparatus, and can speedily adjust a characteristic frequency of the filter to a desired frequency. When performing characteristic adjustment for the filter, the test signal generation unit ( | 2008-09-11 |
20080218256 | Channel Filtering in Radio Communications Systems - A system which provides frequency conversion and continuously variable bandwidth control is implemented using first and second filter networks that exhibit a generalised Chebyshev transfer function. The first and second filter networks may comprise a pseudo-high-pass type filter in combination with a pseudo-low-pass type filter, or in a particularly efficient embodiment, a pseudo-high-pass type filter in combination with an elliptic low pass type filter. | 2008-09-11 |
20080218257 | Distributed track-and-hold amplifier - An apparatus includes an analog input buffer having one or more inputs and one or more outputs, a plurality of differential track-and-hold stages, one or more input transmission lines, and one or more output transmission lines. Each track-and-hold stage has one or more inputs and one or more outputs. The one or more input transmission lines connect the one or more outputs of the differential analog input buffer to the inputs of the track-and-hold stages. The one or more output transmission lines connect to the outputs of the track-and-hold stages. The connections to the inputs of the stages are spatially distributed along the one or more input transmission lines, and connections to the outputs of the stages are spatially distributed along the one or more output transmission lines. | 2008-09-11 |
20080218258 | DIGITAL ISOLATOR - A signal isolator comprises an isolation barrier, a transmitter, a differentiator, and a recovery circuit. The transmitter is coupled to a first side of the isolation barrier and is configured to receive and convert an information signal to a differential signal that encodes information in the information signal in a single transition edge. The differentiator is coupled to a second side that is isolated from the first side of the isolation harrier and differentiates the differential signal. The recovery circuit is coupled to the differentiator and operates to recover an output information signal based on the information in the single transition edge. | 2008-09-11 |
20080218259 | Method and apparatus for distortion of audio signals and emulation of vacuum tube amplifiers - A method for digitally processing audio signals to emulate the effects of vacuum tube amplifiers and preamplifiers, musical instrument amplification systems, and distortion effects. By use of a parametrically-controlled non-linear transfer function, non-linear filters, feedback elements, and power-law function models, the dynamic behavior and distortion effects of tube amplification stages are simulated. This provides users with the capability to reproduce the desired sounds of vintage and modern tube amplifier systems and effects with the conveniences and control associated with digital signal processing systems and software. | 2008-09-11 |
20080218260 | MULTIPLE RF PATH AMPLIFIERS - An amplifier is disclosed for providing processing of a variable RF signal, the amplifier comprising a first parallel gain stage and a plurality of second parallel gain stages electrically disposed between an input fixed impedance matching circuit and an output fixed impedance matching circuit. Wherein in operation each of the first parallel gain stage and plurality of second parallel gain stages are for processing the variable RF signal according to at least a characteristic of the RF power or frequency range. Each of the plurality of second parallel gain stages comprising a tunable impedance matching circuit such that when the second parallel gain stage is in operation the tunable impedance matching circuit providing a transformation of impedance to match between the second amplifier and output fixed matching circuit within the frequency range, and other than providing a match within the frequency range when not in operation. | 2008-09-11 |
20080218261 | RF Power Amplifier Mirror Circuit for Sensing Current - An apparatus and method is disclosed for providing a mirror circuit for detecting a change in current of a RF power amplifier. The mirror circuit includes a voltage operably coupled with the mirror circuit, a bias circuit operably coupled with the mirror circuit, wherein the bias circuit is capable of applying a bias voltage to the mirror circuit, and an output reference signal. The output reference signal is proportional to the change of current in the RF power amplifier. | 2008-09-11 |
20080218262 | PREDISTORTION WITH ASYMMETRIC USAGE OF AVAILABLE BANDWIDTH - The invention relates to a method for performing predistortion of a radio frequency signal, said radio frequency signal comprising a wanted signal and a first and a second intermodulation distortion signal sideband, comprising: defining a predistortion window, positioning said predistortion window asymmetrically around said radio frequency signal, predistorting said radio frequency signal within the positioned predistortion window. | 2008-09-11 |
20080218263 | Wideband differential amplifier including single-ended amplifiers coupled to a four-port transformer - A differential amplifier is formed from a first single-ended amplifier circuit, a second single-ended amplifier circuit, and a four-port transformer circuit coupled to the first and second single-ended amplifier circuits to form the differential amplifier. | 2008-09-11 |
20080218264 | CLASS D AMPLIFIER ARRANGEMENT - An amplifier arrangement for operation at supply voltages of at least 100V and at output powers of at least 1 kW includes a half-bridge formed from two switching elements connected in series, two supply voltage terminals, and an output connection between the switching elements. A bypass capacitor is in parallel with the switching elements, and a current path is through the switching elements and the bypass capacitor, where the current path has a length of 10 cm or less, the half-bridge and the bypass capacitor are arranged on an area of 30 cm2, and a resonant circuit formed by capacitances and inductances in the current path has a resonance frequency of 100 MHz or greater. | 2008-09-11 |
20080218265 | Amplifier structures that enhance transient currents and signal swing - Amplifier embodiments are provided that are well suited for systems which require high signal gains and high transient currents that can drive various loads (e.g., capacitive loads). These embodiments are also well suited for electronic systems in which the available amplifier headroom is significantly limited. Exemplary systems are multiplying digital-to-analog converters in pipelined converter systems. | 2008-09-11 |
20080218266 | Amplifier circuit with input terminals thereof connected to sampling capacitors - Sampling capacitors are connected respectively to a pair of differential input terminals of an operational amplifier. The sampling capacitors sample input signals. Source terminals and drain terminals of dummy switches are connected respectively to paths connecting the operational amplifier and the sampling capacitors, so that a common-mode voltage of differential input voltages to the operational amplifier is adjusted by gate-channel capacitances. | 2008-09-11 |
20080218267 | Amplifier with level shifting feedback network - An amplifier circuit includes a low noise first stage and a wide dynamic range second stage. A feedback network coupled between the output of the second stage and the input of the first stage provides DC level shifting of the common mode input voltage. The common mode input voltage is shifted to a value that allows the output of the first stage to be compatible with the input of the second stage. | 2008-09-11 |
20080218268 | AUTOMATIC GAIN CONTROL CIRCUIT - An automatic gain control circuit for controlling the gain of a variable gain amplifier block includes a count control signal generating block, an up-down counter, a gain control signal generating block, and a downcount clock signal generating block. The up-down counter upcounts an upcount clock signal or downcounts a downcount clock signal according to a count control signal generated by the count control signal generating block. The gain control signal generating block generates a gain control signal corresponding to a count value of the up-down counter. The downcount clock signal generating block generates a downcount clock signal whose frequency corresponds to the count value of the up-down counter. | 2008-09-11 |
20080218269 | POWER AMPLIFIER CIRCUIT, CONTROL METHOD THEREOF AND CONTROL PROGRAM THEREOF - A power amplifier circuit includes a first variable gain amplifier for amplifying an input signal, a second variable gain amplifier for amplifying an output signal of the first amplifier, and a control circuit for controlling the gain of the first variable gain amplifier based on the output signal of the first variable gain amplifier and the gain of the second variable gain amplifier. | 2008-09-11 |
20080218270 | MULTI-MODE POWER AMPLIFIER WITH LOW GAIN VARIATION OVER TEMPERATURE - A multi-mode RF amplifier is described having at least a higher and a lower power path coupling an input to an output. At a pre-selected output power level, the higher power path is enabled while the lower power path is disabled when more output power is required. The process is reversed when less power is needed. The present invention matches the power gain variation over temperature characteristic of each path such that, especially at the cross over point, the gain delta (the difference in power gain between the two paths) has minimal variation over temperature. Such power gain characteristic is required for meeting the test requirements, specifically the inner loop power control, for third generation (3G) cellular handsets. | 2008-09-11 |
20080218271 | RF POWER AMPLIFIER PROTECTION - A circuit and method for protecting a radio frequency power amplifier against peak drain voltage. A detector circuit has an input connected to a drain of a power transistor of an amplification stage of the power amplifier to detect a peak drain voltage therefrom. The detector circuit outputs a protection signal when the detected peak drain voltage exceeds a predetermined reference level. A shutdown circuit is coupled to the detector circuit and inputs the protection signal therefrom. The protection signal is used to remove a gate bias of at least one amplification stage of the power amplifier. High frequency components are used in the detector and protection circuits to immediately reduce the drain voltage from one or more of the amplification stages. | 2008-09-11 |
20080218272 | WIDEBAND DIGITAL SINGLE-TO-DIFFERENTIAL CONVERTER AND METHOD OF FORMING SAME - A method and apparatus for single-to-differential conversion includes a single-to-differential stage ( | 2008-09-11 |
20080218273 | TUNABLE RF BANDPASS TRANSCONDUCTANCE AMPLIFIER - Aspects of the disclosure can provide a bandpass transconductance amplifier that can include a minuend transconductance amplifier that converts a voltage signal to a first current and a subtrahend transconductance amplifier that converts the voltage signal to a second current having substantially the same amplitude as the first current but opposite polarity in both a first and a second stopband. The second current can have a substantially smaller amplitude than the first current in a passband. The disclosed bandpass transconductance amplifier can also include a controller that can tune the passband and the stopbands and a summing circuit that can add the first current and the second current. | 2008-09-11 |
20080218274 | PHASE LOCKED LOOP AND DELAY LOCKED LOOP WITH CHOPPER STABILIZED PHASE OFFSET - A control circuit includes a phase frequency detector that receives a reference phase Φ | 2008-09-11 |
20080218275 | Systems and arrangements for operating a phase locked loop - Systems, methods and media for a fast locking phase locked loop (FLPLL) are disclosed. A FLPLL apparatus can include a voltage controlled oscillator (VCO) coupled to a phase frequency detector and can also include a frequency divider as part of a feedback loop. The VCO can accept a pull up voltage and a control signal from the phase frequency detector and provide an output clock signal to circuits that need synchronization. Such a configuration can greatly reduce the time the PLL requires to go from a dormant state to a fully operational state. During this start up mode, a frequency detection module can be utilized to detect an output frequency of the voltage controlled oscillator and when the VCO output frequency is not as high as a reference frequency, the frequency detection module can disabled the feedback loop during this start-up mode. | 2008-09-11 |
20080218276 | MEANS TO CONTROL PLL PHASE SLEW RATE - A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin. | 2008-09-11 |
20080218277 | Apparatus and method for operating a phase-locked loop circuit - An apparatus and method for operating a phase-locked loop circuit are disclosed. The phase locked loop circuit includes a plurality of resistive elements and a plurality of capacitive elements that are distributed in a charge pump, a loop filter and a voltage controlled oscillator. The plurality of resistive elements have a plurality of resistances that vary in proportion to each other. The plurality of capacitive elements have a plurality of capacitive elements that vary in proportion to each other. A damping factor of the phase-locked loop circuit is maintained substantially constant by the plurality of resistive elements and the plurality of capacitive elements. | 2008-09-11 |
20080218278 | MEANS TO CONTROL PLL PHASE SLEW RATE - A charge pump includes a multitude of current sources and current sinks adapted to supply current to or discharge current from a loop filter. The paths between current sources/sinks and the loop filter are selectively activated or deactivated to enable current to flow from the current source(s) to the loop filter or flow from the loop filter to the current sinks(s). Accordingly, the charge pump is adapted to provide more than one bandwidth depending on the bit levels of a select signal. The slew rate of a PLL in which the charge pump is disposed may thus be reduced. The charge pump optionally includes pulse-width limiting circuitry to limit the width of the pulses received from a phase/frequency detector. Accordingly, the slew rate of the PLL may further be reduced without changes in the open loop characteristics or losses in the phase margin. | 2008-09-11 |
20080218279 | Crystal oscillator temperature control and compensation - Crystal oscillator control and calibration is disclosed. Temperature and frequency control circuits included on a printed circuit board (PCB) comprising a crystal oscillator are used to determine, for each of a plurality of set points in a range of sensed internal temperatures sensed by an internal temperature sensing circuit or device located adjacent to the oscillator in a thermally insulated region of the PCB, a corresponding compensation required to be applied to maintain a desired oscillator output frequency. The PCB is configured to use at least the determined compensation values and a sensed internal temperature to determine during operation of the PCB a compensation, if any, to be applied to maintain the desired oscillator output frequency. | 2008-09-11 |
20080218280 | Differential Oscillator Device with Pulsed Power Supply, and Related Driving Method - The present invention concerns a differential oscillator device, comprising resonant electronic means, capable to provide on at least two terminals at least one oscillating signal V | 2008-09-11 |
20080218281 | Anodically Bonded Cell, Method for Making Same and Systems Incorporating Same - A cell suitable for use with an atomic clock and a method for making the same, the cell including: a silicon wafer having a recess formed therein; at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon sealing the recess; and, an alkali metal containing component and buffer gas contained in the recess. The method includes: providing a silicon wafer; forming a cavity through the silicon wafer; introducing an alkali metal containing component and buffer gas into the cavity; and, anodically bonding at least one amorphous silicate member having an ion mobility and temperature expansion coefficient approximately that of silicon to the wafer to close the cavity. | 2008-09-11 |
20080218282 | Hybrid Stochastic Gradient Based Digitally Controlled Oscillator Gain KDCO Estimation - A novel hybrid stochastic gradient adaptation apparatus and method for calibrating the gain of an RF or non-RF digitally controlled oscillator (DCO). The adaptation algorithm determines a true stochastic gradient between a forcing function and its corresponding system measure to estimate the system parameters being adapted. A momentum term is generated and injected into the adaptation algorithm in order to stabilize the algorithm by adding inertia against any large transient variations in the input data. In the case of adaptation of DCO gain K | 2008-09-11 |
20080218283 | Triangular wave generating circuit, and charging and discharging control circuit - A triangular wave generating circuit capable of reducing a time lag between the time of input of a discharging start signal and the time of start of actual discharging is provided. A charging and discharging circuit of the triangular wave oscillation circuit includes: an inverter circuit; a discharging reference potential generating circuit; a first NMOS transistor having a drain connected with a connection point between a first current source circuit and the capacitor, and a gate connected with the discharging reference potential generated by the discharging reference potential generating circuit; a second NMOS transistor having a gate inputted with the switching signal through the inverter circuit, a drain connected with the gate of the first NMOS transistor, and a source connected with a source of the first NMOS transistor; and a third NMOS transistor having a gate inputted with the switching signal, a drain connected with a connection point between the source of the first NMOS transistor and the source of the second NMOS transistor, and a source grounded. | 2008-09-11 |
20080218284 | Circuit and method for switching PFM and PWM - The switching method between pulse frequency modulation and pulse width modulation signals is first based on an output voltage of a power transistor to generate a corresponding pulse frequency modulation signal. Next, it is determined whether the corresponding pulse frequency modulation signal has reached its maximal frequency. If so, the initial pulse width modulation signal is adjusted to have the same width as the pulse frequency modulation signal. Thereafter, the adjusted pulse width modulation signal is outputted. | 2008-09-11 |
20080218285 | High-speed digital transmission signle line - A high-speed digital transmission signal line providing better dynamic resistance to be applied in an LVDS transmission system and functioning as an electronic line, an optical line, and a serial advanced technology attachment (SATA) includes a conductive layer in thickness of 0.018˜0.1 mm and in width of 0.2˜0.8 mm; a first and a second insulation layers each in thickness of 0.04˜0.3 mm being respectively disposed on both sides of the conductive layer; and a ground plate. | 2008-09-11 |
20080218286 | Compact Automatic Impedance Adapter in a Waveguide - The invention relates to a compact automatic impedance adapter in a waveguide, characterised in that the impedance is controlled by plungers, filling the entire guide with a magic-tee coupler plane E/plane H modifying the electrical and magnetic field, one plunger modifying the electrical field (E) in the guide and the second modifying the magnetic field (H). | 2008-09-11 |
20080218287 | CIRCUIT AND METHOD FOR ADJUSTING IMPEDANCE - An impedance adjusting circuit includes a semiconductor device accommodated in a semiconductor device case which has case pins and having a folded conductive line; an external reference resistor connected between a positive power supply line and a first one of the case pins, wherein a first line between the first case pin and the semiconductor device has a specific resistance; a first reference voltage generation resistor connected between the power supply line and a second one of the case pins; a second reference voltage generation resistor connected between the ground and a third one of the case pins; a resistance circuit comprising a second line between the second case pin and the folded conductive line and a third line between the third case pin and the folded conductive line, wherein a resistance between the second case pin and the third case pin is equal to the specific resistance; and a fourth line connected from the semiconductor device to the ground through the second reference voltage generation resistor and having a resistance equal to the specific resistance. The semiconductor device includes an adjusting circuit having a buffer and configured to adjust an output impedance of the buffer to be adaptive for a predetermined impedance. | 2008-09-11 |
20080218288 | NONRECIPROCAL CIRCUIT DEVICE - A nonreciprocal circuit device includes a ferrite to which a direct magnetic field is applied using permanent magnets, central electrodes arranged on the ferrite, and a circuit substrate. The first central electrode is made of conductive films, and the second central electrode is made of conductive films. Some of the conductive films of the second central electrode are arranged on the first main surface of the ferrite, and a conductive film of the first central electrode is arranged on the conductive films through an insulating film. Furthermore, another one of the conductive films of the first central electrode is arranged on the second main surface, and the remainder of the conductive films of the second central electrode are arranged through an insulating film on the conductive film. | 2008-09-11 |
20080218289 | NONRECIPROCAL CIRCUIT DEVICE AND MANUFACTURING METHOD OF THE SAME - A nonreciprocal circuit device includes permanent magnets, a ferrite to which a direct current magnetic field is applied by the permanent magnets, first and second central electrodes arranged on the ferrite, and a circuit substrate. A ferrite-magnet assembly mounted on the circuit substrate is covered with a resin layer. The resin layer includes an innermost layer made of a non-magnetic resin material and a magnetic resin layer having a magnetic filler mixed therein. | 2008-09-11 |
20080218290 | Automatic Driver/Transmission Line/Receiver Impedance Matching Circuitry - An impedance matcher that automatically matches impedance between a driver and a receiver. The impedance matcher includes a phase-locked loop (PLL) circuit that locks onto a data signal provided by the driver. The impedance matcher also includes tunable impedance matching circuitry responsive to one or more voltage-controlled oscillator control signals within the PLL circuit so as to generate an output signal that is impedance matched with the receiver. | 2008-09-11 |
20080218291 | System and method for a digitally tunable impedance matching network - The present disclosure relates generally to digitally tunable impedance matching networks. In one example, a digitally tunable impedance matching network is configured to produce an overall reactance value of approximately X, and includes multiple reactive components that are configured to produce a reactance value in the range of approximately zero to X with a minimum resolution of approximately X/2 | 2008-09-11 |
20080218292 | Low voltage data transmitting circuit and associated methods - A low voltage data transmitting circuit (LVDTC) may be connected to a first transmission line that transmits a first voltage signal to a receiver and a second transmission line that transmits a second voltage signal to the receiver. The LVDTC includes a first resistor coupled to the first transmission line, a second resistor coupled to the second transmission line, and a control unit coupled to the first transmission line and the second transmission line, the control unit being configured to control voltage levels of the first and second voltage signals such that the voltage levels of the first and second voltage signals are higher than a ground voltage level of the receiver, wherein the first and second voltage signals may constitute a differential pair. | 2008-09-11 |
20080218293 | High Frequency Electromagnetic Wave Receiver and Broadband Waveguide Mixer - The present invention provides a broadband waveguide mixer, comprising: a waveguide having a substantially v-shaped groove in its inner surface; a broadband antenna coupling in the V-groove; and mixing means for mixing signals received by the broadband antenna. The present invention further provides a high frequency electromagnetic wave receiver comprising the aforesaid broadband waveguide mixer. The broadband waveguide mixer and the high frequency electromagnetic wave receiver have the advantages of broad single mode operating frequency band, lower loss, lower noise, and they can be easily produced and assembled to lower cost. | 2008-09-11 |
20080218294 | Three-way splitter including a printed element - According to one exemplary embodiment, a three-way splitter includes a printed element and a resistive network comprising discrete resistors. A first printed branch, second printed branch, and third printed branch distribute a received communication signal to respective outputs having substantially the same phase, frequency, and impedance. Each printed branch includes a number of substantially ninety-degree angles. In one embodiment, the printed branches are quarter wavelength transmission lines in a frequency range of 1.5 GHz. In one embodiment, the three-way splitter consumes less than one square inch of surface area on a printed circuit board, and can be used in a satellite receiving system, for example. In this embodiment, the three-way splitter is utilized for frequencies in the range of approximately 900 MHz to 2.2 GHz. | 2008-09-11 |
20080218295 | MEMS resonator array structure and method of operating and using same - A plurality of mechanically coupled MEMS resonators that are arranged in an N x M MEMS array structure. Each MEMS resonators includes a plurality of straight (or substantially straight) elongated beam sections that are connected by curved/rounded sections. Each elongated beam section is connected to another elongated beam section at a distal end via the curved/rounded sections thereby forming a geometric shape (e.g., a rounded square). Further, each resonator is mechanically coupled to at least one other adjacent resonator of the array via a resonator coupling section. The resonator coupling sections may be disposed between elongated beam sections of adjacent resonators. The resonators, when induced, oscillate at the same or substantially the same frequency. The resonators oscillate in a combined elongating (or breathing) mode and bending mode; that is, the beam sections exhibit an elongating-like (or breathing-like) motion and a bending-like motion. The one or more of the resonators of the array structure may include one or more nodal points or areas (i.e., portions of the resonator that are stationary, experience little movement, and/or are substantially stationary during oscillation of the resonator/array) in one or more portions or areas of the curved sections of the structure. The nodal points are suitable and/or preferable locations to anchor the resonator/array to the substrate. | 2008-09-11 |
20080218296 | ELECTRICAL SWITCHING APPARATUS, AND CONDUCTOR ASSEMBLY AND SHUNT ASSEMBLY THEREFOR - A shunt assembly is provided for an electrical switching apparatus including a conductor assembly having a load conductor and a movable contact assembly with a number of movable contact arms. The movable contact assembly is movable in response to a fault current. The shunt assembly includes a number of flexible conductive elements each having a first end electrically connected to the load conductor, a second end electrically connected to a corresponding one of the movable contact arms, and a number of bends disposed between the first and second ends. At least one constraint element is disposed proximate a corresponding one of the bends and constrains movement of the flexible conductive element in response to the fault current, thereby translating the magnetic repulsion force associated with the fault current into a corresponding torque of the movable contact arms of the movable contact assembly. | 2008-09-11 |
20080218297 | CASE FOR CIRCUIT BREAKER WITH MONOLITHIC DOOR - In a case for a circuit breaker in which a terminal is simply replaceable or mountable according to a wiring method of the circuit breaker, the case comprises a case which accommodates components for breaking a circuit, a terminal block portion which provides a common platform for plural types of terminals, and a door engaged with the case in monolithic form so that it may be operable to a closed position for closing the case or an opened position for installing a selected terminal of the plural types of terminals. | 2008-09-11 |
20080218298 | Sealed Rare Earth Magnet and Method for Manufacturing the Same - It is an object of the present invention to provide a rare earth magnet that will not decompose due to hydrogen embrittlement when used in a hydrogen gas atmosphere, and furthermore, does not pose the risk of contaminating a reaction bath with the surface treated film of the magnet. The present invention provides a sealed rare earth magnet comprising: a rare earth magnet; and a case of aluminum or aluminum alloy, wherein the case covers entirety of the rare earth magnet and is sealed by HIP; and the methods for manufacturing the same. | 2008-09-11 |
20080218299 | Method and Structure for Magnetically-Directed, Self-Assembly of Three-Dimensional Structures - A magnetically directed, self-assembled structure has a first body. The first body includes a single magnet or plurality of magnets disposed thereon to form a spatially variable magnetic field in a first predetermined pattern. A second body has a single magnet or plurality of magnets disposed thereon to form a spatially variable magnetic field in a second predetermined pattern. The second predetermined pattern is complementary to the first pattern. The first body is attracted to the second body with an attractive force greater than a mixture force such that the first body and second body are fully aligned to each other and bonded together. | 2008-09-11 |
20080218300 | Transformer - The invention relates to a transformer ( | 2008-09-11 |
20080218301 | MULTILAYER COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME - A multilayer coil component includes a coil formed by stacking first ceramic sheets in which coil conductor patterns are provided and a second ceramic sheet having a lower magnetic permeability than the first ceramic sheets, the coil conductor patterns being connected to each other. The second ceramic sheet is disposed between the first ceramic sheets. In a main surface of the second ceramic sheet, holes or recesses are provided. The first ceramic sheets adjacent to the second ceramic sheet are in contact with inner peripheral surfaces of the holes. | 2008-09-11 |
20080218302 | Inductive conductivity sensor - A conductivity sensor for measuring conductivity of a medium surrounding the conductivity sensor includes a first toroidal coil bounding a medium-receiving passageway and serving for inducing an electrical current in the medium, and a second toroidal coil also bounding the passageway and serving for registering a magnetic field produced by the electrical current. At least one of the toroidal coils has a plurality of first conductor segments, which extend in a plane of a multi-ply circuit board, a plurality of second conductor segments, which extend in a second plane of the circuit board, and a plurality of through-contacts, which connect the first conductor segments with the second conductor segments, wherein the first conductor segments, the second conductor segments and the through-contacts form, together, the windings of a toroidal coil. | 2008-09-11 |
20080218303 | COIL OF A FORCE-MEASURING SYSTEM, AND METHOD OF MANUFACTURING THE COIL - A multi-layered electromagnetic coil for a force-measuring system is based upon the principle of electromagnetic force compensation, as is a method for manufacturing the coil. The coil has a multifilar, specifically bifilar, wiring arrangement of coil wires. Preferably, the coil wires have a substantially rectangular cross-sectional profile. The cross-sectional profile of the coil wire is designed for achieving the densest possible packing of the windings in the coil can be achieved. | 2008-09-11 |
20080218304 | WATER RESISTANT IN-LINE FUSE HOLDER - Embodiments for an in-line fuse holder each include at least one housing and two mating pieces, which can snap-fit together and be held moveably together via a strap. Each embodiment houses at least one fuse, such as an automotive fuse. In one example, the fuse includes a first housing forming a first cavity, which is configured to house a first portion of the fuse. The first housing also includes a projection having sides that taper outwardly as the sides extend away from the first housing. The fuse holder also includes a second housing forming a second cavity, which is configured to house a second portion of the fuse. The second housing includes a channel having sides that taper outwardly as the sides extend into the second housing. The projection and channel snap-fit together in a water resistant relationship. | 2008-09-11 |