36th week of 2014 patent applcation highlights part 33 |
Patent application number | Title | Published |
20140248718 | PATTERNING OF MAGNETIC TUNNEL JUNCTION (MTJ) FILM STACKS - Chemical modification of non-volatile magnetic random access memory (MRAM) magnetic tunnel junctions (MTJs) for film stack etching is described. In an example, a method of etching a MTJ film stack includes modifying one or more layers of the MTJ film stack with a phosphorous trifluoride (PF | 2014-09-04 |
20140248719 | MTJ MANUFACTURING METHOD UTILIZING IN-SITU ANNEALING AND ETCH BACK - The present invention is directed to a method for manufacturing spin transfer torque magnetic random access memory (STTMRAM) devices. The method, which utilizes in-situ annealing and etch-back of the magnetic tunnel junction (MTJ) film stack, comprises the steps of depositing a barrier layer on top of a bottom magnetic layer and then depositing an interface magnetic layer on top of the barrier layer to form an MTJ film stack; annealing the MTJ film stack at a first temperature and then cool the MTJ film stack to a second temperature lower than the first temperature; etching away a top portion of the interface magnetic layer; and depositing at least one top layer on top of the etched interface magnetic layer. The method may further include the step of annealing the MTJ film stack at a third temperature between the first and second temperature after the step of depositing at least one top layer. | 2014-09-04 |
20140248720 | DEVICE FOR DETERMINING THE TEMPERATURE OF A SUBSTRATE - An apparatus for determining the temperature of a substrate, in particular of a semiconductor wafer during a heating thereof by means of a first radiation source is described. Furthermore, an apparatus and a method for thermally treating substrates are described, in which the substrate is heated by means of at least one first radiation source. The apparatus comprises a first grating structure having grating lines, which are opaque with respect to a substantial portion of the radiation of the first radiation source, wherein the grating structure is arranged between the first radiation source and the substrate, and a drive unit for moving the first grating structure. Furthermore, a first radiation detector is provided, which is directed directly onto the surface of the substrate facing the grating structure, and a device for determining radiation emitted by the substrate due to its own temperature and for determining the temperature of the substrate on the basis of the radiation detected by the first radiation detector. | 2014-09-04 |
20140248721 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A method of manufacturing a semiconductor device according to the present invention includes, in a silicon substrate of the semiconductor chip, providing two TSVs (Through-Silicon-Vias) that are formed such that interfaces with the silicon substrate are covered with insulating films and bottom surface sides thereof do not penetrate through the silicon substrate, providing a high concentration impurity region in a peripheral region of the bottom surface sides of the TSVs in the silicon substrate, connecting a test circuit to the TSVs, inputting a test signal from one of the TSVs and detecting the test signal output via the high concentration impurity region and the other TSV, thereby evaluating a failure of the semiconductor chip, thinning a bottom surface of the semiconductor chip and removing the high concentration impurity region. | 2014-09-04 |
20140248722 | Packaging and Function Tests for Package-on-Package and System-in-Package Structures - A method includes placing a plurality of bottom units onto a jig, wherein the plurality of bottom units is not sawed apart and forms an integrated component. Each of the plurality of bottom units includes a package substrate and a die bonded to the package substrate. A plurality of upper component stacks is placed onto the plurality of bottom units, wherein solder balls are located between the plurality of upper component and the plurality of bottom units. A reflow is performed to join the plurality of upper component stacks with respective ones of the plurality of bottom units through the solder balls. | 2014-09-04 |
20140248723 | WAFER SCALE PACKAGING PLATFORM FOR TRANSCEIVERS - A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules. | 2014-09-04 |
20140248724 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGES - A method for manufacturing LED packages includes steps: providing a lead frame including many pairs of first, second electrodes and first and second tie bars, the first electrodes and second electrodes each including a main body and an extension electrode protruding outward from the main body; forming many molded bodies to engage with the first and second electrodes, the first and second main bodies being embedded into the molded bodies, and the first and second extension electrodes being exposed out from a periphery of the molded body; preforming two first through grooves at joints where each first electrode meets the first tie bar and two second through grooves at joints where each second electrode meets the second tie bar; disposing LED dies in corresponding receiving cavities; and cutting the molded bodies through the grooves to obtain a plurality of individual LED packages. | 2014-09-04 |
20140248725 | METHOD FOR MANUFACTURING LIGHT EMITTING DIODE PACKAGES - A method for manufacturing LED packages includes steps: providing a lead frame including many pairs of first and second electrodes, and first and second tie bars, the first electrodes and second electrodes each including a main body and an extension electrode protruding outward from the main body; forming many molded bodies to engage with the pairs of the first and second electrodes, the first and second main bodies being embedded into the molded bodies, and the first and second extension electrodes being exposed out from a corresponding molded body; preforming many first grooves at a bottom of each molded body; disposing LED dies in the corresponding receiving cavities; and cutting the molded bodies along edges thereof defining the first grooves in a first direction and then along a second direction perpendicular to the first direction to obtain many individual LED packages. | 2014-09-04 |
20140248726 | METHOD FOR FABRICATING THE OLED USING ROLL TO ROLL PROCESSING - A method for fabricating the OLED including a color conversion layer using roll-to-roll processing is provided. To elaborate, the method for fabricating an OLED comprising: bonding an OLED and an inorganic phosphor to each other through roll-to-roll processing is provided, wherein the inorganic phosphor is provided as a color conversion layer. | 2014-09-04 |
20140248727 | Flexible Lighting Devices - A first device and methods for manufacturing the first device are provided. The first device may comprise a flexible substrate and at least one organic light emitting device (OLED) disposed over the flexible substrate. The first device may have a flexural rigidity between 10 | 2014-09-04 |
20140248728 | OPTOELECTRONIC DEVICE WITH LIGHT DIRECTING ARRANGEMENT AND METHOD OF FORMING THE ARRANGEMENT - An optoelectronic device comprises a body of an indirect bandgap semiconductor material having a surface and a photon active region on one side of the surface. A light directing arrangement is formed integrally with the body on an opposite side of the surface. | 2014-09-04 |
20140248729 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a substrate and a stacked body on the substrate via a joining metal layer. The stacked body includes a device portion and a peripheral portion. The device portion includes from a bottommost layer to a topmost layer included in the stacked body. The peripheral portion surrounding and provided around the device portion; the peripheral portion is a portion of the bottommost layer to the topmost layer included in the stacked body and includes a portion of a semiconductor layer in contact with the joining metal layer. | 2014-09-04 |
20140248730 | MEMS Device and Method of Formation Thereof - The present disclosure provides a method including providing a first substrate; and forming a microelectromechanical system (MEMS) device on a first surface of the first substrate. A bond pad is formed on at least one bonding site on the first surface of the first substrate. The bonding site is recessed from the first surface. Thus, a top surface of the bond pad may lie below the plane of the top surface of the substrate. A device with recessed connective element(s) (e.g., bond pad) is also described. In further embodiments, a protective layer is formed on the recessed connective element during dicing of a substrate. | 2014-09-04 |
20140248731 | APPARATUS INTEGRATING MICROELECTROMECHANICAL SYSTEM DEVICE WITH CIRCUIT CHIP AND METHODS FOR FABRICATING THE SAME - One embodiment discloses an apparatus integrating a microelectromechanical system device with a circuit chip which includes a circuit chip, a microelectromechanical system device, a sealing ring, and a lid. The circuit chip comprises a substrate and a plurality of metal bonding areas. The substrate has an active surface with electrical circuit area, and the metal bonding areas are disposed on the active surface and electrically connected to the electrical circuits. The microelectromechanical system device comprises a plurality of bases and at least one sensing element. The bases are connected to at least one of the metal bonding areas. The at least one sensing element is elastically connected to the bases. The sealing ring surrounds the bases, and is connected to at least one of the metal bonding areas. The lid is opposite to the active surface of the circuit chip, and is connected to the sealing ring to have a hermetic chamber which seals the sensing element and the active surface of the circuit chip. | 2014-09-04 |
20140248732 | LIQUID CRYSTAL DISPLAY DEVICE HAVING TOUCH SENSOR EMBEDDED THEREIN, METHOD OF DRIVING THE SAME AND METHOD OF FABRICATING THE SAME - A liquid crystal display device having a touch sensor embedded therein is disclosed. The present invention includes a liquid crystal layer between first and second substrates, a pixel on the second substrate to apply a horizontal electric field to the liquid crystal layer, a touch sensor on the second substrate, the touch sensor detecting a touch by forming a touch capacitor with a touch object for touching the first substrate, and a readout line outputting a sensing signal from the touch sensor. The touch sensor includes a sensing electrode on the second substrate to form the sensing capacitor with the touch object, first and second sensor gate lines, a first sensor thin film transistor supplying a sensing driving voltage to the sensing electrode in response to a control of the first sensor gate line, and a second sensor thin film transistor supplying electric charges of the sensing electrode as the sensing signal in response to a control of the second sensor gate line. | 2014-09-04 |
20140248733 | METHOD OF MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE - The present invention provides a method of manufacturing a photoelectric conversion device for forming a semiconductor layer on a substrate by the plasma CVD method. The method includes a first plasma processing step in which a processing temperature reaches a first temperature; a second plasma processing step in which the processing temperature reaches a second temperature; a temperature regulating step of lowering the processing temperature to a third temperature lower than the first temperature and the second temperature after the first plasma processing step and before the second plasma processing step; and a temperature raising step of raising the processing temperature from the third temperature to the second temperature. The first plasma processing step, the temperature regulating step, the temperature raising step, and the second plasma processing step are carried out within the same reaction chamber. | 2014-09-04 |
20140248734 | CMOS Image Sensors and Methods for Forming the Same - A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions. | 2014-09-04 |
20140248735 | THIN-FILM ENCAPSULATED INFRARED SENSOR - A method of fabricating a bolometer infrared sensor includes depositing a first sacrificial layer on a surface of a substrate over a sensor region, and forming an absorber structure for the infrared sensor on top of the first sacrificial layer. A second sacrificial layer is deposited on top of the absorber structure. An encapsulating thin film is then deposited on top of the second sacrificial layer. Vent holes are formed in the encapsulating thin film. The first and the second sacrificial layers are removed below the encapsulating thin film to release the absorber structure and form a cavity above the sensing region that extends down to the substrate in which the absorber structure is located via the vent holes. The vent holes are then closed in a vacuum environment to seal the absorber structure within the cavity. | 2014-09-04 |
20140248736 | Method Of Forming A Low Profile Image Sensor Package - An image sensor package, and method of making same, that includes a printed circuit board having a first substrate with an aperture extending therethrough, one or more circuit layers, and a plurality of first contact pads electrically coupled to the one or more circuit layers. A sensor chip mounted to the printed circuit board and disposed at least partially in the aperture. The sensor chip includes a second substrate, a plurality of photo detectors formed on or in the second substrate, and a plurality of second contact pads formed at the surface of the second substrate which are electrically coupled to the photo detectors. Electrical connectors each electrically connect one of the first contact pads and one of the second contact pads. A lens module is mounted to the printed circuit board and has one or more lenses disposed for focusing light onto the photo detectors. | 2014-09-04 |
20140248737 | METHOD OF MANUFACTURING OPTICAL IMAGE STABILIZER - A method of manufacturing an optical image stabilizer including providing a silicon-on-insulator (SOI) substrate that includes first and second silicon each provided on an upper surface and a lower surface of the substrate, having an insulator layer therebetween, forming a table, a cantilever arm connected to the table, an anchor connected to the cantilever arm, and an electrode opposite to the cantilever arm by etching the first silicon, allowing the table and the cantilever arm to levitate from the second silicon by removing an insulator layer disposed under the table and the cantilever arm, and mounting an image sensor on the table. | 2014-09-04 |
20140248738 | Method of P-Type Doping of Cadmium Telluride - A method of p-type doping cadmium telluride (CdTe) is disclosed. The method comprising the steps of, (a) providing a first component comprising cadmium telluride (CdTe) comprising an interfacial region, and (b) subjecting the CdTe to a functionalizing treatment to obtain p-type doped CdTe, said functionalizing treatment comprising a thermal treatment of at least a portion of the interfacial region in the presence of a first material comprising a p-type dopant, and of a second material comprising a halogen. A method of making a photovoltaic cell is also disclosed. | 2014-09-04 |
20140248739 | HEATING A FURNACE FOR THE GROWTH OF SEMICONDUCTOR MATERIAL - A multi-ingot furnace for the growth of crystalline semiconductor material has one or more heating devices for heating a hot zone in which crucibles containing semiconductor material are received. At least one of the heating devices is arranged to apply a predetermined differential heat flux profile across a horizontal cross-section of the semiconductor material in one or more of the crucibles, the predetermined differential heat flux profile being selected in dependence the position of the one or more crucibles in an array. In this manner, the heating device can at least partially compensate for differences in the temperature across the semiconductor material that arises from its geometric position in the furnace. This reduces the possibility of defects such as dislocations during the growth of a crystalline semiconductor material. Associated methods are also disclosed. | 2014-09-04 |
20140248740 | MIXED VALENT OXIDE MEMORY AND METHOD - Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure. | 2014-09-04 |
20140248741 | PACKAGE-ON-PACKAGE ASSEMBLY AND METHOD - A package-on-package (PoP) assembly is provided. The package-on-package (PoP) assembly includes a first integrated circuit package and an anisotropic conductive film (ACF) disposed on a top surface of the first integrated circuit package, wherein the anisotropic conductive film comprises a plurality of conductive particles. The package-on-package (PoP) assembly also includes a second integrated circuit package disposed on a top surface of the anisotropic conductive film. | 2014-09-04 |
20140248742 | MULTI-CHIP PACKAGE HAVING A SUBSTRATE WITH A PLURALITY OF VERTICALLY EMBEDDED DIE AND A PROCESS OF FORMING THE SAME - An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate. | 2014-09-04 |
20140248743 | SEMICONDUCTOR MEMORY MODULES AND METHODS OF FABRICATING THE SAME - The inventive concept provides semiconductor memory modules and methods of fabricating the same. The semiconductor memory module may include a module board having a first surface and a second surface opposite to the first surface, and memory chips mounted directly on the module board by a flip-chip bonding method. Each of the memory chips may include a passivation layer disposed on a rear surface of each of the memory chips, and the passivation layer may have a color different from a natural color of single-crystalline silicon. | 2014-09-04 |
20140248744 | SEMICONDUCTOR SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device, which prevents waste generation from being caused peeling of films and prevents failure of peeling from being caused by waste due to peeling of films. A first semiconductor substrate is used which has a structure in which a peeling layer is not formed in a section subjected to a first dividing treatment, so that the peeling layer is not exposed at the end surface of a second semiconductor substrate when the second semiconductor substrate is cut out of the first semiconductor substrate. In addition, a supporting material is provided on a layer to be peeled of the second semiconductor substrate before the second semiconductor substrate is subjected to a second dividing treatment. | 2014-09-04 |
20140248745 | Three-Dimensional Integrated Circuit (3DIC) - An embodiment 3DIC device includes a semiconductor chip, a die, and a polymer. The semiconductor chip includes a semiconductor substrate, wherein the semiconductor substrate comprises a first edge, and a dielectric layer over the semiconductor substrate. The die is disposed over and bonded to the semiconductor chip. The polymer is molded onto the semiconductor chip and the die. The polymer includes a portion level with the dielectric layer, wherein the portion of the polymer comprises a second edge vertically aligned to the first edge of the semiconductor substrate and a third edge contacting the dielectric layer, wherein the second and the third edges are opposite edges of the portion of the polymer. | 2014-09-04 |
20140248746 | MAKING A FLIP-CHIP ASSEMBLY WITH BOND FINGERS - A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. Applying a transversely extending solder resist strip over the first longitudinal end portions of the bond fingers. The strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps. Each tooth portion and each gap aligned with a different one of the bond fingers in each adjacent pair of bond fingers. | 2014-09-04 |
20140248747 | CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING - In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead. | 2014-09-04 |
20140248748 | DISPLAY DEVICE - A display device for improving an aperture ratio of the pixel is provided. In the display device, a transparent oxide layer, an insulating film, and a conductive layer are sequentially stacked on a pixel region on a substrate, the conductive layer has a gate electrode of a thin film transistor connected to a gate signal line, and a region of the transparent oxide layer other than at least a channel region portion directly below the gate electrode is converted into an electrically conductive region, and a source signal line, a source region portion of the thin film transistor connected to the source signal line, a pixel electrode, and a drain region portion of the thin film transistor connected to the pixel electrode are formed from the conductive region. | 2014-09-04 |
20140248749 | STRESS MEMORIZATION TECHNIQUE - A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process. | 2014-09-04 |
20140248750 | VERTICAL TYPE SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A vertical memory device and a method of fabricating the same are provided. The vertical type semiconductor device includes a common source region formed in a cell area of a semiconductor substrate. A channel region is formed on the common source region. The channel region has a predetermined height and a first diameter. A drain region is formed on the channel region. The drain region has a predetermined height and a second diameter larger than the first diameter. A first gate electrode surrounding the channel region. | 2014-09-04 |
20140248751 | METHOD AND APPARATUS FOR ENHANCING CHANNEL STRAIN - An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers. The second gate structure includes a high-k dielectric layer adjacent the second channel region, and a metal layer. | 2014-09-04 |
20140248752 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE HAVING SPACER ELEMENTS - The present disclosure describes a method of fabricating semiconductor device including providing a semiconductor substrate and a gate stack disposed on the semiconductor substrate. A first spacer element is formed on the substrate abutting the first gate stack. In an embodiment, a source/drain region is then formed. A second spacer element is then formed is adjacent the first spacer element. The second spacer element has a second height from the surface of the substrate, and the first height is greater than the second height. In embodiments, the second spacer element is used as an etch stop in forming a contact to the source/drain region. | 2014-09-04 |
20140248753 | ANALOG TRANSISTOR - An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped | 2014-09-04 |
20140248754 | CONTROLLED AIR GAP FORMATION - A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps. | 2014-09-04 |
20140248755 | METHODS OF FABRICATING NONVOLATILE MEMORY DEVICES INCLUDING VOIDS BETWEEN ACTIVE REGIONS AND RELATED DEVICES - A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed. | 2014-09-04 |
20140248756 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, the method including providing a substrate; forming a field trench in the substrate; and forming a diffusion barrier region under the field trench, wherein the diffusion barrier region includes carbon. | 2014-09-04 |
20140248757 | WAFER PROCESSING METHOD - A wafer processing method for dividing a wafer along a plurality of division lines to obtain a plurality of individual chips. The wafer processing method includes a filament forming step of applying a pulsed laser beam having a transmission wavelength to the wafer along each division line in the condition where the focal point of the pulsed laser beam is set inside the wafer in a subject area to be divided, thereby forming a plurality of amorphous filaments inside the wafer along each division line, and an etching step of etching the amorphous filaments formed inside the wafer along each division line by using an etching agent to thereby divide the wafer into the individual chips along the division lines. | 2014-09-04 |
20140248758 | METHOD OF SEVERING A SEMICONDUCTOR DEVICE COMPOSITE - A method of severing a semiconductor device composite includes a carrier having a main surface and a semiconductor layer sequence arranged on the main surface including forming a separating trench in the semiconductor device composite by a first laser cut such that the separating trench only partially severs the semiconductor device composite in a vertical direction running perpendicular to the main surface, and severing the semiconductor device composite completely along the separating trench with a severing cut with a laser. | 2014-09-04 |
20140248759 | SAFE HANDLING OF LOW ENERGY, HIGH DOSE ARSENIC, PHOSPHORUS, AND BORON IMPLANTED WAFERS - A method of preventing toxic gas formation after an implantation process is disclosed. Certain dopants, when implanted into films disposed on a substrate, may react when exposed to moisture to form a toxic gas and/or a flammable gas. By in-situ exposing the doped film to an oxygen containing compound, dopant that is shallowly implanted into the layer stack reacts to form a dopant oxide, thereby reducing potential toxic gas and/or flammable gas formation. Alternatively, a capping layer may be formed in-situ over the implanted film to reduce the potential generation of toxic gas and/or flammable gas. | 2014-09-04 |
20140248760 | METHODS OF FORMING DUAL GATE STRUCTURES - Semiconductor devices including dual gate structures and methods of forming such semiconductor devices are disclosed. For example, semiconductor devices are disclosed that include a first gate stack that may include a first conductive gate structure formed from a first material, and a second gate stack that may include a dielectric structure formed from an oxide of the first material. For another example, methods including forming a high-K dielectric material layer over a semiconductor substrate, forming a first conductive material layer over the high-K dielectric material layer, oxidizing a portion of the first conductive material layer to convert the portion of the first conductive material layer to a dielectric material layer, and forming a second conductive material layer over both the conductive material layer and the dielectric material layer are also disclosed. | 2014-09-04 |
20140248761 | SEMICONDUCTOR DEVICE HAVING DUAL METAL SILICIDE LAYERS AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is manufactured using dual metal silicide layers. The semiconductor device includes a substrate having first and second regions, a first metal gate electrode on the substrate in the first region, a second metal gate electrode on the substrate in the second region, a first epitaxial layer on and in the substrate at both sides of the first metal gate electrode, a second epitaxial layer on and in the substrate at both sides of the second metal gate electrode, a first metal silicide layer on the first epitaxial layer, a second metal silicide layer on the second epitaxial layer, an interlayer dielectric layer on the first and second metal silicide layers, contact plugs passing through the interlayer dielectric layer and electrically connected to the first and second metal silicide layers. | 2014-09-04 |
20140248762 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device comprises the following steps. First, a substrate is provided, at least one fin structure is formed on the substrate, and a metal layer is then deposited on the fin structure to form a salicide layer. After depositing the metal layer, the metal layer is removed but no RTP is performed before the metal layer is removed. Then a RTP is performed after the metal layer is removed. | 2014-09-04 |
20140248763 | Vertical Bit Line Non-Volatile Memory Systems And Methods Of Fabrication - Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines. | 2014-09-04 |
20140248764 | METHODS OF FORMING STRUCTURES ON AN INTEGRATED CIRCUIT PRODUCT - One illustrative method disclosed herein includes forming a seed layer above a substrate that includes a conductive region, wherein the seed layer is comprised of a metal-containing material, forming a nucleation layer on the seed layer, wherein the nucleation layer is comprised of a transition metal oxide ceramic material, and performing a thermal treatment process at a temperature so as to generate a plurality of spaced-apart, vertically oriented alloy structures, wherein the alloy structures are comprised of at least one material from the seed layer and at least one material from the nucleation layer. | 2014-09-04 |
20140248765 | SEMICONDUCTOR MEMORY DEVICE HAVING DUMMY CONDUCTIVE PATTERNS ON INTERCONNECTION AND FABRICATION METHOD THEREOF - A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area. | 2014-09-04 |
20140248766 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 2014-09-04 |
20140248767 | Methods Of Fabricating Integrated Circuitry - A method of fabricating integrated circuitry includes forming a first conductive line. First elemental tungsten is deposited directly against an elevationally outer surface of the first conductive line selectively relative to any exposed non-conductive material. Dielectric material is formed elevationally over the first conductive line and a via is formed there-through to conductive material of the first conductive line at a location where the first tungsten was deposited. Second elemental tungsten is non-selectively deposited to within the via and electrically couples to the first conductive line. A second conductive line is formed elevationally outward of and electrically coupled to the second tungsten that is within the via. | 2014-09-04 |
20140248768 | Mask Assignment Optimization - A method for optimizing mask assignment for multiple pattern processes includes, through a computing system, defining which of a number of vias to be formed between two metal layers are critical based on metal lines interacting with the vias, determining overlay control errors for an alignment tree that defines mask alignment for formation of the two metal layers and the vias, and setting both the alignment tree and mask assignment for the vias so as to maximize the placement of critical vias on masks that have less overlay control error to the masks forming the relevant metal lines. | 2014-09-04 |
20140248769 | Methods of Processing Substrates and Methods of Forming Conductive Connections to Substrates - Embodiments disclosed include methods of processing substrates, including methods of forming conductive connections to substrates. In one embodiment, a method of processing a substrate includes forming a material to be etched over a first material of a substrate. The material to be etched and the first material are of different compositions. The material to be etched is etched in a dry etch chamber to expose the first material. After the etching, the first material is contacted with a non-oxygen-containing gas in situ within the dry etch chamber effective to form a second material physically contacting onto the first material. The second material comprises a component of the first material and a component of the gas. In one embodiment, the first material is contacted with a gas that may or may not include oxygen in situ within the dry etch chamber effective to form a conductive second material. | 2014-09-04 |
20140248770 | MICROWAVE-ASSISTED HEATING OF STRONG ACID SOLUTION TO REMOVE NICKEL PLATINUM/PLATINUM RESIDUES - A method is provided for removing residual Ni/Pt and/or Pt from a semiconductor substrate in a post salicidation cleaning process using microwave heating of a stripping solution. Embodiments include depositing a Ni/Pt layer on a semiconductor substrate; annealing the deposited Ni/Pt layer, forming a nickel/platinum silicide and residual Ni/Pt and/or Pt; removing the residual Ni/Pt and/or Pt from the semiconductor substrate by: microwave heating a strong acid solution in a non-reactive container; exposing the residual Ni/Pt and/or Pt to the microwave heated strong acid solution; and rinsing the semiconductor substrate with water H | 2014-09-04 |
20140248771 | METHODS FOR FORMING A CONDUCTIVE MATERIAL AND METHODS FOR FORMING A CONDUCTIVE STRUCTURE - A method of forming a conductive material comprises forming at least one opening extending through an organic material and an insulative material underlying the organic material to expose at least a portion of a substrate and a conductive contact in the substrate. The method further comprises lining exposed surfaces of the insulative material, the conductive contact, and the at least a portion of the substrate in the at least one opening with a conductive material without forming the conductive material on the organic material. | 2014-09-04 |
20140248772 | METHOD FOR TUNING A DEPOSITION RATE DURING AN ATOMIC LAYER DEPOSITION PROCESS - Embodiments of the invention provide methods for depositing a material on a substrate within a processing chamber during a vapor deposition process, such as an atomic layer deposition (ALD) process. In one embodiment, a method is provided which includes sequentially exposing the substrate to a first precursor gas and at least a second precursor gas while depositing a material on the substrate during the ALD process, and continuously or periodically exposing the substrate to a treatment gas prior to and/or during the ALD process. The deposition rate of the material being deposited may be controlled by varying the amount of treatment gas exposed to the substrate. In one example, tantalum nitride is deposited on the substrate and the alkylamino metal precursor gas contains a tantalum precursor, such as pentakis(dimethylamino) tantalum (PDMAT), the second precursor gas contains a nitrogen precursor, such as ammonia, and the treatment gas contains dimethylamine (DMA). | 2014-09-04 |
20140248773 | PATTERNING METHOD AND METHOD OF FORMING MEMORY DEVICE - A method of forming memory device is provided. A substrate having at least two cell areas and at least one peripheral area between the cell areas is provided. A target layer, a sacrificed layer and a first mask layer having first mask patterns in the cell areas and second mask patterns in the peripheral area are sequentially formed on the substrate. Sacrificed layer is partially removed to form sacrificed patterns by using the first mask layer as a mask. Spacers are formed on sidewalls of the sacrificed patterns. The sacrificed patterns and at least the spacers in the peripheral area are removed. A second mask layer is formed in the cell areas. Target layer is partially removed, using the second mask layer and remaining spacers as a mask, to form word lines in the cell areas and select gates in a portion of cell areas adjacent to the peripheral area. | 2014-09-04 |
20140248774 | LIQUID TREATMENT APPARATUS AND LIQUID TREATMENT METHOD - The liquid treatment apparatus according to the present invention includes a substrate holder configured to horizontally hold a substrate, and a top plate configured to be rotatable and to cover the substrate held by the substrate holder from above so as to define a treatment space. In the treatment space, a chemical liquid is supplied by a chemical liquid nozzle onto the substrate, and an atmosphere replacement gas is supplied by a replacement nozzle into the treatment space. The replacement nozzle is supported by a replacement nozzle support arm configured to be horizontally moved between an advanced position at which the replacement nozzle support arm is advanced into the treatment space and a retracted position at which the replacement nozzle support arm is retracted outside from the treatment space. The replacement nozzle is configured to discharge, above the substrate, the atmosphere replacement gas upward. | 2014-09-04 |
20140248775 | CLEANING AGENT AND METHOD FOR PRODUCING SILICON CARBIDE SINGLE-CRYSTAL SUBSTRATE - The present invention provides a detergent for effectively cleaning, by a safe and simple method, a manganese component remaining on and adhered to a substrate surface, after polishing a silicon carbide single crystal substrate with a manganese compound-containing polishing agent. The present invention relates to a detergent for cleaning a silicon carbide single crystal substrate polished with a manganese compound-containing polishing agent, the detergent including at least one of ascorbic acid and erythorbic acid, in which the detergent has a pH of 6 or less. | 2014-09-04 |
20140248776 | COMPOSITION FOR POLISHING COMPOUND SEMICONDUCTOR - Disclosed is a polishing composition that contains at least abrasive grains, an oxidizing agent having a redox potential equal to or greater than 1.8 V at a pH for application of polishing, and water. The abrasive grains are preferably composed of at least one substance selected from among silicon oxide, aluminum oxide, cerium oxide, zirconium oxide, titanium oxide, manganese oxide, silicon carbide, and silicon nitride. The oxidizing agent is preferably composed of at least one substance selected from among sodium persulfate, potassium persulfate, and ammonium persulfate. The polishing composition preferably has a pH equal to or less than 3. | 2014-09-04 |
20140248777 | RESIST COMPOSITION AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A resist composition includes: a crosslinking material that is crosslinked in the presence of an acid; an acid amplifier; and a solvent. | 2014-09-04 |
20140248778 | METHODS OF FORMING ASYMMETRIC SPACERS ON VARIOUS STRUCTURES ON INTEGRATED CIRCUIT PRODUCTS - One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure. | 2014-09-04 |
20140248779 | LINE WIDTH ROUGHNESS IMPROVEMENT WITH NOBLE GAS PLASMA - A method for forming lines in an etch layer on a substrate may comprise providing a ultra-violet (UV) producing gas to a vacuum chamber having a photoresist mask, ionizing the UV producing gas to produce UV rays to irradiate the photoresist mask, and etching the lines into the etch layer through the photoresist mask. | 2014-09-04 |
20140248780 | ENHANCED ETCHING PROCESSES USING REMOTE PLASMA SOURCES - Methods of etching a patterned substrate may include flowing an oxygen-containing precursor into a first remote plasma region fluidly coupled with a substrate processing region. The oxygen-containing precursor may be flowed into the region while forming a plasma in the first remote plasma region to produce oxygen-containing plasma effluents. The methods may also include flowing a fluorine-containing precursor into a second remote plasma region fluidly coupled with the substrate processing region while forming a plasma in the second remote plasma region to produce fluorine-containing plasma effluents. The methods may include flowing the oxygen-containing plasma effluents and fluorine-containing plasma effluents into the processing region, and using the effluents to etch a patterned substrate housed in the substrate processing region. | 2014-09-04 |
20140248781 | SEMI-AQUEOUS POLYMER REMOVAL COMPOSITIONS WITH ENHANCED COMPATIBILITY TO COPPER, TUNGSTEN, AND POROUS LOW-K DIELECTRICS - A composition is provided that is effective for removing post etch treatment (PET) polymeric films and photoresist from semiconductor substrates. The composition exhibits excellent polymer film removal capability while maintaining compatibility with copper and low-κ dielectrics and contains water, ethylene glycol, a glycol ether solvent, morpholinopropylamine and a corrosion inhibiting compound and optionally one or more metal ion chelating agent, one or more other polar organic solvent, one or more tertiary amine, one or more aluminum corrosion inhibition agent, and one or more surfactant. | 2014-09-04 |
20140248782 | SUBSTRATE PROCESSING METHOD - A substrate processing method includes rotating a substrate about a central axis thereof; starting irradiation of a surface of the substrate with soft X-rays; simultaneously with or after starting the irradiation of the surface of the substrate with the soft X-rays, starting supply of pure water onto the surface of the substrate; stopping the supply of the pure water onto the surface of the substrate; and then stopping the irradiation of the surface of the substrate with the soft X-rays. | 2014-09-04 |
20140248783 | CLEANING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM - A cleaning method includes: providing a process container in which a process of forming a film on a substrate is performed; and removing a deposit including the film adhered to the process container by supplying a cleaning gas into the process container after performing the process. The act of removing the deposit includes generating a mixture gas of a fluorine-containing gas and a nitrosyl fluoride gas as the cleaning gas by mixture and reaction of the fluorine-containing gas and a nitrogen monoxide gas in a mixture part and supplying the mixture gas from the mixture part into the process container after removing exothermic energy generated by the reaction. | 2014-09-04 |
20140248784 | MICROWAVE PROCESSING APPARATUS AND MICROWAVE PROCESSING METHOD - A microwave processing apparatus includes a processing chamber configured to accommodate an object to be processed, a support member configured to support the object by contact with the object in the processing chamber, and a microwave introducing unit configured to generate a microwave for processing the object and introduce the microwave into the processing chamber. The microwave processing apparatus further includes a heat absorbing layer provided on a wall surface of a member facing the object supported by the supporting member in the processing chamber. The heat absorbing layer is made of a material that transmits the microwave and has an emissivity higher than an emissivity of the member facing the object. | 2014-09-04 |
20140248785 | CABLE CONNECTOR WITH IMPROVED GROUNDING PLATE - A cable connector includes an insulative housing including two sidewalls and a mating slot defined between the two sidewalls, and a plurality of terminals received in the insulative housing. The terminals include contacting portions exposed to the mating slot and connecting portions behind a rear end of the insulating housing. The two sidewalls are loaded with a firs row and a second row of the plurality of terminals respectively. The first row includes signal terminals and grounding terminals. A grounding plate is inserted in the insulating housing and between two rows of terminals. The grounding plate defines resilient arms and connecting legs, the resilient arms slant to the first row and touch with the grounding terminals. | 2014-09-04 |
20140248786 | Threadless Light Bulb Socket - A threadless light socket assembly allows a light bulb to be changed by pushing or pulling the light bulb into or out of the socket provides an outer insulator housing and an insulator cap which carrying a ground socket in a medial channel that grounds a light bulb base to a power supply. Plural spring biased thread locks protrude into center of the ground socket and are staggered in height to align with threads defined in a light bulb base. A positive contact is in the socket assembly supplies positive power from a power supply to the light bulb base. The threadless light socket has interchangeable components to allow installation in new and existing light fixtures. | 2014-09-04 |
20140248787 | CONNECTOR - It is aimed to reliably restrict the insertion of a terminal fitting in an improper posture. A connector includes terminal fittings | 2014-09-04 |
20140248788 | LEVER-FIT-TYPE CONNECTOR - A lever-fit-type connector includes: a first connector; a lever provided on the first connector; and a second connector configured to be fitted with the first connector by an operation of the lever, wherein the lever includes a U-shaped elastic member including: a proximal end portion fixed to the lever; a distal end portion projecting in a vertical direction; a projecting portion projecting in a horizontal direction in the vicinity of the distal end portion; a U-shaped portion disposed between the proximal end portion and the distal end portion; and an engaging portion disposed between the distal end portion and the U-shaped portion, the U-shaped elastic member has a clearance between the proximal end portion and the distal end portion in the horizontal direction, and one of the first and second connectors includes an engaging portion operable to be engaged with the engaging portion of the U-shaped elastic member. | 2014-09-04 |
20140248789 | LOCKABLE ELECTRICAL CONNECTOR ASSEMBLIES - Lockable electrical connector assemblies that couple electrical connectors to prevent the electrical connectors from unintentionally disconnecting are disclosed. The electrical connector assembly has a first electrical connector, a second electrical connector, and a retention ring that has one end surrounding and able to rotate about the second electrical connector. The first electrical connector preferably has tabs that extend away from the first electrical connector. The retention ring has a second end shaped to receive and lock the tabs of the male electrical connector. To form a locked connection, a user rotates the retention ring that causes the retention ring to confine the tabs of the first electrical connector. The user continues to rotate the retention ring until retention ring is placed into a locked position. | 2014-09-04 |
20140248790 | MULTI-POLE WIRE CONNECTOR SOCKET - A multi-pole wire connection socket comprises: a frame, configured with a plurality of conductive elements and a plurality of inset holes; a plurality of guillotine elements, having a plurality of protrusions at positions for allowing the protrusions to inset into the inset holes for enabling the guillotine elements to pivot relative to the frame; wherein the plural conductive elements have a plurality of conductive rings; and there is a plurality of via holes formed on the plural guillotine elements, which are provided for a plurality of wires to thread through. Operationally, the insulation around wires, threading through the via holes and the conductive rings, will be cut open for exposing the wires to couple electrically with the conductive elements as soon as wires are bended by the plural guillotine elements Thereby, the wires are electrically connected without having to use any tool for peeling off the insulations of the wires. | 2014-09-04 |
20140248791 | CABLE CONNECTOR ASSEMBLY - A cable connector assembly comprises an electrical connector and a cable connected to a rear side of the electrical connector. The electrical connector comprises an insulative housing and a plurality of conductive terminals fixed thereto. The cable comprises a plurality of wires, a filler among the wires and an insulative covering which covers outer peripheries of the wires and the filler. The wires and the conductive terminals are electrically connected. The cable connector assembly further comprises an inner mold and a casing surrounding an outer periphery of the inner mold. The inner mold is integrally formed at outer peripheries of connections between the conductive terminals and the wires by over-molding. A part of the filler is embedded into the inner mold for stress relief. | 2014-09-04 |
20140248792 | SENSE PIN FOR AN ELECTRICAL CONNECTOR - An electrical connector is provided for mating with a mating connector. The electrical connector includes a housing and electrical contacts held by the housing. The electrical contacts are configured to mate with corresponding mating contacts of the mating connector. A sense pin is held by the housing and is configured to mate with a corresponding mating contact of the mating connector. The sense pin extends a length that includes a tip segment and a sensing segment. The tip and sensing segments have different electrical characteristics. The tip segment includes a tip of the sense pin. The tip segment extends between the sensing segment and the tip such that the sensing segment is offset from the tip along the length of the sense pin. The sensing segment is configured to indicate that the electrical contacts and the mating contacts are de-mated by more than a predetermined de-mating distance. | 2014-09-04 |
20140248793 | WATERPROOF STRUCTURE FOR CONNECTOR - A waterproof structure for a connector includes a housing, a shield wire, a shield terminal, a first packing, and a second packing. The housing has a tubular housing part. The shield wire passes through the inside of the tubular housing part and extends from the housing. The shield terminal has a first section, a second section and a third section. The first section and the second section get into the tubular housing part such that the shield wire passes through the inside of the shield terminal, the first section joints with a braided shield wire of the shield wire, and the third section protrudes from the tubular housing part. The first packing seals a gap between the second section of the shield terminal and the tubular housing part. The second packing seals a gap between the shield wire and the third section of the shield terminal. | 2014-09-04 |
20140248794 | TRANSCEIVER RECEPTACLE CAGE - A connector cage includes a bezel, having a plurality of slots formed therein, and a cage structure including upper and lower sides and multiple partitions extending between the upper and lower sides to define receptacles for receiving cable connectors. Multiple tabs protrude out of at least one of the sides in locations at which the tabs fit into the slots in the bezel, and are folded over the slots so as to secure the cage structure to the bezel. The cage may also include multiple snap-on spring subassemblies, each spring subassembly secured to a front end of a respective partition and comprising leaves that bow outward to contact the shells of the connectors that are inserted into the receptacles adjacent to the partition. | 2014-09-04 |
20140248795 | Electric Plug System - An electric plug system includes a stabilizing base constructed to stand on a horizontal floor surface, a vertical support element supported by and extending from the base and defining a vertical axis, and an electrical socket block coupled to a top portion of the vertical support element and supported thereby. The electrical socket block has a plurality of electrical sockets constructed to receive the plugs of the devices. Also, the system includes an electrical wire extending from the horizontal electrical socket block, down the vertical support element, and along or through the base and there-beyond, the electrical wire terminating in an electrical plug constructed to plug into the wall or floor electrical outlet. The system can include a device holder removably attached to the vertical support element. The base can include a first base portion and a second base portion removably attached to one another. | 2014-09-04 |
20140248796 | RECEPTACLE CONNECTOR - A receptacle connector ( | 2014-09-04 |
20140248797 | COAXIAL CONNECTOR WITH VISIBLE POST - A coaxial cable connector includes a shell having an inner side wall defining a bore and an end opening at a first end of the shell, and a post is slidably mounted in the bore. The post includes a base engaging the shell inner side wall and a tube projecting from the base, the tube having an interior and an end aperture, and at least one of the post and the shell has a first detent for releasably holding the post in a first position in the bore and a second detent for securing the post at a second position in the bore. | 2014-09-04 |
20140248798 | Coaxial Cable Connector With Alignment And Compression Features - A coaxial cable connector includes an outer barrel having a longitudinal axis, the outer barrel formed with an inner compression band. A coaxial fitting is mounted at a front end of the outer barrel for coupling to an electrical device, and a coaxial compression collar is applied to the outer barrel. An outer compression band formed in the compression collar moves between an uncompressed condition and a compressed condition in response to axial compression of the coaxial cable connector. Movement of the outer compression band from the uncompressed condition to the compressed condition shapes the inner compressed into a pawl which allows introduction of a cable into the connector and then prevents removal of the cable from the connector. | 2014-09-04 |
20140248799 | SHIELDED CONNECTOR UNIT - A shielded connector unit includes a lower shielded connector to be connected downwards to a lower positioned first instrument, an upper shielded connector to be connected sideways to a second instrument positioned above the first instrument, and a flexible conductive part made up of an electric wire which is adapted to connect the lower shielded connector to the upper shielded connector and a braid which is adapted to enclose a bare portion of the electric wire existing between a shielding shell of the lower shielded connector and a shielding shell of the upper shielded connector. The shielded connector unit further includes a hard protector that is adapted to enclose and protect the conductive part from the outside while ensuring flexibility of at least a portion of the conductive part. | 2014-09-04 |
20140248800 | CONNECTOR - A connector includes: a connector housing formed in a tubular shape by an insulating synthetic resin; a cover for closing an opening of one end side in an axial direction of the connector housing; and plural terminal fittings formed inside the connector housing by insert molding, one end of the terminal fittings each being arranged in an opening for coupling of the other end side in the axial direction of the connector housing and the other end of the terminal fittings each being connected to one end of an electric wire. The one end of the terminal fittings each led out of one inner wall part of the connector housing traverses the opening for coupling, and a distal end of the terminal fittings each is buried in the other inner wall part opposed to the one inner wall part. | 2014-09-04 |
20140248801 | CONTACTLESS PLUG CONNECTOR AND CONTACTLESS PLUG CONNECTOR SYSTEM - The invention relates to contactless plug connectors and contactless plug connector systems for electromagnetically connecting a corresponding mating plug connector. In order to allow for an electromagnetic connection, the invention suggest providing at least one input terminal for inputting a baseband input signal; an antenna element arranged at the mating end of the contactless plug connector; and a transmitting circuit for modulating the inputted baseband input signal on a predetermined carrier frequency and for transmitting the modulated baseband input signal via the antenna element as a radio wave with the predetermined carrier frequency. In particular, the contactless plug connector and contactless plug connector system include an electromagnetic shielding element arranged to surround the transmitting circuit and the antenna element with a rim portion forming an opening at the mating end of the contactless plug connector. | 2014-09-04 |
20140248802 | SMART TAP - A smart tap into which one or more than one power plugs can be inserted, including a voltage waveform measurement unit, a current waveform measurement unit, a communication unit, a control unit, and an arithmetic unit. The voltage waveform measurement unit and the current waveform measurement unit are units which measure a voltage waveform and a current waveform of power supplied to each of one or more home appliances via a corresponding respective power plugs connected to the home appliances. The communication unit is a unit which transmits the voltage waveform and the current waveform or a result of processing of the waveforms to a server. The control unit is a unit which controls switching of the power supplied to the home appliance and the amount of the supplied power in accordance with the control signal. | 2014-09-04 |
20140248803 | Coaxial Electrical Connector Assembly - Example coaxial connector assemblies are described. In one example, a coaxial connector assembly ( | 2014-09-04 |
20140248804 | HOSPITAL BED HAVING WIRELESS DATA AND LOCATING CAPABILITY - A system for use with a hospital bed having circuitry and a standard AC power outlet spaced from the hospital bed is provided. The system includes a cable assembly couplable to the circuitry of the hospital bed. The cable assembly has power conductors and at least one data conductor. The cable assembly also has a plug including a first power coupler coupled to the power conductors and a first data coupler coupled to the at least one data conductor. The system also includes a second data coupler mountable adjacent the standard AC power outlet. The second data coupler is configured to couple to the first data coupler when the first power coupler is coupled to the standard AC power outlet. | 2014-09-04 |
20140248805 | ELECTRICAL CONNECTOR WITH TERMINAL ARRAY - An electrical connector is provided. The connector includes a housing having a wire end and a mating end. A terminal array extends between the wire end and the mating end of the housing. The terminal array has second terminals and first terminals. Each of the second terminals and the first terminals has a wire contact positioned at the wire end of the housing and a mating contact positioned at the mating end of the housing. The wire contact of each second terminal is positioned closer to the wire end of the housing than the wire contact of each first terminal. The mating contacts of the second terminals are positioned adjacent the mating contacts of the first terminals. | 2014-09-04 |
20140248806 | ELECTRICAL CONNECTOR HAVING CROSSTALK COMPENSATION INSERT - An electrical connector includes a front wire terminal and a rear wire terminal. The front wire terminal and the rear wire terminal are configured to couple to a conductor of a cable. A front signal trace is coupled to the front wire terminal. A rear signal trace is coupled to the rear wire terminal. The front signal trace is positioned adjacent to the rear signal trace. A front mating contact is coupled to the front signal trace. A rear mating contact is coupled to the rear signal trace. The front signal trace conveys an electrical signal between the front wire terminal and the front mating contact. The rear signal trace conveys an electrical signal between the rear wire terminal and the rear mating contact. An electro-mechanical compensation is positioned between the front signal trace and the rear signal trace to control crosstalk between the front signal trace and the rear signal trace. | 2014-09-04 |
20140248807 | COMMUNICATION CONNECTOR - The present invention generally relates to communication connectors and internal components thereof. In one embodiment, the present invention is a communication jack comprising back-rotated plug interface contacts having variable cross-sectional widths. In another embodiment, the present invention is a communication jack having back-rotated plug interface contacts where at least two of the plug interface contacts have a differing beam length. In yet another embodiment, the present invention is a communication jack having back-rotated plug interface contacts where at least two of the plug interface contacts have opposing bends in a deflection zone. | 2014-09-04 |
20140248808 | METHOD FOR PRODUCING A SCREW CONNECTION TERMINAL - A method for producing a screw connection terminal includes providing a flat metal. The method includes forming a conductor insertion opening into a longitudinal lateral surface of the flat metal. The method includes driving apart the material of the flat metal so as to introduce an eyelet opening into an end face surface of the flat metal. A diameter of the eyelet opening is larger than a thickness of the flat metal in a region of the conductor insertion opening. The method also includes introducing a thread into the eyelet opening. | 2014-09-04 |
20140248809 | FITTING TYPE CONNECTING TERMINAL AND METHOD FOR PRODUCING SAME - In a fitting type connecting terminal having male and female terminals, each of which has a tin plating layer formed on an electrically conductive base material, a surface of a contact portion of one of the male and female terminals with the other thereof has a plurality of grooves or recessed portions which are spaced from each other in longitudinal directions, and the grooves or recessed portions are formed so as to satisfy d≦b, d≦a≦L and a+c≦L assuming that the width of each of the grooves or recessed portions is | 2014-09-04 |
20140248810 | WATER JET PROPULSION WATERCRAFT - A water jet propulsion watercraft includes a hull having a sealed engine room, an engine installed in the engine room, a jet propulsion unit arranged to be driven by the engine so as to suck in water from around the hull and jet the water, a saddle type seat disposed above the engine room, a first exhaust pipe, an exhaust pipe cooling unit, and a catalyst unit. The first exhaust pipe is attached to a side of the engine inside the engine room, extends rearward from the side of the engine, and is arranged to guide exhaust gas discharged from the engine. The exhaust pipe cooling unit is arranged to cool the first exhaust pipe. The catalyst unit is connected to the first exhaust pipe, is disposed inside the engine room so as to oppose a rear surface of the engine, and is arranged to promote reaction of components contained in the exhaust gas. | 2014-09-04 |
20140248811 | SPUNBOND NONWOVEN FABRICS - The instant invention provides nonwoven fabrics and staple or binder fibres prepared from an ethylene-based polymer having a Comonomer Distribution Constant in the range of from greater than from 100 to 400, a vinyl unsaturation of less than 0.1 vinyls per one thousand carbon atoms present in the backbone of the ethylene-based polymer composition; a zero shear viscosity ratio (ZSVR) in the range from 1 to less than 2; a density in the range of 0.930 to 0. 970 g/cm3, a melt index (12) in the range of from 15 to 30 or from 10 to 50 g/10 minutes, a molecular weight distribution (Mw/Mn) in the range of from 2 to 3.5, and a molecular weight distribution (Mz/Mw) in the range of from less than 2. | 2014-09-04 |
20140248812 | RE-USABLE HIGH-TEMPERATURE RESISTANT SOFTGOODS FOR AEROSPACE APPLICATIONS - High-temperature fabrics with a coatings to provide oxidation protection at high temperatures, and capable of being formed into a variety of softgoods parts, and methods for their manufacture are disclosed. | 2014-09-04 |
20140248813 | CRYSTAL-CLEAR POLYURETHANES - The present invention relates to processes for preparing compact transparent polyurethanes by mixing (a) isocyanates with (b) compounds having at least two isocyanate-reactive groups, (c) catalysts, and optionally (d) auxiliaries and additives to give a reaction mixture and carrying out reaction to the compact transparent polyurethanes, the isocyanates (a) comprising at least 50 wt % of biurets of hexamethylene diisocyanate. The present invention further relates to a compact, transparent polyurethane prepared by a process of the invention, and to the use of such a compact, transparent polyurethane as a surface coating, more particularly in the interior of means of transport. | 2014-09-04 |
20140248814 | COMPOSITE FLAME BARRIER - A composite flame barrier includes a woven or nonwoven fiber sheet material including flame resistant fibers of oxidized polyacrylonitrile; a mineral hydrate material at least partially embedded within the fiber sheet material. The fiber sheet material may be covered on one or two sides with an outer laminar material. The composite flame barrier is particularly useful in fire-rated wall assemblies, especially those designed to provide two, three and four hour fire-ratings, when tested according to ASTM E-119 or similar testing methods and standards. | 2014-09-04 |
20140248815 | METHOD OF FORMING A WEB FROM FIBROUS MATERIALS - Fibrous material webs and methods of making the fibrous material webs. Binderless webs can be formed in a continuous process where fiber material, such as glass is melted and formed into fibers. The fibers are formed into a web of binderless glass fibers or a web with a dry binder. The binderless web or the web with dry binder can be layered and/or the fibers that make up the web can be mechanically entangled, for example, by needling. | 2014-09-04 |
20140248816 | BI-COMPONENT FIBER AND FABRICS MADE THEREFROM - The instant invention provides bi-component fibers and fabrics made therefrom. The bi-component fiber according to the present invention comprises: (a) from 5 to 95 percent by weight of a first component comprising at least one or more first polymers, based on the total weight of the bi-component fiber; (b) from 5 to 95 percent by weight of a second component comprising at least an ethylene-based polymer composition, based on the total weight of the bicomponent fiber, wherein said ethylene-based polymer composition comprises; (i) less than or equal to 100 percent by weight of the units derived from ethylene; and (ii) less than 30 percent by weight of units derived from one or more α-olefin comonomers; wherein said ethylene-based polymer composition is characterized by having a Comonomer Distribution Constant in the range of from greater than from 100 to 400, a vinyl unsaturation of less than 0.1 vinyls per one thousand carbon atoms present in the backbone of the ethylene-based polymer composition; a zero shear viscosity ratio (ZSVR) in the range from 1 to less than 2; a density in the range of 0.920 to 0.970 g/cm | 2014-09-04 |
20140248817 | MANUFACTURING METHOD FOR DISPLAY DEVICE PROVIDED WITH THIN FILM ELECTRONIC CIRCUIT - A method of manufacturing a display device provided with a thin-film electronic circuit | 2014-09-04 |