35th week of 2012 patent applcation highlights part 38 |
Patent application number | Title | Published |
20120220033 | INHIBITION OF VIRAL GENE EXPRESSION USING SMALL INTERFERING RNA - The invention provides methods, compositions, and kits comprising small interfering RNA (shRNA or siRNA) that are useful for inhibition of viral-mediated gene expression. Small interfering RNAs as described herein can be used in methods of treatment of HCV infection. ShRNA and siRNA constructs targetING the internal ribosome entry site (IRES) sequence of HCV are described. | 2012-08-30 |
20120220034 | Methods for Reprogramming Cells and Uses Thereof - Described herein are methods for cell dedifferentiation, transformation and eukaryotic cell reprogramming Also described are cells, cell lines, and tissues that can be transplanted in a patient after steps of in vitro dedifferentiation and in vitro re-programming In particular embodiments the cells are Stem-Like Cells (SLCs), including Neural Stem-Like Cells (NSLCs) Also described are methods for generating these cells from human somatic cells and other types of cells Also provided are compositions and methods of using of the cells so generated in human therapy and in other areas. | 2012-08-30 |
20120220035 | TEMPERATURE-RESPONSIVE CO-POLYMERS AND USES THEREOF - This disclosure relates to temperature-responsive co-polymers, such as poly(N-isopropylacrylamide-co-hydroxypropyl methacrylate-co-3-trimethoxysilypropyl methacrylate). The disclosure also relates to polymeric films formed from these co-polymers and particular applications of these polymeric films, particularly in the cell culture field. More specifically, the present disclosure relates to the use of these polymeric films in the cell culture field to provide a means of controlling cellular adhesion to, and detachment from, the surface of a cell culture support substrate. | 2012-08-30 |
20120220036 | Media, Kits, Systems and Methods for the Micropropagation of Bamboo - Disclosed herein are media, kits, systems and methods for achieving micropropagation of bamboo on a commercially-relevant scale. | 2012-08-30 |
20120220037 | METHODS AND MATERIALS FOR PRODUCING TRANSGENIC ARTIODACTYLS - Swine animal models comprising a genomic disruption of an endogenous gene chosen from the group consisting of a Low-Density Lipoprotein Receptor gene LDLR, Duchene's Muscular Dystrophy (DMD) gene, and hairless gene (HR). Methods of preparing transfected cells useful for making a transgenic animal comprising exposing a first group of cells to a transfection agent and reseeding the group with additional cells that have not been exposed to the agent. The transgenic animals are useful for medical and scientific animal models of human diseases and conditions, as well as sources for cells, tissues, and biomaterials. | 2012-08-30 |
20120220038 | REAGENT KIT FOR DETECTING LUPUS ANTICOAGULANT AND METHOD OF DETERMINING PRESENCE OR ABSENCE OF LUPUS ANTICOAGULANT - In order to provide a reagent kit for detecting LA which can clearly separate a lupus anticoagulant (LA)-positive specimen group from an LA-negative specimen group, it is configured that the reagent kit for detecting LA contains a first clotting time-measuring reagent and a second clotting time-measuring reagent and at least one of the first clotting time-measuring reagent and the second clotting time-measuring reagent contains alkali metal salt. The presence or absence of LA can be determined using the kit. | 2012-08-30 |
20120220039 | METHOD AND SYSTEM FOR DETECTING RESIDUAL POISON IN HUMAN BODY - A method and system for detecting residual poison in human body are provided. Using the disclosed HPLC-Chip-mass spectrometry (MS)/MS and/or HPLC-MS/MS method to detect the residual poison, the method of the present invention mainly includes sample preparation, liquid chromatography and mass spectrometry. The method of the present invention has advantages of low sample size, high specificity, low detection limit, high sensitivity, low cost, high accuracy and stability, etc. | 2012-08-30 |
20120220040 | METHOD OF QUANTITATIVELY DETERMINING 8-ISOPROSTANE - A method of quantitatively determining 8-isoprostane is provided that includes fluorescently labeling 8-isoprostane with a quinoxalinone derivative in an excess amount relative to 8-isoprostane, separating a fluorescently labeled 8-isoprostane from a unreacted quinoxalinone derivative by contacting a reaction mixture containing the fluorescently labeled 8-isoprostane and the unreacted quinoxalinone derivative with a cation exchange support having a sulfonic acid or a sulfonate immobilized thereon, and quantitatively determining the fluorescently labeled 8-isoprostane that has been separated from the unreacted quinoxalinone derivative. | 2012-08-30 |
20120220041 | Organic Chemical Sensor Apparatus, Method, and System - An organic chemical sensor includes a dielectric core that comprises an elastomer and a high dielectric constant material. The elastomer absorbs an organic chemical to be sensed. An electrically conductive layer is secured to a first side of the dielectric core. A permeable conductive layer is secured to a second side of the dielectric core. The permeable conductive layer is electrically conductive and permeable to the organic chemical to be sensed. The absorption of the organic chemical to be sensed by the elastomeric layer causes a decrease in the capacitance between the electrically conductive layer and the permeable conductive layer. | 2012-08-30 |
20120220042 | EVIDENCE COLLECTOR WITH INTEGRAL QUANTIFIED REAGENTS AND METHOD OF MODULATING SPECIMEN DRYING TIME - Apparatus and methods are provided for evidence specimen collection having integral reagent holders to hold reagent vials and having drying agent or desiccant holding areas that permit the renewal of the desiccant and permit the introduction of variously size desiccant qualities to allow modulation of the specimen drying time to achieve early stabilization of specimens while holding the specimen in an isolated drying area during storage and shipment and for simultaneous collection of multiple evidence samples with simultaneous storage, drying, marking, evidence security and shipping provided and with the provision for simultaneous storage, drying, marking, evidence security and shipping provided for a control specimen. | 2012-08-30 |
20120220043 | EVIDENCE COLLECTOR WITH INTEGRAL QUANTIFIED REAGENTS AND METHOD OF MODULATING SPECIMEN DRYING TIME - Apparatus and methods are provided for evidence specimen collection having integral reagent holders to hold reagent vials and having drying agent or desiccant holding areas that permit the renewal of the desiccant and permit the introduction of variously size desiccant qualities to allow modulation of the specimen drying time to achieve early stabilization of specimens while holding the specimen in an isolated drying area during storage and shipment and for simultaneous collection of multiple evidence samples with simultaneous storage, drying, marking, evidence security and shipping provided and with the provision for simultaneous storage, drying, marking, evidence security and shipping provided for a control specimen. | 2012-08-30 |
20120220044 | Apparatus, System, and Method of Processing Biopsy Specimen - A biopsy pipette with a filter attached in an internal compartment of a pipette designed to prevent lodging and possible loss of the tissue specimen for analysis. A biopsy test tube may be provided with a biopsy bag attached in the internal compartment of the test tube. Further, a biopsy cassette may be provided with an opening configured to receive a pipette. An automated and non-automated system and method of using the biopsy pipette, biopsy test tube, and biopsy cassette in the processing of biopsy specimen is also disclosed. | 2012-08-30 |
20120220045 | Double Trench Well for Assay Procedures - Apparatuses, systems and methods for using assay preparation plates comprising wells with two trenches are presented. More specifically, well plates are presented that comprising an array of wells configured to retain a plurality of beads suspended in a fluid during an assay procedure, each well in the array comprising a first trench and a second trench, wherein the working volume of each well is between about 25 uL and about 10 mL. | 2012-08-30 |
20120220046 | Method and apparatus for forming the doped cryo-biology specimen of electron microscope - The invention discloses a method and apparatus for forming the doped cryo-biology specimen of electron microscope. The invention applies rapid cryogenic freezing to the biology specimen, and dopes certain concentration of protons and electrons into the cryo-biology specimen for conducting the observation using electron microscope. The invention reduces the radiation damage of cryogenic biology specimen and amorphous ice caused by the electron radiation, and observes the prototype of biomolecules and biomaterials clearly. | 2012-08-30 |
20120220047 | MICROFLUIDIC SEPARATION OF PLASMA FOR COLORMETRIC ASSAY - A device includes a plasma separation membrane, a capillary channel positioned adjacent the plasma separation membrane to receive plasma from blood placed on the plasma separation membrane, at least one cuvette coupled to the capillary channel, a gas permeable membrane, and a distribution channel coupled to the capillary channel to provide plasma to the cuvette, wherein the cuvette is configured to hold an amount of plasma with reagent suitable for colorimetric assay by a tester to hold the device. Variations include the use of a quantiation channel to provide a selected amount of plasma and a mixing channel to mix plasma with a diluent. | 2012-08-30 |
20120220048 | MAGNETIC MARKER PARTICLE AND METHOD FOR PRODUCING THE SAME - There is provided a magnetic marker particle. The magnetic marker particle comprises a magnetic particle and a polymer deposited on the surface of the magnetic particle, wherein the deposited polymer comprises a combination of a carboxyl group and a polyethylene glycol chain or a combination of a carboxyl group and a sulfo group. | 2012-08-30 |
20120220049 | ASSAY METHOD AND DEVICE - The present invention relates to a method and a device for detecting the presence of an analyte. More particularly, the present invention relates to the method and device for detecting the presence of immunoglobulins directed at polymorphic alloantigens such as HLA antigens and/or other products of the major histocompatibility complex (MHC). | 2012-08-30 |
20120220050 | METHOD OF PURIFYING 8-ISOPROSTANE - A method of purifying 8-isoprostane is provided that includes a step of contacting a liquid sample containing 8-isoprostane with an ion exchange support having a quaternary ammonium salt immobilized thereon such that 8-isoprostane in the liquid sample is retained on the ion exchange support and a step of eluting 8-isoprostane from the ion exchange support using a first eluent containing a water-soluble organic solvent and water as main components. | 2012-08-30 |
20120220051 | Immunogenicity Assay - Assays for detecting antibodies to pharmaceutical preparations, food allergens and environmental allergens are described. | 2012-08-30 |
20120220052 | SURVIVAL PROGNOSTIC ASSAY - Assay kit and Assay for determination of likely survival of a subject Assay kits for determining the total amount of free-light chains (FLC) in a sample are provided. Also provided are a general health screen method comprising detecting an amount of free light chains (FLC) in a sample from a subject, wherein a lower amount of FLC is associated with increased survival and/or better general health of the subject, and a higher level of FLC indicates the possible presence of an undetected medical problem. | 2012-08-30 |
20120220053 | GRAPHENE-ENCAPSULATED NANOPARTICLE-BASED BIOSENSOR FOR THE SELECTIVE DETECTION OF BIOMARKERS - A field effect transistor (FET) with a source electrode and a drain electrode distanced apart from each other on a semi-conductor substrate, and a gate electrode consisting of a uniform layer of reduced graphene oxide encapsulated semiconductor nanoparticles (rGO-NPs), wherein the gate electrode is disposed between and contacts both the source and drain electrodes. Methods of making and assay methods using the FETs are also disclosed, including methods in which the rGO-NPs are functionalized with binding partners for biomarkers. | 2012-08-30 |
20120220054 | DEVICE FOR DETECTION OF TARGET MOLECULES AND USES THEREOF - Devices and methods for the detection of target molecules are disclosed. Devices and methods for detecting food-borne target molecules are also disclosed. | 2012-08-30 |
20120220055 | Method for Detecting Cardiac Ischemia via Changes in B-Natriuretic Peptide Levels - The present invention relates to a method of detecting cardiac ischemia by measuring the levels of BNP or NTproBNP. Increases in BNP or NTproBNP levels in an individual are indicative of cardiac ischemia. | 2012-08-30 |
20120220056 | MECHANICAL COUPLING IN A MULTI-CHIP MODULE USING MAGNETIC COMPONENTS - A multi-chip module (MCM) is described. This MCM includes at least two substrates that are remateably mechanically coupled by positive and negative features on facing surfaces of the substrates. These positive and negative features mate with each other. In particular, a positive feature may mate with a given pair of negative features, which includes negative features on each of the substrates. Furthermore, at least one of the negative features in the given pair may include a hard magnetic material, and the positive feature and the other negative feature in the given pair may include a soft magnetic material that provide a flux-return path to the hard magnetic material. In this way, the hard magnetic material may facilitate the remateable mechanical coupling of the substrates. | 2012-08-30 |
20120220057 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - Ferroelectric capacitors ( | 2012-08-30 |
20120220058 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system. | 2012-08-30 |
20120220059 | METHOD FOR PRODUCING LIGHT-EMITTING DIODE DEVICE - A method for producing a light-emitting diode device includes the steps of: preparing a light-emitting laminate including an optical semiconductor layer, and an electrode unit formed on the optical semiconductor layer; forming an encapsulating resin layer on the optical semiconductor layer so as to cover the electrode unit, the encapsulating resin layer containing a light reflection component; partially removing the encapsulating resin layer so as to expose the top face of the electrode unit, thereby producing a light-emitting diode element; and disposing the light-emitting diode element and a base substrate provided with terminals so that the light-emitting diode element and the base substrate face each other, and that the electrode unit and the terminals are electrically connected, thereby flip chip mounting the light-emitting diode element on the base substrate. | 2012-08-30 |
20120220060 | METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT-EMITTING APPARATUS - There is provided a method for manufacturing a light-emitting element comprising a semiconductor layered structure of Group III-V compound semiconductor layers; the manufacturing method including a step of forming a projection/depression structure on a light extraction surface of the semiconductor layered structure using as an etchant an aqueous solution containing hydrobromic acid. | 2012-08-30 |
20120220061 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS - An organic light emitting display (OLED) apparatus and a method of manufacturing the same, the OLED apparatus including: a substrate; an active layer formed on the substrate; a gate electrode insulated from the active layer; source and drain electrodes insulated from the gate electrode and electrically connected to the active layer; a pixel defining layer formed on the source and drain electrodes, having an aperture to expose one of the source and drain electrodes; an intermediate layer formed in the aperture and comprising an organic light emitting layer; and a facing electrode which is formed on the intermediate layer. One of the source and drain electrodes has an extension that operates as a pixel electrode. The aperture exposes the extended portion. The intermediate layer is formed on the extended portion. | 2012-08-30 |
20120220062 | LIQUID CRYSTAL DISPLAY DEVICE AND MANUFACTURING METHOD OF LIQUID CRYSTAL DISPLAY DEVICE - To sophisticate a portable electronic appliance without hindering reduction of the weight and the size, more specifically, to sophisticate a liquid crystal display apparatus installed in a portable electronic appliance without hindering the mechanical strength, a liquid crystal display apparatus includes a first plastic substrate, a light-emitting device which is disposed over the first plastic substrate, resin which covers the light-emitting device, an insulating film which is in contact with the resin, a semiconductor device which is in contact with the insulating film, a liquid crystal cell which is electrically connected to the semiconductor device, and a second plastic substrate, wherein the semiconductor device and the liquid crystal cell are disposed between the first plastic substrate and the second plastic substrate. | 2012-08-30 |
20120220063 | VERTICAL-STRUCTURE SEMICONDUCTOR LIGHT EMITTING ELEMENT AND A PRODUCTION METHOD THEREFOR - The present invention relates to a vertical-structure semiconductor light emitting device and a production method thereof, more specifically, to a vertical-structure semiconductor light emitting device having a high-performance heat sink support comprising a thick metal film or metal foil. The vertical-structure semiconductor light emitting element produced in accordance with the present invention constitutes a highly reliable light emitting element with absolutely no thermal or mechanical damage since it has the high performance heatsink support and so suffers not fine micro- cracking and can be freely subjected to heat treatment and to post-processing including of a side-surface passivation thin film. | 2012-08-30 |
20120220064 | EPITAXIAL FORMATION SUPPORT STRUCTURES AND ASSOCIATED METHODS - Epitaxial formation support structures and associated methods of manufacturing epitaxial formation support structures and solid state lighting devices are disclosed herein. In several embodiments, a method of manufacturing an epitaxial formation support substrate can include forming an uncured support substrate that has a first side, a second side opposite the first side, and coefficient of thermal expansion substantially similar to N-type gallium nitride. The method can further include positioning the first side of the uncured support substrate on a first surface of a first reference plate and positioning a second surface of a second reference plate on the second side to form a stack. The first and second surfaces can include uniformly flat portions. The method can also include firing the stack to sinter the uncured support substrate. At least side of the support substrate can form a planar surface that is substantially uniformly flat. | 2012-08-30 |
20120220065 | METHOD FOR REDUCING TILT OF TRANSPARENT WINDOW DURING MANUFACTURING OF IMAGE SENSOR - The present invention discloses a method for reducing the tilt of a transparent window during manufacturing of an image sensor. The method includes the following steps: providing a semimanufacture of the image sensor; carrying out a preheating process; carrying out an adhesive spreading process; carrying out a transparent window closing process; and carrying out a packaging process. By carrying out the preheating process, the environmental conditions can be stabilized during the adhesive spreading process and the transparent window closing process such that the transparent window can be kept highly flat after combining By the implementation of the present invention, the chance of tilt and crack of the transparent window during manufacturing of the image sensor can be reduced, thereby achieving the goal for a better yield rate. | 2012-08-30 |
20120220066 | CZTS/SE PRECURSOR INKS AND METHODS FOR PREPARING CZTS/SE THIN FILMS AND CZTS/SE-BASED PHOTOVOLTAIC CELLS - The present invention relates to coated binary and ternary nanoparticle chalcogenide compositions that can be used as copper zinc tin chalcogenide precursor inks. In addition, this invention provides processes for manufacturing copper zinc tin chalcogenide thin films and photovoltaic cells incorporating such thin films. | 2012-08-30 |
20120220067 | FURNACE AND METHOD OF FORMING THIN FILM USING THE SAME - A furnace includes a chamber extended in a first direction to accommodate a plurality of substrates, a process plate on which the substrates are mounted, and the process plate is disposed in the chamber and extended in the first direction. The process plate includes a plurality of thru-holes penetrating through an upper surface and a lower surface of the process plate. The furnace further includes at least one fan disposed under the lower surface to flow air in the chamber in a second direction such that the air flows from the upper surface to the lower surface through the thru-holes and a heater operatively connected to the chamber to heat the air in the chamber. | 2012-08-30 |
20120220068 | Method to Form a Device by Constructing a Support Element on a Thin Semiconductor Lamina - A semiconductor assembly is described in which a support element is constructed on a surface of a semiconductor lamina. Following formation of the thin lamina, which may have a thickness about 50 microns or less, the support element is formed, for example by plating, or by application of a precursor and curing in situ, resulting in a support element which may be, for example, metal, ceramic, polymer, etc. This is in contrast to pre-formed support element which is affixed to the lamina following its formation, or to a donor wafer from which the lamina is subsequently cleaved. | 2012-08-30 |
20120220069 | METHOD OF PRODUCING CONDUCTIVE THIN FILM - An embodiment of this invention provides a method to produce a conductive thin film, which comprises: providing a substrate; forming a first metal oxide layer on the substrate; forming an indium-free metal layer on the first metal oxide layer; and forming a second metal oxide layer on the indium-free layer, wherein the first metal oxide layer, the indium-free metal layer, and the second oxide layer are all solution processed. | 2012-08-30 |
20120220070 | METHOD OF MANUFACTURING SOLAR CELL - A method of manufacturing a solar cell includes the following steps. An ion implantation process is performed to a first surface of a substrate to form a first doping layer. Then, the ion implantation process is performed to a second surface of the substrate to form a second doping layer. After that, an annealing process is performed to the structure formed by the substrate, the first doping layer and the second doping layer, and forming a first passivation layer on the first doping layer and a second passivation layer on the second doping layer by the annealing process. A third passivation layer is formed on the first passivation layer formed after the annealing process and a fourth passivation layer is formed on the second passivation layer formed after the annealing process. Afterward, conductive electrodes are formed on the third passivation layer and the fourth passivation layer, respectively. | 2012-08-30 |
20120220071 | SCREEN MASK AND MANUFACTURING METHOD OF A SOLAR CELL USING THE SCREEN MASK - A screen mask has a mesh, a frame, and at least one emulsion pattern. The mesh includes a squeeze surface pressed by a squeegee, and a discharge surface discharging a paste. The frame fixes an edge of the mesh. The emulsion pattern is placed on the discharge surface and includes a main pattern, and an auxiliary pattern spaced apart from the main pattern. | 2012-08-30 |
20120220072 | COPPER NANO PASTE, METHOD FOR FORMING THE COPPER NANO PASTE, AND METHOD FOR FORMING ELECTRODE USING THE COPPER NANO PASTE - Provided is a copper nano paste that can be calcined at a relatively low temperature. The copper nano paste includes: a binder added in an amount of 0.1 to 30 parts by weight; an additive added in an amount of not more than 10 parts by weight; and copper particles added in an amount of 1 to 95 parts by weight, wherein the copper particles have a particle size of 150 nm or less, and the surfaces of the copper particles are coated with a capping material. | 2012-08-30 |
20120220073 | METHODS OF MANUFACTURING A SOLAR CELL - Provided are methods of fabricating a solar cell and a vacuum deposition apparatus used therefor. The method may include forming a lower electrode on a substrate, forming a light absorption layer on the lower electrode, forming a buffer layer on the light absorption layer, and forming a window electrode layer on the buffer layer. The forming of the buffer layer may include a deposition step of forming a cationic metal material and a diffusion step of diffusing an anionic non-metal material into the cationic metal material. | 2012-08-30 |
20120220074 | METHOD AND APPARATUS FOR PRODUCTION OF DSSC - An apparatus and method for producing a dye-sensitized cell are provided, in which a pre-transparent electrode and an opposite electrode are partially bonded, dye molecules are applied to the bonded electrodes followed by washing, an electrolyte is injected, and then the electrodes are hermetically sealed. With the apparatus and method, the manufacturing cost can be reduced and the manufacturing process can be simplified. | 2012-08-30 |
20120220075 | Solution-Processed Organic Electronic Structural Element with Improved Electrode Layer - A solution-processed organic electronic structural element has an improved electrode layer. Located between the active organic layer and the electrode layer there is either an interface or an interlayer containing a cesium salt. | 2012-08-30 |
20120220076 | Method of Making a Multicomponent Film - Described herein is a method and liquid-based precursor composition for depositing a multicomponent film. In one embodiment, the method and compositions described herein are used to deposit Germanium Tellurium (GeTe), Antimony Tellurium (SbTe), Antimony Germanium (SbGe), Germanium Antimony Tellurium (GST), Indium Antimony Tellurium (IST), Silver Indium Antimony Tellurium (AIST), Cadmium Telluride (CdTe), Cadmium Selenide (CdSe), Zinc Telluride (ZnTe), Zinc Selenide (ZnSe), Copper indium gallium selenide (CIGS) films or other tellurium and selenium based metal compounds for phase change memory and photovoltaic devices. | 2012-08-30 |
20120220077 | THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THE SAME AND FLAT PANEL DISPLAY DEVICE HAVING THE SAME - A thin film transistor, a method of manufacturing the thin film transistor, and a flat panel display device including the thin film transistor. The thin film transistor includes: a gate electrode formed on a substrate; a gate insulating film formed on the gate electrode; an activation layer formed on the gate insulating film; a passivation layer including a compound semiconductor oxide, formed on the activation layer; and source and drain electrodes that contact the activation layer. | 2012-08-30 |
20120220078 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having stable electric characteristics in which an oxide semiconductor is used. An oxide semiconductor layer is subjected to heat treatment for dehydration or dehydrogenation treatment in a nitrogen gas or an inert gas atmosphere such as a rare gas (e.g., argon or helium) or under reduced pressure and to a cooling step for treatment for supplying oxygen in an atmosphere of oxygen, an atmosphere of oxygen and nitrogen, or the air (having a dew point of preferably lower than or equal to −40° C., still preferably lower than or equal to −50° C.) atmosphere. The oxide semiconductor layer is thus highly purified, whereby an i-type oxide semiconductor layer is formed. A semiconductor device including a thin film transistor having the oxide semiconductor layer is manufactured. | 2012-08-30 |
20120220079 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor device, an opening formed in a semiconductor substrate by using a mask and covering an inner side face of the opening with a sidewall protective film. The mask is removed, while a part of the sidewall protective film remains. | 2012-08-30 |
20120220080 | Method for Fabricating Flip-Attached and Underfilled Semiconductor Devices - A semiconductor device, which comprises a workpiece with an outline and a plurality of contact pads and further an external part with a plurality of terminal pads. This part is spaced from the workpiece and the terminal pads are aligned with the workpiece contact pads, respectively. A reflow element interconnects each of the contact pads with its respective terminal pad. Thermoplastic material fills the space between the workpiece and the part; this material adheres to the workpiece, the part and the reflow elements. Further, the material has an outline substantially in line with the outline of the workpiece, and fills the space substantially without voids. Due to the thermoplastic character of the filling material, the finished device can be reworked, when the temperature range for reflowing the reflow elements is reached. | 2012-08-30 |
20120220081 | METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE STRUCTURE - A method of fabricating a semiconductor package structure is provided that includes: providing a chip having an active surface and a plurality of conductive bumps formed on the active surface, and a base substrate having an underfill layer formed on a surface thereof; attaching the active surface of the chip to the underfill layer, such that the conductive bumps are embedded in the underfill layer; removing the base substrate to expose the underfill layer; and attaching the chip to a package substrate via the underfill layer, such that the chip is electrically connected to the package substrate by the conductive bumps. Since the underfill layer is attached to the active surface of the chip first, and the underfill layer is provided on the package substrate, performing a soldering process is not needed, material cost is decreased, and the fabrication process is simplified. | 2012-08-30 |
20120220082 | SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES - Semiconductor packages and methods of forming a semiconductor package are disclosed. The method includes providing at least one die having first and second surfaces. The second surface of the die includes a plurality of conductive pads. A permanent carrier is provided and the at least one die is attached to the permanent carrier. The first surface of the at least one die is facing the permanent carrier. A cap having first and second surfaces is formed to encapsulate the at least one die. The first surface of the cap contacts the permanent carrier and the second surface of the cap is disposed at a different plane than the second surface of the die. | 2012-08-30 |
20120220083 | HYBRID FIN FIELD-EFFECT TRANSISTOR STRUCTURES AND RELATED METHODS - Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. | 2012-08-30 |
20120220084 | METHOD OF FABRICATING POLYCRYSTALLINE SILICON LAYER, TFT FABRICATED USING THE SAME, METHOD OF FABRICATING TFT, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE SAME - A method of fabricating a polycrystalline silicon layer includes: forming an amorphous silicon layer on a substrate; crystallizing the amorphous silicon layer into a polycrystalline silicon layer using a crystallization-inducing metal; forming a metal layer pattern or metal silicide layer pattern in contact with an upper or lower region of the polycrystalline silicon layer corresponding to a region excluding a channel region in the polycrystalline silicon layer; and annealing the substrate to getter the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer to the region in the polycrystalline silicon layer having the metal layer pattern or metal silicide layer pattern. Accordingly, the crystallization-inducing metal existing in the channel region of the polycrystalline silicon layer can be effectively removed, and thus a thin film transistor having an improved leakage current characteristic and an OLED display device including the same can be fabricated. | 2012-08-30 |
20120220085 | THIN FILM TRANSISTOR, METHOD OF FABRICATING THE SAME, AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE HAVING THE THIN FILM TRANSISTOR - A thin film transistor (TFT), a method of fabricating the same, and an organic light emitting diode (OLED) display device including the TFT. The TFT includes a substrate having a pixel region and a non-pixel region, a semiconductor layer, a gate insulating layer, a gate electrode, and source and drain electrodes disposed on the pixel region, at least one gettering site disposed on the non-pixel region, and at least one connection portion to connect the at least one gettering site and the semiconductor layer. The method of fabricating the TFT includes patterning a polycrystalline silicon (poly-Si) layer to form a plurality of semiconductor layers, connection portions, and at least one gettering site, the semiconductor layers being connected to the at least one gettering site via the connection portions, and annealing the substrate to getter the plurality of semiconductor layers. | 2012-08-30 |
20120220086 | METHODS FOR FABRICATING A CMOS INTEGRATED CIRCUIT HAVING A DUAL STRESS LAYER (DSL) - Methods are provided for fabricating a CMOS integrated circuit having a dual stress layer without NiSi hole formation. One method includes depositing a tensile stress layer overlying a semiconductor substrate. A portion of the tensile stress layer is removed, leaving a remaining portion, before applying a curing radiation. A curing radiation is then applied to the remaining portion; and a compressive stress layer is deposited overlying the semiconductor substrate and the remaining portion. | 2012-08-30 |
20120220087 | VARIABLE RESISTANCE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME - A variable resistance memory device includes a substrate having a cell array region and a peripheral circuit region, an epitaxial semiconductor layer on the cell array region and the peripheral circuit region, and a peripheral transistor whose channel region is constituted by the epitaxial semiconductor layer on the peripheral circuit region. The peripheral transistor is formed by forming a gate electrode structure on the epitaxial semiconductor layer, and implanting impurities into the epitaxial semiconductor layer to form a source/drain region. | 2012-08-30 |
20120220088 | ULTRAHIGH DENSITY VERTICAL NAND MEMORY DEVICE AND METHOD OF MAKING THEREOF - Monolithic, three dimensional NAND strings include a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes having a strip shape extending substantially parallel to the major surface of the substrate, the blocking dielectric comprising a plurality of blocking dielectric segments, a plurality of discrete charge storage segments, and a tunnel dielectric located between each one of the plurality of the discrete charge storage segments and the semiconductor channel. | 2012-08-30 |
20120220089 | COMPOUND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A gate electrode is formed so as to embed an electrode material in a recess for an electrode, which has been formed in a structure of stacked compound semiconductors, through a gate insulation film, and also a field plate electrode that comes in Schottky contact with the structure of the stacked compound semiconductors is formed by embedding an electrode material in a recess for an electrode, which has been formed in the structure of the stacked compound semiconductors so that the field plate electrode directly comes in contact with the structure of the stacked compound semiconductors at least on the bottom face of the recess for the electrode. | 2012-08-30 |
20120220090 | METHOD FOR MANUFACTURING AN INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region. | 2012-08-30 |
20120220091 | METHODS OF MAKING POWER SEMICONDUCTOR DEVICES WITH THICK BOTTOM OXIDE LAYER - A method for forming thick oxide at the bottom of a trench formed in a semiconductor substrate includes forming a conformal oxide film by a sub-atmospheric chemical vapor deposition process that fills the trench and covers a top surface of the substrate. The method also includes etching the oxide film off the top surface of the substrate and inside the trench to leave a substantially flat layer of oxide having a target thickness at the bottom of the trench. | 2012-08-30 |
20120220092 | METHOD OF FORMING A HYBRID SPLIT GATE SIMICONDUCTOR - Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches. | 2012-08-30 |
20120220093 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present application discloses a method for manufacturing a semiconductor device, comprising: forming a local buried isolation dielectric layer in a semiconductor substrate; forming a fin in the semiconductor substrate and on top of the local buried isolation dielectric layer; forming a gate stack structure on a top surface and side surfaces of the fin; forming source/drain structures in portions of the fin which are on opposite sides of the gate stack structure; and performing metallization. A conventional quasi-planar top-down process is utilized in the present invention to achieve a good compatibility with the CMOS planar processes, easy integration, and suppression of short channel effects, which promotes the development of MOSFETs having reduced sizes. | 2012-08-30 |
20120220094 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer. | 2012-08-30 |
20120220095 | SEMICONDUCTOR DEVICE FABRICATION METHOD FOR IMPROVED ISOLATION REGIONS AND DEFECT-FREE ACTIVE SEMICONDUCTOR MATERIAL - A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon. | 2012-08-30 |
20120220096 | PLASMA DOPING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A plasma doping method capable of introducing impurities into an object to be processed uniformly is supplied. Plasma of a diborane gas containing boron, which is a p-type impurity, and an argon gas, which is a rare gas, is generated, and no bias potential is applied to a silicon substrate. Thereby, the boron radicals in the plasma are deposited on the surface of the silicon substrate. After that, the supply of the diborane gas is stopped, and bias potential is applied to the silicon substrate. Thereby, the argon ions in the plasma are radiated onto the surface of the silicon substrate. The radiated argon ions collide with the boron radicals, and thereby boron radicals are introduced into the silicon substrate. The introduced boron radicals are activated by thermal processing, and thereby a p-type impurity diffusion layer is formed in the silicon substrate. | 2012-08-30 |
20120220097 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area | 2012-08-30 |
20120220098 | Methods of Forming Dielectric Material-Containing Structures - Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components. | 2012-08-30 |
20120220099 | Forming a Phase Change Memory With an Ovonic Threshold Switch - A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current. | 2012-08-30 |
20120220100 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 2012-08-30 |
20120220101 | INTERNAL CONDUCTIVE LAYER - The invention provides advances in the arts with useful and novel methods for assembling multi-layer semiconductor structures having one or more internal conductive layers. The disclosed structures provide advantages in terms of resistance to Single Event Effects (SEE) particularly useful in electronics designed for radiation hardness. Disclosed methods include steps for providing two semiconductor layers, each having a conductive surface, and bonding them together with their conductive surfaces adjoining in order to form an internal conductive layer within a completed multi-layer structure. The conductive surfaces may include metals selected for their superior conductivity, refractory metals, selected primarily for their heat-resistance, or conductive dopants. In alternative embodiments, vertical interconnects are also included. | 2012-08-30 |
20120220102 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method of manufacturing semiconductor wafers, the method comprising providing a donor wafer comprising a semiconductor substrate; performing a lithography step and process the said donor wafer accordingly; and performing at least two layers transfer out of said donor wafer wherein each of said at least two layer had been effected by said process | 2012-08-30 |
20120220103 | SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer. | 2012-08-30 |
20120220104 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME - A semiconductor IC includes grooves formed in a substrate to define a first dummy region and second dummy regions formed at a scribing area, and third dummy regions and a fourth dummy region formed at a product area. A width of the first dummy region is greater than widths of each of the second and third dummy regions and a width of the fourth dummy region is greater than widths of each of the third dummy regions. A conductor pattern is formed over the first dummy region for optical pattern recognition. The first dummy region is formed under the conductor pattern so the grooves are not formed under the conductor pattern. The second dummy regions are spaced from one another by a predetermined spacing at the scribing area, and the third dummy regions are spaced from one another by a predetermined spacing at the product area. | 2012-08-30 |
20120220105 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE - A method of manufacturing a semiconductor device includes: holding a semiconductor substrate with a surface inclined with respect to the vertical direction and the horizontal direction; and immersing the semiconductor substrate in a cleaning solution including an acid. | 2012-08-30 |
20120220106 | CARBON NANOTUBE FORMING METHOD AND PRE-TREATMENT METHOD THEREFOR - A carbon nanotube forming method including providing a target substrate to be processed, a catalytic metal layer being formed on a surface of the target substrate; producing catalytic fine metal particles whose surfaces are oxidized by action of an oxygen plasma on the catalytic metal layer at a temperature T | 2012-08-30 |
20120220107 | SUBSTRATE PROCESSING APPARATUS, WAFER HOLDER, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a substrate processing apparatus having a stack structure of wafers that can endure a high temperature without bad influence on film-forming precision. The stack structure includes a holder base ( | 2012-08-30 |
20120220108 | SUBSTRATE PROCESSING APPARATUS, AND METHOD OF MANUFACTURING SUBSTRATE - When processing such as SiC epitaxial growth is performed at an ultrahigh temperature of 1500° C. to 1700° C., a film-forming gas can be decreased to heat-resistant temperature of a manifold and film quality uniformity can be improved. A substrate processing apparatus includes a reaction chamber for processing a plurality of substrates, a boat for holding the plurality of substrates, a gas supply nozzle for supplying a film-forming gas to the plurality of substrates, an exhaust port for exhausting the film-forming gas supplied into the reaction chamber, a heat exchange part which defines a second flow path narrower than a first flow path defined by an inner wall of the reaction chamber and the boat, and a gas discharge part installed under the lowermost substrate of the plurality of substrates. | 2012-08-30 |
20120220109 | PLASMA CVD DEVICE AND METHOD OF MANUFACTURING SILICON THIN FILM - A plasma CVD device comprises a vacuum vessel that houses a discharge electrode plate and a ground electrode plate to which is attached a substrate for thin film formation. The plasma CVD device has an earth cover at an interval from and facing the aforementioned discharge electrode plate; the aforementioned discharge electrode plate has gas inlets and exhaust outlets (which expel gas introduced through said gas inlets) that are connected at one end to equipment supplying raw gas for thin film formation and that open at the other end at the bottom face of the aforementioned discharge electrode plate; the aforementioned earth cover has second gas inlets corresponding to the aforementioned gas inlets, and second exhaust outlets corresponding to the aforementioned exhaust outlets. The plasma CVD device has an electric potential control plate disposed at an interval from and facing the aforementioned ground cover. | 2012-08-30 |
20120220110 | SEMICONDUCTOR FABRICATION APPARATUSES TO PERFORM SEMICONDUCTOR ETCHING AND DEPOSITION PROCESSES AND METHODS OF FORMING SEMICONDUCTOR DEVICE USING THE SAME - A semiconductor fabrication apparatus and a method of fabricating a semiconductor device using the same performs semiconductor etching and deposition processes at an edge of a semiconductor substrate after disposing the semiconductor substrate at a predetermined place in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus has lower, middle and upper electrodes sequentially stacked. The semiconductor substrate is disposed on the middle electrode. Semiconductor etching and deposition processes are performed on the semiconductor substrate in the semiconductor fabrication apparatus. The semiconductor fabrication apparatus forms electrical fields along an edge of the middle electrode during performance of the semiconductor etching and deposition processes. | 2012-08-30 |
20120220111 | INJECTION METHOD WITH SCHOTTKY SOURCE/DRAIN - An injection method for non-volatile memory cells with a Schottky source and drain is described. Carrier injection efficiency is controlled by an interface characteristic of silicide and silicon. A Schottky barrier is modified by controlling an overlap of a gate and a source/drain and by controlling implantation, activation and/or gate processes. | 2012-08-30 |
20120220112 | POSITIVE RESIST COMPOSITION AND PATTERNING PROCESS - A positive resist composition based on a polymer comprising recurring units of (meth)acrylate having a cyclic acid labile group and a dihydroxynaphthalene novolak resin, and containing a photoacid generator is improved in resolution, step coverage and adhesion on a highly reflective stepped substrate, has high resolution, and forms a pattern of good profile and minimal edge roughness through exposure and development. | 2012-08-30 |
20120220113 | Method of Manufacturing Semiconductor Device Having Metal Gate - The present invention provides a method of manufacturing semiconductor device having metal gate. First, a substrate is provided. A first conductive type transistor having a first sacrifice gate and a second conductive type transistor having a second sacrifice gate are disposed on the substrate. The first sacrifice gate is removed to form a first trench and then a first metal layer and a first material layer are formed in the first trench. Next, the first metal layer and the first material layer are flattened. The second sacrifice gate is removed to form a second trench and then a second metal layer and a second material layer are formed in the second trench. Lastly, the second metal layer and the second material layer are flattened. | 2012-08-30 |
20120220114 | TENSILE STRESS ENHANCEMENT OF NITRIDE FILM FOR STRESSED CHANNEL FIELD EFFECT TRANSISTOR FABRICATION - A method for inducing a tensile stress in a channel of a field effect transistor (FET) includes forming a nitride film over the FET; forming a contact hole to the FET through the nitride film; and performing ultraviolet (UV) curing of the nitride film after forming the contact hole to the FET through the nitride film, wherein the UV cured nitride film induces the tensile stress in the channel of the FET. | 2012-08-30 |
20120220115 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming at least two gate patterns on a substrate, forming sidewalls surrounding the gate patterns, wherein the sidewalls extend above an upper surface of the gate patterns, and forming a first conducting material in a first space and a second space, wherein the first space is provided above the gate patterns and between the sidewalls that extend above the upper surface of the gate patterns and the second space is provided between the gate patterns. | 2012-08-30 |
20120220116 | Dry Chemical Cleaning For Semiconductor Processing - A deposition process including a dry etch process, followed by a deposition process of a high-k dielectric is disclosed. The dry etch process involves placing a substrate to be cleaned into a processing chamber to remove surface oxides. A gas mixture is energized to form a plasma of reactive gas which reacts with an oxide on the substrate, forming a thin film. The substrate is heated to vaporize the thin film and expose a substrate surface. The substrate surface is substantially free of oxides. Deposition is then used to form a layer on the substrate surface. | 2012-08-30 |
20120220117 | POLYMER AND SOLDER PILLARS FOR CONNECTING CHIP AND CARRIER - A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars. | 2012-08-30 |
20120220118 | CHIP AND MANUFACTURING METHOD THEREOF - A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has an active surface. The semiconductor device includes at least a connecting element and at least a bump. The connecting element is disposed on the activate surface and has a minimum dimension smaller than 100 microns. The bump is disposed on the connecting element and is electrically connected to the active surface by the connecting element. The bump includes a pillar part disposed on the connecting element and a top part disposed at the top of the pillar part. The pillar part has a first dimension and a second dimension both parallel to the active surface. The first dimension is longer than 1.2 times the second dimension. The top part is composed of solder and will melt under the determined temperature. The pillar part will not melt under a determined temperature. | 2012-08-30 |
20120220119 | SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS - Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance. | 2012-08-30 |
20120220120 | METHOD FOR FABRICATING BURIED BIT LINE IN SEMICONDUCTOR DEVICE - A method for fabricating a buried bit line in a semiconductor device includes forming a liner oxide layer over the entire surface of a substrate having bodies isolated by a trench, selectively etching the liner oxide layer contacted with one side surface of the trench to a given depth, forming a sacrifice layer at a larger height than an etched surface of the liner oxide layer wherein the sacrifice layer partially fills the trench to the larger height, forming a liner nitride layer on sidewalls of the trench over the sacrifice layer, removing the sacrifice layer to expose a part of a body at the one side surface of the trench, forming a barrier layer along the entire surface of the resultant structure including the liner oxide layer, and forming a buried bit line over the barrier layer to be contacted with the exposed part of the body. | 2012-08-30 |
20120220121 | FILM FORMING METHOD AND STORAGE MEDIUM - In a film forming method for forming a Co film on a substrate provided in a processing chamber, gaseous Co | 2012-08-30 |
20120220122 | NITRIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes an insulating layer and a metal layer formed on a nitride semiconductor layer. The insulating layer makes contact with the nitride semiconductor layer. A separation preventing layer is formed between the insulating layer and the metal layer so as to make contact with each of these layers. The separation preventing layer has, as a main component, at least one kind of oxide of a metal selected from the group consisting of tungsten, molybdenum, chromium, titanium, nickel, hafnium, zinc, indium and yttrium. | 2012-08-30 |
20120220123 | THROUGH-HOLE ELECTRODE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A through-hole electrode substrate related to an embodiment of the present invention is arranged with a semiconductor substrate having a plurality of through-holes, an insulating layer formed with an insulating material on the inner walls of the plurality of through-holes and on at least one surface of the semiconductor substrate, a plurality of through-hole electrodes formed with a metal material inside the through-hole, and a plurality of gas discharge parts formed to contact with each of the plurality of through-hole electrodes which is exposed on at least one surface of the semiconductor substrate, the plurality of gas discharge parts externally discharges gas which is discharged from the inside of the plurality of through-hole electrodes. | 2012-08-30 |
20120220124 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an insulation layer containing an impurity, forming a contact hole by etching the insulation layer, performing a treatment to decrease a concentration of the impurity on a surface of the insulation layer, and rinsing the contact hole. | 2012-08-30 |
20120220125 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate including first landing plugs and second landing plugs that are arrayed on a first line, forming a capping layer over the substrate, forming hole-type first trenches that expose the second landing plugs by selectively etching the capping layer, forming an insulation layer over the substrate including the first trenches, forming line-type second trenches that are stretched on the first line while overlapping with the first trenches by selectively etching the insulation layer, and forming a first conductive layer inside the second trenches. | 2012-08-30 |
20120220126 | Selective Metal Deposition Over Dielectric Layers - Selective deposition of metal over dielectric layers in a manner that minimizes of eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured as allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over substrate layer. | 2012-08-30 |
20120220127 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device includes: forming a metal layer having a surface containing gold; growing a first silicon nitride layer in contact with the metal layer by a plasma-enhanced vapor deposition method; growing a second silicon nitride layer in contact with the first silicon nitride layer by a plasma-enhanced vapor deposition method at a layer-forming rate higher than that of the first silicon nitride layer, the second silicon nitride layer having a silicon composition ratio smaller than that of the first silicon nitride layer. | 2012-08-30 |
20120220128 | METHOD FOR MANUFACTURING A TRANSISTOR - The invention provides a method for manufacturing a transistor which includes: providing a substrate having a plurality of transistors formed thereon, wherein each transistor includes a gate; forming a stressed layer and a first oxide layer on the transistors and on the substrate successively; forming a sacrificial layer on the first oxide layer; patterning the sacrificial layer to remove a part of the sacrificial layer which covers on the gates of the transistors; forming a second oxide layer on the residual sacrificial layer and on a part of the first oxide layer which is exposed after the part of the sacrificial layer is removed; performing a first planarization process to remove a part of the second oxide layer located on the gates of the transistors; performing a second planarization process to remove the residual second oxide layer; and performing a third planarization process to remove the stressed layer. | 2012-08-30 |
20120220129 | METHOD FOR FORMING MASK FOR FORMING CONTACT HOLES OF SEMICONDUCTOR DEVICE - A method for forming a mask for forming contact holes of a semiconductor device includes coating an etch target layer with a first photoresist layer, patterning the first photoresist layer in a type of lines and spaces to form a first photoresist pattern, wherein the first photoresist pattern comprises pads formed at both ends of the first photoresist pattern, and lines repeatedly formed between the pads at the both ends, forming a protective layer on a surface of the first photoresist pattern by performing a freezing process onto the first photoresist pattern, and forming a second photoresist pattern having a type of lines stretched in a second direction which is perpendicular to the first direction on the etch target layer including the protective layer. | 2012-08-30 |
20120220130 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a trench over a substrate, forming a spin on dielectric (SOD) layer in a first part of the trench, and forming an oxide layer within the trench, where the oxide layer is formed over the SOD layer by using a process for plasma chemical vapor deposition. | 2012-08-30 |
20120220131 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor memory device includes forming a photoresist layer on a substrate, performing an exposure process such by illuminating a first area of the photoresist layer with a first amount of a light and illuminating a second area of the photoresist layer with a light of a second amount smaller than the first amount, removing the first area of the photoresist layer to form a photoresist pattern, and forming a capping layer on a surface of the photoresist pattern. | 2012-08-30 |
20120220132 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a core layer, an anti-reflection film and a photoresist layer on a layer to be etched of a substrate; trimming first line patterns of the photoresist layer; forming a first film on the first line patterns; removing the first film such that the first film is left in sidewall portions of the first line patterns of the photoresist layer; removing the photoresist layer; producing the core layer into second line patterns by etching the anti-reflection film and the core layer; forming a second film on the core layer produced into the second line patterns; removing the second film such that the second film is left in sidewall portions of the second line patterns of the core layer; and producing the layer to be etched into third line patterns by etching the layer to be etched. | 2012-08-30 |