33rd week of 2015 patent applcation highlights part 54 |
Patent application number | Title | Published |
20150228692 | SOLID-STATE IMAGE PICKUP DEVICE - A solid-state image pickup device includes a plurality of pixels, each of the pixels including a photoelectric conversion portion, a charge holding portion, a floating diffusion, and a transfer portion. The pixel also includes a beneath-holding-portion isolation layer and a pixel isolation layer. An end portion on a photoelectric conversion portion side of the pixel isolation layer is away from the photoelectric conversion portion compared to an end portion on a photoelectric conversion portion side of the beneath-holding-portion isolation layer, and an N-type semiconductor region constituting part of the photoelectric conversion portion is disposed under at least part of the beneath-holding-portion isolation layer. | 2015-08-13 |
20150228693 | SOLID-STATE IMAGE PICKUP UNIT AND ELECTRONIC APPARATUS - There is configured a solid-state image pickup unit including a photoelectric conversion section formed on a light incident side of a substrate; a first charge accumulation section accumulating a signal charge generated by the photoelectric conversion section; a second charge accumulation section formed in a region other than a light-condensing region where incident light is condensed in the substrate on a side opposite to a light incident side and formed to be laminated together with the first charge accumulation section in a depth direction of the substrate; and a floating diffusion section formed in a region other than the light-condensing region in the substrate on the side opposite to the light incident side and converting the signal charge into a voltage. | 2015-08-13 |
20150228694 | Monolithically integrated CMOS and acoustic wave device - An integrated CMOS and acoustic wave device, including: an electrically insulating piezoelectric thin film having opposed first and second surfaces; one or more CMOS devices formed in a semiconductor thin film disposed on one or more portions of the first surface of the piezoelectric thin film; and at least one acoustic wave structure having electrically conductive transducer electrodes disposed on at least one of the first and second surfaces of the piezoelectric thin film. | 2015-08-13 |
20150228695 | MAGNETIC MEMORY DEVICE - According to one embodiment, a magnetic memory device includes a semiconductor substrate, a memory cell array area on the semiconductor substrate, the memory cell array area including magnetoresistive elements, each of the magnetoresistive elements having a reference layer with an invariable magnetization, a storage layer with a variable magnetization, and a tunnel barrier layer therebetween, a magnetic field generating area which generates a first magnetic field cancelling a second magnetic field applying from the reference layer to the storage layer, and which is separated from the magnetoresistive elements, and a closed magnetic path area functioning as a closed magnetic path of the first magnetic field, and surrounding the memory cell array area and the magnetic field generating area. | 2015-08-13 |
20150228696 | Organic Lighting Device and Lighting Equipment - An organic luminous means and an illumination device comprising such a luminous means are specified. An optical display apparatus, emergency lighting, motor vehicle interior lighting, an item of furniture, a construction material, a glazing and a display comprising such a luminous means and, respectively, comprising an illumination device having such a luminous means are furthermore specified. | 2015-08-13 |
20150228697 | ORGANIC LIGHT EMITTING DIODE (OLED) DEVICE AND A METHOD OF FABRICATING THE SAME - The present invention provides a color OLED device and method of fabricating the same. The color OLED device includes an OLED substrate, an OLED cover adhered to the OLED substrate and a color conversion layer formed on the OLED cover. The OLED substrate includes an OLED element formed thereon, and the OLED element includes a light emitting layer. The color conversion layer includes a plurality of quantum dots, light emitting from the light emitting layer is converted to colored light with the plurality of quantum dots in the color conversion layer. According to present invention, a color OLED device can be colorized with the plurality of quantum dots in the color conversion layer; moreover, with the characteristics of the plurality of quantum dots, a thickness of the color OLED device including the light emitting layer can be shrunken, lifetime, and color purity thereof can be enhanced. | 2015-08-13 |
20150228698 | PORTABLE INFORMATION APPLIANCE - An object of the present invention is to provide a portable information appliance having a thin organic electroluminescent illumination panel capable of color adjustment and uniform light emission. | 2015-08-13 |
20150228699 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting display apparatus includes: a substrate; a thin film transistor (TFT) on the substrate and including an active layer, a gate electrode overlapping a gate region of the active layer, a source electrode overlapping a source region of the active layer, and a drain electrode overlapping a drain region of the active layer; a first electrode electrically connected to one of the source electrode or the drain electrode; a first dummy conductive pattern overlapping a dummy region of the active layer between the gate region and one of the source region or the drain region corresponding to the one of the source electrode or the drain electrode; an intermediate layer on the first electrode and comprising at least an organic emission layer; and a second electrode on the intermediate layer. | 2015-08-13 |
20150228700 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY - An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels and each pixel includes a first area configured to emit light and a second area configured to transmit external light therethrough. Each pixel also includes a first electrode formed in the first area and an organic layer formed in the first area and the second area, wherein the organic layer covers the first electrode. Each pixel further includes a second electrode covering at least the organic layer formed in the first area and having a first opening exposing at least a portion of the organic layer formed in the second area. A reflection prevention layer is formed substantially covering the organic layer formed in the second area. The reflection prevention layer has a refractive index lower than that of the organic layer. | 2015-08-13 |
20150228701 | ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND METHOD FOR FABRICATING THE SAME - Disclosed is an organic light-emitting diode (OLED) display panel. An OLED display panel comprises a plurality of signal lines and a thin film transistor formed on a substrate, an interlayer insulating layer, a first electrode, a bank, an organic light-emitting layer, a second electrode, a first passivation layer, an organic layer, a second passivation layer and a barrier film, wherein the bank is formed to completely cover the interlayer insulating layer, and an inclination formed by side surfaces of the bank and the interlayer insulating layer is made to be gradual. | 2015-08-13 |
20150228702 | DISPLAY DEVICE - Provided is a display device including a display panel having a display area including a plurality of pixel columns, the display device including: a first pixel column including i pixels (i is a natural number) from among the plurality of pixel columns; a second pixel column including j pixels (j is a different natural number than i) from among the plurality of pixel columns; a first data line connected to the i pixels in the first pixel column, and to k pixels (k is a smaller natural number than j) from among the j pixels in the second pixel column; a second data line connected to j minus k (j-k) pixels from among the j pixels in the second pixel column; and gate lines connected to pixels in the first pixel column and the second pixel column. | 2015-08-13 |
20150228703 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n | 2015-08-13 |
20150228704 | DISPLAY DEVICE AND ELECTRONIC DEVICE - To provide a display device that is suitable for increasing in size, a display device in which display unevenness is suppressed, or a display device that can display an image along a curved surface. The display device includes a first display panel and a second display panel each including a pair of substrates. The first display panel and the second display panel each include a first region which can transmit visible light, a second region which can block visible light, and a third region which can perform display. The third region of the first display panel and the first region of the second display panel overlap each other. The third region of the first display panel and the second region of the second display panel do not overlap each other. | 2015-08-13 |
20150228705 | ORGANIC LIGHT-EMITTING DIODE (OLED) DISPLAY AND METHOD OF MANUFACTURING THE SAME - An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the OLED display comprises a driving thin-film transistor (TFT), a data line electrically connected to the driving TFT and having a first color, an OLED, and a light absorption layer. The OLED is electrically connected to the driving TFT. The light absorption layer is formed over the data line and has a second color different from the first color. | 2015-08-13 |
20150228706 | DISPLAY DEVICE - A display device according to an example embodiment of the present invention includes a display panel configured to display an image, the display panel including a plurality of pixels, a chip on film (COF) coupled to the display panel, the COF comprising a driver, a plurality of COF wires and a plurality of COF pads, and a flexible printed circuit board (FPCB) coupled to the COF, the FPCB including a plurality of FPCB wires and a plurality of FPCB pads, wherein the plurality of COF pads are arranged in two rows, and wherein one or more COF pads of the plurality of COF pads in a first row of the two rows are one or more dummy pads. | 2015-08-13 |
20150228707 | INDUCTOR DESIGN ON FLOATING UBM BALLS FOR WAFER LEVEL PACKAGE (WLP) - An inductor design on a wafer level package (WLP) does not need to depopulate the solder balls on the die because the solder balls form part of the inductor. One terminal on the inductor couples to the die, the other terminal couples to a single solder ball on the die, and the remaining solder balls that mechanically contact the inductor remain electrically floating. The resulting device has better inductance, direct current (DC) resistance, board-level reliability (BLR), and quality factor (Q). | 2015-08-13 |
20150228708 | TUNABLE POLY RESISTORS FOR HYBRID REPLACEMENT GATE TECHNOLOGY AND METHODS OF MANUFACTURING - A poly resistor manufacturing method which allows resistor targeting and/or tuning by process rather than by design is disclosed. Embodiments include forming a high-k dielectric on a STI layer; forming a Ti layer on the high-k dielectric; forming a dummy Si layer on the TiN layer; forming spacers at opposite sides of the high-k dielectric, TiN, and dummy Si layers; forming an ILD surrounding the spacers; removing a portion of the dummy Si layer adjacent to each spacer, down to the TiN layer, to form a metal resistor end region; filling each metal resistor end region with a pWF stack; recessing the dummy Si layer between the pWF stacks; forming a TiN hardmask over the ILD, the spacers, the pWF stacks, and the recessed dummy Si layer; forming a nWF stack over the TiN hardmask; and planarizing the nWF metal stack and the TiN hardmask down to the ILD. | 2015-08-13 |
20150228709 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a semiconductor device having a substrate including first and second regions. First interlayer insulation layers and conductive patterns alternately are stacked on a first region of the substrate. A second interlayer insulation layer covers the first interlayer insulation layers and the conductive patterns. A resistor is formed in the second interlayer insulation layer in the second region of the substrate. | 2015-08-13 |
20150228710 | Methods to Improve Electrical Performance of ZrO2 Based High-K Dielectric Materials for DRAM Applications - A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly-doped or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly-doped or non-doped material will become crystalline (ā§30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack. | 2015-08-13 |
20150228711 | Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Manufacturing Capacitors - Semiconductor devices, methods of manufacture thereof, and methods of manufacturing capacitors are disclosed. In an embodiment, a method of manufacturing a capacitor includes: etching a trench in a workpiece. The trench may extend into the workpiece from a major surface of the workpiece. The method further includes lining the trench with a bottom electrode material and lining the bottom electrode material in the trench with a dielectric material. The dielectric material may have edges proximate the major surface of the workpiece. The method further includes forming a top electrode material over the dielectric material in the trench, and etching away a portion of the bottom electrode material and a portion of the top electrode material proximate the edges of the dielectric material. | 2015-08-13 |
20150228712 | HIGH QUALITY FACTOR CAPACITORS AND METHODS FOR FABRICATING HIGH QUALITY FACTOR CAPACITORS - Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape. | 2015-08-13 |
20150228713 | High Voltage Diode - A trench-isolated RESURF diode structure ( | 2015-08-13 |
20150228714 | ISOLATION METHODS FOR LEAKAGE, LOSS AND NON-LINEARITY MITIGATION IN RADIO-FREQUENCY INTEGRATED CIRCUITS ON HIGH-RESISTIVITY SILICON-ON-INSULATOR SUBSTRATES - A radio frequency integrated circuit with a silicon-on-insulator substrate includes a buried oxide layer that is disposed over a silicon substrate. The silicon-on-insulator substrate has a silicon layer that is disposed over the buried oxide layer. The integrated circuit includes a transistor disposed on the silicon layer, and a guard-ring in the silicon-on-insulator substrate that surrounds the transistor on the silicon layer. Depletion regions on the silicon substrate corresponding to areas surrounding the transistor is defined by the application of a voltage to the guard-ring. Isolation of radio frequency transmission lines on silicon-on-insulator substrates is also possible with this configuration. | 2015-08-13 |
20150228715 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming a first active region, a second active region, an inactive region located between the first active region and the second active region, and a third active region, which crosses the inactive region to electrically connect the first active region to the second active region, in a semiconductor layer; forming an insulating layer on the semiconductor layer; and forming an opening selectively in the insulating layer by dry etching. | 2015-08-13 |
20150228716 | METHOD FOR PRODUCING A SEMICONDUCTOR BODY HAVING A RECOMBINATION ZONE, SEMICONDUCTOR COMPONENT HAVING A RECOMBINATION ZONE, AND METHOD FOR PRODUCING SUCH A SEMICONDUCTOR COMPONENT - A semiconductor body may include impurities. The impurities may act as recombination centers in the semiconductor body and form a recombination zone are introduced into the semiconductor body during the process of producing the semiconductor body. | 2015-08-13 |
20150228717 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device having high durability against avalanche breakdown is provided. A method for manufacturing a semiconductor device is provided with an IGBT region, a diode region, and a peripheral region includes: forming crystal defects in an n-type region by implanting charged particles into an n-type region in the diode region and an n-type region in the peripheral region; and forming crystal defects in the n-type region by implanting charged particles into an n-type region in the IGBT region and the n-type region in the peripheral region. | 2015-08-13 |
20150228718 | VERTICAL STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR DEVICE - According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a substrate; forming an etch stop layer over the vertical structure; forming an oxide layer over the etch stop layer; performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer; etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation layer; oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping treatment. | 2015-08-13 |
20150228719 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second fin-shaped silicon layers on a substrate, each corresponding to the dimensions of a sidewall pattern around a dummy pattern. First and second pillar-shaped silicon layers reside on the first and second fin-shaped silicon layers, respectively. An n-type diffusion layer resides in an upper portion of the first fin-shaped silicon layer and in upper and lower portions of the first pillar-shaped silicon layer. A p-type diffusion layer resides in an upper portion of the second fin-shaped silicon layer and upper and lower portions of the second pillar-shaped silicon layer. First and second gate insulating films and metal gate electrodes are around the first and second pillar-shaped silicon layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped silicon layers. | 2015-08-13 |
20150228720 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - A semiconductor structure includes a wafer including a first surface and a periphery, a plurality of protrusions protruded from the first surface and a plurality of recesses spaced from each other by the plurality of protrusions, and each of the plurality of recesses is extended from the periphery of the wafer and is elongated across the first surface of the wafer. | 2015-08-13 |
20150228721 | FIN STRUCTURE AND METHOD FOR FORMING THE SAME - According to an exemplary embodiment, a method of forming a fin structure is provided. The method includes the following operations: etching a first dielectric layer to form at least one recess and a first core portion of a fin core; form an oxide layer as a shallow trench isolation layer in the recess; etching back the oxide layer to expose a portion of the fin core; and forming a fin shell to cover a sidewall of the exposed portion of the fin core. | 2015-08-13 |
20150228722 | SEMICONDUCTOR DEVICE INCLUDING FIN-TYPE FIELD EFFECT TRANSISTOR - Provided is a semiconductor device including: a substrate; a first fin-field effect transistor comprising a first fin-type semiconductor layer having a first height and a first width, formed on the substrate; and a second fin-field effect transistor comprising a second fin-type semiconductor layer having a second height and a second width, formed on the substrate. The first fin-field effect transistor and the second fin-field effect transistor are separated by a predetermined distance. The first height is greater than the second height and the first width is less than the second width. | 2015-08-13 |
20150228723 | Semiconductor Device, Method for Manufacturing the Same and IGBT with Emitter Electrode Electrically Connected with Impurity Zone - A semiconductor device includes a semiconductor body including a drift zone of a first conductivity type, an emitter region of a second, complementary conductivity type configured to inject charge carriers into the drift zone, and an emitter electrode. The emitter electrode includes a metal silicide layer in direct ohmic contact with the emitter region. A net impurity concentration in a portion of the emitter region directly adjoining the metal silicide layer is at most 1Ć10 | 2015-08-13 |
20150228724 | Modulating Germanium Percentage in MOS Devices - An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is overlying the first silicon germanium region, wherein the second silicon germanium region has a second germanium percentage higher than the first germanium percentage. A metal silicide region is over and in contact with the second silicon germanium region. | 2015-08-13 |
20150228725 | Buried-Channel FinFET Device and Method - A fin field effect transistor (FinFET), and a method of fabrication, is introduced. In an embodiment, trenches are formed in a substrate, wherein a region between adjacent trenches defines a fin. A dielectric material is formed in the trenches. The fins are doped to form source, drain and buried channel regions. A gate stack is formed over the buried channel regions. Contacts are formed to provide electrical contacts to the source/drain regions and the gate. | 2015-08-13 |
20150228726 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device includes: first and second electrodes; a first semiconductor region being in ohmic contact with the first electrode; a second semiconductor region being in contact with the first semiconductor region and the first electrode, and the second semiconductor region having a lower impurity concentration than the first semiconductor region; a first semiconductor layer; a second semiconductor layer; a third semiconductor region; a fourth semiconductor region being in contact with the second electrode; and a third electrode in contact with the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region via an insulating film. A peak of impurity concentration profile of the first semiconductor layer in a direction from the first electrode toward the second electrode is located between the first semiconductor region and the second semiconductor layer and located between the second semiconductor region and the second semiconductor layer. | 2015-08-13 |
20150228727 | DIAMOND SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - The present invention provides a diamond semiconductor device which includes: a diamond substrate; a diamond step section disposed over substrate surface of the diamond substrate having a {001} crystal face to rise substantially perpendicularly to substrate surface; an n-type phosphorus-doped diamond region; and a diamond insulation region. In the diamond step section, a first step section having a {110} crystal face over a side surface is integrated with a second step section having a {100} crystal face over a side surface. The phosphorus-doped diamond region is formed by crystal growth started from base angle of the step shape of the first step section over the side surface of the first step section and substrate surface of the diamond substrate as growth base planes. The diamond insulation region is formed by crystal growth over the side surface of the second step section and substrate surface of the diamond substrate as growth base planes. | 2015-08-13 |
20150228728 | FORMATION OF LARGE SCALE SINGLE CRYSTALLINE GRAPHENE - A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate. | 2015-08-13 |
20150228729 | PROTECTION CIRCUIT INCLUDING VERTICAL GALLIUM NITRIDE SCHOTTKY DIODE AND SCHOTTKY DIODE - A circuit includes a vertical conduction gallium nitride-based Schottky diode and a vertical conduction silicon based PN junction diode connected in parallel. The Schottky diode and the PN junction diode are packaged in the same semiconductor package and the PN junction diode does not conduct in response to the Schottky diode being forward biased. In some embodiments, the silicon based PN junction diode has a breakdown voltage lower than a breakdown voltage of the gallium nitride-based Schottky diode. The silicon based PN junction diode enters breakdown in response to the gallium nitride-based Schottky diode being reverse biased to divert a reverse bias avalanche current away from the gallium nitride-based Schottky diode. | 2015-08-13 |
20150228730 | METAL-OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR, METHOD OF FABRICATING THE SAME, AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME - Example embodiments relate to a metal-oxide semiconductor field effect transistor (MOSFET) of a high performance operating with a necessary threshold voltage while including a channel region formed based on a group III-V compound, and a method of manufacturing the MOSFET. The MOSFET includes a substrate, a semiconductor layer including a group III-V compound on the substrate, and a gate structure disposed on the semiconductor layer, and including a gate electrode formed based on metal and undergone an ion implantation process. | 2015-08-13 |
20150228731 | MODIFIED CHANNEL POSITION TO SUPPRESS HOT CARRIER INJECTION IN FINFETS - Some embodiments relate to an integrated circuit (IC) including one or more finFET devices. A finFET includes a fin of semiconductor material extending upwards from a semiconductor substrate. First and second source/drain regions, which have a first doping type, are spaced apart laterally from one another in the fin. A channel region is disposed in the fin and physically separates the first and second source/drain regions from one another. The channel region has a second doping type opposite the first doping type. A conductive gate electrode straddles the fin about the channel region and is separated from the channel region by a gate dielectric. A shallow doped region, which has the first doping type, is disposed near a surface of the fin around upper and sidewall fin regions. The shallow doped region extends continuously under the gate electrode between outer edges of the gate electrode. | 2015-08-13 |
20150228732 | THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME AND METHOD OF MANUFACTURING THE SAME - A thin film transistor substrate includes a gate electrode on a base substrate, an active pattern on the gate electrode, a source electrode on a first end of the active pattern, a drain electrode on a second end of the active pattern, an organic insulation layer on the source electrode and the drain electrode, and a transparent electrode contacting the drain electrode through a contact opening in the organic insulation layer. The drain electrode is spaced from the source electrode. The organic insulation layer includes a first thickness portion around the contact opening and a second thickness portion adjacent to the first thickness portion. The second thickness portion has a thickness greater than that of the first thickness portion. | 2015-08-13 |
20150228733 | Array Substrate, Manufacturing Method Thereof, and Display Device - The present disclosure provides an array substrate, a manufacturing method thereof, and a display device. The array substrate comprises a gate electrode, a gate line, a data line, a gate insulating layer, an active layer, a source electrode and a drain electrode on a substrate. The gate electrode, the gate line and the data line are arranged on an identical layer, the gate line intersects the data line at a right angle, and the data line is disconnected at an intersection with the gate line. The source electrode and the drain electrode are arranged above the gate electrode, the gate line and the data line, and the disconnected data lines are connected via the source electrode. | 2015-08-13 |
20150228734 | SEMICONDUCTOR STRUCTURE HAVING CONTACT PLUG AND METHOD OF MAKING THE SAME - The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same. | 2015-08-13 |
20150228735 | Semiconductor Device And Method For Manufacturing The Same - The present invention provides a method for manufacturing a semiconductor device, which comprises: providing an SOI substrate, which comprises a base layer, an insulating layer located on the base layer and a active layer located on the insulating layer; forming a gate stack on the SOI substrate; etching the active layer, the insulating layer and a part of the base layer of the SOI substrate with the gate stack as a mask, so as to form trenches on both sides of the gate stack; forming a crystal dielectric layer within the trenches, wherein the upper surface of the crystal dielectric layer is lower than the upper surface of the insulating layer and not lower than the lower surface of the insulating layer; and forming source/drain regions on the crystal dielectric layer. The present invention further provides a semiconductor device. The present invention is capable of eliminating pathway for leakage current between source/drain regions and SOI substrate at the meantime of reducing contact resistance at source/drain regions. | 2015-08-13 |
20150228736 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device includes processes of: (a) implant first conductivity type first impurities in a first region of a first surface; (b) form a second conductivity type semiconductor region exposed in the second region of the first surface by implanting second conductivity type second impurities in the second region; (c) implant charged particles at a dose amount larger than those of the first and the second impurities in a third region of the first surface which at least partially overlaps with the first region and is adjacent to the second region so that an implantation depth of the charged particles becomes shallower than that of the first impurities. After having performed the processes of (a) to (c), a metal is deposited on the second and the third regions, and the metal is caused to react with the semiconductor substrate to form the silicide layer. | 2015-08-13 |
20150228737 | SEMICONDUCTOR DEVICE - A semiconductor device includes a base region of a second conduction type provided over a drain region of a first conduction type, an outer peripheral well region of a second conduction type provided to cover the outer peripheral end of the base region and having an impurity concentration lower than that of the base region, a buried electrode buried in the semiconductor substrate not to overlap the outer peripheral well region, plural gate electrodes connected to the buried electrode and buried in the substrate such that each of them is adjacent to a source region, a gate interconnect provided over the substrate to overlap a portion of the outer peripheral well region in a plan view and connected to the buried electrode, and a grounding electrode provided over the substrate and connected to a portion of the outer peripheral well region not overlapping the gate interconnect in a plan view. | 2015-08-13 |
20150228738 | SPLIT-GATE FLASH CELL WITH COMPOSITE CONTROL GATE AND METHOD FOR FORMING THE SAME - A split-gate flash cell device and method for forming the same are not provided. The split-gate flash cell device includes a floating gate transistor. The floating gate transistor includes a floating gate and a control gate disposed over at least a portion of the floating gate, along a side of the floating gate and over a portion of the substrate adjacent the floating gate. The control gate includes a portion of SiGe material. In some embodiments, the control gate is a composite material with a lower SiGe layer and an upper material layer. The upper material layer is polysilicon or other suitable materials. | 2015-08-13 |
20150228739 | SPLIT GATE EMBEDDED MEMORY TECHNOLOGY AND MANUFACTURING METHOD THEREOF - A device and method of forming the device using a split gate embedded memory technology are presented. The device includes two polysilicon layers, one for floating gate poly and the other for logic, HV and stack gate and split gate. An oxide-nitride-oxide process of the manufacturing method results in low reliability risk and good uniformity in the device. Moreover, embodiments of the manufacturing method have good controllability of the profile and critical dimension of select gates in production. Furthermore, there is no need to provide non-volatile memory and high-voltage protection for devices manufactured by embodiments of the manufacturing method of the present disclosure. | 2015-08-13 |
20150228740 | Semiconductor Structure For Flash Memory Cells And Method Of Making Same - Semiconductor structures are presented. An exemplary semiconductor structure comprises a common source region having a sawtooth profile, and a flat erase gate disposed above the common source region. Methods of making semiconductor structures are also presented. An exemplary method comprises forming a plurality of trenches in a substrate thereby forming a plurality of active regions; forming a common source region in the substrate in a direction perpendicular to the active regions. The exemplary method further comprises, after forming the common source region, forming a dielectric feature on the substrate thereby filling the trenches and forming a plurality of shallow trench isolation features, and forming an erase gate on the dielectric feature. | 2015-08-13 |
20150228741 | FLOATING GATE FLASH CELL WITH EXTENDED FLOATING GATE - Provided is a floating gate flash cell and method for forming the same. The flash includes two floating gate transistors and a common source area therebetween. Each floating gate transistor includes a floating gate having a central portion disposed over a substrate surface and opposed lateral edges that extend into trenches and below the substrate surface. A control gate is disposed over said floating gate with a control gate dielectric between the floating gate and the control gate. The floating gates have side edges that are orthogonal to the opposed lateral edges and a common source area which is a substrate diffusion area, is positioned between respective facing side edges of the floating gates. | 2015-08-13 |
20150228742 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device and a method of manufacturing the semiconductor device includes forming a first and a second gate electrode on a semiconductor substrate, forming a first and a second insulator on the first and second gate electrodes, forming a third insulator on the second insulator, a first thickness of the third insulator on the first gate electrode being different than a second thickness of the third insulator on the second gate electrode, and etching-back the first, second and third insulators to form a first spacer beside the first gate electrode and a second spacer beside the second gate electrode. Herein, a horizontal length of the first spacer being contacted with a surface of the semiconductor substrate is different from a horizontal length of the second spacer being contacted with a surface of the semiconductor substrate. | 2015-08-13 |
20150228743 | FIN FIELD-EFFECT TRANSISTORS HAVING CONTROLLED FIN HEIGHT - An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration. The apparatus further includes a low fin density area on the semiconductor substrate including a second dielectric between the second group of fins in the low fin density area, said second dielectric having a second dopant concentration. The first dielectric and the second dielectric are a same material as deposited and the first dopant concentration and the second dopant concentration are different. | 2015-08-13 |
20150228744 | TRANSISTOR DEVICE WITH INTEGRATED GATE-RESISTOR - A transistor device includes an individual transistor cell arranged in a transistor cell field on a semiconductor body, the individual transistor cell having a gate electrode. The transistor device further includes a gate contact, electrically coupled to the gate electrode and configured to switch on the individual transistor cell by providing a gate current in a first direction and configured to switch off the individual transistor cell by providing a gate current in a second direction, the second direction being opposite to the first direction. The transistor device also includes a gate-resistor structure monolithically integrated in the transistor device. The gate-resistor structure provides a first resistance for the gate current when the gate current flows in the first direction, and provides a second resistance for the gate current, which is different from the first resistance, when the gate current flows in the second direction. | 2015-08-13 |
20150228745 | SELF-ALIGNED LINER FORMED ON METAL SEMICONDUCTOR ALLOY CONTACTS - Metal semiconductor alloy contacts are provided on each of a source region and a drain region which are present in a semiconductor substrate. A transition metal is then deposited on each of the metal semiconductor alloy contacts, and during the deposition of the transition metal, the deposited transition metal reacts preferably, but not necessarily always, in-situ with a portion of each the metal semiconductor alloy contacts forming a transition metal-metal semiconductor alloy liner atop each metal semiconductor alloy contact. Each transition metal-metal semiconductor alloy liner that is provided has outer edges that are vertically coincident with outer edges of each metal semiconductor alloy contact. The transition metal-metal semiconductor alloy liner is more etch resistant as compared to the underlying metal semiconductor alloy. As such, the transition metal-metal semiconductor alloy liner can serve as an effective etch stop layer during any subsequently performed etch process. | 2015-08-13 |
20150228746 | MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE - Methods of modifying a self-aligned contact process in a semiconductor fabrication and a semiconductor device are provided. A method includes forming a transistor over a substrate, including depositing a high-k dielectric layer over the substrate; depositing a work function metal layer over the high-k dielectric layer; forming a metal gate over the work function metal layer; forming two spacers sandwiching the work function metal layer and the metal gate; and forming a doped region in the substrate; etching the work function metal layer and the metal gate to leave a metal residue over inner walls of the two spacers exposing the work function metal layer and the metal gate; modifying the metal residue and the exposed work function metal layer and metal gate to form a metal compound; depositing an insulator covering the metal compound; and forming contact pads respectively electrically connected to the metal gate and the doped region. | 2015-08-13 |
20150228747 | MULTIPLE THICKNESS GATE DIELECTRICS FOR REPLACEMENT GATE FIELD EFFECT TRANSISTORS - After removal of the disposable gate structures to form gate cavities in a planarization dielectric layer, a silicon oxide layer is conformally deposited on silicon-oxide-based gate dielectric portions in the gate cavities. A portion of the silicon oxide layer can be nitridated to form a silicon oxynitride layer. A patterned masking material layer can be employed to physically expose a semiconductor surface from a first-type gate cavity. The silicon oxide layer can be removed while preserving an underlying silicon-oxide-based gate dielectric portion in a second-type gate cavity. A stack of a silicon oxynitride layer and an underlying silicon-oxide-based gate dielectric can be protected by a patterned masking material layer in a third-type gate cavity during removal of the silicon oxide layer in the second-type gate cavity. A high dielectric constant gate dielectric layer can be formed in the gate cavities to provide gate dielectrics of different types. | 2015-08-13 |
20150228748 | MULTI-COMPOSITION GATE DIELECTRIC FIELD EFFECT TRANSISTORS - A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric. | 2015-08-13 |
20150228749 | ENABLING ENHANCED RELIABILITY AND MOBILITY FOR REPLACEMENT GATE PLANAR AND FINFET STRUCTURES - A method for semiconductor fabrication includes forming at least one of a diffusion barrier layer and a metal containing layer over a dielectric layer in a gate cavity. A first anneal is performed to diffuse elements from the at least one of the diffusion barrier layer and the metal containing layer into the dielectric layer. The metal containing layer and the diffusion barrier layer are removed. A second anneal is performed to adjust diffusion of the elements in the dielectric layer to provide a gate dielectric region. | 2015-08-13 |
20150228750 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance. | 2015-08-13 |
20150228751 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device forms a salicide layer to surround an upper surface and a circumference of a lateral surface of a pillar. A contact area between the pillar and a lower electrode may be increased to reduce a contact resistance. | 2015-08-13 |
20150228752 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In aspects of the invention, an n-type epitaxial layer that forms an n | 2015-08-13 |
20150228753 | SELF ALIGNED EMBEDDED GATE CARBON TRANSISTORS - Transistors with self-aligned source/drain regions and methods for making the same. The methods include forming a gate structure embedded in a recess in a substrate; removing substrate material around the gate structure to create self-aligned source and drain recesses; forming a channel layer over the gate structure and the source and drain recesses; and forming source and drain contacts in the source and drain recesses. The source and drain contacts extend above the channel layer. | 2015-08-13 |
20150228754 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap. | 2015-08-13 |
20150228755 | INTEGRATED CIRCUITS WITH RELAXED SILICON / GERMANIUM FINS - Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively. | 2015-08-13 |
20150228756 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an Al | 2015-08-13 |
20150228757 | SIDE GATE ASSIST IN METAL GATE FIRST PROCESS - A method of making a semiconductor device in a gate first process with side gate assists. A first gate may be formed within a gate region. The first gate may include a first gate conductor separated from a semiconductor substrate by a first insulator disposed between the first gate conductor and the semiconductor substrate. A second gate may be formed within the gate region. The second gate may include a second gate conductor separated from a vertical surface of the first gate conductor and the semiconductor substrate by a second insulator. A first electrical contact and a second electrical contact may be formed. The first and second electrical contacts may be disposed on opposite ends of the gate region for respectively connecting the first gate conductor and the second gate conductor to a respective voltage. | 2015-08-13 |
20150228758 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A method for manufacturing a semiconductor device having a field-effect transistor, including forming a trench in a semiconductor substrate, forming a first insulating film in the trench, forming an intrinsic polycrystalline silicon film over the first insulating film, and introducing first conductive type impurities into the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. Next, a second insulating film is formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film, upper part of the trench ton form a second gate electrode. | 2015-08-13 |
20150228759 | VERTICAL DEVICE AND METHOD OF FORMING THE SAME - According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes the following operations: providing a vertical structure over a substrate; forming a first dielectric layer over the vertical structure and the substrate; laterally etching a sidewall of the first dielectric layer; replacing a portion of the first dielectric layer over the vertical structure with a second dielectric layer; and etching a portion of the first dielectric layer to expose the lateral surface of the vertical structure. | 2015-08-13 |
20150228760 | METHOD FOR SYSTEM FOR MANUFACTURING TFT, TFT, AND ARRAY SUBSTRATE - The method for manufacturing the TFT includes: forming a semiconductor film, a doped semiconductor film, a source/drain electrode film, and a first patterned photoresist layer sequentially; performing first etching to remove the source/drain electrode film on a region that is not covered by the first patterned photoresist layer; performing second etching to remove the doped semiconductor film and the semiconductor film on a region that is not covered by the first patterned photoresist layer; performing ashing treatment on the photoresist layer to remove the photoresist layer on the channel region; hard-baking the photoresist layer after the ashing treatment; performing third etching to remove the source/drain electrode film on a region that is not covered by the photoresist layer; and performing fourth etching to remove the doped semiconductor film on the region that is not covered by the photoresist layer. | 2015-08-13 |
20150228761 | DIAMOND SHAPED EPITAXY - In a first embodiment of the present invention, a semiconductor device manufacturing process includes forming a plurality of fins on a semiconductor substrate, forming diamond shaped epitaxy on fin sidewalls, merging the diamond shaped epitaxy, and removing the merged epitaxy. In another embodiment of the present invention, a semiconductor device includes a semiconductor substrate including a plurality of fins formed thereupon and unmerged diamond shaped epitaxy formed upon the sidewalls of each fin. The unmerged diamond shaped epitaxy is formed independent from neighboring fin geometry deficiencies. In yet another embodiment, the semiconductor device is included in a design structure embodied in a machine readable storage medium for designing, manufacturing, or testing an integrated circuit. | 2015-08-13 |
20150228762 | GATE STRUCTURE INTEGRATION SCHEME FOR FIN FIELD EFFECT TRANSISTORS - In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence. | 2015-08-13 |
20150228763 | NON-PLANAR FIELD EFFECT TRANSISTOR HAVING A SEMICONDUCTOR FIN AND METHOD FOR MANUFACTURING - A method for manufacturing a semiconductor device includes forming two isolation structures in a substrate to define a fin structure between the two isolation structures in the substrate. A dummy gate and spacers are formed bridging the two isolation structures and over the fin structure. The two isolation structures are etched with the dummy gate and the spacers as a mask to form a plurality of slopes under the spacers in the two isolation structures. A gate etch stop layer is formed overlying the plurality of slopes. The dummy gate and the two isolation structures beneath the dummy gate are removed to create a cavity confined by the spacers and the gate etch stop layer. A gate is then formed in the cavity. | 2015-08-13 |
20150228764 | Method for Producing Multi-Gate in FIN Field-Effect Transistor - A method for producing a multi-gate fin field-effect transistor (FinFET) is provided. The method includes forming a channel layer and a gate medium layer on a substrate; forming an amorphous silicon layer on the substrate, and etching the amorphous silicon layer, to form at least one fin; forming, by using an epitaxial growth process, a first protective layer from both sides to the middle of the substrate along a length direction of the at least one fin until a groove is formed in a middle location along the length direction of the at least one fin; forming a gate electrode layer on the substrate, performing planarization processing on the gate electrode layer to expose the first protective layer, and etching away the first protective layer by using an etching process, so as to form a gate electrode; and forming a source electrode and a drain electrode on the substrate. | 2015-08-13 |
20150228765 | METHOD OF FINFET FORMATION - A method of fabricating a fin for a FinFET device includes providing a semiconductor substrate, forming a patterned silicon germanium layer on the semiconductor substrate, epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer, forming a sacrificial layer covering the patterned silicon germanium layer, and removing the sacrificial layer and a portion of the silicon layer disposed on the top surface of the patterned silicon germanium layer until a top surface of the sacrificial layer is co-planar with the top surface of the patterned silicon germanium layer. The method further includes removing the patterned silicon germanium layer and removing the sacrificial layer to form the fin. The epitaxially formed fin does not have the issues of line width roughness and edge roughness to improve the performance of the FinFET device. | 2015-08-13 |
20150228766 | Formation of High Quality Fin in 3D Structure by Way of Two-Step Implantation - The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed. | 2015-08-13 |
20150228767 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region. | 2015-08-13 |
20150228768 | Tunneling Field Effect Transistor with New Structure and Preparation Method Thereof - A tunneling field effect transistor with a new structure and a preparation method thereof are provided. The tunneling field effect transistor includes an active region between a source and a drain, a gate dielectric layer, and a gate located on a side of the gate dielectric layer deviating from the source, and a tunneling region disposed between the gate dielectric layer and the source and in contact with both the gate dielectric layer and the source. The source includes at least a first area and a second area perpendicularly connected in an āLā shape. The tunneling region is in contact with at least the first area and the second area. The gate dielectric layer is in contact with at least the tunneling region and the source. | 2015-08-13 |
20150228769 | FORMATION OF AN ASYMMETRIC TRENCH IN A SEMICONDUCTOR SUBSTRATE AND A BIPOLAR SEMICONDUCTOR DEVICE HAVING AN ASYMMETRIC TRENCH ISOLATION REGION - Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance C | 2015-08-13 |
20150228770 | Robust ESD Protection with Silicon-Controlled Rectifier - Some embodiments relate to a silicon controlled rectifier (SCR) that includes a current path which couples an SCR anode to an SCR cathode. The current path includes a first vertical current path component coupled to the SCR anode, and a second vertical current path component coupled to the SCR cathode. A horizontal current path component includes a first well region and a second well region that meet at a junction lying along a first plane. The first and second well regions cooperatively span a distance between the first and second vertical current path components. The first and second vertical current path components mirror one another symmetrically about the first plane. | 2015-08-13 |
20150228771 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE CAPABLE OF PREVENTING LATCH-UP ISSUE CAUSED BY UNEXPECTED NOISE - An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region. | 2015-08-13 |
20150228772 | NANOWIRE TRANSISTOR DEVICES AND FORMING TECHNIQUES - Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein. | 2015-08-13 |
20150228773 | SWITCHING ELEMENT - Provided is a switching element that is hardly destroyed even under a high bias condition in an off state because an electric field near a gate electrode is relaxed. A switching element | 2015-08-13 |
20150228774 | SEMICONDUCTOR HETEROJUNCTION DEVICE - A heterojunction semiconductor device ( | 2015-08-13 |
20150228775 | SEMICONDUCTOR STRUCTURES AND METHODS FOR MULTI-DIMENSION OF NANOWIRE DIAMETER TO IMPROVE DRIVE CURRENT - A semiconductor device having a channel formed from a nanowire with a multi-dimensional diameter is provided. The semiconductor device comprises a drain region formed on a semiconductor substrate. The semiconductor device further comprises a nanowire structure formed between a source region and the drain region. The nanowire structure has a first diameter section joined with a second diameter section. The first diameter section is coupled to the drain region and has a diameter greater than the diameter of the second diameter section. The second diameter section is coupled to the source region. The semiconductor device further comprises a gate region formed around the junction at which the first diameter section and the second diameter section are joined. | 2015-08-13 |
20150228776 | METHODS OF FORMING CONTACTS TO SEMICONDUCTOR DEVICES USING A BOTTOM ETCH STOP LAYER AND THE RESULTING DEVICES - One method disclosed includes, among other things, forming a patterned high-k etch stop layer above source/drain regions, performing at least etching process to form at least one contact opening in a layer of insulating material, wherein the patterned high-k etch stop layer acts as an etch stop during the etching process, performing a second etching process to remove portions of the patterned high-k etch stop layer exposed by the contact opening and forming a conductive contact in the contact opening that is conductively coupled to the source/drain regions. The device includes a patterned high-k etch stop layer positioned between the conductive contact and an outermost sidewall spacer, wherein an outer side surface of the patterned high-k etch stop layer contacts the conductive contact. | 2015-08-13 |
20150228777 | SILICON ON INSULATOR DEVICE WITH PARTIALLY RECESSED GATE - Transistors having partially recessed gates are constructed on silicon-on-insulator (SOI) semiconductor wafers provided with a buried oxide layer (BOX), for example, FD-SOI and UTBB devices. An epitaxially grown channel region relaxes constraints on the design of doped source and drain profiles. Formation of a partially recessed gate and raised epitaxial source and drain regions allow further improvements in transistor performance and reduction of short channel effects such as drain induced barrier lowering (DIBL) and control of a characteristic subthreshold slope. Gate recess can be varied to place the channel at different depths relative to the dopant profile, assisted by advanced process control. The partially recessed gate has an associated high-k gate dielectric that is initially formed in contact with three sides of the gate. Subsequent removal of the high-k sidewalls and substitution of a lower-k silicon nitride encapsulant lowers capacitance between the gate and the source and drain regions. | 2015-08-13 |
20150228778 | SEMICONDUCTOR DEVICE HAVING STRUCTURE CAPABLE OF SUPPRESSING OXYGEN DIFFUSION AND METHOD OF MANUFACTURING THE SAME - A semiconductor device is provided. The device includes a substrate; a gate dielectric film formed on the substrate; a gate electrode formed on the gate dielectric film, and source and drain electrodes, wherein a boundary between the gate dielectric film and the substrate is formed with an F (fluorine)-terminated surface to serve as a barrier for preventing oxygen diffusion. | 2015-08-13 |
20150228779 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In aspects of the invention, an n-type epitaxial layer that forms an n | 2015-08-13 |
20150228780 | FinFET DEVICE WITH ABRUPT JUNCTIONS - A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers. | 2015-08-13 |
20150228781 | METHOD FOR MAKING SEMICONDUCTOR DEVICE WITH STRESSED SEMICONDUCTOR AND RELATED DEVICES - A method is for making a semiconductor device. The method may include forming fins above a substrate, each fin having an upper fin portion including a first semiconductor material and a lower fin portion including a dielectric material. The method may include forming recesses into sidewalls of each lower fin portion to expose a lower surface of a respective upper fin portion, and forming a second semiconductor layer surrounding the fins including the exposed lower surfaces of the upper fin portions. The second semiconductor layer may include a second semiconductor material to generate stress in the first semiconductor material. | 2015-08-13 |
20150228782 | FIELD EFFECT TRANSISTOR WITH HETEROSTRUCTURE CHANNEL - In some embodiments, an FET structure comprises a heterostructure, and a gate structure. The heterostructure comprises a first section, a barrier section and a second section such that a portion of the first section, the barrier section, and a portion of the second section form a channel region, and portions of the first section and the second section on opposite sides of the channel region form at least portions of source and drain regions, respectively. When the channel region is p type, the barrier section has a positive valence band offset with respect to each of the first section and the second section, or when the channel region is n type, the barrier section has a positive conduction band offset with respect to each of the first section and the second section. A gate structure is configured over the channel region. | 2015-08-13 |
20150228783 | FIELD EFFECT TRANSISTORS EMPLOYING A THIN CHANNEL REGION ON A CRYSTALLINE INSULATOR STRUCTURE - A single crystalline dielectric layer is provided on an insulator layer including an amorphous dielectric material. The single crystalline dielectric layer can be patterned into various crystalline dielectric portions including dielectric fins, dielectric nanowires, and a dielectric fin-plate assembly. A semiconductor material can be deposited on the single crystalline surfaces of the various crystalline dielectric portions by a selective epitaxial deposition process while not growing on the surfaces of the insulator layer. Single crystalline semiconductor material portions can be formed on the surfaces of the dielectric fins, around the dielectric nanowires, and on horizontal and vertical surfaces of the dielectric fin-plate assembly. Source and drain regions can be formed in the single crystalline semiconductor material portions, and gate electrodes can be formed to provide various field effect transistors. | 2015-08-13 |
20150228784 | SUPERJUNCTION SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device that includes the following is manufactured: an n | 2015-08-13 |
20150228785 | SEMICONDUCTOR DEVICE - A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A gate electrode and gate insulating film surround the pillar-shaped silicon layer and a gate line is connected to the gate electrode and extends in a direction orthogonally intersecting the fin-shaped silicon layer. A first diffusion layer resides in an upper portion of the pillar-shaped silicon layer and a second diffusion layer resides in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer. | 2015-08-13 |
20150228786 | Semiconductor Device - A semiconductor device includes a semiconductor substrate having an active region. A gate trench is disposed to cross the active region. First and second source/drain regions are disposed in the active region at both sides of the gate trench. A gate electrode is disposed in the gate trench. A gate dielectric layer is disposed between the gate electrode and the active region. A stress pattern is disposed on the gate electrode and in the gate trench. The stress pattern has a lower residual stress than silicon nitride. | 2015-08-13 |
20150228787 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device according to an embodiment includes a semiconductor layer. A first conductivity-type source layer is provided in the semiconductor layer. A second conductivity-type drain layer is provided in the semiconductor layer. A gate dielectric film is provided on the semiconductor layer between the source layer and the drain layer. A gate electrode includes a first gate part partially provided on the gate dielectric film on a side of the source layer and a second gate part partially provided on the gate dielectric film on a side of the drain layer. A length of crystal grains of the first gate part in a channel length direction is longer than that of crystal grains of the second gate part in the channel length direction. | 2015-08-13 |
20150228788 | STRESS MEMORIZATION PROCESS AND SEMICONDUCTOR STRUCTURE INCLUDING CONTACT ETCH STOP LAYER - A stress memorization process including the following step is provided. A gate is formed on a substrate. A low-k dielectric layer with a dielectric constant lower than 3 is formed to entirely cover the gate and the substrate. A stress layer is formed to entirely cover the low-k dielectric layer. The stress layer and the low-k dielectric layer are removed. Moreover, a semiconductor structure including a contact etch stop layer is provided. A gate is disposed on a substrate. A porous layer entirely covers the gate and the substrate. A contact etch stop layer entirely covers the porous layer, wherein the thickness of the porous layer is thinner than the thickness of the contact etch stop layer. | 2015-08-13 |
20150228789 | STRESSED CHANNEL BULK FIN FIELD EFFECT TRANSISTOR - Effective transfer of stress to a channel of a fin field effect transistor is provided by forming stress-generating active semiconductor regions that function as a source region and a drain region on a top surface of a single crystalline semiconductor layer. A dielectric material layer is formed on a top surface of the semiconductor layer between semiconductor fins. A gate structure is formed across the semiconductor fins, and the dielectric material layer is patterned employing the gate structure as an etch mask. A gate spacer is formed around the gate stack, and physically exposed portions of the semiconductor fins are removed by an etch. Stress-generating active semiconductor regions are formed by selective epitaxy from physically exposed top surfaces of the semiconductor layer, and apply stress to remaining portions of the semiconductor fins that include channels. | 2015-08-13 |
20150228790 | METHOD OF FABRICATING SPACERS IN A STRAINED SEMICONDUCTOR DEVICE - The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack. | 2015-08-13 |
20150228791 | SEMICONDUCTOR SUBSTRUCTURE HAVING ELEVATED STRAIN MATERIAL-SIDEWALL INTERFACE AND METHOD OF MAKING THE SAME - A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate. | 2015-08-13 |