32nd week of 2015 patent applcation highlights part 62 |
Patent application number | Title | Published |
20150222214 | SYSTEM FOR CONTROLLING THE ELECTROMAGNETIC TORQUE OF AN ELECTRIC MACHINE IN PARTICULAR FOR MOTOR VEHICLE - A system for controlling electromagnetic torque of an electric machine, for example for a motor vehicle. The system can control electromagnetic torque of a permanent-magnet three-phase electric machine and includes a mechanism measuring a current, a transposition mechanism configured to transpose three measured currents into a direct component and a quadratic component of current on the basis of a transform of three-phase systems, a transformation mechanism configured to convert a torque setpoint into a setpoint for the quadratic component of current and a setpoint for the direct component of current, a mechanism for determining control voltages, and a controller configured to apply the control voltages determined to the electric machine. | 2015-08-06 |
20150222215 | DRIVE UNIT OF SYNCHRONOUS MOTOR - Provided is drive unit of a synchronous motor capable of improving the accuracy of magnetic flux operations with a simple configuration. To this end, the drive unit has a magnetic flux operation part which, in the case where a direction of a magnetic field pole of the synchronous motor is regarded as a d-axis and a direction orthogonal to the d-axis is regarded as a q-axis, calculates a magnetic flux of the d-axis and a magnetic flux of the q-axis on the basis of a current of the d-axis, a current of the q-axis, and a field current of the synchronous motor; and a magnetic flux operation error correcting part which calculates a phase difference between an input voltage and an input current of the synchronous motor and corrects an inner-phase difference angle calculated from the magnetic flux of the d-axis and the magnetic flux of the q-axis on the basis of the phase difference. | 2015-08-06 |
20150222216 | MOTOR CONTROL DEVICE, AND MOTOR CONTROL METHOD - In order to highly accurately estimate a temperature of a permanent magnet to be used for a rotor of a motor, provided is a motor control device for a vehicle including a motor as a drive power source, in which an estimation mode setting section sets, when a predetermined condition for estimating the temperature of the permanent magnet to be used for the rotor of the motor is established under a state in which the motor generates drive power to run the vehicle, a current flowing through the motor to 0, and a permanent magnet temperature estimation section estimates the temperature of the permanent magnet based on an induced voltage of the motor in a period during which the current flowing through the motor is 0. | 2015-08-06 |
20150222217 | TRAVELLING WAVE MOTOR PRE-DRIVER USING HIGH RESOLUTION PWM GENERATORS - A motor driver combination for controlling a travelling wave motor includes a pre-driver including a microcontroller unit (MCU) chip including a plurality of high-resolution pulse width modulation (HRPWM) generators providing a frequency resolution better than ten Hz. A digital bus is for transferring digital words received from a controller in a servo and velocity control block to the HRPWM generators, where the digital words provide travelling wave motor operating performance information from the motor during its operation. A clock oscillator providing an accuracy of at least eighty (80) parts per million (ppm) is coupled to or provided by the MCU chip for each of the high-resolution PWM generators. A motor driver includes a plurality of power drivers for providing phased outputs for driving the travelling wave motor including a plurality of inputs coupled to outputs of the plurality of HRPWM generators. The travelling wave motor can be an ultrasonic motor. | 2015-08-06 |
20150222218 | Solar Cell Panel Mount - The present invention provides a solar cell panel mount capable of fixing inclined column members at a predetermined inclination angle simply, stably for a long term, and methods of making and using thereof. | 2015-08-06 |
20150222219 | SOLAR CELL MODULE, AND PRODUCTION METHOD FOR SOLAR CELL MODULE - A solar cell module is configured from a solar cell panel, and a frame structural body. The frame structural body is provided with: a plurality of frame members which are provided to peripheral edges of the solar cell panel, and which have a cross-sectional shape having a hollow portion; corner members which are provided in the hollow portions; holding sections which are provided in the hollow portions, and which hold the corner members; and a plurality of formed rivet sections which apply pressure to the frame members. | 2015-08-06 |
20150222220 | AERODYNAMIC AND FOOTING DESIGN FOR SOLAR PANEL RACKING SYSTEMS - A footing for distributing loads over a mounting surface from a ballasted mounting system supporting a solar panel, the footing comprising a body composed of a closed-cell plastics based foam material capable of experiencing body deformation in the presence of rigid objects pressed against the body and one or more further features of: at least one slot located in an exterior face allowing the flow of water between a first side and a second side of the body and/or a cladding layer affixed to a first exterior face of the body to provide a stacked layer arrangement for the body with the affixed cladding layer, such that a thickness of the cladding layer is less than a thickness of the body and a coefficient of friction for material of the cladding layer is greater than a coefficient of friction for the closed-cell plastics based foam material, the thickness of the cladding layer providing for said body deformation when the rigid foreign object is pressed against the cladding layer. | 2015-08-06 |
20150222221 | PIVOT-FIT CONNECTION APPARATUS, SYSTEM AND METHOD FOR PHOTOVOLTAIC MODULES - A system and method are disclosed for quickly and easily assembling PV modules into a PV array in a sturdy and durable manner. In examples of the present technology, the system includes various couplings having a first engaging portion adapted to engage a first PV module and a second engaging portion adapted to engage a second PV module. At least one of the engaging portions allows variable positioning of the engaged PV module along the engaging portion. | 2015-08-06 |
20150222222 | PIVOT-FIT CONNECTION APPARATUS, SYSTEM, AND METHOD FOR PHOTOVOLTAIC MODULES - A system and method are disclosed for quickly and easily assembling PV modules into a PV array in a sturdy and durable manner. In examples of the present technology, the system includes various couplings having a first engaging portion adapted to engage a first PV module and a second engaging portion adapted to engage a second PV module. At least one of the engaging portions allows variable positioning of the engaged PV module along the engaging portion. | 2015-08-06 |
20150222223 | OUTSIDE WALL CLADDING ELEMENT AND AN OUTSIDE WALL PROVIDED WITH SUCH AN OUTSIDE WALL CLADDING ELEMENT - Disclosed is an outside wall cladding element for cladding an outside wall ( | 2015-08-06 |
20150222224 | FLEXIBLE BUILDING INTEGRATED PV DEVICE - An article of manufacture includes at least two solar active elements separated by a gap, with a flexible material provided to define the gap. The article provides for enhanced resilience and conformity to an installation surface. | 2015-08-06 |
20150222225 | LEVELER FOR SOLAR MODULE ARRAY - A leveler for a solar module can include a base, a rotatable adjuster, and a follower. The rotatable adjuster can be mounted to the base with a swaging process, or other techniques. The follower can be embedded within a coupler configured to be connectable to solar modules. Turning the rotatable height adjuster changes the relative spacing between the solar module and the base. | 2015-08-06 |
20150222226 | SYSTEM OF SOLAR MODULES CONFIGURED FOR ATTACHMENT TO VERTICAL STRUCTURES - A system of solar PV strip modules and method of use designed to integrate with vertical structures such as poles. The system and method use articulated semi-rigid solar PV strip modules and components with elastic characteristics to enable a high static-friction attachment to the structure. The static friction exceeds the force of gravity, enabling the solar PV strip modules to remain in place upon the vertical structure. The PV strip modules can have a rectangular shape or any other shape that enables customized or variable modular assembly and attachment to the structure. | 2015-08-06 |
20150222227 | MONITORING SYSTEM AND SLAVE DEVICE FOR PHOTOVOLTAIC POWER GENERATION PLANT - A monitoring system includes a slave device ( | 2015-08-06 |
20150222228 | METHOD FOR CHARACTERIZING A PHOTOVOLTAIC ELEMENT, DEVICE FOR CHARACTERIZING THE PHOTOVOLTAIC ELEMENT, ASSOCIATED PROGRAM AND STORAGE MEDIUM - The method for characterizing a photovoltaic element ( | 2015-08-06 |
20150222229 | Oscillator Circuit and Related Method - A device includes a first pin configured to connect to a first terminal of a resonator, a second pin configured to connect to a second terminal of a resonator, a gain stage having a first terminal electrically connected to the first pin, and a voltage drop circuit. The voltage drop circuit includes a first transistor having an input terminal electrically connected to a second terminal of the gain stage, and a second transistor having an input terminal electrically connected to an output terminal of the first transistor, and an output terminal electrically connected to the second pin. | 2015-08-06 |
20150222230 | OUTPUT POWER TUNING USING PULSE POSITION AND PULSE WIDTH CONTROL IN A PULSE POSITION, PULSE WIDTH MODULATION AMPLIFIER - An outphasing amplifier apparatus and method is disclosed that controls pulse width modulation and/or pulse height modulation to improve power-added-efficiency performance and/or compensate for errors caused by quantized pulse position settings is provided herein. | 2015-08-06 |
20150222231 | MICROWAVE AMPLIFIER DEVICE - A microwave amplifier including: a bias circuit that includes a line having an electrical length of one quarter the wavelength at the frequency configured to be amplified by the microwave amplifier and being connected between the output terminal of an amplifier and a bias voltage source, and a capacitor connected between a terminal where the line is connected to the bias voltage source and a ground that defines the reference potential of the microwave amplifier; and a resonant circuit that includes a resistor and a capacitor connected in series between the ground and the terminal where the line is connected to the bias voltage source. | 2015-08-06 |
20150222232 | INPUT SIGNAL AMPLIFIER - An input signal amplifier includes an inverting amplifier that outputs an input signal, a logic of which is inverted; a first switch. that switches an input, terminal of the inverting amplifier to be grounded or not; and a feedback resistor connected in parallel with the inverting amplifier and including a plurality of resistors with different values of resistance. The feedback resistor includes both a second switch that shorts or opens the feedback resistor via at least one of the resistors and a third switch that shorts or opens the feedback resistor via another of the resistors. | 2015-08-06 |
20150222233 | AMPLIFICATION DEVICE AND AMPLIFICATION METHOD - An amplification device includes: a first circuit configured to: split an input signal into a first signal and a second signal, and adjust the first signal so that an amplitude of the first signal is less than an amplitude of the second signal by a reduced value, a first amplifier configured to amplify the adjusted first signal, a second amplifier configured to amplify the second signal, and a second circuit configured to: determine a reflection coefficient in case where the amplified second signal is a travelling wave and the amplified first signal is a reflected wave, and determine the reduced value based on the reflection coefficient. | 2015-08-06 |
20150222234 | POWER AMPLIFIER MODULE - Consumption current may be reduced in a power amplifier module in which a power supply voltage supplied to a power amplification transistor is controlled according to the level of output power. The power amplifier module includes an amplification transistor supplied with the power supply voltage according to the level of output power to amplify a radio-frequency signal, a bias control circuit for generating a bias voltage according to the power supply voltage, and a bias circuit for supplying a bias current according to the bias voltage to the amplification transistor, wherein current flowing through the amplification transistor when the radio-frequency signal is not input is varied according to the level of output power. | 2015-08-06 |
20150222235 | SWITCHED MODE AMPLIFIER - A switching power stage for producing an output voltage to a load may include a power converter and a controller. The power converter may include a power inductor and plurality of switches arranged to sequentially operate in a plurality of switch configurations. The controller may be configured to, based on a measured parameter associated with the switching power stage, select a selected operational mode of the power converter from a plurality of operational modes, and sequentially apply switch configurations from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to transfer electrical energy from an input source of the power converter to the load in accordance with the selected operational mode. | 2015-08-06 |
20150222236 | OPTICAL TRANSMISSION CIRCUIT - The high-speed and high-quality reception operation of a transimpedance amplifier of an optical communication module and a router including the same can be achieved. A preamplifier performs current/voltage conversion with respect to intersymbol interference due to bandwidth shortage of a laser diode. A threshold control circuit which generates positive and negative threshold voltages with respect to a center potential of an output signal, latch circuits, and a selector circuit are provided to the output of the preamplifier. An NRZ signal is received as a duobinary signal based on the sign determination result of the previous bit. The determination error rate of the latch circuits can thus be improved. | 2015-08-06 |
20150222237 | AMPLIFIER WITH REDUCED IDLE POWER LOSS USING SINGLE-ENDED LOOPS - A method of audio signal processing includes receiving a first audio input signal (first input signal) at an input of a first integrating amplifier of a first single-ended (SE) closed loop channel, and second input signal with a polarity reversed relative to the first input signal at an input of a second integrating amplifier configured of a second SE closed loop channel. During audio signal processing a common-mode (CM) reference voltage level applied to a current source coupled to an input of the first and second integrating amplifiers is dynamically changed including whenever a level of the input signals is below a predetermined low level, reducing the CM reference voltage level for implementing low duty cycle (LDC) PWM operation, and whenever the level is above a level that corresponds to an onset of clipping, increasing the CM reference voltage level for at least reducing the clipping to lower crossover distortion. | 2015-08-06 |
20150222238 | SWITCHED CAPACITOR CIRCUITS HAVING LEVEL-SHIFTING BUFFER AMPLIFIERS, AND ASSOCIATED METHODS - Switched capacitor circuits and charge transfer methods comprising a sampling phase and a transfer phase. Circuits and methods are implemented via a plurality of switches, a set of at least two capacitors, at least one buffer amplifier, and an operational amplifier. In one example, during the sampling phase at least one input voltage is sampled, and during the transfer phase at least a first reference voltage provided by the at least one buffer amplifier is subtracted from the at least one input voltage using the operational amplifier. The same set of at least two capacitors may be used in both the sampling phase and the transfer phase. | 2015-08-06 |
20150222239 | METHOD AND DEVICE FOR PRIORITIZING AUDIO DELIVERY IN AN APPLICATION - A client device with one or more processors and memory identifies an action mode of a user of the client device in an application while executing the application. The client device detects an event in the action mode. The client device adjusts an audio mixing mode of sound effects in the application (e.g., adjusting a volume of audio associated with the event and a volume of background music for the application) based on the detected event. | 2015-08-06 |
20150222240 | RECEPTION DEVICE AND RECEPTION METHOD - A reception device includes a low noise amplifier that amplifies a radio signal by a first gain, a variable gain amplifier that amplifies an output of the low noise amplifier by a second gain, an analog-to-digital converter that converts an output of the variable gain amplifier into a digital signal, a gain controller, and a saturation detection unit. The gain controller, when an amplitude of the radio signal exceeds a predetermined value, controls the first and second gains according to the amplitude of the radio signal, and completes the control within a predetermined period. The saturation detection unit detects saturation of the analog-to-digital converter based on the output of the low noise amplifier or the digital signal. The gain controller, after controlling the first and second gains a first time and the saturation is detected by the saturation detection unit, controls the first and second gains a second time. | 2015-08-06 |
20150222241 | Circuit for Signal Transfer and Galvanic Isolation - A circuit for signal transfer and galvanic isolation between first and second digital signal processing units, wherein a first signal path is provided between the first and second signal processing units. The first signal path has a first section, which includes positive and negative signal lines and serves for transfer of a differential signal between the first and second signal processing units. At least one capacitor is provided in the positive signal line and at least one capacitor in the negative signal line. The capacitors serve for galvanic isolation between the first signal processing unit and the second signal processing unit, and the capacitors are embodied, in each case, according to the specifications of the ignition protection type, intrinsic safety. | 2015-08-06 |
20150222242 | WINDOW ANTENNA CONNECTOR WITH IMPEDANCE MATCHING - A connector for an automotive windshield antenna includes a thin trace portion that is electrically equivalent to a series inductor and a wide trace portion that is electrically equivalent to a shunt capacitor. The capacitor and the inductor form a matching LC network that is adjustable to match antenna impedance and transmission line impedance. | 2015-08-06 |
20150222243 | VIBRATION ELEMENT, VIBRATOR, OSCILLATOR, ELECTRONIC APPARATUS, AND MOVING OBJECT - A vibration element includes a piezoelectric substrate including a vibrating section and a thick section having a thickness larger than that of the vibrating section. The thick section includes a first thick section provided along a first outer edge of the vibrating section, a second thick section provided along a second outer edge, and a third thick section provided along another first outer edge. An inclined outer edge section that intersects with each of an X axis and a Z′ axis is provided in a tip section of the piezoelectric substrate. | 2015-08-06 |
20150222244 | VIBRATOR ELEMENT, SENSOR UNIT, ELECTRONIC APPARATUS, MANUFACTURING METHOD OF VIBRATOR ELEMENT, AND MANUFACTURING METHOD OF SENSOR UNIT - A vibration gyro device has a base part and a pair of drive vibrating arms and a pair of detection vibrating arms respectively extended from both ends in a Y-axis direction of the base part. Further, adjustment vibrating arms extended from respective ends of connecting parts respectively extended from both ends in an X-axis direction of the base part in parallel to the drive vibrating arms are provided. At the end sides of the respective adjustment vibrating arms, spindle parts as wider parts are provided. On principal surfaces of the respective adjustment vibrating arms, adjustment electrodes as membranes for adjustment of leakage output of the vibration gyro device are provided. | 2015-08-06 |
20150222245 | METHOD FOR MANUFACTURING VIBRATING ELEMENT, VIBRATING ELEMENT, ELECTRONIC DEVICE, ELECTRONIC APPARATUS, AND MOVING OBJECT - A method for manufacturing a vibrating element includes: providing, on a substrate, a first protective layer and a second protective layer; disposing the substrate in an apparatus including an energy-beam emitting unit for dry etching; and etching, using an energy beam emitted from the energy-beam emitting unit, the substrate on which the first protective layer and the second protective layer are disposed on one side relative to an intersection point at which a center of the energy-beam emitting unit and the substrate intersect each other in a plan view of the substrate. When a distance between the intersection point and the first protective layer is shorter than a distance between the intersection point and the second protective layer, a width of the first protective layer in a direction intersecting the extending direction of the vibrating arm is made narrower than a width of the second protective layer. | 2015-08-06 |
20150222246 | FILTER DEVICE - A filter device includes a first LC parallel resonance circuit having a first inductance and connected between a line connecting an input terminal and an output terminal and a ground potential, a second LC parallel resonance circuit having a second inductance and connected between the line and the ground potential, and at least one elastic wave resonator that is connected between an end portion of the first LC parallel resonance circuit and an end portion of the second LC parallel resonance circuit. Attenuation-frequency characteristics of an LC filter including the first LC parallel resonance circuit, the second LC parallel resonance circuit, and a capacitive property and attenuation-frequency characteristics of the at least one elastic wave resonator are used. | 2015-08-06 |
20150222247 | ANTENNA BRANCHING FILTER - An antenna branching filter includes an antenna terminal, a first filter circuit with a first pass band, and a second filter circuit with a second pass band that does not include the first pass band and with frequencies higher than those of the first pass band. The antenna terminal, the first filter circuit, and the second filter circuit are connected to each other at a first connection point. The second filter circuit includes longitudinally coupled resonator filter circuits. Resonators are provided between the first connection point and the longitudinally coupled resonator filters. Low-frequency band pass circuits with a stop band in the second pass band are provided between second connection points and the ground potential. | 2015-08-06 |
20150222248 | SAMPLING RATE CONVERSION DEVICE - A position coordinate difference calculation section | 2015-08-06 |
20150222249 | Channel Select Filter Apparatus and Method - Channel select filter circuits are described. One circuit implements a multiplying element and digital-to-analog converter as a differential current mode device. Another circuit implementing a multiplying element and digital-to-analog converter with weighted addition, deferred after multiplication of the digital-to-analog converter and multiplier combination. In one such circuit, substantially equal current source magnitudes are in different columns of the circuit. Another such circuit, with substantially equal current source magnitudes, uses non-radix2. Another such circuit, with substantially equal current source magnitudes, has partial segmentation. Another circuit implements a multiplying element and digital-to-analog converter, with partial segmentation, scrambling bit allocation for elements. One such circuit scrambles bit allocation on equally weighted segments, as described herein. Another circuit implements a multiplying element and digital-to-analog converter with selective enablement of duplicate current source devices. Another circuit implements a multiplying element and digital-to-analog converter with variable effective length of the digital-to-analog converter. In one such circuit one or more current sources of a multiplier element are deselected to remove a noise contribution of the multiplier element, as described herein. A complex filter circuit includes a pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a common resistor network to perform weighted addition. One such circuit further includes a second pair of real finite impulse response filter circuits performing addition and subtraction in current domain, sharing a second common resistor network to perform weighted addition. | 2015-08-06 |
20150222250 | Method and Circuit Arrangement for Actuating a Semiconductor Switch - A method for actuating a controllable semiconductor switch by switching the switch on an off in phases in a controlled manner using a control signal is disclosed. The method includes starting a time measurement at the beginning of at least one phase of the phase-wise on-and-off switching procedure to ascertain a time duration, wherein the time measurement is continued until a phase following the at least one phase of the phase-wise on-and-off switching procedure begins. The ascertained time duration is compared with a specified maximal time duration. If the ascertained time duration exceeds the specified maximal time duration, the semiconductor switch is actuated such that the semiconductor switch is switched into a specified operating state. | 2015-08-06 |
20150222251 | HIGH VOLTAGE SWITCHING CIRCUITRY FOR A CROSS-POINT ARRAY - Circuitry for generating voltage levels operative to perform data operations on non-volatile re-writeable memory arrays are disclosed. In some embodiments an integrated circuit includes a substrate and a base layer formed on the substrate to include active devices configured to operate within a first voltage range. Further, the integrated circuit can include a cross-point memory array formed above the base layer and including re-writable two-terminal memory cells that are configured to operate, for example, within a second voltage range that is greater than the first voltage range. Conductive array lines in the cross-point memory array are electrically coupled with the active devices in the base layer. The integrated circuit also can include X-line decoders and Y-line decoders that include devices that operate in the first voltage range. The active devices can include other active circuitry such as sense amps for reading data from the memory cells, for example. | 2015-08-06 |
20150222252 | BUFFER CIRCUIT HAVING AMPLIFIER OFFSET COMPENSATION AND SOURCE DRIVING CIRCUIT INCLUDING THE SAME - Provided are an output buffer circuit having an amplifier offset compensation function and a source driving circuit including the output buffer circuit. The output butler circuit may include a plurality of channel amplifiers, each of which is configured to adjust an amount of current flowing through transistors connected to at least one of a non-inverted input terminal and an inverted input terminal of a differential input unit to compensate an amplifier offset, and adjust buffer input voltage signals to generate output voltage signals. | 2015-08-06 |
20150222253 | CLOCK DOUBLING CIRCUIT AND METHOD OF OPERATION - A clock doubler circuit includes a filtering circuit. The filtering circuit includes a first input to receive a first clock signal, a first output to provide a second clock signal, and a second output to provide a third clock signal. The third clock signal is a complementary signal to the second clock signal. The first clock signal, the second clock signal, and the third clock signal are at a first clock frequency. The second clock signal is a low pass filtered version of the first clock signal. The clock doubler circuit includes a frequency doubling circuit. The frequency doubling circuit includes a first input to receive the second clock signal and a second input to receive the third clock signal. The frequency doubling circuit includes an output node. The output node provides a fourth clock signal at a second clock frequency that is twice the first clock frequency. | 2015-08-06 |
20150222254 | DIGITAL DUTY CYCLE CORRECTION - A digital duty-cycle correction circuit may include an adjustment unit that may be configured to adjust a duty cycle of an oscillating signal based on an adjust signal to generate an adjusted oscillating signal and a sampling unit that may be configured to sample the adjusted oscillating signal. The circuit may also include a counting unit that may be configured to generate an indication of a number of samples of the adjusted oscillating signal that are at the low and high level and to adjust the indication using a selectable duty cycle modify signal based on a desired duty cycle of the adjusting oscillating signal. The circuit may also include a comparing and filtering unit that may be configured to generate the adjust signal based on a comparison of the indication with a comparison count. The indication may be adjustable such that the oscillating signal's duty cycle is adjustable. | 2015-08-06 |
20150222255 | DIGITAL CIRCUIT FOR GENERATING A PULSE-WIDTH MODULATED SIGNAL, PARTICULARLY FOR REGULATING AN ANALOG VARIABLE - A digital circuit configuration for generating a pulse-width modulated signal, particularly for regulating an analog electrical variable using pulse-width modulation, is described in which an actual value of the analog variable present at the input of an A/D converter is converted to a digital output variable, the digital output variable of the A/D converter being provided or supplied to a comparator unit, which compares the output variable to an upper threshold value and to a lower threshold value; at the output of the comparator unit, a signal being present which indicates whether the output variable of the A/D converter lies above the upper threshold value or below the lower threshold value; and it being particularly provided that the output of the A/D converter is connected to a digital timer, using which the pulse-width ratio of a generated pulse-width modulated signal is settable. | 2015-08-06 |
20150222256 | SIGNAL PROCESSING CIRCUIT - In an integration mode, since a switch becomes OFF, a positive feedback path from an output terminal of an operational amplifier to a positive input terminal is blocked. Therefore, oscillation can be prevented even when a voltage of a signal line connected to a reference voltage supply point varies due to an impedance of the reference voltage supply point not being 0. In the integration mode, a resistor and a capacitor function as a noise filter. Further, in a reset mode, a switch becomes ON, and charge is accumulated in the capacitor depending on a reference voltage of the reference voltage supply point. | 2015-08-06 |
20150222257 | ISOLATED HIGH SPEED SWITCH - A circuit structured to drive an isolated high speed voltage metal-oxide-semiconductor field-effect transistor (MOSFET) switch, including a first MOSFET and a second MOSFET configured to operate as a switch, a capacitor, a charging component in parallel with the capacitor, a first switch in series with the charging component, and a second switch in parallel with the charging component and the capacitor. The stored voltage in the capacitor is sent to the gates of the first MOSFET and the second MOSFET when a second switch is open and a first switch is closed. | 2015-08-06 |
20150222258 | COLLECTOR CURRENT DRIVER FOR A BIPOLAR JUNCTION TRANSISTOR TEMPERATURE TRANSDUCER - In one embodiment, a collector current driver is provided that controls the collector current for a bipolar transistor temperature transducer. The collector current driver is configured to use negative feedback to generate an emitter current for the bipolar transistor responsive to target current. | 2015-08-06 |
20150222259 | FIELD EFFECT TRANSISTOR SWITCHING CIRCUIT - Embodiments include an apparatus, system, and method related to a switching circuit. In some embodiments, the switching circuit may include first switch including an n-channel field effect transistor (FET) in the signal path. The switching circuit may further include a second switch in shunt to the first switch. The second switch may include a discharge transistor to provide a discharge path for a body of a switch transistor. Other embodiments may be described and claimed. | 2015-08-06 |
20150222260 | Reduced Generation of Second Harmonics of FETs - A structure and method for reducing second-order harmonic distortion in FET devices used in applications that are sensitive to such distortion, such as switching RF signals. The asymmetry of the drain-to-body capacitance Cdb and source-to-body capacitance Csb of a FET device are equalized by adding offsetting capacitance or a compensating voltage source. | 2015-08-06 |
20150222261 | LINE DRIVER WITH SEPARATE PRE-DRIVER FOR FEED-THROUGH CAPACITANCE - Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first output node and a second output node; a pass-through capacitance coupled with the first output node and the second output node; a first pre-driver to drive an input signal for the differential transistors; and a second pre-driver to drive the input signal for the pass-through capacitance. | 2015-08-06 |
20150222262 | DRIVE DEVICE - A drive device according to one aspect of the disclosure includes a control terminal connector, a switch circuit, a current limit circuit, and a clamp switch on a circuit board. The clamp switch is located in a second quadrant or a fourth quadrant of four quadrants, where the four quadrants are partitioned by two mutually orthogonal virtual lines with the current limit circuit set as an origin and the four quadrants consist of a first quadrant including an area where the control terminal connector is located, the second quadrant, a third quadrant, and the fourth quadrant, in clockwise order. | 2015-08-06 |
20150222263 | GATE DRIVE CIRCUIT - A gate drive circuit in an aspect of the present disclosure includes a modulated signal generation circuit that generates a first modulated signal, a first isolator that isolatedly transmits the first modulated signal, and a first rectifier circuit that generates a first output signal by rectifying the first modulated signal. The first modulated signal includes a first amplitude, a second amplitude larger than the first amplitude, and a third amplitude larger than the second amplitude. The first output signal includes a first output voltage value according to the first amplitude, a second output voltage value according to the second amplitude, and a third output voltage value according to the third amplitude. | 2015-08-06 |
20150222264 | GATE DRIVE CIRCUIT - A gate drive circuit in an aspect of the present disclosure includes: a first electromagnetic resonant coupler that isolatedly transmits a transmission signal from the primary side to the secondary side, and also isolatedly transmits a reflected signal from the secondary side to the primary side; a modulator circuit that modulates a radio-frequency wave with an input signal to generate the transmission signal; a demodulator circuit that demodulates the transmission signal to generate an output signal; a variable capacitance diode into which the transmission signal is input from the first electromagnetic resonant coupler, the variable capacitance diode disposed on the secondary side, the variable capacitance diode allowing a capacitance thereof to vary according to a monitor signal; and a reflected signal rectifier circuit that rectifies the reflected signal input to generate a monitor output signal. | 2015-08-06 |
20150222265 | RELAY MODULE DEVICE - In a relay module device, a signal converting section transmits driving signals of switching elements when receiving input signals from an external device and sets a relationship between the input signals and the driving signals. The relationship includes a first mode in which the signal converting section transmits the driving signals to separately control one of the switching elements with respect to one of the input signals, and a second mode in which the signal converting section transmits the driving signals to concurrently control two or more of the switching elements with respect to one of the input signals. | 2015-08-06 |
20150222266 | LOW TAU SYNCHRONIZER FLIP-FLOP WITH DUAL LOOP FEEDBACK APPROACH TO IMPROVE MEAN TIME BETWEEN FAILURE - A flip-flop and a method of receiving a digital signal from an asynchronous domain. In one embodiment, the flip-flop includes: (1) a first loop coupled to a flip-flop input and having first and second stable states and (2) a second loop coupled to the first loop and having the first and second stable states, properties of cross-coupled inverters in the first and second loops creating a metastable state skewed toward the first stable state in the first loop and skewed toward the second stable state in the second loop. Certain embodiments of the flip-flop have lower time constant and thus a higher Mean Time Between Failure (MTBF). | 2015-08-06 |
20150222267 | TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC - A method for enabling double pumping in a limited switch dynamic logic circuit includes precharging a dynamic node in accordance with a first clock signal and a second clock signal. The dynamic node is evaluated to a first value in response to one or more first input signals of a first evaluation tree in accordance with the first clock signal. The dynamic node is evaluated to a second value in response to one or more second input signals of a second evaluation tree in accordance with the second clock signal. | 2015-08-06 |
20150222268 | CONFIGURABLE ANALOG FRONT ENDS FOR CIRCUITS WITH SUBSTANTIALLY GATE ENCLOSED INNER ELECTRODE MOSFET SWITCH - A configurable integrated circuit (IC) includes a substrate having a semiconductor surface that the IC is formed within and thereon. The IC includes a configurable Analog Front End (cAFE) including at least one circuit module or input/output (IO), an analog switch having at least a first substantially gate enclosed Metal Oxide Semiconductor Field Effect Transistor (SGEFET) having a gate stack including a gate on a gate dielectric, a source, and a drain. The drain or source is a substantially gate enclosed (SGE) inner electrode relative to the gate, and the other of the source and the drain is outside the gate. The inner electrode of the first SGEFET is directly coupled to an analog bus. A switch control provides control signals to at least the gate of the first SGEFET for controlling a connectivity between the circuit module and/or the IO and the analog bus. | 2015-08-06 |
20150222269 | PROGRAMMABLE LOGIC DEVICE - A PLD in which a configuration memory is formed using a nonvolatile memory with a small number of transistors and in which the area of a region where the configuration memory is disposed is reduced is provided. Further, a PLD that is easily capable of dynamic reconfiguration and has a short startup time is provided. A programmable logic device including a memory element, a selector, and an output portion is provided. The memory element includes a transistor in which a channel is formed in an oxide semiconductor film, and a storage capacitor and an inverter which are connected to one of a source and a drain of the transistor. The inverter is connected to the selector. The selector is connected to the output portion. | 2015-08-06 |
20150222270 | FREQUENCY DIVIDING CIRCUIT AND PHASE SYNCHRONIZATION CIRCUIT - A frequency dividing circuit includes: a mode selection section configured to determine an exclusive OR of a first clock signal and a first signal and output the exclusive OR as a second signal in a first operation mode, and to output the first clock signal as the second signal in a second operation mode; and a clock generation section configured to generate and output a second clock signal, based on the second signal and the second clock signal, and to output one of the second clock signal and a third clock signal, as the first signal, the third clock signal having a phase same as a phase of the second clock signal. | 2015-08-06 |
20150222271 | CLOCK SIGNAL GENERATOR - A clock generator suitable for use with memory devices enables generation of memory clock signals having odd or even division ratios, an optional phase shift and a 50% duty cycle. First and second clock gate circuits receive a base clock signal and an inverted version thereof, respectively, and are both gated by the output of two comparators that are set when a value of a down counter receiving the base clock signal reaches a predetermined value. The clock gate circuits each include a multiplexer and D-type flip-flop. The output from either flip-flop, or both their outputs ‘ORed’ together, may be used as a memory clock depending on the desired division ratio and phase shift. The generator is particularly suitable for DDR memory applications that require both edges of the clock signal are evenly placed for launching data on both rising and falling edges. | 2015-08-06 |
20150222272 | OSCILLATOR CIRCUIT AND METHOD FOR GENERATING AN OSCILLATOR SIGNAL - The present invention relates to an oscillator circuit, comprising a switched capacitor circuit comprising a parallel circuit with a current input to be supplied with a reference current on one side and being connected to a reference terminal on the other side. The parallel circuit further comprises a first capacitor in a first branch and, in a second branch, a second capacitor connected in-between a first and second switch. A switch control unit comprises a first input coupled to the current input of the parallel circuit and a second input to be supplied with a reference voltage as well as an oscillator output for providing an oscillator signal. The switch control unit is being designed to operate the first and second switch such that, in a charging phase, the first and second capacitor is charged to a respective level depending on the reference voltage and, in a discharging phase, the charge stored on the first capacitor is discharged using the charge stored on the second capacitor. | 2015-08-06 |
20150222273 | APPARATUS AND METHODS FOR PHASE-LOCKED LOOPS WITH SOFT TRANSITION FROM HOLDOVER TO REACQUIRING PHASE LOCK - Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock. | 2015-08-06 |
20150222274 | SYSTEM READY IN A CLOCK DISTRIBUTION CHIP - Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready. | 2015-08-06 |
20150222275 | Apparatus and Methods for Phase-Locked Loop Startup Operation - A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal. | 2015-08-06 |
20150222276 | DOUBLE PHASE-LOCKED LOOP WITH FREQUENCY STABILIZATION - A double phase-locked has a first phase-locked loop including a first narrowband loop filter configured to reduce phase noise in a first input clock, and a second phase-locked loop including a second loop filter configured to receive a second input clock from a stable clock source. The second clock has a frequency close to said first clock. The first loop has a bandwidth at least an order of magnitude less than the second loop. A coupler couples the first and second phase-locked loops to provide a common output. The double phase-locked loop can be used, for example, to provide time-of-day information in wireless networks or as a fine filter for cleaning phase noise from clock signals recovered over telecom/datacom networks. | 2015-08-06 |
20150222277 | SELF-ADJUSTING CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME - In one form, a clock doubler includes a switched inverter, an exclusive logic circuit, and a control signal generation circuit. The switched inverter has first and second control inputs for respectively receiving first and second control signals, a signal input for receiving a clock input signal, and an output. The exclusive logic circuit has a first input for receiving the clock input signal, a second input coupled to the output of the switched inverter, and an output for providing a clock output signal. A control signal generation circuit provides the first and second control signals in response to the clock output signal. The clock doubler may be used in a clock distribution circuit for an integrated circuit that also includes a phase locked loop for providing the input clock signals, and a plurality of clock sub-domains each having one of the clock doublers. | 2015-08-06 |
20150222278 | Apparatus and Methods for Phase-Locked Loop Oscillator Calibration and Lock Detection - A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active. | 2015-08-06 |
20150222279 | PLL FREQUENCY SYNTHESIZER WITH MULTI-CURVE VCO IMPLEMENTING CLOSED LOOP CURVE SEARCHING - A phase-locked loop circuit using a multi-curve voltage-controlled oscillator (VCO) having a set of operating curves, each operating curve corresponding to a different frequency range over a control voltage range. The phase-locked loop circuit includes a digital control circuit configured to generate a curve select signal using a closed loop curve search operation to select one of the operating curves in the multi-curve VCO, the selected operating curve being used by the VCO to generate an output signal with an output frequency being equal or close to a target frequency of the phase-locked loop. In one embodiment, the digital control circuit implements a binary jump method and an operating curve is selected when the operating curve has an output frequency meeting the target frequency with the control voltage being within a first voltage range being a narrowed and centered voltage range within the control voltage range. | 2015-08-06 |
20150222280 | APPARATUS AND METHODS FOR FAST CHARGE PUMP HOLDOVER ON SIGNAL INTERRUPTION - Provided herein are apparatus and methods for fast charge pump holdover on signal interruption. In certain configurations, a clock generator system includes a phase-locked loop (PLL), a fast detect circuit, and a switch electrically coupled to an input of the PLL's loop filter. The fast detect circuit relatively quickly detects when an input signal to the PLL is lost. The fast detect circuit can quickly detect the loss of phase lock and can place the PLL into a holdover such that the frequency of a clock signal generated by the PLL remains within an acceptable range. | 2015-08-06 |
20150222281 | Stacked Synthesizer for Wide Local Oscillator Generation Using a Dynamic Divider - A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number. | 2015-08-06 |
20150222282 | Timing Compensation Using the System Clock - An integrated circuit including a plurality of internal clock generator circuits from which an internal clock is selected based on an external time reference. A number of cycles of internal clock signals from each of the internal clock generator circuits, or from at least one of those circuits where a frequency relationship is known, is counted relative to a system clock signal based on the external time reference. The lowest frequency internal clock signal providing at least a minimum number of cycles within the system clock period, the minimum number assuring completion of a function within a time constraint, is selected as the internal clock. Robust performance over a wide range of fabrication process parameters and operating conditions is assured. | 2015-08-06 |
20150222283 | CLOCK OPERATION METHOD AND CIRCUIT - In a clock generating circuit, a variable frequency division circuit generates a variable divided clock by dividing a source clock in accordance with a division ratio setting signal. A first clock synchronization circuit generates a first delayed clock that is delayed by a maximum number of clocks from the variable divided clock in synchronization with the source clock and supplies the first delayed clock to a control circuit. One or more second clock synchronization circuits generate one or more second delayed clocks, each of which is delayed by the maximum number of clocks from the variable divided clock in synchronization with the source clock, and supply each of the one or more second delayed clocks to each of one or more functional modules. | 2015-08-06 |
20150222284 | SYSTEM AND METHOD FOR DYNAMIC FREQUENCY ESTIMATION FOR A SPREAD-SPECTRUM DIGITAL PHASE-LOCKED LOOP - A digital phase-and-frequency controller. In one embodiment, the controller includes: (1) a first segment accumulator operable to accumulate errors while an accumulation-selection signal has a first value and (2) a second segment accumulator operable to accumulate errors while said accumulation-selection signal has a second value, and (3) circuitry operable to produce the control signal using the errors accumulated in the first segment accumulator while a use-selection signal has a first value and the errors accumulated in the second segment accumulator while the use-selection signal has a second value. | 2015-08-06 |
20150222285 | ATOMIC OSCILLATOR AND INTERROGATION METHOD OF COHERENT POPULATION TRAPPING RESONANCE - An atomic oscillator includes an alkali-metal cell in which alkali-metal atoms are enclosed, a light source which irradiates the atoms in the alkali-metal cell with laser beams, a photodetector which detects a light amount of the laser beams passing through the alkali-metal cell to enter the photodetector, and a controller which generates sidebands including a pair of laser beams with different wavelengths by performing frequency modulation of a carrier on the light source, causes the pair of laser beams with the different wavelengths to enter the alkali-metal cell, and controls a modulation frequency according to optical absorption characteristics of the atoms by quantum interference effects of a pair of resonance laser beams, wherein the side bands include second-order or higher-order sidebands. | 2015-08-06 |
20150222286 | Apparatus and Method for Digital to Analog Conversion with Current Mirror Amplification - A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current. | 2015-08-06 |
20150222287 | TRAVELING-WAVE BASED HIGH-SPEED SAMPLING SYSTEMS - Communications data interface sampling systems configured effectively with fully-symmetric dual-loop traveling wave oscillators providing high frequency evenly spaced multiple phases to represent analog-in-nature continuous signals as digital stream of samples with best approximation to the original signal. | 2015-08-06 |
20150222288 | ANALOG TO DIGITAL CONVERTER AND A METHOD OF OPERATING AN ANALOG TO DIGITAL CONVERTER - Example embodiments of this disclosure can provide an apparatus, a system, and a method of correcting for charge lost from a sampling capacitor as a result of an analog to digital conversion being performed. In an embodiment, there is provided a method of operating an analog to digital converter comprising at least a first sampling capacitor used to sample an input signal, where the method can further comprise a correction step of modifying the voltage across the at least first sampling capacitor, the correction step being performed prior to commencing an acquire phase. | 2015-08-06 |
20150222289 | SIGMA-DELTA MODULATOR AND ANALOG-TO-DIGITAL CONVERTER - A Sigma-Delta modulator and an analog-to-digital converter. The Sigma-Delta modulator comprises a quantizer, a correction module and an RC integrator. The correction module comprises a predetermined resistance through which a correction level is generated. The correction module is used to compare the correction level with a predetermined reference voltage by using a comparator in the quantizer, so as to generate a digital correction signal, based on which the resistance in a resistance correction array in the RC integrator is corrected. The predetermined resistance is of the same type as the resistance in the resistance correction array in the RC integrator. The Sigma-Delta modulator and the analog-to-digital converter can correct the resistance deviation in the RC integrator. | 2015-08-06 |
20150222290 | COMMUNICATION APPARATUS, IMAGE FORMING APPARATUS, COMMUNICATION METHOD, AND COMPUTER-READABLE STORAGE MEDIUM - A communication apparatus includes a serializer configured to convert parallel data into serial data and output the serial data; and a deserializer configured to convert the serial data output from the serializer into parallel data and output the parallel data. The serializer is configured to add first data used for detecting unique data in the parallel data before the unique data, add second data used for detecting the unique data after the unique data, and add third data whose length is variable to each of the first data and the second data. | 2015-08-06 |
20150222291 | MEMORY CONTROLLER, STORAGE DEVICE AND MEMORY CONTROL METHOD - According to one embodiment, a memory controller comprises an encoding unit that encodes first unit data and second unit data to generate a first codeword and a second codeword; a rearranging unit that extracts a first bit string in specific bit positions from each of the first and second codewords to generate first page data and to generate second page data containing the remaining bit strings other than the first bit strings respectively in the first and second codewords; and a write control unit that writes the first page data and the second page data respectively into a first page and a second page of a nonvolatile memory. | 2015-08-06 |
20150222292 | MULTI-BIT ERROR CORRECTION METHOD AND APPARATUS BASED ON A BCH CODE AND MEMORY SYSTEM - Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein. | 2015-08-06 |
20150222293 | Maintaining running disparity while utilizing different line-codes - Methods and systems for encoding a frame utilizing at least two line-codes having different minimal Hamming distances. The method includes maintaining over the frame absolute value of running disparity lower than or equal to K, while: encoding a first part of the frame utilizing a first line-code having a binary code word length N′ and a minimal Hamming distance D′; and encoding a second part of the frame utilizing a second line-code having a binary code word length N″ and a minimal Hamming distance D″ lower than D′. Where the value of K is lower than both N′/2 and N″/2. | 2015-08-06 |
20150222294 | METHOD AND APPARATUS FOR WIRELESS DATA TRANSMISSION SUBJECT TO PERIODIC SIGNAL BLOCKAGES - Approaches for satellite data transmissions are provided, which accommodate for periodic signal blockages without packet loss. A data stream is segmented into packets for wireless transmission, wherein the transmission is subject to a periodic blockage, wherein the periodic blockage comprises two blockages occurring within a time period, and each blockage is of a respective duration and recurs at regular intervals based on the time period. A forward error correction outer code is applied to the packets for recovery of data erasures due to the periodic blockage, wherein the application of the outer code comprises applying an error correction code to each of the packets to generate a respective codeblock. Each codeblock is interleaved to prevent erasure of consecutive parity bits within the codeblock. The encoded and interleaved codeblocks are transmitted over a wireless channel, wherein a number of data erasures occur within each codeblock due to the periodic blockage. | 2015-08-06 |
20150222295 | ENCODING/DECODING METHOD, DEVICE, AND SYSTEM - Embodiments of the present invention provide an encoding/decoding method, apparatus, and system. The present invention is used to improve the decoding performance and improve accuracy of a survivor path. The method includes: encoding information bits to obtain a first-level encoded code word; obtaining a sorting value of each check bit of the first-level encoded code word, and adjusting each check bit to a corresponding position according to the sorting value of each check bit, where the sorting value refers to a value of S when the check bit is related to first S information bits of the information bits in the first-level encoded code word, and S is a non-zero integer; and performing second-level encoding on the first-level encoded code word after positions of the check bits are adjusted, thereby obtaining a second-level encoded code word. The present invention is applicable to various communication systems. | 2015-08-06 |
20150222296 | CIRCUIT, ENCODER AND METHOD FOR PARALLEL BCH CODING - The present invention is applicable to the field of error correction coding, and provides a circuit, an encoder and a method for parallel BCH coding. The method comprises: performing an XOR operation on input sequences {m(p−1), m(p−2), . . . , m(0)} in a current period in sequence corresponding to output upper bits of the previous period of a register separately, outputting operation results as selection signals to a selector, selecting P constant-multinomials {xr<<0) mod g(x), (xr<<1) mod g(x), . . . , (xr<<(p−1)) mod g(x)} with 0 separately in sequence, shifting the selection results and the output of the previous period of the register in P bits towards the upper bits and outputting the selection results, summing the selection results and outputting the sum to the register to serve as an output of the current period of the register; the above steps are repeated specific times to obtain final code output. | 2015-08-06 |
20150222297 | VITERBI DECODING DEVICE AND METHOD FOR DECODING A SIGNAL PRODUCED BY A CONVOLUTIONAL ENCODER - A convolutional encoder may have N different states, each having two predecessor states, each branch from each of the two predecessor states having a static code word CW=(B | 2015-08-06 |
20150222298 | INPUT DEVICE WITH SWITCHABLE FREQUENCY CHANNEL - An input device for switchable use between first and second computer systems. A controller of the input device can execute switching logic to direct a radio transceiver of the input device to switch an operating channel of the radio transceiver to a first channel monitored by the first computer system in response to a first event, and thereby, the input device can be utilized to insert data into the first computer system. The controller can execute switching logic to direct the radio transceiver to switch the operating channel to a second channel monitored by the second computer system in response to a second event, and thereby, the input device can be utilized to insert data into the second computer system. | 2015-08-06 |
20150222299 | SYSTEMS AND METHODS FOR INCREASING THE EFFECTIVENESS OF DIGITAL PRE-DISTORTION IN ELECTRONIC COMMUNICATIONS - Various embodiments of communication systems and methods in which the communication system is operative to find, record, and use sets of pre-distortion parameters in conjunction with a pre-distortion procedure, in which each said set of pre-distortion parameters is operative to specifically counter distortions produced in a power amplifier by a specific combination of level of input signal power and level of analog gain associated with a transmission path of the communication system. In some embodiments, there is a modulator, a transmission chain, a distortion analysis mechanism, and a pre-distortion mechanism, operative to analyze and modify signals so as to counter signal distortion. | 2015-08-06 |
20150222300 | DUPLEXER - A duplexer having good insulation, small geometric dimensions and good decoupling of the transmit signal path from an antenna which may have poor matching is specified. To that end, the duplexer comprises two transmit filters, a receive filter and two 90° hybrids. | 2015-08-06 |
20150222301 | TRANSMITTING CIRCUIT AND TRANSCEIVER SYSTEM INCLUDING THE SAME - A transmitting circuit includes a positive differential node, a negative differential node, a voltage mode driver, and a current mode driver. The voltage mode driver generates a first positive differential signal and a first negative differential signal. The voltage mode driver provides the first positive differential signal to the positive differential node and provides the first negative differential signal to the negative differential node. The current mode driver generates a second positive differential signal and a second negative differential signal. The current mode driver provides the second positive differential signal to the positive differential node and provides the second negative differential signal to the negative differential node. A differential signal voltage swing width between the positive differential node and the negative differential node is based at least on the operational state of the current mode driver and/or the voltage mode driver. | 2015-08-06 |
20150222302 | INFORMATION PROCESSING SYSTEM AND PARAMETER ADJUSTMENT METHOD - An information processing system includes: a transmission device to generate a transmission signal on the basis of a pre-emphasis parameter; a reception device to generate reception data from the transmission signal on the basis of a clock signal; and a processor. The processor sets a center value, calculates and compares an eye diagram width of the center value and an eye diagram width of each peripheral value, when any of the eye diagram widths of the peripheral values is larger than the eye diagram width of the center value, repeats a process for setting as the center value a peripheral value that corresponds to a largest eye diagram width, a process for calculating the eye diagram width of each peripheral value and the comparing process until the eye diagram width of the center value becomes larger than the eye diagram width of each peripheral value. | 2015-08-06 |
20150222303 | HIGH SPEED SIGNALING SYSTEM WITH ADAPTIVE TRANSMIT PRE-EMPHASIS - A high-speed signaling system with adaptive transmit pre-emphasis. A transmit circuit has a plurality of output drivers to output a first signal onto a signal path. A receive circuit is coupled to receive the first signal via the signal path and configured to generate an indication of whether the first signal exceeds a threshold level. A first threshold control circuit is coupled to receive the indication from the receive circuit and configured to adjust the threshold level according to whether the first signal exceeds the threshold level. A drive strength control circuit is coupled to receive the indication from the receive circuit and configured to adjust a drive strength of at least one output driver of the plurality of output drivers according to whether the first signal exceeds the threshold level. | 2015-08-06 |
20150222304 | INTERFERENCE MANAGEMENT INFORMATION SIGNALING - Certain aspects of the present disclosure relate to techniques and apparatus for signaling interference management information, such as network assisted interference cancelation (NAIC) information as downlink control information (DCI). According to certain aspects, a method is provided for wireless communications by an interfering or potentially interfering base station. The method generally includes generating information for use by a user equipment (UE) in performing interference mitigation when processing a signal from a serving base station and transmitting the information to the UE. The method may further include generating an indication of how the interfering or potentially interfering base station transmits the information and how one or more cells transmit information for use by the UE in performing interference mitigation when processing a signal from the serving base station and transmitting the indication to the UE. | 2015-08-06 |
20150222305 | REDUCING SECOND ORDER DISTORTION IN AN AMPLIFIER - In an embodiment, an apparatus includes a component of a receiver path to receive and process an incoming signal. At least one element of the component is controllable based on a DC output of the component, to compensate for a second order intermodulation product of the apparatus. As one example, the component is a differential amplifier including a first transistor and a second transistor. | 2015-08-06 |
20150222306 | RADIO-FREQUENCY SIGNAL RECEPTION CIRCUIT AND ISOLATED SIGNAL TRANSMISSION APPARATUS - A radio-frequency signal reception circuit that detects an input signal includes an input reference terminal, a first input terminal into which a first input signal is input, a second input terminal into which a second input signal is input, an output terminal and output reference terminal from which an output signal is output, a first detector circuit that detects the first input signal and outputs a first output signal, which is a positive-voltage pulse signal, to the output terminal, a second detector circuit that detects the second input signal and outputs a second output signal, which is a positive-voltage pulse signal, to the output reference terminal, and a transistor connected to the input reference terminal and output reference terminal. The input signal includes the first input signal and second input signal. The output signal includes the first output signal and second output signal. | 2015-08-06 |
20150222307 | RECEPTION QUALITY MEASURING APPARATUS AND RECEPTION QUALITY MEASURING METHOD - A reception quality measuring apparatus ( | 2015-08-06 |
20150222308 | COMMUNICATION DEVICE WITH IMPROVED INTERFERENCE REJECTION AND A METHOD THEREOF - A communication device is disclosed. The device may be in particular a radio transmitter and a receiver that can operate with low power consumption and with improved interference rejection, therefore particularly suitable for use in low-power communication systems, such as wireless sensor networks and wireless body area networks. In one aspect, multiple frequency tones (carriers) are used to carry information from the transmitter, such that a RF signal having multiple radio frequency components is produced and transmitted. In the receiver, an envelope detector is still the RF down-converter. After down-converting intermodulation components are extracted containing amplitude, phase and frequency information of the multiple radio frequency components. This allows the desired signal (the baseband information) to be distinguished from the carriers and unwanted interference. | 2015-08-06 |
20150222309 | COMPENSATION APPARATUS AND WIRELESS COMMUNICATION EQUIPMENT - A compensation apparatus is provided which performs a compensation process of removing an image component in a quadrature-demodulated signal. The compensation apparatus includes a quadrature demodulation compensation section that compensates for the quadrature-demodulated signal including an I signal and a Q signal. The quadrature demodulation compensation section is configured to perform a compensation process of compensating for a characteristic difference between the frequency characteristic of a first filter that performs filtering of the I signal and the frequency characteristic of a second filter that performs filtering of the Q signal. | 2015-08-06 |
20150222310 | Methods and systems for dual-using a reception channel - Various embodiments of wireless communication systems and methods in which the system seamlessly dual-uses a receiver chain for incoming transmissions and for other signal sensing purposes. The system is configured such that there are multiple receiver chains, and at least one receiver chain alternates between receiving a communication signal with information payload and receiving other signals solely for the purposes of monitoring and/or improving some aspects of the system. In various embodiments, the alternating receiver chain receives alternatively signals with information payloads and signals which have passes through a power amplifier with amplifier distortion characteristics. In various embodiments, the alternating receiver chain receives alternatively signals with information payloads and signals which may be associated with background noise, or other radio transmissions. | 2015-08-06 |
20150222311 | HOUSING FOR ELECTROSTATIC DISCHARGE PROTECTION OF A PORTABLE COMMUNICATION DEVICE - A housing ( | 2015-08-06 |
20150222312 | Adaptive Maximum Power Limiting Using Capacitive Sensing in a Wireless Device - An apparatus for satisfying Specific Absorption Rate (SAR) compliance criteria including a first capacitance sensor, a second capacitance sensor, a memory, and a processor. The memory is configured to store pre-established proximity regions that include a free space region of proximity based on baseline capacitance measurements obtained from the sensors when no human body is proximate a wireless device and a first region of proximity based on initial capacitance measurements obtained from the sensors when the human body is spaced apart from the wireless device by a first predetermined separation distance. The processor is configured to instruct a radio frequency (RF) transmitter to operate at a first output power when subsequent capacitance measurements received from the sensors are within the free space region of proximity and at a second output power, less than the first output power when the subsequent capacitance measurements are within the first region of proximity. | 2015-08-06 |
20150222313 | AUTOMATED ARRANGEMENT OF A MOBILE APPARATUS IN EQUIPMENT - An arrangement for mounting of a mobile apparatus in equipment provided with a first movable support displaceable along a main axis, the first movable support being able to receive the mobile apparatus for it to be arranged in a location in which it is held in position by a holding device. The holding device is itself displaceable along a longitudinal axis between a retracted position in which the mobile apparatus can be placed in or removed from the location and an extended position in which the mobile apparatus is held in position in the housing. The equipment is in addition provided with a mechanical transmission means arranged between the movable support and the holding device so that the displacements of the mobile apparatus drives those of the holding device. | 2015-08-06 |