30th week of 2011 patent applcation highlights part 14 |
Patent application number | Title | Published |
20110180842 | HIGH VOLTAGE SCRMOS IN BiCMOS PROCESS TECHNOLOGIES - An integrated circuit containing an SCRMOS transistor. The SCRMOS transistor has one drain structure with a centralized drain diffused region and distributed SCR terminals, and a second drain structure with distributed drain diffused regions and SCR terminals. An MOS gate between the centralized drain diffused region and a source diffused region is shorted to the source diffused region. A process of forming the integrated circuit having the SCRMOS transistor is also disclosed. | 2011-07-28 |
20110180843 | CHARGE-BALANCE POWER DEVICE COMPRISING COLUMNAR STRUCTURES AND HAVING REDUCED RESISTANCE, AND METHOD AND SYSTEM OF SAME - An embodiment of a charge-balance power device formed in an epitaxial layer having a first conductivity type and housing at least two columns of a second conductivity type, which extend through the epitaxial layer. A first and a second surface region of the second conductivity type extend along the surface of the epitaxial layer on top of, and in contact with, a respective one of the columns, and a second and a third surface region of the first conductivity type extends within the first and the second surface region, respectively, facing the surface of the epitaxial layer. The columns extend at a distance from each other and are arranged staggered to one another with respect to a first direction and partially facing one another with respect to a second direction transversal to the first direction. | 2011-07-28 |
20110180844 | POWER SEMICONDUCTOR DEVICES INTEGRATED WITH CLAMP DIODES HAVING SEPARATED GATE METAL PADS TO AVOID BREAKDOWN VOLTAGE DEGRADATION - A structure of power semiconductor device integrated with clamp diodes having separated gate metal pads is disclosed. The separated gate metal pads are wire bonded together on the gate lead frame. This improved structure can prevent the degradation of breakdown voltage due to electric field in termination region blocked by polysilicon or gate metal. | 2011-07-28 |
20110180845 | Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies - An electrostatic discharge (ESD) protection circuit includes a triggering diode that includes a junction between a P-grade (PG) region and an N-well. The PG region has a dopant profile equivalent to a P-drain dopant profile of a PMOS transistor having a breakdown voltage represented by V whereby the triggering diode for conducting a current when a voltage greater than the breakdown voltage V is applied. In an exemplary embodiment, the dopant profile of the PG region includes two dopant implant profiles that include a shallow implant profile with a higher dopant concentration and a deep implant profile with a lower dopant concentration. | 2011-07-28 |
20110180846 | Method for Forming Antimony-Based FETs Monolithically - An integrated circuit structure includes a substrate and a first and a second plurality of III-V semiconductor layers. The first plurality of III-V semiconductor layers includes a first bottom barrier over the substrate; a first channel layer over the first bottom barrier; and a first top barrier over the first channel layer. A first field-effect transistor (FET) includes a first channel region, which includes a portion of the first channel layer. The second plurality of III-V semiconductor layers is over the first plurality of III-V semiconductor layers and includes a second bottom barrier; a second channel layer over the second bottom barrier; and a second top barrier over the second channel layer. A second FET includes a second channel region, which includes a portion of the second channel layer. | 2011-07-28 |
20110180847 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - According to one embodiment, a semiconductor device having a Ge- or SiGe-fin structure includes a convex-shaped active area formed along one direction on the surface region of a Si substrate, a buffer layer of Si | 2011-07-28 |
20110180848 | HIGH PERFORMANCE SiGe:C HBT WITH PHOSPHOROUS ATOMIC LAYER DOPING - A base structure for high performance Silicon Germanium:Carbon (SiGe:C) based heterojunction bipolar transistors (HBTs) with phosphorus atomic layer doping (ALD) is disclosed. The ALD process subjects the base substrate to nitrogen gas (in ambient temperature approximately equal to 500 degrees Celsius) and provides an additional SiGe:C spacer layer. During the ALD process, the percent concentrations of Germanium (Ge) and carbon (C) are substantially matched and phosphorus is a preferred dopant. The improved SiGe:C HBT is less sensitive to process temperature and exposure times, and exhibits lower dopant segregation and sharper base profiles. | 2011-07-28 |
20110180849 | SEMICONDUCTOR SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - There is provided a semiconductor wafer having a base wafer, an insulating layer, and a Si | 2011-07-28 |
20110180850 | Configuration and manufacturing method of low-resistance gate structures for semiconductor devices and circuits - The present invention provides methods for fabricating devices with low resistance structures involving a lift-off process. A radiation blocking layer is introduced between two resist layers in order to prevent intermixing of the photoresists. Cavities suitable for the formation of low resistance T-gates or L-gates can be obtained by a first exposure, developing, selective etching of blocking layer and a second exposure and developing. In another embodiment, a low resistance gate structure with pillars to enhance mechanical stability or strength is provided. | 2011-07-28 |
20110180851 | CMOS DEVICES WITH A SINGLE WORK FUNCTION GATE ELECTRODE AND METHOD OF FABRICATION - Described herein are a device utilizing a gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby. Further described herein are methods of fabricating a device formed of complementary (pMOS and nMOS) transistors having semiconductor channel regions which have been band gap engineered to achieve a low threshold voltage. | 2011-07-28 |
20110180852 | ASYMMETRIC SOURCE/DRAIN JUNCTIONS FOR LOW POWER SILICON ON INSULATOR DEVICES - A semiconductor device includes a buried insulator layer formed on a bulk substrate; a first type semiconductor material formed on the buried insulator layer, and corresponding to a body region of a field effect transistor (FET); a second type of semiconductor material formed over the buried insulator layer, adjacent opposing sides of the body region, and corresponding to source and drain regions of the FET; the second type of semiconductor material having a different bandgap than the first type of semiconductor material; wherein a source side p/n junction of the FET is located substantially within whichever of the first and the second type of semiconductor material having a lower bandgap, and a drain side p/n junction of the FET is located substantially entirely within whichever of the first and the second type of semiconductor material having a higher bandgap. | 2011-07-28 |
20110180853 | CARRIER MOBILITY ENHANCED CHANNEL DEVICES AND METHOD OF MANUFACTURE - An integrated circuit with stress enhanced channels, a design structure and a method of manufacturing the integrated circuit is provided. The method includes forming a dummy gate structure on a substrate and forming a trench in the dummy gate structure. The method further includes filling a portion of the trench with a strain inducing material and filling a remaining portion of the trench with gate material. | 2011-07-28 |
20110180854 | Normally-off gallium nitride-based semiconductor devices - A method includes forming a relaxed layer in a semiconductor device. The method also includes forming a tensile layer over the relaxed layer, where the tensile layer has tensile stress. The method further includes forming a compressive layer over the relaxed layer, where the compressive layer has compressive stress. The compressive layer has a piezoelectric polarization that is approximately equal to or greater than a spontaneous polarization in the relaxed, tensile, and compressive layers. The piezoelectric polarization in the compressive layer could be in an opposite direction than the spontaneous polarization in the compressive layer. The relaxed layer could include gallium nitride, the tensile layer could include aluminum gallium nitride, and the compressive layer could include aluminum indium gallium nitride. | 2011-07-28 |
20110180855 | NON-DIRECT BOND COPPER ISOLATED LATERAL WIDE BAND GAP SEMICONDUCTOR DEVICE - Non-direct bond copper isolated lateral wide band gap semiconductor devices are provided. One semiconductor device includes a heat sink, a buffer layer directly overlying the heat sink, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Another semiconductor device includes a heat sink, a substrate directly overlying the heat sink, a buffer layer directly overlying the substrate, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Being formed of a group-III nitride enables the various epitaxial layers to be electrically isolated from their respective heat sinks. | 2011-07-28 |
20110180856 | SENSING DEVICE - Provided is a sensing device, which includes a reactive material layer ( | 2011-07-28 |
20110180857 | STRUCTURE HAVING SILICON CMOS TRANSISTORS WITH COLUMN III-V TRANSISTORS ON A COMMON SUBSTRATE - A semiconductor structure having: a silicon substrate having a crystallographic orientation; an insulating layer disposed over the silicon substrate; a silicon layer having a different crystallographic orientation than the crystallographic orientation of the substrate disposed over the insulating layer; and a column III-V transistor device having the same crystallographic orientation as the substrate disposed on the silicon substrate. In one embodiment, the column III-V transistor device is in contact with the substrate. In one embodiment, the device is a GaN device. In one embodiment, the crystallographic orientation of the substrate is <111> and wherein the crystallographic orientation of the silicon layer is <100>. In one embodiment, CMOS transistors are disposed in the silicon layer. In one embodiment, the column III-V transistor device is a column III-N device. In one embodiment, a column III-As, III-P, or III-Sb device is disposed on the top of the <100> silicon layer. | 2011-07-28 |
20110180858 | Semiconductor Device - A semiconductor device. The semiconductor comprises a substrate, a VDMOS, a JFET, a first electrode, a second electrode, a third electrode and a fourth electrode. The VDMOS is formed in the substrate. The JFET is formed in the substrate. Wherein the first electrode, the second electrode and a third electrode are connected to the VDMOS and used as a first gate electrode, a first drain electrode and a first source electrode of the VDMOS respectively. The second electrode, the third electrode and the fourth electrode are connected to the JFET and used as a second drain electrode, a second gate electrode and a second drain electrode of the JFET respectively. | 2011-07-28 |
20110180859 | Semiconductor device, method of manufacturing semiconductor device, and solid-state imaging apparatus - A semiconductor device includes a gate electrode formed on a substrate with a gate insulating layer in between, an insulating layer of property and thickness that allow for a silicide block formed in a first region of the substrate so as to cover the gate electrode, a sidewall formed to at least partly include the insulating layer at a side of the gate electrode, a first impurity region formed by implantation of a first impurity in a peripheral region of the gate electrode formed in the first region of the substrate before the insulating layer is formed, a second impurity region formed by implantation of a second impurity in a peripheral region of the sidewall of the gate electrode formed in a second region of the substrate after the sidewall is formed, and a silicide layer formed on a surface of the second impurity region of the substrate. | 2011-07-28 |
20110180860 | Solid-state imaging apparatus, method of manufacturing same, and electronic apparatus - A solid-state imaging apparatus includes a plurality of pixels each including a photoelectric conversion unit and pixel transistors, which are formed on a semiconductor substrate; a floating diffusion unit in the pixel; a first-conductivity-type ion implantation area for surface pinning, which is formed over the surface on the side of the photoelectric conversion unit and the surface of the semiconductor substrate; and a second-conductivity-type ion implantation area for forming an overflow path serving as an overflow path for the floating diffusion unit, the second-conductivity-type ion implantation area being formed below the entire area of the first-conductivity-type ion implantation area. An overflow barrier is formed using the second-conductivity-type ion implantation area. A charge storage area is formed using an area in which the second-conductivity-type semiconductor area and the second-conductivity-type ion implantation area superpose each other. | 2011-07-28 |
20110180861 | MAGNETIC RANDOM ACCESS MEMORY HAVING MAGNETORESISTIVE EFFECT ELEMENT - A magnetic random access memory includes the following structure. A first magnetoresistive effect element is formed on a semiconductor substrate. The first magnetoresistive effect element includes a first fixed layer, a first nonmagnetic layer and a first free layer. The first fixed layer has an invariable magnetization direction. The first nonmagnetic layer is formed on the first fixed layer. The first free layer is formed on the first nonmagnetic layer and has a variable magnetization direction. An active region is formed on the substrate. A first select transistor includes a first diffusion region and a second diffusion region which are formed in the active region. The first diffusion region is electrically connected to the first free layer. A second select transistor includes the first diffusion region and a third diffusion region which are formed in the active region. A first interconnect layer is electrically connected to the first fixed layer. | 2011-07-28 |
20110180862 | EMBEDDED DYNAMIC RANDOM ACCESS MEMORY DEVICE AND METHOD - Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer. One embodiment of the invention provides an integrated circuit for an embedded dynamic random access memory (eDRAM) comprising: a semiconductor-on-insulator (SOI) wafer including: an n-type substrate; an insulator layer atop the n-type substrate; and an active semiconductor layer atop the insulator layer; a plurality of deep trenches, each extending from a surface of the active semiconductor layer into the n-type substrate; a dielectric liner along a surface of each of the plurality of deep trenches; and an n-type conductor within each of the plurality of deep trenches, the dielectric liner separating the n-type conductor from the n-type substrate; wherein the n-type substrate, the dielectric liner, and the n-type conductor form a buried plate, a node dielectric, and a node plate, respectively, of a cell capacitor. | 2011-07-28 |
20110180863 | DRAM Unit Cells, Capacitors, Methods Of Forming DRAM Unit Cells, And Methods Of Forming Capacitors - Some embodiments include methods of forming capacitors. A first capacitor storage node may be formed within a first opening in a first sacrificial material. A second sacrificial material may be formed over the first capacitor storage node and over the first sacrificial material, and a retaining structure may be formed over the second sacrificial material. A second opening may be formed through the retaining structure and the second sacrificial material, and a second capacitor storage node may be formed within the second opening and against the first storage node. The first and second sacrificial materials may be removed, and then capacitor dielectric material may be formed along the first and second storage nodes. Capacitor electrode material may then be formed along the capacitor dielectric material. Some embodiments include methods of forming DRAM unit cells, and some embodiments include DRAM unit cell constructions. | 2011-07-28 |
20110180864 | MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A memory device is provided, including a substrate, a conductive layer, a charge storage layer, a plurality of isolation structures, a plurality of first doped regions, and a plurality of second doped regions. The substrate has a plurality of trenches. The conductive layer is disposed on the substrate and fills the trenches. The charge storage layer is disposed between the substrate and the conductive layer. The isolation structures are disposed in the substrate between two adjacent trenches, respectively. The first doped regions are disposed in an upper portion of the substrate between each isolation structure and each trench, respectively. The second doped regions are disposed in the substrate under a bottom portion of the trenches, in which each isolation structure is disposed between two adjacent second doped regions. | 2011-07-28 |
20110180865 | CHARGE STORAGE NODES WITH CONDUCTIVE NANODOTS - Memory cells formed to include a charge storage node having conductive nanodots over a charge storage material are useful in non-volatile memory devices and electronic systems. | 2011-07-28 |
20110180866 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, an insulating film, a non-doped semiconductor film, a semiconductor pillar, a charge storage film, a contact, and a spacer insulating film. The stacked body is provided on the substrate. The stacked body includes a plurality of doped semiconductor films stacked. The insulating film is provided between the doped semiconductor films in a first region. The non-doped semiconductor film is provided between the doped semiconductor films in a second region. The semiconductor pillar pierces the stacked body in a stacking direction of the stacked body in the first region. The charge storage film is provided between the doped semiconductor film and the semiconductor pillar. The contact pierces the stacked body in the stacking direction in the second region. The spacer insulating film is provided around the contact. | 2011-07-28 |
20110180867 | METAL TRANSISTOR DEVICE - The present invention is related to a depletion or enhancement mode metal transistor in which the channel regions of a transistor device comprises a thin film metal or metal composite layer formed over an insulating substrate. | 2011-07-28 |
20110180868 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and a method for manufacturing the same. According to the present invention, a method of manufacturing a semiconductor device includes: forming a recess on a semiconductor substrate; forming a first gate electrode material and a hard mask layer on an entire surface including the recess; etching the hard mask layer and the first gate electrode material to form the first gate electrode pattern on a lower portion of inside of the recess; forming a second gate electrode material on an entire surface including the recess; and etching the second gate electrode material and separating the second gate electrode material. | 2011-07-28 |
20110180869 | SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCTION THEREOF - A semiconductor device contains a first transistor including a single trench which is formed on a substrate between a source region and a drain region and a gate electrode which is formed in the single trench, a second transistor including at least two trenches which are formed on the substrate between a source region and a drain region and a gate electrode which is formed in the at least two trenches, and also contains a device isolation insulating which isolates the region in which the transistor is formed. The first transistor has first distance between the single trench and the device isolation insulating film and the second transistor has second distance between the adjoining trenches, such the first distance is less than the second distance in a gate width direction. | 2011-07-28 |
20110180870 | HIGH VOLTAGE SCRMOS IN BiCMOS PROCESS TECHNOLOGIES - An integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. The RESURF region is the same conductivity type as the drift region and is more heavily doped than the drift region. An SCRMOS transistor with a RESURF region around the drain region and SCR terminal. A process of forming an integrated circuit having an SCRMOS transistor with a RESURF region around the drain region and SCR terminal. | 2011-07-28 |
20110180871 | FIELD EFFECT TRANSISTORS (FETS) AND METHODS OF MANUFACTURE - An improved field effect transistors (FETs) and methods of manufacturing the field effect transistors (FETs) are provided. The method of manufacturing a zero capacitance random access memory cell (ZRAM) includes comprises forming a finFET on a substrate and enhancing a storage capacitance of the finFET. The enhancement can be by either adding a storage capacity to the finFET or altering a portion of the finFET after formation of a fin body of the finFET. | 2011-07-28 |
20110180872 | ASYMMETRIC EPITAXY AND APPLICATION THEREOF - The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming a gate structure on top of a semiconductor substrate, the gate structure including a gate stack and spacers adjacent to sidewalls of the gate stack, and having a first side and a second side opposite to the first side; performing angled ion-implantation from the first side of the gate structure in the substrate, thereby forming an ion-implanted region adjacent to the first side, wherein the gate structure prevents the angled ion-implantation from reaching the substrate adjacent to the second side of the gate structure; and performing epitaxial growth on the substrate at the first and second sides of the gate structure. As a result, epitaxial growth on the ion-implanted region is much slower than a region experiencing no ion-implantation. A source region formed to the second side of the gate structure by the epitaxial growth has a height higher than a drain region formed to the first side of the gate structure by the epitaxial growth. A semiconductor structure formed thereby is also provided. | 2011-07-28 |
20110180873 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The invention also provides a semiconductor device comprising: a plurality of first gate patterns disposed in a cell area of a substrate region; a plurality of first junction regions disposed in the cell area respectively adjacent to the first gate patterns; buried insulation film buried in the middle area of the substrate region at a bottom region of the cell area; at least one second gate pattern disposed in a peripheral area of the substrate region; and a plurality of second junction regions disposed in the substrate region respectively adjacent to the second gate pattern. | 2011-07-28 |
20110180874 | SEMICONDUCTOR DEVICE - It is desired to effectively suppress breaking of a protection target circuit caused by direct application of an ESD surge voltage to the circuit. The semiconductor device includes: a VDD pad; a signal output pad; a GND pad; a high-potential power source line; a signal line; a low-potential power source line; main ESD protection elements; a PMOS transistor; and an output circuit. The output circuit includes: an NMOS transistor N | 2011-07-28 |
20110180875 | ESD Protection Device and Method - An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region. | 2011-07-28 |
20110180876 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - A semiconductor device comprises a switching element. The switching element comprises a first channel terminal, a second channel terminal and a switching terminal. One of the first and second channel terminals provides a reference terminal and the switching element is arranged such that an impedance of the switching element between the first channel terminal and second channel terminal is dependant upon a voltage across the switching terminal and the reference terminal. The semiconductor device further comprises a first resistance element operably coupled between the first channel terminal and the switching terminal and a second resistance element operably coupled between the switching terminal and the second channel terminal of the semiconductor device. When a negative current is encountered at the first channel terminal, the negative current causes both a voltage drop across the switching terminal and the first channel terminal and a voltage drop across the second channel terminal and the switching terminal. | 2011-07-28 |
20110180877 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - To provide a technique capable of positioning of a semiconductor chip and a mounting substrate with high precision by improving visibility of an alignment mark. In a semiconductor chip constituting an LCD driver, a mark is formed in an alignment mark formation region over a semiconductor substrate. The mark is formed in the same layer as that of an uppermost layer wiring (third layer wiring) in an integrated circuit formation region. Then, in the lower layer of the mark and a background region surrounding the mark, patterns are formed. At this time, the pattern P | 2011-07-28 |
20110180878 | High Side Semiconductor Structure - A high side semiconductor structure is provided. The high side semiconductor structure includes a substrate, a first deep well, a second deep well, a first active element, a second active element and a doped well. The first deep well and the second deep well are formed in the substrate, wherein the first deep well and the second deep well have identical type of ion doping. The first active element and the second active element are respectively formed in the first deep well and the second deep well. The doped well is formed in the substrate and is disposed between the first deep well and the second deep well. The doped well, the first deep well and the second deep well are interspaced, and the type of ion doping of the first deep well and the second deep well is complementary with that of the doped well. | 2011-07-28 |
20110180879 | CMOS TRANSISTOR, SEMICONDUCTOR DEVICE INCLUDING THE TRANSISTOR, AND SEMICONDUCTOR MODULE INCLUDING THE DEVICE - Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module. | 2011-07-28 |
20110180880 | DUAL METAL AND DUAL DIELECTRIC INTEGRATION FOR METAL HIGH-K FETS - The present invention, in one embodiment, provides a method of forming a semiconductor device that includes providing a substrate including a first conductivity type region and a second conductivity type region; forming a gate stack including a gate dielectric atop the first conductivity type region and the second conductivity type region of the substrate and a first metal gate conductor overlying the high-k gate dielectric; removing a portion of the first metal gate conductor that is present in the first conductivity type region to expose the gate dielectric present in the first conductivity type region; applying a nitrogen based plasma to the substrate, wherein the nitrogen based plasma nitrides the gate dielectric that is present in the first conductivity type region and nitrides the first metal gate conductor that is present in the second conductivity type region; and forming a second metal gate conductor overlying at least the gate dielectric that is present in the first conductivity type region. | 2011-07-28 |
20110180881 | INTEGRATION SCHEME FOR REDUCING BORDER REGION MORPHOLOGY IN HYBRID ORIENTATION TECHNOLOGY (HOT) USING DIRECT SILICON BONDED (DSB) SUBSTRATES - Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming ( | 2011-07-28 |
20110180882 | Semiconductor Device and Method of Fabricating the Same - According to an aspect of the invention, there is provided a semiconductor device including a first semiconductor element formed on a semiconductor substrate and using electrons as carriers, and a second semiconductor element formed on the semiconductor substrate and using holes as carriers, a first insulating film and a second insulating film formed on source/drain regions and gate electrodes of the first element and the second element, the first insulating film having tensile stress with respect to the first element, and the second insulating film having compression stress with respect to the second element, and sidewall spacers of the gate electrodes of the first element and the second element, at least portions of the sidewall spacers being removed, wherein at least one of the first insulating film and the second insulating film does not close a spacing between the gate electrodes of the first element and the second element. | 2011-07-28 |
20110180883 | METHOD AND STRUCTURE TO IMPROVE BODY EFFECT AND JUNCTION CAPACITANCE - A method and structure implant a first-type impurity within a substrate to form a channel region within the substrate adjacent a top surface of the substrate; form a gate stack on the top surface of the substrate above the channel region; and implant a second-type impurity within the substrate to form source and drain regions within the substrate adjacent the top surface. The channel region is positioned between the source and drain regions. The second-type impurity has an opposite polarity with respect to the first-type impurity. The method and structure implant a greater concentration of the first-type impurity, relative to a concentration of the first-type impurity within the channel region, to form a primary body doping region within the substrate below (relative to the top surface) the channel region; and to form secondary body doping regions within the substrate below (relative to the top surface) the source and drain regions. | 2011-07-28 |
20110180884 | METHODS, APPARATUSES, AND SYSTEMS FOR MICROMECHANICAL GAS CHEMICAL SENSING CAPACITOR - A capacitive chemical sensor, along with methods of making and using the sensor are provided. The sensors described herein eliminate undesirable capacitance by etching away the substrate underneath the capacitive chemical sensor, eliminating most of the substrate capacitance and making changes in the chemical-sensitive layer capacitance easier to detect. | 2011-07-28 |
20110180885 | METHOD FOR ENCAPSULATING AN MEMS COMPONENT - Method for producing an MST device, and MST device | 2011-07-28 |
20110180886 | Method for Manufacturing a Micromachined Device and the Micromachined Device Made Thereof - Methods for manufacturing micromachined devices and the devices obtained are disclosed. In one embodiment, the method comprises providing a structural layer comprising an amorphous semiconductor material, forming a shielding layer on a first portion of the structural layer and leaving exposed a second portion of the structural layer, and annealing the second portion using a first fluence. The method further comprises removing the shielding layer, and annealing the first portion and the second portion using a second fluence that is less than half the first fluence. In an embodiment, the device comprises a substrate layer, an underlying layer formed on the substrate layer, and a sacrificial layer formed on only a portion of the underlying layer. The device further comprises a structural layer that is in contact with the underlying layer and comprises a first region annealed using a first fluence and a second region annealed using a second fluence. | 2011-07-28 |
20110180887 | Encapsulation, MEMS and Encapsulation Method - A method and encapsulation of a sensitive mechanical component structure in one embodiment includes a semiconductor substrate, and a film covering a component structure on the substrate, said film including at least one polymer layer, and at least one cavity formed between the component structure and the film, wherein at least one through contact penetrates through the film. | 2011-07-28 |
20110180888 | MAGNETIC STACK DESIGN - A magnetic stack having a free layer having a switchable magnetization orientation, a reference layer having a pinned magnetization orientation, and a barrier layer therebetween. The stack includes an annular antiferromagnetic pinning layer electrically isolated from the free layer and in physical contact with the reference layer. In some embodiments, the reference layer is larger than the free layer. | 2011-07-28 |
20110180889 | X-RAY DETECTOR - An X-ray detector includes a substrate; a gate line that is extended in a first direction on the substrate; a gate electrode that is extended from the gate line; a semiconductor layer that is positioned on the gate electrode; a source electrode and drain electrode that are positioned on the semiconductor layer; a lower electrode that is extended from the drain electrode; a photodiode that is positioned on the lower electrode; a first insulation layer that is positioned on the source electrode and the drain electrode and that includes a first opening that exposes the source electrode; and a data line that is extended in a second direction intersecting a first direction on the first insulation layer to intersect the gate line with the first insulation layer interposed between the data line and the gate line, and the data line being electrically connected to the source electrode through the first opening. | 2011-07-28 |
20110180890 | RADIOGRAPHIC IMAGE DETECTOR, METHOD OF PRODUCING THE SAME, AND PROTECTIVE MEMBER - A method of producing a radiographic image detector includes: preparing a thin-film transistor substrate comprising an insulating substrate and a thin-film transistor that is disposed on a surface of the insulating substrate at a first side; attaching, to the thin-film transistor substrate, a protective member comprising a protective member support and an adhesive layer that includes conductive particles and that is disposed on the protective member support, such that the adhesive layer and a surface of the thin-film transistor substrate at the first side contact each other; polishing a surface of the thin-film transistor substrate at a second side opposite to the first side, after the attaching of the protective member; separating and removing the protective member from the thin-film transistor substrate after the polishing; and providing a scintillator layer on a surface of the thin-film transistor substrate at the first side, after the removing of the protective member. | 2011-07-28 |
20110180891 | CONDUCTOR PACKAGE STRUCTURE AND METHOD OF THE SAME - The present invention provides a conductor package structure comprising an optical sensor element. A filling material is filled around the optical sensor element. At least one conductor element is formed through the filling material from top side to the back side for signal connection. A redistribution layer is formed on the at least one conductor element and coupled to die pad of the optical sensor element. A transparent material is formed on the redistribution layer. | 2011-07-28 |
20110180892 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package and a method for manufacturing the same are provided. The semiconductor package includes a semiconductor chip having a first surface, a second surface and a pixel area, first adhesion patterns disposed on the first surface, second adhesion patterns disposed between the first adhesion patterns and the pixel area and disposed on the first surface, and external connection terminals disposed on the second surface, wherein the second adhesion patterns and the external connection terminals are disposed to overlap each other. | 2011-07-28 |
20110180893 | IMAGING MODULE, FABRICATING METHOD THEREFOR, AND IMAGING DEVICE - An imaging module includes an imaging chip including a micro-lens guiding incident light and an imaging element in a semiconductor substrate and converting the incident light into an electric signal, and a polarizing glass chip including a polarizing filter glass having a polarizer determining a polarization direction of the incident light arranged on a transparent substrate such that the polarizer faces the micro-lens and a spacer member connected to the polarizing filter glass to adjust a gap between the polarizer and the micro-lens of the imaging chip. In the imaging module, a melt-bonding surface of the spacer member is melt-bonded to the semiconductor substrate such that the polarizer of the polarizing glass chip and the micro-lens of the imaging chip are arranged close to each other via the gap, and the imaging element and the micro-lens of the imaging chip are sealed by the polarizing glass chip. | 2011-07-28 |
20110180894 | NANOSTRUCTURED PHOTODIODE - The present invention provides a photodiode comprising a p-i-n or pn junction at least partly formed by first and second regions ( | 2011-07-28 |
20110180895 | METHOD OF MANUFACTURING A CMOS IMAGE SENSOR - Disclosed is a method of manufacturing a CMOS image sensor, capable of preventing hillock-type defects caused by the delamination of interconnections from occurring in the CMOS image sensor. The method of manufacturing the CMOS image sensor includes preparing a substrate having a first metal interconnection, forming an interlayer insulation layer over the first metal interconnection, forming a contact hole to expose a part of the first metal interconnection by etching the interlayer insulation layer, forming a buffer layer on the interlayer insulation layer along an inner surface of the contact hole, performing an annealing process, forming a spacer on an inner sidewall of the contact hole by etching the buffer layer, forming a barrier metal layer along a top surface of the interlayer insulation layer including the spacer, forming a contact plug on the barrier metal layer such that the contact hole is filled with the contact plug, and forming a second metal interconnection on the interlayer insulation layer such that the second metal interconnection makes contact with the contact plug. | 2011-07-28 |
20110180896 | METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS - A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided. | 2011-07-28 |
20110180897 | PACKAGED SEMICONDUCTOR PRODUCT AND METHOD FOR MANUFACTURE THEREOF - Packaged semiconductor product ( | 2011-07-28 |
20110180898 | SEMICONDUCTOR DEVICE - According to the embodiments, a core block is formed on a semiconductor chip, and is constructed of an integrated circuit that can operate independently. A power-supply switch is formed on the semiconductor chip, and connects or disconnects the core block to or from a power line. A capacitor is formed on the semiconductor chip, and is connected to the power line in parallel to the core block. A selection switch is formed on the semiconductor chip, and connects or disconnects the capacitor to or from the power line. | 2011-07-28 |
20110180899 | SEMICONDUCTOR DEVICE - A semiconductor device has a package structure provided with leads that are external connection terminals. A base substance is an island, and at least the surface thereof is formed of a conductive material. A semiconductor substrate is mounted on the surface of the base substance, and a ground potential is supplied from the surface of the base substance. A shunt capacitor is provided with an electrode pair of a first electrode and a second electrode formed in parallel, and mounted with the first electrode being electrically connected to the surface of the base substance. An internal bonding wire connects a pad provided on the semiconductor substrate for external connection, to the second electrode of the shunt capacitor. The lead is the external connection terminal of the semiconductor device. An external bonding wire connects the lead to the second electrode of the shunt capacitor. | 2011-07-28 |
20110180900 | SEMICONDUCTOR CHIP, SEMICONDUCTOR MOUNTING MODULE, MOBILE COMMUNICATION DEVICE, AND PROCESS FOR PRODUCING SEMICONDUCTOR CHIP - A semiconductor chip comprising a capacitor capable of effectively controlling the voltage drop of an LSI is provided. A semiconductor substrate is provided with an element electrode having at least its surface constituted of an aluminum electrode. The surface of the aluminum electrode is roughened. An oxide film is provided on the aluminum electrode. A conductive film is provided on the oxide film. The aluminum electrode, oxide film and conductive film form a capacitor. | 2011-07-28 |
20110180901 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device having a structure free from variations in resistance even when a stress is applied thereto; and a manufacturing method of the device. The semiconductor device has a metal resistor layer in a region between a passivation film and an uppermost level aluminum interconnect. This makes it possible to realize a high-precision resistor having few variations in resistance due to a mold stress that occurs in a packaging step or thereafter and therefore, makes it possible to form a high-precision analog circuit. | 2011-07-28 |
20110180902 | REVERSE CONDUCTING IGBT - In a reverse conducting IGBT, diode cathode regions are formed dispersedly on the back side of a device chip. When the distribution density of the diode cathode region becomes low, VF of a fly-back diode, that is, a forward voltage drop becomes large. On the other hand, when the distribution density of the diode cathode region becomes high, it becomes hard for a PN junction at a collector part to turn ON and a snap back occurs. In contrast to this, there is a method of providing about one to several diode cathode absent regions having a macro area, however, the arrangement of the regions itself directly affects the device characteristics, and therefore, it is difficult to control the device characteristics and variations thereof. | 2011-07-28 |
20110180903 | SEMICONDUCTOR SUBSTRATE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE - There is provided a semiconductor wafer having a base wafer, an insulating layer, and a Si | 2011-07-28 |
20110180904 | GROUP III NITRIDE SEMICONDUCTOR SUBSTRATE AND METHOD FOR CLEANING THE SAME - A Group-III nitride semiconductor substrate having a flat surface with a dangling bond density of higher than 14.0 nm | 2011-07-28 |
20110180905 | GeSbTe MATERIAL INCLUDING SUPERFLOW LAYER(S), AND USE OF Ge TO PREVENT INTERACTION OF Te FROM SbXTeY AND GeXTeY RESULTING IN HIGH Te CONTENT AND FILM CRYSTALLINITY - A multilayer film stack containing germanium, antimony and tellurium that can be annealed to form a GST product material of homogeneous and smooth character, wherein at least one antimony-containing layer is isolated from a tellurium-containing layer by an intervening germanium layer, and the multilayer film stack comprises at least two intervening germanium layers. The multilayer film stack can be formed by vapor deposition techniques such as chemical vapor deposition or atomic layer deposition. The annealable multilayer film stack can be formed in high aspect ratio vias to form phase change memory devices of superior character with respect to the stoichiometric and morphological characteristics of the GST product material. | 2011-07-28 |
20110180906 | METHOD OF APPLYING A PATTERN OF METAL, METAL OXIDE AND/OR SEMICONDUCTOR MATERIAL ON A SUBSTRATE - A method of applying a pattern of metal, metal oxide, and/or semiconductor material on a substrate, a pattern created by that method, and uses of that pattern. | 2011-07-28 |
20110180907 | Organic Electronic Devices and Methods of Making the Same Using Solution Processing Techniques - A method of manufacturing an organic electronic device, the method comprising: providing a substrate; forming a well-defining structure over the substrate; and depositing a solution of organic semiconductive material and/or organic conductive material in wells defined by the well-defining structure, wherein the well-defining structure is formed by depositing a solution comprising a mixture of a first insulating material and a second insulating material, the second insulating material having a lower wettability than the first insulating material, and allowing the first and second insulating materials to at least partially phase separate wherein the second insulating material phase separates in a direction away from the substrate. | 2011-07-28 |
20110180908 | WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME - A wiring board includes a laminated body having first and second surfaces and including first, second and third insulation layers in the order of the first, second and third insulation layers from the first surface toward the second surface. The first insulation layer has a first hole which penetrates through the first insulation layer and includes a first conductor made of a plating in the first hole. The second insulation layer has a second hole which penetrates through the second insulation layer and includes a second conductor made of a conductive paste in the second hole. The third insulation layer has a third hole which penetrates through the third insulation layer and includes a third conductor made of a plating in the third hole. The first, second and third conductors are positioned along the same axis and are electrically continuous with each other. | 2011-07-28 |
20110180909 | SEMICONDUCTOR DEVICE - A semiconductor device includes an n-type semiconductor substrate, an alternating conductivity type layer on semiconductor substrate, the alternating conductivity type layer including n-type drift regions and p-type partition regions arranged alternately, p-type channel regions on the alternating conductivity type layer, and trenches formed from the surfaces of the p-type channel regions down to respective n-type drift regions or both the n-type drift regions and the p-type partition regions. The bottom of each trench is near or over the pn-junction between the p-type partition region and the n-type drift region. The semiconductor device facilitates preventing the on-resistance from increasing, obtaining a higher breakdown voltage, and reducing the variations caused in the characteristics thereof. | 2011-07-28 |
20110180910 | VERTICAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A vertical semiconductor device with improved junction profile and a method of manufacturing the same are provided. The vertical semiconductor device includes a pillar vertically extended from a surface of a semiconductor substrate, a silicon layer formed in a bit line contact region of one sidewall of the pillar, and a junction region formed within a portion of the pillar contacting with the silicon layer. | 2011-07-28 |
20110180911 | METHODS FOR RELAXATION AND TRANSFER OF STRAINED LAYERS AND STRUCTURES FABRICATED THEREBY - The present invention provides methods for forming at least partially relaxed strained material layers on a target substrate. The methods include forming islands of the strained material layer on an intermediate substrate, at least partially relaxing the strained material islands by a first heat treatment, and transferring the at least partially relaxed strained material islands to the target substrate. The at least partial relaxation is facilitated by the presence of low-viscosity or compliant layers adjacent to the strained material layer. The invention also provides semiconductor structures having an at least partially relaxed strained material layer, and semiconductor devices fabricated using an at least partially relaxed strained material layer. | 2011-07-28 |
20110180912 | PATTERNED THIN SOI - A semiconductor structure for electronics or optoelectronics that includes successively a bulk substrate, an oxide layer and a semiconductor layer, wherein the oxide layer comprises regions of different thicknesses which are selectively controlled. | 2011-07-28 |
20110180913 | METHOD OF STACKING FLIP-CHIP ON WIRE-BONDED CHIP - Some of the embodiments of the present disclosure provide apparatuses, systems, and methods for stacking chips. A first chip may be mounted on a substrate, wherein an active surface of the first chip faces away from the substrate, and wherein the first chip includes a plurality of bump pads located on the active surface of the first chip, and a wire may bond a first bump pad of the plurality of bump pads to the substrate. An intermediate layer may be disposed on at least a portion of the active surface of the first chip, and a via within the intermediate layer may extend to a second bump pad of the plurality of bump pads. A second chip may be disposed on the intermediate layer, wherein an active surface of the second chip faces towards the substrate, and wherein the second chip includes a third bump pad (i) located on the active surface of the second chip and (ii) aligned with the via formed in the intermediate layer. A corresponding bump may be disposed on one or more of (i) the second bump pad located on the active surface of the first chip and (ii) the third bump pad located on the active surface of the second chip, and within the via, wherein the corresponding bump electrically connects the second bump pad with the third bump pad. Other embodiments are also described and claimed. | 2011-07-28 |
20110180914 | INTEGRATED CIRCUIT PACKAGE-IN-PACKAGE SYSTEM WITH WIRE-IN-FILM ENCAPSULANT AND METHOD FOR MANUFACTURING THEREOF - A method for manufacturing a multiple encapsulation integrated circuit package-in-package system includes: dicing a top integrated circuit wafer having a bottom encapsulant thereon to form a top integrated circuit die with the bottom encapsulant; positioning internal leadfingers adjacent and connected to a bottom integrated circuit die; pressing the bottom encapsulant on to the bottom integrated circuit die; connecting the top integrated circuit die to external leadfingers adjacent the internal leadfingers; and forming a top encapsulant over the top integrated circuit die. | 2011-07-28 |
20110180915 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - An electronic device includes a heat sink, a substrate mounted on the heat sink, a coating layer formed on the substrate, a lead frame fixed to the heat sink, and a mold resin sealing the substrate and the lead frame. The coating layer is made of one of a polyimide-based resin and a polyamideimide-based resin. The lead frame has a fixing terminal fixed to the heat sink through an adhesive layer. The adhesive layer is made of the same material as the coating layer. | 2011-07-28 |
20110180916 | MULTI-CHIP PACKAGE HAVING FRAME INTERPOSER - A multi-chip package is provided. The multi-chip package may include a frame interposer, a first chip stack with n number of semiconductor chips on a first surface of the frame interposer, and a second chip stack with m number of semiconductor chips on a second surface of the frame interposer. The interposer may have first and second openings. The first chip stack may extend over one of the first and second openings and may expose the other of the first and second openings. The second chip stack may extend over the other of the first and second openings and may expose the one of the first and second openings. | 2011-07-28 |
20110180917 | MICROELECTRONIC ASSEMBLY WITH AN EMBEDDED WAVEGUIDE ADAPTER AND METHOD FOR FORMING THE SAME - A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate ( | 2011-07-28 |
20110180918 | Arrangement Comprising at Least One Power Semiconductor Module and a Transport Packaging - An arrangement comprising at least one power semiconductor module and a transport packaging, wherein the power semiconductor module has a base element, a housing and connection elements and the transport packaging has a generally planar cover layer, a cover film and at least one trough-like plastic shaped body for each power semiconductor module. The at least one plastic shaped body only partly encloses the respective power semiconductor module and a part of the plastic shaped body does not directly contact the power semiconductor module. Furthermore, a first side of the at least one power semiconductor module becomes situated directly or indirectly on the first main surface of the cover layer, while the cover film covers the further sides of the power semiconductor module directly and/or indirectly, and bears at least partly against the plastic shaped body. | 2011-07-28 |
20110180919 | MULTI-TIERED INTEGRATED CIRCUIT PACKAGE - An integrated circuit package base includes a plurality of tiers. In some examples, an integrated circuit package encloses a plurality of stacked integrated circuits that are each electrically coupled to an electrical contact located on a respective tier of the package base. The tiers of the integrated circuit package can have different elevations relative to a bottom surface of the integrated circuit package. | 2011-07-28 |
20110180920 | CO-AXIAL RESTRAINT FOR CONNECTORS WITHIN FLIP-CHIP PACKAGES - An assembly can include a microelectronic element such as, for example, a semiconductor element having circuits and semiconductor devices fabricated therein, and a plurality of electrical connectors, e.g., solder balls attached to contacts of the microelectronic element. The connectors can be surrounded by first, inner regions | 2011-07-28 |
20110180921 | INTEGRATED CIRCUIT PACKAGE - A method of manufacturing a ball grid array, BGA, integrated circuit package, comprising forming a double sided printed circuit board, PCB, with blind vias interconnecting electrically the circuits on the opposed surfaces of the PCB, with at least one through-hole to allow fluid or gas to pass through the PCB, and an integrated circuit connected to the printed circuit on one side of the PCB; soldering a lid onto the said one side of the PCB to enclose the integrated circuit, whilst allowing thermally expanding gas or fluid to escape through the or each through-hole, whereby to form a package which is hermetically sealed except for the or each through-hole, and which has a cavity between the integrated circuit and the lid; applying a BGA to the side of the PCB opposed to the said one side, whereby to solder the balls of the BGA to respective portions of the printed circuit and to align one of the balls axially with each through-hole; and soldering the ball or balls into the through-hole, or into each respective through-hole, to hermetically seal the package. | 2011-07-28 |
20110180922 | SEMICONDUCTOR CHIP, SEAL-RING STRUCTURE AND MANUFACTURING PROCESS THEREOF - A semiconductor chip includes an integrated circuit region, at least one alignment indicator region and a seal-ring. The alignment indicator region is disposed near the integrated circuit region. The seal-ring surrounding the integrated circuit region is disposed outside of the integrated circuit region, and is formed as a mark for alignment on the alignment indicator region at a corner of the semiconductor chip. A manufacturing process of the seal-ring structure is also disclosed. | 2011-07-28 |
20110180923 | RELIABILITY ENHANCEMENT OF METAL THERMAL INTERFACE - A frontside of a chip is bonded to a top surface of a chip carrier. Seal material is dispensed at a periphery of the top surface of the chip carrier. A solder TIM having a first side and a second side is provided. The first side of the TIM contacts a backside of the chip. A reflow is performed to melt the TIM. The second side of the TIM is bonded to a lid. The seal material is cured. The lid is attached to the top surface of the chip carrier. Backfill material is injected into a space between the top surface of the chip carrier and the lid. The backfill material abuts sides of the TIM. The backfill material is cured. TIM solder cracking and associated thermal degradation are mitigated. | 2011-07-28 |
20110180924 | MEMS MODULE PACKAGE - A MEMS module package includes a carrier, a lid capped on the carrier, a spacer disposed between the carrier and the lid, and a chip mounted on the spacer and electrically connected with the carrier. The spacer has a channel in communication between a chamber and a receiving hole of the lid, and the chip is received in the chamber of the lid and corresponding to the channel of the spacer. Therefore, an external signal can be transmitted from the receiving hole of the lid into the chamber of the lid through the channel of the spacer so as be received by the chip. | 2011-07-28 |
20110180925 | Microfabricated Pillar Fins For Thermal Management - An electrical package with improved thermal management. The electrical package includes a die having an exposed back surface. The package further includes a plurality of fins extending outwardly from the back surface for dissipating heat from the package. The die can be arranged in a multi-die stacking configuration. In another embodiment, a method of forming a die for improved thermal management of an electrical package is provided. | 2011-07-28 |
20110180926 | Microelectromechanical Systems Embedded in a Substrate - An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device. | 2011-07-28 |
20110180927 | ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, CIRCUIT BOARD MOUNTED WITH THE SAME, AND ELECTRONIC APPLIANCE COMPRISING THE CIRCUIT BOARD - An integrated type semiconductor device that is capable of reducing cost or improving the reliability of connecting semiconductor chips together or chips to a circuit board. One embodiment of such an integrated type semiconductor device comprises a first semiconductor device having a semiconductor chip with electrodes, a stress-relieving layer prepared on the semiconductor chip, a wire formed across the electrodes and the stress-relieving layer, and solder balls formed on the wire over the stress-relieving layer; and a bare chip as a second semiconductor device to be electrically connected to the first semiconductor device. | 2011-07-28 |
20110180928 | ETCHED RECESS PACKAGE ON PACKAGE SYSTEM - An integrated circuit package system includes: interconnection pads; a first device mounted below the interconnection pads; a bond wire, or a solder ball connecting the first device to the interconnection pads; a lead connected to the interconnection pad or to the first device; an encapsulation having a top surface encapsulating the first device; and a recess in the top surface of the encapsulation with the interconnection pads exposed therefrom. | 2011-07-28 |
20110180929 | GOLD-TIN-INDIUM SOLDER FOR PROCESSING COMPATIBILITY WITH LEAD-FREE TIN-BASED SOLDER - Disclosed in this specification is a lead-free soldering alloy made of gold, tin and indium. The tin is present in a concentration of 17.5% to 20.5%, the indium is present in a concentration of 2.0% to 6.0% and the balance is gold and the alloy has a melting point between 290° C. and 340° C. and preferably between 300° C. and 340° C. The soldering alloy is particularly useful for hermetically sealing semiconductor devices since the melting temperature is sufficiently high to permit post-seal heating and sufficiently low to allow sealing of the semiconductor without causing damage. | 2011-07-28 |
20110180930 | WIRING BOARD, MANUFACTURING METHOD OF THE WIRING BOARD, AND SEMICONDUCTOR PACKAGE - A wiring board includes a ceramic substrate including a plurality of stacked ceramic layers, an internal wiring, and an electrode electrically connected to the internal wiring, the electrode being exposed from a first surface of the ceramic substrate; and a silicon substrate including a wiring layer, the wiring layer including a wiring pattern and a via-fill, the wiring pattern being formed on a main surface of the silicon substrate, an end of the via-fill being electrically connected to the wiring pattern, another end of the via-fill being exposed from a rear surface of the silicon substrate positioned opposite to the main surface, wherein the another end of the via-fill is bonded to the electrode of the ceramic substrate via a metal layer. | 2011-07-28 |
20110180931 | ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE - The invention relates to an semi-conductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner. | 2011-07-28 |
20110180932 | METHOD OF MANUFACTURING LAYERED CHIP PACKAGE - A layered chip package includes a main body, and wiring including a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of semiconductor chips stacked, and a plurality of electrodes that electrically connect the semiconductor chips to the wires. A method of manufacturing the layered chip package includes the steps of: fabricating a substructure that includes an array of a plurality of pre-separation main bodies and a plurality of holes for accommodating a plurality of preliminary wires, the holes being formed between two adjacent pre-separation main bodies; forming the preliminary wires in the plurality of holes by plating; and cutting the substructure so that the plurality of pre-separation main bodies are separated from each other and the preliminary wires are split into two sets of wires of two separate main bodies, whereby a plurality of layered chip packages are formed. | 2011-07-28 |
20110180933 | SEMICONDUCTOR MODULE AND SEMICONDUCTOR MODULE MANUFACTURING METHOD - A wiring layer is formed on a substrate, and a semiconductor device is mounted on the substrate. The wiring layer and the semiconductor device are sealed by a sealing resin. A conductive member is used to fill a through hole formed in the sealing resin in a predetermined position of the wiring layer and is provided so as to cover over the sealing resin. The metal foil is provided on the upper surface of the conductive member, and the metal foil and the wiring layer are electrically connected via the conductive member. | 2011-07-28 |
20110180934 | SEMICONDUCTOR DEVICE - A semiconductor device may include: first and second wiring boards separated from each other via a gap; a semiconductor chip; first and second groups of electrode pads; and first and second groups of connection pads. The semiconductor chip is fixed to upper surfaces of the first and second wiring boards, and has a first portion adjacent to the gap. The first and second groups of electrode pads are disposed on the first portion. The first and second groups of electrode pads are aligned adjacent to side surfaces of the first and second wiring boards, respectively. The side surfaces of the first and second wiring boards face each other. The first and second groups of connection pads are disposed on lower surfaces of the first and second wiring boards, respectively. The first and second groups of connection pads are aligned adjacent to the side surfaces of the first and second wiring boards, respectively. | 2011-07-28 |
20110180935 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a conductive pillar, having substantially parallel vertical sides, in direct contact with the substrate; mounting an integrated circuit to the substrate beside a conductive pillar location; and encapsulating the integrated circuit with an encapsulation having a top surface formed for the conductive pillar to extend beyond. | 2011-07-28 |
20110180936 | SEMICONDUCTOR DEVICE STRUCTURES AND ELECTRONIC DEVICES INCLUDING SAME HYBRID CONDUCTIVE VIAS - A conductive via of a semiconductor device includes a relatively small diameter portion extending into an active surface of a fabrication substrate and a corresponding, relatively large diameter portion that extends into a back side of the fabrication substrate. This type of conductive via may be fabricated by forming the relatively small diameter portion before or during BEOL processing, while the large diameter portion of each conductive via may be fabricated after BEOL processing is complete. Electronic devices that include one or more semiconductor devices with such conductive vias are also disclosed. | 2011-07-28 |
20110180937 | STACKED PACKAGE OF SEMICONDUCTOR DEVICE - Provided is a stacked package of a semiconductor device and a method of manufacturing the same. The stacked package of a semiconductor device may include at least one first semiconductor chip, at least one second semiconductor chip, at least one interposer between the at least one first semiconductor chip and the at least one second semiconductor chip, and a third semiconductor chip on the at least one first semiconductor chip. The at least one first semiconductor chip and the at least one second semiconductor chip may be configured to perform a first function and a second function and each may include a plurality of bonding pads. The third semiconductor chip may be configured to perform a third function which is different from the first and the second functions. The package may further include external connection leads may be configured to electrically connect the third semiconductor chip to the outside. | 2011-07-28 |
20110180938 | ELECTRONIC DEVICE AND METHOD OF MANUFACTURING THE SAME - In an electronic device, a silicone adhesive bonding first and second members is made from a composition comprising: (A) 100 parts by mass of an organopolysiloxane containing in one molecule at least two alkenyl groups and being free of silicon-bonded hydroxyl and alkoxy groups wherein the content of cyclic siloxanes having 4 to 20 siloxane units is at most 0.1 mass %; (B) an organopolysiloxane containing in one molecule at least two silicon-bonded hydrogen atoms and being free of an alkenyl group, and silicon-bonded hydroxyl and alkoxy groups; (C) at least 0.05 parts by mass of an adhesion promoter; (D) 100 to 2000 parts by mass of a thermally conductive filler; and (E) a hydrosilylation-reaction catalyst. (B) is contained such that the silicon-bonded hydrogen atoms is in the range of 0.5 to 10 mol per 1 mol of the alkenyl groups of (A), and the sum of (B) and (C) is 0.5 to 10 mass % of the sum of (A), (B) and (C). | 2011-07-28 |
20110180939 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device capable of adhering semiconductor elements and a support member for mounting semiconductor elements, such as lead frames, organic substrates or the like, even in a relatively low temperature range without damaging adhesion property and workability and of suppressing the occurrence of voids. The method of manufacturing a semiconductor device according to the invention is a method of manufacturing a semiconductor device comprising a semiconductor element and a support member adhered to the semiconductor element through a cured material of an adhesive film, wherein the method comprises the steps (a) to (d) in this order;
| 2011-07-28 |
20110180940 | INTERCONNECTION STRUCTURE AND ITS DESIGN METHOD - An interconnection structure includes a semiconductor chip, a mounting substrate on which the semiconductor chip is mounted, and a group of bonding wires provided to connect the semiconductor chip and the mounting substrate. The group of bonding wires includes: a first signal bonding wire contained in a first envelope and provided to propagate a signal; a first power supply bonding wire contained in the first envelope and applied with a first power supply voltage; and a second power supply bonding wire contained in a second envelope and applied with a second power supply voltage. One of the first envelope and the second envelope is arranged between the other of the first envelope and the second envelope and the mounting substrate. The second power supply bonding wire is arranged in a position in which electromagnetic coupling between the second power supply bonding wire and the first signal bonding wire is smaller than electromagnetic coupling between the second power supply bonding wire and the first power supply bonding wire. | 2011-07-28 |
20110180941 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided is a three-dimensional semiconductor device and method for fabricating the same. The device includes a first electrode structure and a second electrode structure stacked sequentially on a substrate. The first and second electrode structures include stacked first electrodes and stacked second electrodes, respectively. Each of the first and second electrodes includes a horizontal portion parallel with the substrate and an extension portion extending from the horizontal portion along a direction penetrating an upper surface of the substrate. Here, the substrate may be closer to top surfaces of the extension portions of the first electrodes than to the horizontal portion of at least one of the second electrodes. | 2011-07-28 |