29th week of 2012 patent applcation highlights part 19 |
Patent application number | Title | Published |
20120181980 | Power Transfer System and Noncontact Charging Device - A high-voltage side conductor is formed near the upper surface of a power transmission device, and a low-voltage side conductor is formed near the lower surface of the power transmission device. The power transmission device includes an alternating voltage generating circuit. A high-voltage side conductor is formed near the lower surface of a power reception device, and a low-voltage side conductor is formed near the upper surface of the power reception device. The power reception device includes a load circuit. When the high-voltage side conductors face a capacitive coupling conductor of an auxiliary sheet, capacitances are generated respectively between the high-voltage side conductors and the capacitive coupling conductor. Thus, the high-voltage side conductors are capacitively coupled to each other via the capacitive coupling conductor. | 2012-07-19 |
20120181981 | ENERGY SUPPLY UNIT, LAND VEHICLE, REPLACEMENT STATION AND METHOD FOR REPLACEMENT OF AN ENERGY SUPPLY UNIT CONTAINED IN A LAND VEHICLE - The invention relates to an energy supply unit ( | 2012-07-19 |
20120181982 | Localized Charging of Electric Vehicles - The described method and system provide for managing the charging of individual electric vehicles with respect to local substations or grids to lower the load on a given substation or grid. When the load on a substation or grid reaches a warning threshold, a call center may facilitate the implementation of a charging plan to reduce the load. The call center may locate and identify vehicles that are being charged in the relevant area and may further manage the charging of the located vehicles to reduce the load through a charging plan. The plan may be based on the current State of charge of each vehicle, the historical use and projected use of each vehicle, vehicle charging patterns, and the severity of the load on the substation or grid. | 2012-07-19 |
20120181983 | DUAL-CHARGER SYSTEM - A charger system for use in a vehicle to charge a vehicle battery includes a first charger and a second charger. The chargers are connected to a vehicle bus. Each charger has a master indication digital input and decodes the input to determine its role as master charger or slave charger. The master charger configures its connection to the vehicle bus to use a master node message set. The slave charger configures its connection to the vehicle bus to use a slave node message set. | 2012-07-19 |
20120181984 | CHARGING APPARATUS - A charging apparatus for charging electric power supplied from a power source to a charging target includes a station section configured to supply the electric power to the charging target. The station section includes a base extending in a vertical direction and a protrusion fixed to a part of the base and protruding frontward than the base. Space for disposing at least one article is formed on at least one of the upper side and the lower side of the protrusion. | 2012-07-19 |
20120181985 | NETWORK-CONTROLLED CHARGING SYSTEM FOR ELECTRIC VEHICLES - A network-controlled charge transfer device for electric vehicles includes a control device to turn electric supply on and off to enable and disable charge transfer for electric vehicles, a transceiver to communicate requests for charge transfer with a remote server and receive communications from the remote server, and a controller, coupled with the control device and the transceiver, to cause the control device to turn the electric supply on based on communication from the remote server. | 2012-07-19 |
20120181986 | NETWORK-CONTROLLED CHARGING SYSTEM FOR ELECTRIC VEHICLES - A server of a network-controlled charging system for electric vehicles receives a request for charge transfer for an electric vehicle at a network-controlled charge transfer device, determines whether to enable charge transfer, and responsive to determining to enable charge transfer, transmits a communication to the network-controlled charge transfer device that indicates to the network-controlled charge transfer device to enable charge transfer. | 2012-07-19 |
20120181987 | SYSTEM FOR CHARGE AND DISCHARGE OF BATTERY PACK - A system configured to charge and discharge a battery pack is disclosed. The system includes a battery management unit configured to receive a wake up voltage, and a wake up unit configured to apply the wake up voltage to the first port during normal operation. | 2012-07-19 |
20120181988 | SECONDARY BATTERY SYSTEM AND CHARGING SYSTEM FOR SECONDARY BATTERY - A secondary battery system includes a secondary battery, an abnormality detecting unit OC which detects whether the secondary battery has become abnormal, and a signal generating circuit which outputs a signal to an externally connected device based on detection information of the abnormality detecting unit OC. The signal generating circuit includes a circuit element that can be held at least in a first state and in a second state. The signal generating circuit is configured to change an output state of a signal to the externally connected device based on whether the circuit element is in the first state or in the second state. The signal generating circuit is configured to switch the circuit element from the first state to the second state when the abnormality detecting unit OC has detected the abnormal state, and not to return the circuit element to the first state. | 2012-07-19 |
20120181989 | ELECTRIC ENERGY GENERATING APPARATUS AND MOBILE ELECTRIC DEVICE THEREOF - An electric energy generating apparatus and a mobile electronic device equipped with the electric energy generating apparatus are disclosed. The electric energy generating apparatus includes a kinetic energy generating module, a kinetic energy transmission module, an electric generator and a voltage regulation module. The kinetic energy generating module is provided for generating kinetic energy; the kinetic energy transmission module is provided for transmitting the kinetic energy generated by the kinetic energy generating module to the electric generator; the electric generator is provided for converting the kinetic energy into electric energy; and the voltage regulation module is provided for regulating and outputting a voltage. The invention can convert the kinetic energy into the electric energy anytime and anywhere to overcome the problems of running out of battery power or resulting in a failure of operating the mobile electronic device and provide an easily accessible green power source from man power. | 2012-07-19 |
20120181990 | DC POWER SUPPLY APPARATUS - A DC power supply apparatus includes a charging circuit, which charges a secondary battery of a vehicle from an AC power source device or a DC power source device. The charging circuit includes a non-insulating converter circuit and an insulating converter circuit. A breaker relay disconnects the AC power source device and the charging circuit in an initial charging period to supply a large charging current to the secondary battery by the non-insulating converter circuit. As a result, charging can be performed with high efficiency without the insulation transformer. The breaker relay connects the AC power source device and the charging circuit after the initial charging period. Only the insulating converter circuit supplies the charging current to the secondary battery. Thus, adverse effect of stray capacitance of a circuit of the vehicle can be eliminated. | 2012-07-19 |
20120181991 | RAPID CHARGING AND POWER MANAGEMENT OF A BATTERY-POWERED FLUID ANALYTE METER - A system and method is described for rapid charging and power management of a battery for a meter. A charger component is operably associated with the meter and is capable of executing a rapid charge algorithm for a rechargeable battery. The algorithm includes monitoring for a connection to an external power source and implementing a charging routine of a battery at a first charge rate and then at a second charge rate. The second charge rate is lower than the first charge rate. A temperature rise in the rechargeable battery due to the first charge rate has a negligible heat transfer effect on the fluid sample. The meter can also include a power switch for controlling current flow to a battery fuel gauge. The power switch is open when the meter enters into a sleep mode. The state of battery charge is determined after the meter exits the sleep mode. | 2012-07-19 |
20120181992 | METHOD FOR CHARGING AND METHOD FOR DETERMINING AN END-OF-CHARGE CRITERION OF A NICKEL-BASED BATTERY - The method for charging an electrochemical nickel-based battery having a predetermined nominal capacity, including at least one measurement of the voltage of the battery and one measurement of the temperature representative of the battery. The battery is connected to an intermittent source of energy. The charging of the battery is stopped when the voltage measured at the terminals of the battery reaches a voltage threshold, depending on the measured temperature and representative of a capacity charged in the battery corresponding to a charging efficiency equal to or higher than 90% of the maximum charging efficiency. | 2012-07-19 |
20120181993 | WIND TURBINE - A wind turbine includes a rotor, a permanent magnet generator and a generator converter, whereby an electric or electronic switch, which is arranged between the permanent magnet generator and the generator converter, is provided for selectively connecting the permanent magnet generator to at least one braking resistor. | 2012-07-19 |
20120181994 | BOOSTING SYSTEM, DIAGNOSING METHOD, AND COMPUTER READABLE MEDIUM STORING DIAGNOSING PROGRAM - The present invention provides a boosting system, a diagnosing method and a diagnosing program, that may diagnose a boosting section while suppressing consumption of electric power and current, and without being carrying out by a CPU. Namely, during an initializing operation, difference between power supply voltage and own threshold voltage charges capacitor C | 2012-07-19 |
20120181995 | VOLTAGE REGULATOR AND VOLTAGE REGULATION METHOD - A voltage regulator includes a voltage output unit configured to output an output voltage to a voltage output terminal; a first resistance divider configured to regulate a divided resistance value in response to a first series of control signals; and a second resistance divider configured to regulate the divided resistance value, which is determined in the first resistance divider, in response to a second series of control signals. A voltage level of the output voltage output through the voltage output terminal is regulated according to a ratio of the divided resistance value determined through the first resistance divider and the second resistance divider and a resistance value of a reference resistor. | 2012-07-19 |
20120181996 | MULTI CHIP MODULE, METHOD FOR OPERATING THE SAME AND DC/DC CONVERTER - A multi chip module having a current sensing circuit and a semiconductor half bridge configuration having two vertically stacked field effect transistor dies that are connected by horizontally extending tap clips at respective opposite sides of their channels, wherein the current sensing circuit is coupled to two checkpoints, at least one being located on one of the tap clips so as to measure a voltage drop over a predetermined portion of the tap clip acting as a shunt resistor for sensing a current that is provided to a switching node of the half bridge configuration. | 2012-07-19 |
20120181997 | METHOD AND SYSTEM FOR HYSTERESIS CONTROL OF A POWER CIRCUIT - A device for providing electric power to a load, having two switch members (Z | 2012-07-19 |
20120181998 | ENHANCED EFFICIENCY LOW-DROPOUT LINEAR REGULATOR AND CORRESPONDING METHOD - A low-dropout linear regulator includes an error amplifier which includes a cascaded arrangement of a differential amplifier and a gain stage. The gain stage includes a transistor driven by the differential amplifier to produce at a drive signal for an output stage of the regulator. The transistor is interposed over its source-drain line between a first resistive load included in a RC network creating a zero in the open loop gain of the regulator, and a second resistive load to produce a drive signal for the output stage of the regulator. The second resistive load is a non-linear compensation element to render current consumption linearly proportional to the load current to the regulator. The first resistive load is a non-linear element causing the frequency of said zero created by the RC network to decrease as the load current of the regulator decreases. | 2012-07-19 |
20120181999 | High accuracy inductor peak current control scheme for switching power supply - The invention is composed of peak current generator, peak current detector, peak current error amplifier and compensator, peak current controller and MOSFET driver. The advantage of the invention is to control switching converter's inductor peak current in high accuracy. The invention can automatically compensate error due to inductor current rising slope, the delay times Td, Tp of comparator and driver and comparator's offset voltage. The invention can largely decrease performance requirements of comparator and driver circuit and help to down the cost to implement the system. | 2012-07-19 |
20120182000 | SOFT START CIRCUIT - There is provided a soft start circuit including: a resonator generating a resonant voltage; a voltage detector detecting an output voltage of a power converter; a reference voltage selector selecting one of a voltage detected by the voltage detector and the resonant voltage as a reference voltage, based on a driving signal for turning the power converter on or off; and an error amplifier generating a control signal for controlling the output voltage of the power converter from the reference voltage selected by the reference voltage selector and the voltage detected by the voltage detector. The soft start circuit is capable of preventing semiconductor devices of the power converter from being burned out and preventing overshooting of the output voltage. | 2012-07-19 |
20120182001 | LOW INPUT VOLTAGE BOOST CONVERTER OPERABLE AT LOW TEMPERATURES AND BOOST CONTROLLER THEREOF - A low input voltage boost converter operable at low temperatures, comprising a boost controller and an NMOS transistor. The boost controller has a driver unit, a first inverter circuit, a second inverter circuit, and a comparator circuit, wherein the first inverter circuit is used to enhance the high level of a switching signal during a startup period. | 2012-07-19 |
20120182002 | POWER SUPPLY CONTROLLER HAVING ANALOG TO DIGITAL CONVERTER - A power supply controller includes a switching circuit which, in response to a control signal, transfers an analog signal to an output node as an outputted analog signal, the output node being coupled to an inductor and a capacitor, an analog to digital (A/D) converter which converts an outputted analog signal to a digital signal, a pulse width modulation (PWM) generator circuit which produces a PWM signal based on the digital signal, a driver which produces the control signal in response to the PWM signal, and a conversion range setting unit which sets a range data for the A/D converter based on the digital signal during a first period, and which sets the range data based on the PWM signal during a second period. | 2012-07-19 |
20120182003 | System and Method for Controlling a Switched-Mode Power Supply - In an embodiment, a method of operating a switched-mode power supply includes producing an error signal based on a difference between a power supply output voltage and a reference voltage. A clock frequency is produced that is proportional to the error signal up to maximum frequency, and a sensed current signal is produced that is proportional to a current in switched-mode power supply. The error signal is summed with the sensed current signal to produce a first signal, and the first signal is compared to a first threshold. The method also includes producing a first edge of a drive signal at a first edge of the clock signal, and producing a second edge of the drive signal when the first signal crosses the first threshold in a first direction based on the comparing, where the second edge opposite the first edge. | 2012-07-19 |
20120182004 | POWER SUPPLY CONTROLLER - A power supply controller includes a switch circuit to be provided between the power source and power supply path, the switch circuit switches the power supply from the power source to the load between on and off, and a power-supply-path protection circuit. The power-supply-path protection circuit controls switching operation of the switch circuit according to a power-supply command signal that commands to start or terminate the power supply to the load, to calculate a temperature of the power-supply path, and if the calculated temperature reaches a predetermined upper limit, to inhibit the switch circuit from the power supply, thereby protecting the power-supply path. In a case where the power supply by the switch circuit is inhibited, if the temperature of the power supply path decreases to a predetermined threshold temperature, the power-supply-path protection circuit removes inhibition of the power supply by the switch circuit. | 2012-07-19 |
20120182005 | VOLTAGE CONTROL DEVICE FOR A FUEL CELL - The invention relates to a device for controlling the voltage of a cell of a fuel cell, characterized in that said control device comprises a first transistor (Q | 2012-07-19 |
20120182006 | ADVANCED METERING INFRASTRUCTURE (AMI) CARTRIDGE FOR AN ENERGY METER - An advanced metering infrastructure (AMI) cartridge includes an AMI cartridge housing having an interior zone, and an AMI module system supported within the interior zone of the AMI cartridge module housing. The AMI module system includes an AMI module and an energy meter interface configured and disposed to detachably connect to an energy meter. | 2012-07-19 |
20120182007 | FLOW CHAMBER HAVING A GMR SENSOR AND A CELL GUIDING DEVICE - Magnetically labeled cells in a flow chamber cytometer are detected by a GMR sensor. The flow chamber includes a cell guiding device having at least one first and one second magnetic or magnetizable flow strip. The flow strips, which serve to guide the flowing cells across the sensor in a target-oriented manner, are mounted at a distance from each other such that a magnetic field B | 2012-07-19 |
20120182008 | ROTATION ANGLE DETECTING DEVICE - Three magnetic sensors are arranged around a rotor at predetermined angular intervals about the rotation axis of the rotor. Sinusoidal signals that have a phase difference of a predetermined degree of 45° are output from the respective magnetic sensors. A rotation angle computing device detects a magnetic pole transition in a first output signal as follows. Specifically, the rotation angle computing device detects a magnetic pole transition in the first output signal based on a value having a larger absolute value between a current value of the second sinusoidal signal and a current value of the third sinusoidal signal, an immediately preceding value of the first sinusoidal signal and a current value of the first sinusoidal signal. | 2012-07-19 |
20120182009 | ROTATION ANGLE DETECTING DEVICE - Three magnetic sensors are arranged around a rotor at predetermined angular intervals about the rotation axis of the rotor. Sinusoidal signals having a phase difference of 120° are output from the magnetic sensors. A rotation angle computing device detects a magnetic pole transition in a first output signal as follows. The rotation angle computing device detects a magnetic pole transition in the first output signal based on a current value of one of the second and third sinusoidal signals, an absolute value of a difference between an immediately preceding value and the current value of the one of the second and third sinusoidal signals being larger than an absolute value of a difference between an immediately preceding value and the current value of the other of the second and third sinusoidal signals, an immediately preceding value of the first sinusoidal signal and a current value of the first sinusoidal signal. | 2012-07-19 |
20120182010 | MAGNETIC FIELD SENSOR - A magnetic field sensor for measuring a magnetic field at a sensor location has a printed circuit board, including electrically insulating material; a magnetic field sensor element situated on the printed circuit board and connected via electrical contacts to first printed conductors provided on the printed circuit board; and at least one second printed conductor for generating a test magnetic field, the second printed conductor being provided on the printed circuit board and generating a predetermined test magnetic field when a calibration current is applied at the sensor location. | 2012-07-19 |
20120182011 | PHASE DETECTION IN AN ATOMIC SENSING SYSTEM - One embodiment of the invention includes an atomic sensing system. The system includes an atomic sensing device configured to generate an output signal along an output axis in response to a plurality of control parameters. The system also includes a signal generator configured to apply a reference signal to a cross-axis that is approximately orthogonal to the output axis. The system also includes a phase measurement system configured to demodulate the output signal relative to the reference signal to measure a relative phase alignment between the output axis and a physical axis of the atomic sensing device based on the reference signal. | 2012-07-19 |
20120182012 | APPARATUS AND METHOD FOR PROTECTING A MAGNETIC RESONANCE IMAGING MAGNET DURING QUENCH - A superconducting magnet assembly comprising a plurality of superconducting magnet coil portions forming a coil series circuit to provide a magnetic field, a power supply to supply power to the plurality of superconducting magnet coil portions during a magnet ramp mode of operation, and a ramp switch coupled to the superconducting magnet coil portions, wherein the ramp switch is configured to be open during a magnet ramp mode and closed during a persistent mode. A dump resistor is disposed externally to the vessel and is connectable by the ramp switch to the superconducting magnet coil portions. Further, a controller is coupled to at least one superconducting magnet coil portion and the ramp switch and is configured to detect a quench onset condition in the at least one superconducting magnet coil portion and to open the ramp switch upon detection of the quench onset condition in order to dump magnet energy. | 2012-07-19 |
20120182013 | ANTENNA ARRANGEMENT FOR MAGNETIC RESONANCE APPLICATIONS - An antenna arrangement for magnetic resonance applications includes antenna elements substantially parallel to a common central axis, distributed around the central axis at a distance from the central axis, and enclosing an essentially cylindrical volume. The antenna arrangement includes intermediate connections that connect to immediately adjacent antenna elements at connection points that lie between the ends of the antenna elements. A preamplifier connects to each of the intermediate connections and has an output that, in a receive mode, corresponds to a respective feed-out point. In send mode, the antenna arrangement injects radio-frequency signals into the antenna elements using the injection points. The antenna arrangement is also configured to adjust the intermediate connections to a higher resistance when the antenna arrangement is in the send mode and at least some of the intermediate connections to a lower resistance when the antenna arrangement is in the receive mode. | 2012-07-19 |
20120182014 | MAGNETIC RESONANCE MICROCOIL AND METHOD OF USE - A magnetic resonance imaging device includes an elongate flexible member having a proximal end, a distal end, and a lumen extending between the proximal end and the distal end and a solenoid coil affixed to the distal end of the elongate flexible member, the solenoid coil having a plurality of wire turns, the solenoid coil connected to a twisted-pair of leads extending proximally along the length of the flexible member. A connector is disposed at the proximal end of the elongate flexible member, the connector operatively coupled to the twisted-pair of leads. In an alternative embodiment, a coaxial cable substitutes for the lumen-containing elongate flexible member. | 2012-07-19 |
20120182015 | DRUM-TYPE STANDING WAVE TRAP - A standing wave trap for a magnetic resonance tomography system includes a local coil connecting lead and at least one flexible printed circuit board in the local coil connecting lead. The local coil connecting lead is wound. | 2012-07-19 |
20120182016 | SENSOR DEVICE AND METHOD FOR THE GEOELECTRICAL PROSPECTING OF RAW MINERAL DEPOSITS - A sensor device and a method for the geoelectrical prospecting of the location, the (stratographic) arrangement, and the course of raw mineral deposits and of the adjoining rock delimiting these deposits, particularly in the continuous working of the mineral deposits, having a sensor head whose front surface forms the sensor measuring surface, and at least one electrode. The sensor head can make contact with a ground surface, and a central electrode and a plurality of outer electrodes distributed geometrically uniformly around the central electrode are arranged on the sensor measuring surface, the central electrode and the outer electrodes being electrically conductive and electrically separated from one another. | 2012-07-19 |
20120182017 | Subsurface electromagnetic survey technique using expendable conductivity, temperature, and depth measurement devices - A method for modeling conductivity distribution in a formation below a body of water includes measuring electromagnetic response of the formation with an electromagnetic survey system; measuring at least one of water conductivity, water dielectric constant, and water temperature with respect to depth in the water; generating an initial model of conductivity distribution of the formation; discretizing the measurements of at least one of water conductivity, water dielectric constant, and water temperature with respect to depth into at least one layer; generating a forward model of a response of the electromagnetic survey system to the initial model and the discretized measurements; comparing the forward model to the measured electromagnetic response to determine differences; adjusting the initial model to reduce the differences; and repeating generating a forward model, comparing the forward model to the measured electromagnetic response, and adjusting the initial model until the differences fall below a selected threshold. | 2012-07-19 |
20120182018 | APPARATUS AND METHOD FOR SENSING FAILURE - Provided is an apparatus for sensing a failure that may apply, using a current control unit, a current to at least one first light emitting diode (LED) string and at least one second LED string that may be connected in parallel with each other, and as a result of sensing whether a failure occurs with respect to each of the at least one first LED string and the at least one second LED string, when a failure is sensed with respect to at least one of the at least one first LED string and the at least one second LED string, may transmit failure information to the current control unit, thereby blocking the entire current that may be applied to the at least one first LED string and the at least one second LED string, using the current control unit. | 2012-07-19 |
20120182019 | BATTERY MONITORING CIRCUIT AND BATTERY MONITORING SYSTEM - A battery monitoring circuit monitors voltages of a plurality of secondary cells connected in series. The battery monitoring circuit comprises a first switch element, a second switch element, a third switch element, and a first capacitor. The battery monitoring circuit comprises an operational amplifier of which an inverting input terminal is connected to a second end of the first capacitor, a non-inverting input terminal is connected to a fixed potential, and an output is connected to the second end of the first capacitor. The battery monitoring circuit comprises an A/D converter which performs analog-to-digital conversion on a signal output by the operational amplifier and outputs an obtained digital signal. The battery monitoring circuit comprises a control circuit which performs on/off control on the first to third switch elements and controls operations of the operational amplifier and the A/D converter. | 2012-07-19 |
20120182020 | SECONDARY BATTERY TESTER, SECONDARY BATTERY TESTING METHOD, AND MANUFACTURING METHOD OF SECONDARY BATTERY - There is provided a secondary battery tester for testing a state of a secondary battery based on an impedance characteristic of the secondary battery. The tester includes: an impedance acquiring section configured to acquire an impedance value of the secondary battery; and a determining section configured to determine a state of a solid electrolyte interface (SEI) layer of the secondary battery based on the impedance value acquired by the impedance acquiring section. | 2012-07-19 |
20120182021 | DIFFERENTIAL CURRENT MONITORING FOR PARALLEL-CONNECTED BATTERIES - A system for determining battery characteristics based on differential current monitoring includes a first battery; a second battery, the second battery being connected in parallel with the first battery; and a differential current measurement module comprising at least one current measuring device, the differential current measurement module being configured to determine a differential current associated with the first battery and the second battery. A method for determining battery characteristics based on differential current monitoring includes determining a differential current associated with a first battery and a second battery, the first battery being connected in parallel with the second battery. | 2012-07-19 |
20120182022 | METHOD OF INDICATING VOLTAGE, VOLTAGE INDICATING APPARATUS, AND BATTERY PACK - One terminal of a switch | 2012-07-19 |
20120182023 | METHOD FOR LOCATING FAULT OF SUBMARINE CABLE, REPEATER, AND COMMUNICATION SYSTEM - A method for locating a fault of a submarine cable, a device, and a communication system are provided. A light pulse output by a Repeater (RPT) is incident to a location of a fault as a probe light pulse. The RPT obtains a time difference between the probe light pulse and the reflected probe light pulse, and sends the time difference to a terrestrial Submarine Line Terminal Equipment (SLTE) so that the SLTE may easily locate the fault according to principles of an Optical Time Domain Reflector (OTDR). Compared with the prior art, the method may locate the fault of the submarine cable more quickly and accurately, so that maintainers may maintain the submarine cable in time. | 2012-07-19 |
20120182024 | GROUND FAULT DETECTION CIRCUIT AND GROUND FAULT DETECTION APPARATUS - A ground fault detection circuit includes: a first switch circuit that connects/disconnects a first path between a positive bus bar and a ground potential section, the positive bus bar being connected to positive electrodes of secondary battery units through a field-effect transistor including a parasitic diode; a second switch circuit that connects/disconnects a second path between a negative bus bar and a ground potential section, the negative bus bar being connected to negative electrodes of the secondary battery units; and a ground fault detection unit that detects a ground fault of the positive bus bar or the negative bus bar based on an electric current flowing through the first path or the second path. | 2012-07-19 |
20120182025 | Optically Stimulated Differential Impedance Spectroscopy - Methods and apparatuses for evaluating a material are described. Embodiments typically involve use of an impedance measurement sensor to measure the impedance of a sample of the material under at least two different states of illumination. The states of illumination may include (a) substantially no optical stimulation, (b) substantial optical stimulation, (c) optical stimulation at a first wavelength of light, (d) optical stimulation at a second wavelength of light, (e) a first level of light intensity, and (f) a second level of light intensity. Typically a difference in impedance between the impedance of the sample at the two states of illumination is measured to determine a characteristic of the material. | 2012-07-19 |
20120182026 | CLOCK GENERATING APPARATUS, TEST APPARATUS AND CLOCK GENERATING METHOD - There is provided a clock generating apparatus for generating a recovered clock by recovering a clock from an edge of a received signal, including a recovered clock generating section that generates the recovered clock, a multi-strobe generating section that generates a plurality of strobes with different phases, in accordance with a pulse of the recovered clock, a detecting section that detects a position of an edge of the received signal relative to the strobes, by referring to values of the received signal obtained at respective timings of the strobes, and an adjusting section that adjusts a phase of the recovered clock, in accordance with the position of the edge of the received signal. | 2012-07-19 |
20120182027 | MEASURING ARRANGEMENT FOR DETERMINING ELECTRICAL CONDUCTIVITY OF A MEASURED LIQUID - A measuring arrangement for determining electrical conductivity of a measured liquid, comprising: a container, in which the measured liquid is accommodated, a gradiometer arrangement, comprising an exciter coil, a first receiving coil and a second receiving coil, wherein the first and the second receiving coils are arranged symmetrically relative to the exciter coil, and a measurement circuit embodied to excite the exciter coil for producing an alternating magnetic field passing through the first receiving coil, the second receiving coil and the measured liquid. The receiving coils are influenced in different manner by the magnetic field induced by the alternating magnetic field in the measured liquid and directed counter to the alternating magnetic field. The measurement circuit is furthermore embodied to register an electrical signal of the receiving coils and to derive from such the electrical conductivity of the liquid. | 2012-07-19 |
20120182028 | CAPACITANCE DETECTING DEVICE - In a capacitance detecting device including an offset adjustment circuit for removing offset from charge transmitted to an integrator from a charge reading mechanism, the offset adjustment circuit includes a variable capacitance element switching the number of capacitative elements connected in parallel to a charge transmission line made up of a plurality of the capacitative elements and setting the number to a predetermined capacitance value; and a capacitative element for adjustment connected in parallel to the variable capacitance element and parallel, and having a capacitance value corresponding to the minimum value of the capacitative elements constituting the variable capacitance element. Driving is controlled so that offset removal is performed only N times (M>N; M and N are natural numbers) in the capacitative element for adjustment while offset removal is repeated M times in the variable capacitance element. | 2012-07-19 |
20120182029 | Apparatus and Method for Monitoring a Tool Machine - The invention refers to an apparatus for monitoring the operation of an electrically conductive tool ( | 2012-07-19 |
20120182030 | Device for the Measurement of Electrical Properties of Fluids and Method for Measuring Said Electrical Properties | 2012-07-19 |
20120182031 | Test apparatus and test method - Provided is a test apparatus that tests a device under test, comprising an inductance load section that is provided in a path through which test current flows to the device under test and that has an inductance component; a switching section that switches whether the test current is supplied to the device under test from the inductance load section; a cut-off control section that severs the path by switching the switching section according to a state of the device under test; and a voltage control section that controls voltage of the path between the inductance load section and the switching section to be no greater than a predetermined clamp voltage. | 2012-07-19 |
20120182032 | TEST MODE CONTROLLER AND ELECTRONIC APPARATUS WITH SELF-TESTING THEREOF - A test mode controller comprises an enable signal generator, a control signal generator, and a latch. The enable signal generator receives a power signal and a second control signal, and generates a first enable signal and a second enable signal respectively to the latch and the control signal generator. The control signal generator receives a power indicating voltage and a reference voltage, and generates the first control signal to the latch when the first enable signal is enabled. The latch receives the first control signal, and generates the second control signal according to the first control signal when the second enable signal is enabled. The second control signal controls a chip to operate in a test mode or a normal mode. Accordingly, the test mode controller may reduce the test time without a test pin, and may also reduce the chip area and the package cost. | 2012-07-19 |
20120182033 | DIE TESTING USING TOP SURFACE TEST PADS - Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size. | 2012-07-19 |
20120182034 | CONTACT ASSEMBLY - A contact assembly for receiving a spring probe unit includes an elongate contact element adapted to electrically contact the spring probe unit. The contact element includes a stop for restraining movement of the spring probe unit towards the stop in the direction of an axis along the length of the contact element, and urging means, adapted to urge the spring probe unit against the contact element for removable engagement of the spring probe unit with the contact element. | 2012-07-19 |
20120182035 | BUMPED SEMICONDUCTOR WAFER OR DIE LEVEL ELECTRICAL INTERCONNECT - A probe assembly that acts as a temporary interconnect between terminals on an IC device and a test station. The probe assembly includes a plurality of stud bumps arranged on a first surface of a substrate in a configuration corresponding to the terminal on the IC device. The stud bumps include a shape adapted to temporarily couple with the terminals on the IC device. A plurality of conductive traces on the substrate electrically couple the stud bumps with the test station. | 2012-07-19 |
20120182036 | CONTACT PROBE AND SOCKET - A contact probe includes: a first and second plungers, one of the first and second plungers being connected to an object to be inspected, the other being connected to an inspecting board; and a spring urging the first and second plungers so as to be separated from each other. The first plunger includes a distal end side columnar part and a flange part. The flange part includes a first portion that has a first length from a center point, which is, greater than a radius of the distal end side columnar part, in a first direction perpendicular to an axial direction, and includes a second portion that has a second length from the center point, which is smaller than the radius of the distal end side columnar part, in a second direction perpendicular to the axial direction and different from the first direction. | 2012-07-19 |
20120182037 | IC DEVICE TESTING SOCKET - To provide an IC device testing socket, capable of improving signal transmission efficiency during testing an IC device, without deteriorating the replacement workability of contact pins. A substrate | 2012-07-19 |
20120182038 | Characterization of Electrical Power Distribution Systems Using Characterization Matrices - Embodiments of methods and apparatuses for characterizing an electrical power distribution system are disclosed. One method includes applying a plurality of test signals to a first plurality of test points of the electrical power distribution system, measuring a plurality of response signals at a second plurality of test points of the electrical distribution system, deriving a characterization matrix for the electrical power distribution system from the plurality of test signals and response signals, and characterizing the electrical power distribution system based on the derived characterization matrix. | 2012-07-19 |
20120182039 | SYSTEMS AND METHODS FOR TESTING POWER SUPPLIES - A system and method for testing a power supply. A selection of one or more power supplies to test is received. A tester is automatically configured to test the one or more power supplies utilizing test parameters associated with the selection. A power-end of each of the one or more power supplies is received in power ports of the tester. An adapter-end of each of the one or more power supplies is received in adapter ports of the tester. The one or more power supplies are automatically tested utilizing test parameters. Performance characteristics of the loop one or more power supplies are measured during testing. Indications are given whether each of the one or more power supplies past the testing. | 2012-07-19 |
20120182040 | METHOD OF TESTING PARTIAL DISCHARGE OF ROTATING ELECTRICAL MACHINE DRIVEN BY INVERTER - In a rotating electrical machine, a conductive foil or conductive rubber is applied to the surface of insulation layer of a conductor series connection area or to the surface of insulation layer of a turn conductor of coils of rotating electrical machine winding, waveforms of grounding voltages of the individual turn conductor portions are measured through the medium of an electrostatic capacitance of the insulation layer of coil conductor series connection area or through the medium of the insulation layer of coil turn conductor, and a partial discharge is measured while measuring a voltage developing in the coil or across a winding turn in the coil from a difference between the waveforms of grounding voltages. | 2012-07-19 |
20120182041 | Method for supporting a tie of a chip to an electronic apparatus - A method for supporting a tie of a chip to an electronic apparatus includes generating once a chip-specific characteristic variable in a chip, reading out the chip-specific characteristic variable by the chip, and transmitting characteristic data representing the read-out characteristic variable of the chip to an electronic apparatus. | 2012-07-19 |
20120182042 | SEMICONDUCTOR APPARATUS, METHOD FOR ASSIGNING CHIP IDS THEREIN, AND METHOD FOR SETTING CHIP IDS THEREOF - A semiconductor apparatus having first and second chips includes a first operation unit disposed in the first chip, and is configured to perform a predetermined arithmetic operation for an initial code according to a first repair signal and generate a first operation code; and a second operation unit disposed in the second chip, and configured to perform the predetermined arithmetic operation for the first operation code according to a second repair signal and generate a second operation code. | 2012-07-19 |
20120182043 | Method of Half-Bit Pre-Emphasis for Multi-Level Signal - Methods and apparatus for improving transmission channel efficiency are provided. In an example, a digital signal is received. A leading portion of a bit in the digital signal is pre-emphasized. The received digital signal is modulated with a pre-emphasis signal to pre-emphasize a leading portion of the bit in the digital signal. The pre-emphasis signal provides pre-emphasis substantially when a clock is high and the received digital signal transitions. The pre-emphasis signal does not provide pre-emphasis when the received digital signal is low or the received digital signal is unchanged. The pre-emphasized digital signal is then transmitted via the transmission channel. In an example, the received digital signal us a pulse-amplitude modulated multilevel signal. | 2012-07-19 |
20120182044 | Methods and Systems for Reducing Supply and Termination Noise - Described is a communication system in a first integrated circuit (IC) communicates with a second IC via single-ended communication channels. A bidirectional reference channel extends between the first and second ICs and is terminated on both ends. The termination impedances at each end of the reference channel support different modes for communicating signals in different directions. The termination impedances for the reference channel can be optimized for each signaling direction. | 2012-07-19 |
20120182045 | Method for the creation of an electronic signal box replacing an existing signal box - According to one aspect of the invention, the circuit logic of an existing relay interlocking system is mapped onto a functionally equivalent circuit of electronic components. Semiconductor components that are functionally identical to the components of the relay circuit are thus preferably used. The circuit logic is created, for example, by transforming an interlocking table or track diagram into a logic circuit by means of an automatic compiler according to predefined rules. | 2012-07-19 |
20120182046 | TIMING OPERATIONS IN AN IC WITH CONFIGURABLE CIRCUITS - Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs. | 2012-07-19 |
20120182047 | SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM - A semiconductor integrated circuit has: N input terminals; N output terminals; a plurality of flip-flops including N flip-flops and R redundant flip-flops; a selector section configured to select N selected flip-flops from the plurality of flip-flops depending on reconfiguration information and to switch data flow such that data input to the N input terminals are respectively output to the N output terminals by the N selected flip-flops; and an error detection section. At a test mode, the N flip-flops form a scan chain and a scan data is input to the scan chain. The error detection section detects an error flip-flop included in the N flip-flops based on scan input/output data respectively input/output to/from the N flip-flops at the test mode and further generates the reconfiguration information such that the detected error flip-flop is excluded from the N selected flip-flops. | 2012-07-19 |
20120182048 | RADIATION HARDENED CIRCUIT DESIGN FOR MULTINODE UPSETS - This invention relates to Multiple Interlocked Cells (MICE) design as a hardening technique for CMOS logic gates consisting of two or more redundant nodes with node isolation components. This technique is used to modify existing standard CMOS logic gates or create new complex logic gates using common mask layers existing at ultra-deep sub-micron CMOS foundries. For single node upset immunity in logic or register, a primary cell and a redundant cell are used. For multi-node immunity, the primary cell is combined with two or more redundant nodes are used with physical layout spacing techniques which will insure that a single particle track cannot upset all three nodes simultaneously, and logic circuits built using this technique are immune to upsets in any environment. Circuits built using the MICE technique are also immune to single event transients without requiring the large time delays used in other hardening techniques. | 2012-07-19 |
20120182049 | System and Method for Driving a Switch Transistor - In an embodiment, a method of driving a switch transistor includes activating the switch transistor by charging a control node of the switch transistor at a first charging rate for a first time duration. After charging the control node of the switch transistor at the first charging rate, the control node of the switch transistor is further charged at a second charging rate until the control node of the switch transistor reaches a target signal level, where the second charging rate is less than the first charging rate. | 2012-07-19 |
20120182050 | GATE DRIVING CIRCUIT AND DISPLAY DEVICE INCLUDING THE SAME - Embodiments may be directed to a gate driving circuit. The gate driving circuit includes a pre-charge unit, a pull-up unit, a boosting unit, and a discharge unit. The pre-charge unit pre-charges a first node in response to a first input signal. The pull-up unit outputs a first clock signal as a gate driving signal in response to a first node signal of the first node. The boosting unit boosts the first node signal of the first node in response to the first node signal and the first clock signal. The discharge unit discharges the first node to a gate-off voltage level in response to a second input signal and a second clock signal. | 2012-07-19 |
20120182051 | DRIVING CIRCUIT FOR TRANSISTOR - A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a conduction state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector. | 2012-07-19 |
20120182052 | Device for providing electrical signals with high immunity to noise - Device for providing electrical signals with high immunity to noise. The invention develops a device for processing electrical signals ( | 2012-07-19 |
20120182053 | HALF CYCLE DELAY LOCKED LOOP - An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay introduced by the N delay elements is M/2. The integrated circuit also includes a plurality of inverters, each coupled to an output of one of the N delay elements, where the plurality is less than N. The integrated circuit also includes a phase detector coupled to the input node and an inverted Nth phase-shifted signal. The integrated circuit also includes a charge pump coupled to the phase detector and the delay elements. | 2012-07-19 |
20120182054 | PROGRAMMABLE RING OSCILLATOR USED AS A TEMPERATURE SENSOR - A method of programming a ring oscillator for use as a temperature sensor comprises selecting an initial number of delay elements for use in a ring oscillator. The method further comprise starting a system clock counter and counting pulses of the ring oscillator until the system clock counter reaches a programmed value. The method also comprises determining whether a number of counted ring oscillator pulses is between lower and upper count thresholds and changing the number of delay elements for the ring oscillator as a result of the number of counted ring oscillator pulses being less than the lower count threshold or greater than the upper count threshold. | 2012-07-19 |
20120182055 | FLOP TYPE SELECTION FOR VERY LARGE SCALE INTEGRATED CIRCUITS - A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC. | 2012-07-19 |
20120182056 | LOW ENERGY FLIP-FLOPS - Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes. | 2012-07-19 |
20120182057 | POWER SUPPLY INDUCED SIGNAL JITTER COMPENSATION - Examples of circuits and methods for compensating for power supply induced signal jitter in path elements sensitive to power supply variation. An example includes a signal path coupling an input to an output, the signal path including a delay element having a first delay and a bias-controlled delay element having a second delay. The first delay of the delay element exhibits a first response to changes in power applied thereto and the second delay of the bias-controlled delay element exhibits a second response to changes in the power applied such that the second response compensates at least in part for the first response. | 2012-07-19 |
20120182058 | NEGATIVE CHARGE PUMP - A charge pump includes a first node configured to receive a first voltage and a second node coupled to the first node through a first transistor. The second node is configured to output a voltage having a greater voltage magnitude than the first voltage. A first capacitor is coupled to a third node, and a fourth node is configured to receive a first clock signal. The third node is disposed between a drain of the first transistor and the fourth node. A leaky circuit device is coupled in parallel with the first capacitor for draining charges of a first polarity away from the second node. | 2012-07-19 |
20120182059 | SEAMLESS COARSE AND FINE DELAY STRUCTURE FOR HIGH PERFORMANCE DLL - A clock synchronization system and method avoids output clock jitter at high frequencies and also achieves a smooth phase transition at the boundary of the coarse and fine delays. The system may use a delay line configured to generate two intermediate clocks from the input reference clock and having a fixed phase difference therebetween. A phase mixer receives these two intermediate clocks and generates the final output clock having a phase between the phases of the intermediate clocks. The shifting in the delay line at high clock frequencies does not affect the phase relationship between the intermediate clocks fed into the phase mixer. The output clock from the phase mixer is time synchronized with the input reference clock and does not exhibit any jitter or noise even at high clock frequency inputs. Because of the rules governing abstracts, this abstract should not be used to construe the claims. | 2012-07-19 |
20120182060 | NEGATIVE VOLTAGE LEVEL SHIFTER CIRCUIT - A negative voltage level shifter circuit includes a pair of input transistors, a gate of each input transistor being driven by one of an input signal and an inverted version of the input signal, a cascode sub-circuit coupled to the pair of input transistors, and a pair of cross-coupled transistors for locking a state of the voltage level shifter depending on the input signal, wherein respective gates of the cross-coupled transistors are driven by outputs of respective comparator sub-circuits. | 2012-07-19 |
20120182061 | RADIO-FREQUENCY SWITCH CIRCUIT - A radio-frequency switch circuit of the invention includes: n-stage through FETs (field effect transistors) connected in series between the antenna terminal and each of the radio-frequency terminals, where n is a natural number; a radio-frequency leakage prevention resistor connected to a gate of the through FETs; a control signal line commonly connected to the gates of the n-stage through FETs connected to the same radio-frequency terminal; and a resistor connected to each of at least two of the control signal lines and connected to the radio-frequency leakage prevention resistor in series The two control signal lines are capacitively coupled between the resistor and the through FETs. | 2012-07-19 |
20120182062 | TEMPERATURE SENSOR DEVICE - Provided is a temperature sensor device operable at a lower voltage. The temperature sensor device detects temperature based on an output voltage of a forward voltage generator for generating a forward voltage of a PN junction. The forward voltage generator includes a level shift voltage generation circuit, and an output voltage of the temperature sensor device is given based on the forward voltage of the PN junction and a voltage of the level shift voltage generation circuit. | 2012-07-19 |
20120182063 | Power Device Using Photoelectron Injection to Modulate Conductivity and the Method Thereof - The present invention belongs to the technical field of semiconductor devices, and discloses a power device using photoelectron injection to modulate conductivity and the method thereof. The power device comprises at least one photoelectron injection light source and a power MOS transistor. The present invention uses photoelectron injection method to inject carriers to the drift region under the gate of the power MOS transistor, thus modulating the conductivity and further decreasing the specific on-resistance of the power MOS transistor. Moreover, as the doping concentration of the drift region can be decreased and the blocking voltage can be increased, the performance of the power MOS transistor can be greatly improved and the application of power MOS transistor can be expanded to high-voltage fields. | 2012-07-19 |
20120182064 | VOLTAGE CHARACTERISTIC REGULATING METHOD OF LATCH CIRCUIT, VOLTAGE CHARACTERISTIC REGULATING METHOD OF SEMICONDUCTOR DEVICE, AND VOLTAGE CHARACTERISTIC REGULATOR OF LATCH CIRCUIT - The voltage Vdd is set to be lower than in the normal operation (step S | 2012-07-19 |
20120182065 | RESISTIVE DIVIDER CIRCUIT AND VOLTAGE DETECTION CIRCUIT - A resistive divider circuit capable of preventing an increase in trimming error under a particular condition by eliminating the effects of on resistances of switch elements, and a voltage detection circuit of high precision are provided. The resistive divider circuit includes a plurality of resistance elements connected in series, the resistance elements having weighted resistance values, and switch elements connected in parallel with the respective resistance elements, where it is configured such that ratios between the resistance values of the resistance elements and resistance values of the corresponding switch elements in a shorted state are constant. | 2012-07-19 |
20120182066 | METHOD OF MANUFACTURING A PACKAGE FOR EMBEDDING ONE OR MORE ELECTRONIC COMPONENTS - The present invention relates to the field of integrating electronic systems that operate at mm-wave and THz frequencies. A monolithic multichip package, a carrier structure for such a package as well as manufacturing methods for manufacturing such a package and such a carrier structure are proposed to obtain a package that fully shields different functions of the mm-wave/THz system. The package is poured into place by polymerizing photo sensitive monomers. It gradually grows around and above the MMICs (Monolithically Microwave Integrated Circuit) making connection to the MMICs but recessing the high frequency areas of the chip. The proposed approach leads to functional blocks that are electromagnetically completely shielded. These units can be combined and cascaded according to system needs. | 2012-07-19 |
20120182067 | SWITCHED-CAPACITOR PROGRAMMABLE-GAIN AMPLIFIER - A programmable-gain amplifier has a first input node coupled to receive a first input signal and a control input coupled to receive a gain select signal. The programmable-gain amplifier includes a differential amplifier having a first input and a first output and a plurality of capacitors. A first terminal of each of the plurality of capacitors is coupled to the first input of the differential amplifier, and a second terminal of each of the plurality of capacitors is coupled to the first input node during a sampling phase of the programmable-gain amplifier and selectively coupled to the first output of the differential amplifier, based on the gain select signal, during a gain phase of the programmable-gain amplifier. | 2012-07-19 |
20120182068 | DC OFFSET TRACKING CIRCUIT - This document discusses, among other things, an amplifier circuit including first and second amplifiers configured to receive an input signal and to provide a differential output signal using a feedback loop including a transconductance amplifier. A non-inverting input of a first amplifier can be configured to receive an input signal. The feedback loop can be configured to receive the outputs from the first and second amplifiers and to provide a feedback signal to the non-inverting input of the second amplifier, for example, to reduce a DC offset error or to increase a dynamic range of the amplifier circuit. | 2012-07-19 |
20120182069 | AMPLIFIER SYSTEM FOR A POWER CONVERTER - An amplifier system for a power converter includes at least a first switching device and a second switching device formed in an integrated circuit in a substrate of a semiconductor. The first and second switching devices may be formed in a half bridge configuration and may be cooperatively switchable to generate an amplified output signal on an output node of the semiconductor. A resistor and a capacitor may be coupled in parallel between a power supply input node and a substrate node included in the semiconductor. The capacitor may be selectively charged to a de-biasing voltage during a switching cycle of the first and second switching devices to reverse bias a parasitic switching device appearing in the integrated circuit. | 2012-07-19 |
20120182070 | OUTPUT STAGE FORMED INSIDE AND ON TOP OF AN SOI-TYPE SUBSTRATE - A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state. | 2012-07-19 |
20120182071 | OPERATIONAL AMPLIFIER CIRCUIT - An operational amplifier circuit may include a fully differential amplifier circuit that has a common mode feedback, the fully differential amplifier circuit performing operational amplification using a common mode base voltage as a center, a common mode detection circuit that detects a common mode output voltage of the fully differential amplifier circuit, a sample and hold circuit that performs sample and hold of an output of the common mode detection circuit, an operational circuit that detects a deviation between the output of the sample and hold circuit and a common mode reference voltage, the operational circuit outputting a voltage corresponding to the detected deviation and the common mode reference voltage, and a switching circuit that selects the common mode reference voltage or an output of the operational circuit to output the common mode reference voltage or the output as the common mode base voltage. | 2012-07-19 |
20120182072 | Self-Biasing Radio Frequency Circuitry - The present disclosure describes self-biasing radio frequency circuitry. In some aspects a radio frequency (RF) signal is amplified via a circuit having a first transistor configured to source current to an output of the circuit and a second transistor configured to sink current from the output of the circuit, and another signal is provided, without active circuitry, from the output of the circuit to a gate of the first transistor effective to bias a voltage at the output of the circuit. By so doing, the output of the circuit can be biased without active circuitry which can reduce design complexity of and substrate area consumed by the circuit. | 2012-07-19 |
20120182073 | Apparatus and Method for Programmable Power Management in a Programmable Analog Circuit Block - An apparatus and method for programmable power management in a programmable analog circuit block. Specifically, the present invention describes an operational amplifier circuit that includes current sources that are coupled in parallel. Configuration bits are asserted to selectively enable or selectively disable one or more of the current sources in order to modulate the performance of the operational amplifier circuit block. Selective addition or removal of current sources increases or decreases the amount of current within the operational amplifier and, correspondingly, the speed and power consumption of the operational amplifier. Combinations of asserted configuration bits pass a bias voltage in order enable selected current sources. In one embodiment, the bias voltage can be increased in order to increase the current output of one of the current sources which, correspondingly, increases the speed of the operational amplifier circuit block. | 2012-07-19 |
20120182074 | SINGLE DIE POWER AMPLIFIER WITH CLOSED LOOP POWER CONTROL - An apparatus on a single integrated circuit (IC) die includes a multiple stage power amplifier having at least first and second stages, a multiple stage voltage regulator for providing a regulated voltage signal to the at least first and second stages of the multiple stage power amplifier, a power coupler for providing a portion of a power output of the multiple stage power amplifier to a power detector, the power detector for developing a power detect signal, and a power control loop including at least the second stage and an output stage of the multiple stage power amplifier, the power coupler, the power detector, and at least one stage of the multiple stage voltage regulator, the power control loop controlling only the second stage and the output stage of the multiple stage power amplifier. | 2012-07-19 |
20120182075 | APPARATUS AND METHOD FOR MILLER COMPENSATION FOR MULTI-STAGE AMPLIFIER - An amplifier circuit includes a first amplifier stage having a first output node; a second amplifier stage having a second output node; and a compensation block electrically coupled between the first and second output nodes. The compensation block has a compensation capacitor electrically coupled to the first node and electrically connectable to the second node, and has an impedance electrically connectable to the compensation capacitor. The compensation capacitor is electrically coupled via a switch to the impedance such that the compensation capacitor can contribute a zero to shunt branch formed by the compensation capacitor and impedance when the compensation capacitor is disconnected from the second node. | 2012-07-19 |
20120182076 | LIMITER CIRCUIT AND VOLTAGE CONTROLLED OSCILLATOR INCLUDING THE SAME - A limiter circuit in a voltage controlled oscillator (VCO) includes a first control circuit, a second control circuit and a driving circuit having a pull-up transistor and a pull-down transistor. The first control circuit generates a first driving control signal for controlling the pull-up transistor based on an AC input signal and a first DC bias voltage. The second control circuit generates a second driving control signal for controlling the pull-down transistor based on the AC input signal and a second DC bias voltage. The driving circuit generates an output signal based on the first driving control signal and the second driving control signal. The output signal swings between a first voltage at the pull-up transistor and a second voltage at the pull-down transistor. | 2012-07-19 |
20120182077 | OSCILLATOR - A MEMS oscillator including: an oscillator unit being capable of outputting an output from an amplifier as an original oscillator signal that includes a feedback type oscillator circuit including a MEMS resonator and an amplifier, and an automatic gain controller receiving the output from the amplifier and controlling a gain of the amplifier based on a level of the output to maintain a level of the output from the amplifier constant; and a corrector unit that receives the original oscillator signal, that generates from the original oscillator signal a signal of a predetermined set frequency, and that outputs the generated signal of the predetermined set frequency as an output signal. The corrector unit receives, separately from the original oscillator signal, an information signal that includes a signal having a correspondence relationship between a gain at a resonance frequency of the MEMS resonator from the oscillator unit, corrects a frequency of the original oscillator signal based on the information signal to generate the signal of the predetermined set frequency, and outputs the generated signal of the predetermined set frequency as the output signal. | 2012-07-19 |
20120182078 | QUADRATURE VOLTAGE-CONTROLLED OSCILLATOR AND METHOD OF PROVIDING FOUR-PHASE OUTPUT SIGNALS - A quadrature VCO includes a first oscillator unit and a second oscillator unit. Each of the first and second oscillator unit is composed of a DC bias source, a complementary cross-coupled pair, an LC resonator unit, a frequency-doubling sub-harmonic coupler unit, and a ground terminal. When the LC resonator units of the first and second oscillator units are operated, four signals of different phases can be outputted via the output terminals. In this way, the output phase difference of the two oscillator units can keep 180 degrees and allow the two oscillator units to mutually inject signals to generate quadrature output signals. | 2012-07-19 |
20120182079 | MONITORING NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI) AND/OR POSITIVE BIAS TEMPERATURE INSTABILITY (PBTI) - A ring oscillator circuit for measurement of negative bias temperature instability effect and/or positive bias temperature instability effect includes a ring oscillator having first and second rails, and an odd number (at least 3) of repeating circuit structures. Each of the repeating circuit structures in turn includes an input terminal and an output terminal; a first p-type transistor having a gate, a first drain-source terminal coupled to the first rail, and a second drain source terminal selectively coupled to the output terminal; a first n-type transistor having a gate, a first drain-source terminal coupled to the second rail, and a second drain source terminal selectively coupled to the output terminal; and repeating-circuit-structure control circuitry. The ring oscillator circuit also includes a voltage supply and control block. | 2012-07-19 |