28th week of 2014 patent applcation highlights part 15 |
Patent application number | Title | Published |
20140191324 | METHODS OF FORMING BULK FINFET DEVICES BY PERFORMING A RECESSING PROCESS ON LINER MATERIALS TO DEFINE DIFFERENT FIN HEIGHTS AND FINFET DEVICES WITH SUCH RECESSED LINER MATERIALS - One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin. | 2014-07-10 |
20140191325 | Fin-Shaped Field Effect Transistor (FINFET) Structures Having Multiple Threshold Voltages (Vt) and Method of Forming - Various embodiments include fin-shaped field effect transistor (finFET) structures that enhance work function and threshold voltage (Vt) control, along with methods of forming such structures. The finFET structures can include a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET). In some embodiments, the PFET has fins separated by a first distance and the NFET has fins separated by a second distance, where the first distance and the second distance are distinct from one another. In some embodiments, the PFET or the NFET include fins that are separated from one another by non-uniform distances. In some embodiments, the PFET or the NFET include adjacent fins that are separated by distinct distances at their source and drain regions. | 2014-07-10 |
20140191326 | PHOTONICS DEVICE AND CMOS DEVICE HAVING A COMMON GATE - A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. | 2014-07-10 |
20140191327 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a memory cell array with memory cells, each including first and second conduction type transistors, column-side peripheral circuits disposed with the same row-direction interval as the memory cells, a first conduction type well region formed within the memory cell array, a second conduction type well region formed within the first conduction type well region and is disposed separately in the row direction, a second conduction type well contact region disposed extending in the row direction among the memory cells, a first conduction type well contact region disposed extending in the column direction among the memory cells, a column-side peripheral contact region, a first conduction type back gate voltage line connecting to the first conduction type well region; and a second conduction type back gate voltage line connecting to the second conduction type well. | 2014-07-10 |
20140191328 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a memory cell array having memory cells, each including first and second conduction type transistors, a peripheral circuit having the first and second conduction type transistors, a first conduction type memory cell array well region within the memory cell array region, a second conduction type memory cell array well region within the first conduction type memory cell array well region, a first conduction type peripheral circuit well region within the peripheral circuit region, a second conduction type peripheral circuit well region within the first conduction type peripheral circuit well region, and a second conduction type isolation region between the first conduction type memory cell array well region and the first conduction type peripheral circuit well region. At least a portion of first conduction type transistors of first conduction type transistors of the peripheral circuit is formed in the second conduction type isolation region. | 2014-07-10 |
20140191329 | METHOD FOR PRODUCING METAL CONTACTS WITHIN AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT - An integrated circuit includes a MOS transistor having a gate region and source and drain regions separated from the gate region by insulating spacers. At least two metal contact pads respectively contact with two metal silicide regions (for example, a cobalt silicide) which lie within the source and drain regions. The silicide regions are located at the level of lower parts of the two metal contact pads and are separate by a distance from the insulating spacers. | 2014-07-10 |
20140191330 | FINFET AND METHOD OF FABRICATION - An improved finFET and method of fabrication is disclosed. Embodiments of the present invention take advantage of the different epitaxial growth rates of {110} and {100} silicon. Fins are formed that have {110} silicon on the fin tops and {100} silicon on the long fin sides (sidewalls). The lateral epitaxial growth rate is faster than the vertical epitaxial growth rate. The resulting merged fins have a reduced merged region in the vertical dimension, which reduces parasitic capacitance. Other fins are formed with {110} silicon on the fin tops and also {110} silicon on the long fin sides. These fins have a slower epitaxial growth rate than the {100} side fins, and remain unmerged in a semiconductor integrated circuit, such as an SRAM circuit. | 2014-07-10 |
20140191331 | Transistor and Its Method of Manufacture - A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of dielectric material over the exposed portion of the region of semiconductive material; and depositing electrically conductive material to form a layer of electrically conductive material over said layer of dielectric material, the layer of dielectric material electrically isolating the layer of electrically conductive material from the second and third portions of the conductive region. | 2014-07-10 |
20140191332 | PFET DEVICES WITH DIFFERENT STRUCTURES AND PERFORMANCE CHARACTERISTICS - Disclosed herein is a device that includes a first PFET transistor formed in and above a first active region of a semiconducting substrate, a second PFET transistor formed in and above a second active region of the semiconducting substrate, wherein at least one of a thickness of the first and second channel semiconductor materials or a concentration of germanium in the first and second channel semiconductor materials are different. | 2014-07-10 |
20140191333 | METHOD OF PROTECTING AN INTERLAYER DIELECTRIC LAYER AND STRUCTURE FORMED THEREBY - This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures. | 2014-07-10 |
20140191334 | STACKED POWER SEMICONDUCTOR DEVICE USING DUAL LEAD FRAME - A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip. | 2014-07-10 |
20140191335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts. | 2014-07-10 |
20140191336 | CROSS-HAIR CELL WORDLINE FORMATION - Methods and devices depicting fabrication of non-planar access devices having fins and narrow trenches, among which is a method that includes wet etching a conductor to form a recessed region and subsequently etching the conductor to form gates on the fins. The wet etching may include formation of recesses which are may be backfilled with a fill material to form spacers on the conductor. Portions of a plug may be removed during the wet etch to form overhanging spacers to provide further protection of the conductor during the dry etch. | 2014-07-10 |
20140191337 | Stacked Half-Bridge Package - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source. | 2014-07-10 |
20140191338 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other. | 2014-07-10 |
20140191339 | SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate having a plurality of first doped regions and second doped regions; and forming a first dielectric layer on the semiconductor substrate. The method also includes forming a first gate dielectric layer and a second gate dielectric layer; and forming a first metal gate and a second metal gate on the first gate dielectric layer and the second gate dielectric layer, respectively. Further, the method includes forming a third dielectric layer on the second metal gate; and forming a second dielectric layer on the first dielectric layer. Further, the method also includes forming at least one opening exposing at least one first metal gate and one first doped region; and forming a contact layer contacting with the first metal gate and the first doped region to be used as a share contact structure. | 2014-07-10 |
20140191340 | Transistors, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions - Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string. | 2014-07-10 |
20140191341 | Method and Apparatus for a Semiconductor Structure - A semiconductor structure may include a first device having first surface with a first bonding layer formed thereon and a second device having a first surface with a second bonding layer formed thereon. The first bonding layer may provide an electrically conductive path to at least one electrical device in the first device. The second bonding layer may provide an electrically conductive path to at least one electrical device in the second device. One of the first or the second devices may include MEMS electrical devices. The first and/or the second bonding layers may be formed of a getter material, which may provide absorption for outgassing. | 2014-07-10 |
20140191342 | MEMS SENSOR - There is provided a MEMS sensor including a signal processing LSI equipped with a temperature sensor for measuring temperature of a sensor, and a MEMS sensor chip overlaid on the signal processing LSI, the MEMS sensor chip being mounted on a heat generating part of the signal processing LSI. This MEMS sensor decreases the effects caused by thermally triggered changes in temperature characteristics. | 2014-07-10 |
20140191343 | SOUND TRANSDUCER AND MICROPHONE USING SAME - Provided is an acoustic transducer including: a semiconductor substrate; a vibrating membrane, provided above the semiconductor substrate, including a vibrating electrode; and a fixed membrane, provided above the semiconductor substrate, including a fixed electrode, the acoustic transducer detecting a sound wave according to changes in capacitances between the vibrating electrode and the fixed electrode, converting the sound wave into electrical signals, and outputting the electrical signals. At least one of the vibrating electrode and the fixed electrode is divided into a plurality of divided electrodes, and the plurality of divided electrodes outputting the electrical signals. | 2014-07-10 |
20140191344 | MEMS PROCESS AND DEVICE - A method of fabricating a micro-electrical-mechanical system (MEMS) transducer comprises the steps of forming a membrane on a substrate, and forming a back-volume in the substrate. The step of forming a back-volume in the substrate comprises the steps of forming a first back-volume portion and a second back-volume portion, the first back-volume portion being separated from the second back-volume portion by a step in a sidewall of the back-volume. The cross-sectional area of the second back-volume portion can be made greater than the cross-sectional area of the membrane, thereby enabling the back-volume to be increased without being constrained by the cross-sectional area of the membrane . The back-volume may comprise a third back-volume portion. The third back-volume portion enables the effective diameter of the membrane to be formed more accurately. | 2014-07-10 |
20140191345 | MAGNETIC MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A magnetic memory with a memory layer having magnetization, the direction of magnetization of which changes according to information recorded therein; a reference layer having a fixed magnetization against which magnetization of the memory layer can be compared; a nonmagnetization layer between the memory layer and the reference layer; and an electrode on one side of the memory layer facing away from the reference layer, wherein, the memory device memorizes the information by reversal of the magnetization of the memory layer by a spin torque generated when a current flows between the memory layer, the nonmagnetization layer and the reference layer, and a heat conductivity of a center portion of the electrode is lower than a heat conductivity of surroundings thereof. The memory and reference preferably have vertical magnetizations. | 2014-07-10 |
20140191346 | MAGNETIC MEMORY DEVICES INCLUDING MAGNETIC LAYERS SEPARATED BY TUNNEL BARRIERS - A magnetic memory device may include a first vertical magnetic layer, a non-magnetic layer on the first vertical magnetic layer, and a first junction magnetic layer on the non-magnetic layer, with the non-magnetic layer being between the first vertical magnetic layer and the first junction magnetic layer. A tunnel barrier may be on the first junction magnetic layer, with the first junction magnetic layer being between the non-magnetic layer and the tunnel barrier. A second junction magnetic layer may be on the tunnel barrier with the tunnel barrier being between the first and second junction magnetic layers, and a second vertical magnetic layer may be on the second junction magnetic layer with the second junction magnetic layer being between the tunnel barrier and the second vertical magnetic layer. | 2014-07-10 |
20140191347 | SOLID-STATE IMAGING DEVICE - According to one embodiment, a solid-state imaging device includes a semiconductor substrate including a pixel area and a peripheral circuit area, an interconnection structure provided on a first principal surface of the semiconductor substrate and including first interconnection layers electrically connected to the peripheral circuit area, a second interconnection layer provided in the peripheral circuit area and on a second principal surface of the semiconductor substrate, a third interconnection layer provided above the second interconnection layer with an insulating layer therebetween, and through electrodes electrically connecting the second interconnection layer to the third interconnection layer. | 2014-07-10 |
20140191348 | INTEGRATED CIRCUIT AND MANUFACTURING METHOD - Disclosed is an integrated circuit comprising a substrate ( | 2014-07-10 |
20140191349 | SOLID-STATE IMAGING APPARATUS AND METHOD OF MANUFACTURING THE SAME - The present invention provides a solid-state imaging apparatus which has hollow portions provided around each of color filters and achieves the prevention of the peeling of each of the color filters. The solid-state imaging apparatus having a plurality of light receiving portions provided on a semiconductor substrate includes: a plurality of color filters arranged correspondingly to each of the plurality of light receiving portions; and hollow portions formed around each of the plurality of color filters, wherein each of the color filters has one peripheral part contacting with adjacent one or more of the color filters. | 2014-07-10 |
20140191350 | IMAGE SENSOR CHIP PACKAGE AND FABRICATING METHOD THEREOF - An image sensor chip package is disclosed, which includes a substrate, an image sensor component formed on the substrate, a spacer formed on the substrate and surrounding the image sensor component, and a transparent plate. A stress notch is formed on a side of the transparent plate, and a breaking surface is extended from the stress notch. A method for fabricating the image sensor chip package is also disclosed. | 2014-07-10 |
20140191351 | MINIATURE PHASE-CORRECTED ANTENNAS FOR HIGH RESOLUTION FOCAL PLANE THz IMAGING ARRAYS - An imaging/detection device includes a hemispherical lens having a surface opposite a curvature of the hemispherical lens, where the hemispherical lens defines an optical axis. The imaging/detection device also includes a plurality of detectors arranged on a focal plane array that is positioned near the surface of the hemispherical lens. Each of the detectors respectively includes a diode and an antenna monolithically integrated with the diode. Additionally, at least one of the detectors is offset by a distance from the optical axis of the hemispherical lens and is configured such that a radiating pattern of the respective antenna is tilted by an angle and directed toward the optical axis of the hemispherical lens. A maximum direction of the radiating pattern of the respective antenna is related to the distance by which the detector is offset from the optical axis of the hemispherical lens. | 2014-07-10 |
20140191352 | WAFER-LEVEL PACKAGING METHOD OF BSI IMAGE SENSORS HAVING DIFFERENT CUTTING PROCESSES - A wafer-level packaging method of BSI image sensors includes the following steps: S1: providing a wafer package body comprising a silicon base, an interconnect layer, a hollow wall and a substrate; S2: cutting the wafer package body via a first blade in a first cutting process to separate the interconnect layer of adjacent BSI image sensors; and S3: cutting the wafer package body via a second blade in a second cutting process to obtain independent BSI image sensors. As a result, damage of the interconnect layer and the substrate may be decreased to improve performance and reliability of the BSI image sensor. | 2014-07-10 |
20140191353 | SOLID-STATE IMAGING DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC EQUIPMENT - A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film. | 2014-07-10 |
20140191354 | LASER SYSTEM WITH POLARIZED OBLIQUE INCIDENCE ANGLE AND ASSOCIATED METHODS - Novel laser processed semiconductor materials, systems, and methods associated with the manufacture and use of such materials are provided. In one aspect, for example, a method of processing a semiconductor material can include providing a semiconductor material and irradiating a target region of the semiconductor material with a beam of laser radiation to form a laser treated region. The laser radiation is irradiated at an angle of incidence relative to the semiconductor material surface normal of from about 5° to about 89°, and the laser radiation can be at least substantially p-polarized. | 2014-07-10 |
20140191355 | IMAGE SENSORS WITH MULTIPLE OUTPUT STRUCTURES - In various embodiments, image sensors incorporate multiple output structures by including multiple sub-arrays, at least one of which includes a region of active pixels, a dark pixel region that is fanned and/or slanted, a dark pixel region that is unfanned and unslanted, a horizontal CCD, and an output structure for conversion of charge to voltage. | 2014-07-10 |
20140191356 | SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus is disclosed in which, in a first unit cell, light is collected to maximize an amount of light received when the light is incident at a first angle-of-incidence, and in a second unit cell adjacent to the first unit cell, light is collected to maximize an amount of light received when the light is incident at a second angle-of-incidence, the amount of light received when the light is incident at a third angle-of-incidence on the first unit cell is equal to the amount of light received when the light is incident at the third angle-of-incidence on the second unit cell, the first angle-of-incidence is greater than the third angle-of-incidence by a predetermined amount, and the second angle-of-incidence is smaller than the third angle-of-incidence by the predetermined amount. | 2014-07-10 |
20140191357 | MULTI-SUBSTRATE IMAGE SENSOR HAVING A DUAL DETECTION FUNCTION - The present invention relates to an image sensor in which substrates are stacked, wherein a substrate-stacked image sensor according to the present invention is configured such that a first photodiode is formed on a first substrate, a second photodiode is formed on a second substrate, the two substrates are aligned with and bonded to each other to electrically couple the two photodiodes to each other, thereby forming a complete photodiode within one pixel. | 2014-07-10 |
20140191358 | Two-Portion Shallow-Trench Isolation - A shallow trench isolation (STI) and method of forming the same is provided. The STI structure comprises an upper insulating portion and a lower insulating portion, wherein the lower insulating portion includes a first insulator and an insulating layer surrounding the first insulator, the upper insulating portion includes a second insulator and a buffer layer surrounding the second insulator. A part of the buffer layer interfaces between the first insulator and the second insulator, and the outer sidewall of the buffer layer and the sidewall of the first insulator are leveled. | 2014-07-10 |
20140191359 | SEMICONDUCTOR-ON-OXIDE STRUCTURE AND METHOD OF FORMING - Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer. | 2014-07-10 |
20140191360 | ESD PROTECTION DEVICE AND METHOD FOR PRODUCING THE SAME - An ESD protection device includes a first discharge electrode and a second discharge electrode arranged to oppose each other, a discharge supporting electrode formed so as to span between the first and second discharge electrodes, and an insulator substrate that retains the first and second discharge electrodes and the discharge supporting electrode. The discharge supporting electrode is constituted by a group of a plurality of metal particles each coated with a semiconductor film containing silicon carbide. This discharge supporting electrode is obtained by firing a semiconductor-metal complex powder in which a semiconductor powder composed of silicon carbide is fixed to surfaces of metal particles. Selection is made so that the relationship between a coating amount Q [wt %] of the semiconductor powder in the semiconductor-metal complex powder and a specific surface area S [m | 2014-07-10 |
20140191361 | ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS - A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip. | 2014-07-10 |
20140191362 | ELECTROLESS PLATING OF COBALT ALLOYS FOR ON CHIP INDUCTORS - A method for forming an on-chip magnetic structure includes forming a seed layer over a substrate of a semiconductor chip. The seed layer is patterned to provide a plating location. A cobalt based alloy is electrolessly plated at the plating location to form an inductive structure on the semiconductor chip. | 2014-07-10 |
20140191363 | EXTERNAL STORAGE DEVICE AND METHOD OF MANUFACTURING EXTERNAL STORAGE DEVICE - An external storage device including an interconnect substrate having a contact type external terminal, at least one semiconductor chip disposed over a first surface of the interconnect substrate, and a sealing resin layer which seals the at least one semiconductor chip and does not cover the external terminal. The at least one semiconductor chip includes a storage device, an inductor being connected to the storage device, a driver circuit configured to control the inductor and an interconnect layer. The interconnect layer is formed at a first surface of the semiconductor chip and includes the inductor. The first surface of the semiconductor chip is other than facing the first surface of the interconnect substrate, and the inductor and the driver circuit are connected to each other through the interconnect layer. | 2014-07-10 |
20140191364 | METHOD OF FABRICATING METAL-INSULATOR-METAL (MIM) CAPACITOR WITHIN TOPMOST THICK INTER-METAL DIELECTRIC LAYERS - Embodiments of MIM capacitors may be embedded into a thick IMD layer with enough thickness (e.g., 10 KŘ30 KÅ) to get high capacitance, which may be on top of a thinner IMD layer. MIM capacitors may be formed among three adjacent metal layers which have two thick IMD layers separating the three adjacent metal layers. Materials such as TaN or TiN are used as bottom/top electrodes & Cu barrier. The metal layer above the thick IMD layer may act as the top electrode connection. The metal layer under the thick IMD layer may act as the bottom electrode connection. The capacitor may be of different shapes such as cylindrical shape, or a concave shape. Many kinds of materials (Si3N4, ZrO2, HfO2, BST . . . etc.) can be used as the dielectric material. The MIM capacitors are formed by one or two extra masks while forming other non-capacitor logic of the circuit. | 2014-07-10 |
20140191365 | DEVICE DESIGN FOR PARTIALLY ORIENTED RUTILE DIELECTRICS - Methods include forming a dielectric layer from a first material above a substrate. The dielectric layer is formed such that a preferred crystal direction for at least one electrical property of the first material is parallel to a surface of the dielectric layer. Next, forming a first and second trench within the dielectric layer wherein the first and second trenches have at least one curved portion. Forming a second material within the first trench and a third material within the second trench wherein the first material is different from the second and third materials. The first and second trenches are separated by a distance between 3-20 nm. | 2014-07-10 |
20140191366 | High-K and Metal Filled Trench-Type EDRAM Capacitor with Electrode Depth and Dimension Control - Partial removal of organic planarizing layer (OPL) material forms a plug of OPL material within an aperture that protects underlying material or electronic device such as a deep trench capacitor during other manufacturing processes. The OPL plug thus can absorb any differences or non-uniformity in, for example, etch rates across the chip or wafer and preserve recess dimensions previously formed. control of a lateral component of later removal of the OPL plug by etching also can increase tolerance of overlay error in forming connections and thus avoid loss in manufacturing yield. | 2014-07-10 |
20140191367 | SANDWICH DAMASCENE RESISTOR - A method is provided for forming sandwich damascene resistors in MOL processes and the resulting devices. Embodiments include forming on a substrate a film stack including an interlayer dielectric (ILD), a first dielectric layer, and a sacrifice layer (SL); removing a portion of the SL and the first dielectric layer, forming a first cavity; conformally forming a layer of resistive material in the first cavity and over the SL; depositing a second dielectric layer over the layer of resistive material and filling the first cavity; and removing the second dielectric layer, the layer of resistive material not in the first cavity, and at least a partial depth of the SL. | 2014-07-10 |
20140191368 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal. | 2014-07-10 |
20140191369 | NITRIDE SEMICONDUTOR DEVICE - A nitride semiconductor device includes a first nitride semiconductor layer, and an npn junction structure including a second nitride semiconductor layer of an n-type conductivity, a third nitride semiconductor layer of a p-type conductivity, and a fourth nitride semiconductor layer of an n-type conductivity layered in this order on the first nitride semiconductor layer. The third nitride semiconductor layer includes two or more uncovered regions which are uncovered with the fourth nitride semiconductor layer. | 2014-07-10 |
20140191370 | SILICON SINGLE CRYSTAL WAFER, MANUFACTURING METHOD THEREOF AND METHOD OF DETECTING DEFECTS - A silicon single crystal wafer is provided. The silicon single crystal wafer includes an IDP which is divided into an NiG region and an NIDP region, wherein the IDP region is a region where a Cu based defect is not detected, the NiG region is a region where an Ni based defect is detected and the NIPD region is a region where an Ni based defect is not detected. | 2014-07-10 |
20140191371 | Catalytic Etch With Magnetic Direction Control - A material can be locally etched with arbitrary changes in the direction of the etch. A ferromagnetic-material-including catalytic particle is employed to etch the material. A wet etch chemical or a plasma condition can be employed in conjunction with the ferromagnetic-material-including catalytic particle to etch a material through a catalytic reaction between the catalytic particle and the material. During a catalytic etch process, a magnetic field is applied to the ferromagnetic-material-including catalytic particle to direct the movement of the particle to any direction, which is chosen so as to form a contiguous cavity having at least two cavity portions having different directions. The direction of the magnetic field can be controlled so as to form the contiguous cavity in a preplanned pattern, and each segment of the contiguous cavity can extend along an arbitrary direction. | 2014-07-10 |
20140191372 | SPACER ASSISTED PITCH DIVISION LITHOGRAPHY - Spacer-based pitch division lithography techniques are disclosed that realize pitches with both variable line widths and variable space widths, using a single spacer deposition. The resulting feature pitches can be at or below the resolution limit of the exposure system being used, but they need not be, and may be further reduced (e.g., halved) as many times as desired with subsequent spacer formation and pattern transfer processes as described herein. Such spacer-based pitch division techniques can be used, for instance, to define narrow conductive runs, metal gates and other such small features at a pitch smaller than the original backbone pattern. | 2014-07-10 |
20140191373 | Composite Wafer and Method for Manufacturing the Same - A composite wafer | 2014-07-10 |
20140191374 | FILM THICKNESS METROLOGY - Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure. | 2014-07-10 |
20140191375 | METHODS FOR FABRICATING THREE-DIMENSIONAL NANO-SCALE STRUCTURES AND DEVICES - A method of fabricating a 3 dimensional structure, includes: forming a stack of at least 2 layers of photo resist material having different photo resist sensitivities upon a substrate; exposing the stack to beams of electromagnetic radiation or charged particles of different dosages to achieve selective solubility along a height of the stack; and dissolving soluble portions of the stack with a solvent to produce a 3 dimensional structure of desired geometry. | 2014-07-10 |
20140191376 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, including: a substrate; a first semiconductor element disposed on the substrate and having a first conductive pad grounded to the substrate; a conductive layer formed on the first semiconductor element and electrically connected to the substrate; a second semiconductor element disposed on the first semiconductor element through the conductive layer; and an encapsulant formed on the substrate and encapsulating the first and second semiconductor elements. Therefore, the first and second semiconductor elements are protected from electromagnetic interference (EMI) shielding with the conductive layer being connected to the grounding pad of the substrate. A fabrication method of the semiconductor package is also provided. | 2014-07-10 |
20140191377 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit package comprising a substrate and at least one semiconductor die is described. A connection unit may provide electrical connections between the substrate and the semiconductor die. The connection unit may comprise a stack of conduction layers and isolation layers stacked atop each other. The stack may include a microstrip line or a coplanar waveguide. The microstrip line or the coplanar waveguide may be part of a balun, a power divider, or a directional coupler. | 2014-07-10 |
20140191378 | INTEGRATED CIRCUIT PACKAGE - An integrated circuit (IC) package including a bottom leadframe, an interposer mounted on the bottom leadframe, a flipchip die mounted on the interposer and a top leadframe electrically connected to the interposer. Also, a method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe. | 2014-07-10 |
20140191379 | LOW-K CHIP PACKAGING STRUCTURE - A low-k chip packaging structure comprising chip body I ( | 2014-07-10 |
20140191380 | INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING - An integrated circuit (“IC”) device and method of making it. The IC device may include a conductive lead frame that has a die pad with a relatively larger central body portion and at least one relatively smaller peripheral portion in electrical continuity with the central body portion. The peripheral portion(s) project laterally outwardly from the central body portion of the die pad. Lateral displacement of a portion(s) of an encapsulation layer overlying the peripheral portion(s) is resisted by abutting surfaces on the peripheral portion(s) and the encapsulation layer. | 2014-07-10 |
20140191381 | INTEGRATED CIRCUIT MODULE WITH DUAL LEADFRAME - An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die. | 2014-07-10 |
20140191382 | CIRCUIT SUBSTRATE, METHOD OF MANUFACTURING CIRCUIT SUBSTRATE, AND ELECTRONIC COMPONENT - A circuit substrate includes: a mounting region having an exposed surface that is planarized, and in which a predetermined chip is to be mounted; patterns provided in the mounting region, and including respective top faces that form a part of the exposed surface; and solder bumps provided on the respective patterns, and having substantially same shape as one another. | 2014-07-10 |
20140191383 | POWER DEVICE AND METHOD OF PACKAGING SAME - A method of packaging a power semiconductor die includes providing a first lead frame of a dual gauge lead frame. The first lead frame includes a thick die pad. A tape is attached to a first side of the thick die pad and the power die is attached to a second side of the thick die pad. A second lead frame of the dual gauge lead frame is provided. The second lead frame has thin lead fingers. One end of the lead fingers is attached to an active surface of the power die such that the lead fingers are electrically connected to bonding pads of the power die. A molding compound is then dispensed onto a top surface of the dual gauge lead frame such that the molding compound covers the power die and the lead fingers. | 2014-07-10 |
20140191384 | PRE-ENCAPSULATED ETCHING-THEN-PLATING LEAD FRAME STRUCTURE WITH ISLAND AND METHOD FOR MANUFACTURING THE SAME - A method for manufacturing a lead frame structure for semiconductor packaging. The method includes providing a metal substrate having a top surface and a back surface, forming a first photoresist film on the top surface of the metal substrate, forming a top surface etching pattern in the first photoresist film using photolithography, forming a second photoresist film on the back surface of the metal substrate, forming a back surface etching pattern in the second photoresist film using photolithography, performing an etching process on the top surface and the back surface of the metal substrate, removing the first photoresist film and the second photoresist film, placing the etched metal substrate in a mold, encapsulating the etched metal substrate using the mold; and performing a plating process on the encapsulated metal substrate. | 2014-07-10 |
20140191385 | Process for Producing a Metal Device Housed in a Closed Housing within an Integrated Circuit, and Corresponding Integrated Circuit - An integrated circuit includes a number of metallization levels separated by an insulating region disposed over a substrate. A housing includes walls formed from metal portions produced in various metallization levels. A metal device is housed in the housing. An aperture is produced in at least one wall of the housing. An external mechanism outside of the housing is configured so as to form an obstacle to diffusion of a fluid out of the housing through the at least one aperture. At least one through-metallization passes through the external mechanism and penetrates into the housing through the aperture in order to make contact with at least one element of the metal device. | 2014-07-10 |
20140191386 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided. The semiconductor package includes a substrate; a semiconductor element having opposite active and inactive surfaces and disposed on the substrate via the active surface thereof, wherein the inactive surface of the semiconductor element is roughened; a thermally conductive layer bonded to the inactive surface of the semiconductor element; and a heat sink disposed on the thermally conductive layer. The roughened inactive surface facilitates the bonding between the semiconductor element and the thermally conductive layer so as to eliminate the need to perform a gold coating process and the use of a flux and consequently reduce the formation of voids in the thermally conductive layer. | 2014-07-10 |
20140191387 | METHOD OF FABRICATING LAND GRID ARRAY SEMICONDUCTOR PACKAGE - A fan-out wafer level package is provided with a semiconductor die embedded in a reconstituted wafer. A redistribution layer is positioned over the semiconductor die, and includes a land grid array on a face of the package. A copper heat spreader is formed in the redistribution layer over the die in a same layer as a plurality of electrical traces configured to couple circuit pads of the semiconductor die to respective contact lands of the land grid array. In operation, the heat spreader improves efficiency of heat transfer from the die to the circuit board. | 2014-07-10 |
20140191388 | 3D STACKING SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A 3D stacking semiconductor device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. N layers of stacking structures are provided. Each stacking structure includes a conductive layer and an insulating layer. A first photoresister layer is provided. The stacking structures are etched P−1 times by using the first photoresister layer as a mask. A second photoresister layer is provided. The stacking structures are etched Q−1 times by using the second photoresister layer as a mask. The first photoresister layer is trimmed along a first direction. The second photoresister layer is trimmed along a second direction. The first direction is different from the second direction. A plurality of contact points are arranged along the first and the second directions in a matrix. The included angle between the first direction and the second direction is an acute angle. | 2014-07-10 |
20140191389 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate in which a cell region and a contact region are defined, a pad structure including a plurality of first conductive layers and a plurality of first insulating layers formed alternately with each other in the contact region of the substrate, wherein an end of the pad structure is patterned stepwise, portions of the first conductive layers exposed at the end of the pad structure are defined as a plurality of pad portions, and the plurality of pad portions have a greater thickness than unexposed portions of the plurality of first conductive layers. | 2014-07-10 |
20140191390 | Metal Routing Architecture for Integrated Circuits - A device includes a substrate, a metal pad over the substrate, and a metal trace electrically disconnected from the metal pad. The metal pad and the metal trace are level with each other. A passivation layer includes a portion overlapping an edge portion of the metal pad. A metal pillar is overlying the metal pad, and is electrically connected to the metal pad. The metal trace has a portion overlapped by the metal pillar. | 2014-07-10 |
20140191391 | ELONGATED BUMP STRUCTURES IN PACKAGE STRUCTURE - A package structure includes a chip attached to a substrate. The chip includes a bump structure including a conductive pillar having a length (L) measured along a long axis of the conductive pillar and a width (W) measured along a short axis of the conductive pillar. The substrate includes a pad region and a mask layer overlying the pad region, wherein the mask layer has an opening exposing a portion of the pad region. The chip is attached to the substrate to form an interconnection between the conductive pillar and the pad region. The opening has a first dimension (d1) measured along the long axis and a second dimension (d2) measured along the short axis. In an embodiment, L is greater than d1, and W is less than d2. | 2014-07-10 |
20140191392 | Post-Passivation Interconnect Structure and Methods for Forming the Same - A method includes forming a polymer layer over a passivation layer, wherein the passivation layer further comprises a portion over a metal pad. The polymer layer is patterned to form an opening in the polymer layer, wherein exposed surfaces of the polymer layer have a first roughness. A surface treatment is performed to increase a roughness of the polymer layer to a second roughness greater than the first roughness. A metallic feature is formed over the exposed surface of the polymer layer. | 2014-07-10 |
20140191393 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD THEREOF - A semiconductor package is provided, including a carrier having electrical connecting pads, a semiconductor element disposed on the carrier and having electrode pads, conductive elements electrically connected to the electrode pads and the electrical connecting pads, fluorine ions formed between the conductive elements and the electrode pads or between the conductive elements and the electrical connecting pads, and an encapsulant formed on the carrier and the conductive elements, wherein the electrode pads or the electrical connecting pads are formed by aluminum materials to form fluorine aluminum by way of packaging the fluorine ions after the completion of the packaging process. Accordingly, the corrosion resistance of the semiconductor package is increased. | 2014-07-10 |
20140191394 | Bumps for Chip Scale Packaging - A chip scale semiconductor device comprises a semiconductor die, a first bump and a second bump. The first bump having a first diameter and a first height is formed on an outer region of the semiconductor die. A second bump having a second diameter and a second height is formed on an inner region of the semiconductor die. The second diameter is greater than the first diameter while the second height is the same as the first height. By changing the shape of the bump, the stress and strain can be redistributed through the bump. As a result, the thermal cycling reliability of the chip scale semiconductor device is improved. | 2014-07-10 |
20140191395 | Forming Interconnect Structures Using Pre-Ink-Printed Sheets - A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate. | 2014-07-10 |
20140191396 | SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING BASE FOR SEMICONDUCTOR PACKAGE - In one configuration, a semiconductor package includes a conductive trace embedded in a base and a semiconductor device mounted on the conductive trace via a conductive structure, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. In another configuration, a method for fabricating a semiconductor package includes providing a base, forming at least one conductive trace on the base, forming an additional insulation material on the base, and defining patterns upon the additional insulation material, wherein the pattern is formed on at least one conductive trace, wherein the conductive structure is a bump structure and the width of the bump structure is bigger than the width of the conductive trace. | 2014-07-10 |
20140191397 | PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A package substrate may include an insulating substrate, a dummy pad, a signal pad and a plug. The dummy pad may be formed on an upper surface of the insulating substrate. The signal pad may be formed on the upper surface of the insulating substrate. The signal pad may have an upper surface protruded from an upper surface of the dummy pad. The plug may be vertically formed in the insulating substrate. The plug may have an upper end exposed through the upper surface of the insulating substrate and connected with the signal pad and the dummy pad, and a lower end exposed through a lower surface of the insulating substrate. Thus, a signal bump may accurately make contact with the protruded upper surface of the signal pad. | 2014-07-10 |
20140191398 | Ultraviolet Reflective Rough Adhesive Contact - A device including a first semiconductor layer and a contact to the first semiconductor layer is disclosed. An interface between the first semiconductor layer and the contact includes a first roughness profile having a characteristic height and a characteristic width. The characteristic height can correspond to an average vertical distance between crests and adjacent valleys in the first roughness profile. The characteristic width can correspond to an average lateral distance between the crests and adjacent valleys in the first roughness profile. | 2014-07-10 |
20140191399 | WIRING MATERIAL AND SEMICONDUCTOR MODULE USING THE SAME - There is provided a wiring material including a core layer made of metal and a clad layer made of metal and a fiber in which the core layer is copper or an alloy containing copper and the clad layer is formed of copper or the alloy containing copper and the fiber having a thermal expansion coefficient lower than that of copper, the wiring material having a stacked structure in which at least one surface of the core layer is closely adhered to the clad layer, and the fiber in the clad layer is arranged so as to be parallel to the surface of the core layer. | 2014-07-10 |
20140191400 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece including an insulating material layer disposed thereon. The insulating material layer includes a trench formed therein. The method includes forming a barrier layer on the sidewalls of the trench using a surface modification process and a surface treatment process. | 2014-07-10 |
20140191401 | AIRGAP INTERCONNECT WITH HOOD LAYER AND METHOD OF FORMIING - An airgap interconnect structure with hood layer and methods for forming such an airgap interconnect structure are disclosed. A substrate having a dielectric layer with a plurality of interconnects formed therein is provided. Each interconnect is encapsulated by a barrier layer. A hardmask is formed on the dielectric layer and patterned to expose the dielectric layer between adjacent interconnects where an airgap is desired. The dielectric layer is etched to form a trench, wherein the etching process additionally etches at least a portion of the barrier layer to expose a portion of the side surface of each adjacent copper interconnect. A hood layer is electrolessly plated onto an exposed portion of the top surface and the exposed portion of the side surface to reseal the interconnect. A gap-sealing dielectric layer is formed over the device, sealing the trench to form an airgap. | 2014-07-10 |
20140191402 | Barrier Layer for Copper Interconnect - A device including a dielectric layer overlying a substrate, a conductive line with a sidewall in the dielectric layer, a Ta layer adjoining the sidewall of the conductive line, and a metal oxide formed between the Ta layer and the dielectric layer. | 2014-07-10 |
20140191403 | MULTI-DIE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THEREOF - A multi-die semiconductor package and various methods of manufacturing the same. In one embodiment, the semiconductor package includes: (1) a substrate, (2) a first die coupled to the substrate, the first die having a first set of terminals located along a first edge and bearing a first integrated circuit (IC) that substantially occupies an area of the first die, (3) a second die coupled to the substrate, the second die having a second set of terminals and bearing a second IC that substantially occupies an area of the second die, the first and second ICS being mirror-images of one another and (4) interconnects coupling corresponding terminals of the first and second sets together. | 2014-07-10 |
20140191404 | LOCAL INTERCONNECT STRUCTURE AND FABRICATION METHOD - Local interconnect structures and fabrication methods are provided. A dielectric layer can be formed on a semiconductor substrate. A first film layer can be patterned on the dielectric layer to define a region surrounded by a local interconnect structure to be formed. A sidewall spacer can be formed and patterned surrounding the first film layer on an exposed surface portion of the dielectric layer. A second film layer can be formed on the exposed surface portion of the dielectric layer and can have a top surface substantially flushed with a top surface of the sidewall spacer. The patterned sidewall spacer can be removed to form a first opening. After forming the first opening, the dielectric layer can be etched to form a second opening through the dielectric layer. The second opening can be filled with a conductive material to form the local interconnect structure. | 2014-07-10 |
20140191405 | METHOD OF FORMING PATTERNS FOR SEMICONDUCTOR DEVICE - Provided is a method of forming patterns for a semiconductor device in which fine patterns and large-width patterns are formed simultaneously and adjacent to each other. In the method, a first layer is formed on a substrate so as to cover a first region and a second region which are included in the substrate. Both a blocking pattern covering a portion of the first layer in the first region and a low-density large-width pattern covering a portion of the first layer in the second region are simultaneously formed. A plurality of sacrificial mask patterns are formed on the first layer and the blocking pattern in the first region. A plurality of spacers covering exposed sidewalls of the plurality of sacrificial mask patterns are formed. The plurality of sacrificial mask patterns are removed. The first layer in the first and second regions are simultaneously etched by using the plurality of spacers and the blocking pattern as etch masks in the first region and using the low-density large-width pattern as an etch mask in the second region. | 2014-07-10 |
20140191406 | MANUFACTURING METHOD FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR DEVICE - One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated. | 2014-07-10 |
20140191407 | DIELECTRIC POSTS IN METAL LAYERS - A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%. | 2014-07-10 |
20140191408 | BACKSIDE METAL GROUND PLANE WITH IMPROVED METAL ADHESION AND DESIGN STRUCTURES - A backside metal ground plane with improved metal adhesion and methods of manufacture are disclosed herein. The method includes forming at least one through silicon via (TSV) in a substrate. The method further includes forming an oxide layer on a backside of the substrate. The method further includes forming a metalized ground plane on the oxide layer and in electrical contact with an exposed portion of the at least one TSV. | 2014-07-10 |
20140191409 | FORMING VIAS AND TRENCHES FOR SELF-ALIGNED CONTACTS IN A SEMICONDUCTOR STRUCTURE - A semiconductor structure is formed to include a non-conductive layer with at least one metal line, a first dielectric layer, a first stop layer, a second dielectric layer, a second stop layer, a third stop layer and a fourth stop layer. A first photoresist layer is formed over the upper stop layer to develop at least one via pattern. The structure is selectively etched to form the via pattern in the third stop layer through the fourth stop layer. The first photoresist layer is then removed. A second photoresist layer is formed over the upper stop layer to develop a plurality of trench patterns, each of the trench pattern comprising a via-trench portion in which the trench pattern is formed above the via pattern, and a trench portion that is remaining part of the trench pattern. | 2014-07-10 |
20140191410 | DAMAGE MONITOR STRUCTURE FOR THROUGH-SILICON VIA (TSV) ARRAYS - Described herein are techniques related to techniques for monitoring damage to circuitry or structure neighboring one or more through-silicon vias (TSVs) caused by TSV-related processing. Additionally, techniques for confining diffusion of moisture or chemical from one or more TSVs during TSV-related processing are also described. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 2014-07-10 |
20140191411 | INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnection structure. The method includes providing a substrate having certain semiconductor devices, a metal layer electrically connecting with the semiconductor devices, and a barrier layer on the metal layer. The method also includes forming a dielectric layer on the substrate; and forming an antireflective coating on the dielectric layer. Further, the method includes forming a second mask having a first pattern corresponding to a through hole in the dielectric layer, wherein the antireflective coating significantly reduces lithographic light reflection to avoid photoresist residue in the first pattern; and forming a through hole by etching the dielectric layer and the antireflective coating covering the dielectric layer using the second mask as an etching mask. Further, the method also includes forming a via by filling the through hole with a conductive material. | 2014-07-10 |
20140191412 | INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF - A method is provided for fabricating an interconnection structure. The method includes providing a semiconductor substrate having certain semiconductor devices inside, a dielectric layer covering the semiconductor devices, and vias inside the dielectric layer connecting with connection pads of the semiconductor devices. The method also includes forming a first conductive layer on the semiconductor substrate, and forming a second conductive layer with smaller grain sizes by doping the first conductive layer. Further, the method includes forming an interconnection pad by patterning the second conductive layer, and forming a connection wire on the interconnection pad. | 2014-07-10 |
20140191413 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE COMPRISING A CONDUCTOR LAYER IN THE SEMICONDUCTOR BODY AND SEMICONDUCTOR BODY | 2014-07-10 |
20140191414 | Semiconductor Device and Method for Fabricating the Same - A semiconductor device and a method for fabricating the same are provided. The semiconductor device comprising a substrate including a first surface and a second surface that face each other, a planarization layer formed on the first surface of the substrate, a passivation layer formed on the planarization layer, and a through via contact penetrating the substrate, the planarization layer, and the passivation layer, and being exposed from the passivation layer. | 2014-07-10 |
20140191415 | METHODS FOR ETCHING THROUGH-WAFER VIAS IN A WAFER - Apparatus and methods for plasma etching are disclosed. In one embodiment, a method for etching a plurality of features on a wafer includes positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, and focusing the plasma ions using a plasma focusing ring. The plasma focusing ring is configured to increase a flux of plasma ions arriving at a surface of the wafer to control the formation of the plurality of features and structures associated therewith. | 2014-07-10 |
20140191416 | SEMICONDUCTOR DEVICE - A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size. | 2014-07-10 |
20140191417 | Multi-Chip Package Assembly with Improved Bond Wire Separation - A multi-chip package is disclosed that has a construction capable of preventing and/or reducing electrical shorts caused by shifts in bond wires. The multi-chip package includes a die attach formed between connection points of a bond wire. The die attach is made of a non-conductive material and can be constructed so as to support or encompass a portion of the bond wire. By contacting the bond wire, the die attach restricts the motion of the bond wire by acting as a physical barrier to the bond wire's movement and/or as a source of friction. In this manner, undesired position shifts of the bond wires can be prevented, reducing device failures and allowing for improved manufacturing allowances. | 2014-07-10 |
20140191418 | METAL TO METAL BONDING FOR STACKED (3D) INTEGRATED CIRCUITS - The present invention provides a stabilized fine textured metal microstructure that constitutes a durable activated surface usable for bonding a 3D stacked chip. A fine-grain layer that resists self anneal enables metal to metal bonding at moderate time and temperature and wider process flexibility. | 2014-07-10 |
20140191419 | 3D INTEGRATED CIRCUIT PACKAGE WITH WINDOW INTERPOSER - 3D integrated circuit packages with window interposers and methods to form such semiconductor packages are described. For example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer having a window is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in the window of the interposer and interconnected to the top semiconductor die. In another example, a semiconductor package includes a substrate. A top semiconductor die is disposed above the substrate. An interposer is disposed between and interconnected to the substrate and the top semiconductor die. A bottom semiconductor die is disposed in a same plane as the interposer and interconnected to the top semiconductor die. | 2014-07-10 |
20140191420 | EMBEDDED PACKAGE IN PCB BUILD UP - An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device. | 2014-07-10 |
20140191421 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate, an interlayer insulation film, multiple wiring layers, a first hard film, and an electrical pad. The semiconductor substrate has a semiconductor element. The interlayer insulation film is disposed above the semiconductor substrate. The multiple wiring layers are disposed within the interlayer insulation film. The first hard film is disposed above the interlayer insulation film, and the first hard film is harder than the interlayer insulation film. The electrical pad is disposed above the first hard film, and the electrical pad is used for an external connection. The electrical pad includes a lower layer pad, the upper layer pad, and a second hard film. | 2014-07-10 |
20140191422 | SUBLIMATION METHOD FOR THE PURIFICATION OF ORGANIC SMALL MOLECULES - Disclosed is an improved sublimation method for the purification of organic small molecules. The new method features that barriers are applied in the collection region of sublimation tube so that the gas flow path is modified to pass through or bypass the barriers from the heating region to the vacuum pump. The arrangement of the barriers can effectively separate the main product from the impurities. The main product is enriched in a collection region, while the volatile impurities are enriched in an impurity region. This method has been proved to improve the quality of sublimed materials substantially according to the purity measurements and OLED performance tests. | 2014-07-10 |
20140191423 | Splashguard and Inlet Diffuser for High Vacuum, High Flow Bubbler Vessel - The present invention is a bubbler having a diptube inlet ending in a bubble size reducing outlet and at least one baffle disc positioned between the outlet of the diptube and the outlet of the bubbler to provide a narrow annular space between the baffle disc and the wall of the bubbler to prevent liquid droplets from entering the outlet to the bubbler. The bubble size reducing outlet is an elongated cylindrical porous metal frit situated in a sump of approximately the same dimensions. A metal frit is placed at the inlet of the outlet of the bubbler. The present invention is also a process of delivering a chemical precursor from a bubbler vessel having the above structure. | 2014-07-10 |