27th week of 2014 patent applcation highlights part 16 |
Patent application number | Title | Published |
20140183540 | Display Device - There is provided an active matrix EL display device that can display a clear multi gray-scale color display to reduce the shift in the potential caused by the potential drop due to the wiring resistance of a power source supply line, in order to decrease the unevenness in a display region. A plurality of drawing out ports of the power source supply line are arranged. Further, in the wiring resistance between the external input terminal and the pixel portion power source supply line, potential compensation is performed by supplying potential to the power source supply line by a feedback amplifier. Further, in addition to above structure, the power source supply line may be arranged in a matrix. | 2014-07-03 |
20140183541 | THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND DISPLAY DEVICE - A thin film transistor and a manufacturing method for the same, an array substrate, and a display device are disclosed. The thin film transistor comprises: a substrate ( | 2014-07-03 |
20140183542 | LIGHT EMITTING DEVICE - There is provided a light emitting device which enables a color display with good color balance. A triplet compound is used for a light emitting layer of an EL element that emits red color, and a singlet compound is used for a light emitting layer of an EL element that emits green color and a light emitting layer of an EL element that emits blue color. Thus, an operation voltage of the EL element emitting red color may be made the same as the EL element emitting green color and the EL element emitting blue color. Accordingly, the color display with good color balance can be realized. | 2014-07-03 |
20140183543 | METHOD AND SYSTEM FOR CO-PACKAGING GALLIUM NITRIDE ELECTRONICS - An electronic package includes a leadframe, a plurality of pins, a gallium-nitride (GaN) transistor, and a GaN diode. The GaN transistor includes a drain region, a drift region, a source region, and a gate region; the drain region includes a GaN substrate and a drain contact, the drift region includes a first GaN epitaxial layer coupled to the GaN substrate, the source region includes a source contact and is separated from the GaN substrate by the drift region, and the gate region includes a second GaN epitaxial layer and a gate contact. The GaN diode includes an anode region and a cathode region, the cathode region including the GaN substrate and a cathode contact, and the anode region including a third GaN epitaxial layer coupled to the GaN substrate and an anode contact. The drain contact and the anode contact are electrically connected to the leadframe. | 2014-07-03 |
20140183544 | COMPOUND SEMICONDUCTOR ESD PROTECTION DEVICES - The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode FET (E-FET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type III compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor. | 2014-07-03 |
20140183545 | POLARIZATION EFFECT CARRIER GENERATING DEVICE STRUCTURES HAVING COMPENSATION DOPING TO REDUCE LEAKAGE CURRENT - A semiconductor structure having: a first semiconductor layer; and an electric carrier generating layer disposed on the first semiconductor layer to generate electric carriers within the first semiconductor layer by polarization effects, the electric carrier generating layer having a predetermined conduction band and a predetermined valance band, the electric carrier generating layer having a concentration of non-carrier generating contaminants having an energy level, the difference in the energy level of the non-carrier type contaminants and the energy level of either the conduction band or the valence band being greater than 10 kT, where k is Boltzmann's constant and T is the temperature of the electric carrier generating semiconductor layer, the electric carrier generating semiconductor layer being doped with a dopant having an energy level, the difference in the energy level of the dopant and the energy level of either the conduction band or the valence band being greater than 10 kT, the dopant having a concentration equal to or greater than the concentration of the non-carrier generating contaminants. | 2014-07-03 |
20140183546 | NITRIDE-BASED SEMICONDUCTOR LIGHT-EMITTING DEVICE - A nitride-based semiconductor light-emitting device includes an n-type nitride-based semiconductor layer, an active layer, a p-type nitride-based semiconductor layer, an ohmic contact layer covering a portion of the p-type nitride-based semiconductor layer upper surface, and a p electrode including a first portion contacting the p-type nitride-based semiconductor layer and a second portion contacting the ohmic contact layer. | 2014-07-03 |
20140183547 | SEMICONDUCTOR DEVICE - According to an embodiment, a semiconductor device includes a base including a mounting portion having conductivity, and a terminal insulated from the mounting portion. The device also includes a semiconductor element provided on the mounting portion and having a first face and a second face opposite to the first face, the semiconductor element having an electrode electrically connected to the terminal on the first face, and contacting the mounting portion via the second face, and a resistance element electrically connecting the mounting portion to the terminal. A resistance value of the resistance element is greater than a reciprocal of the product ωC, wherein C is a capacitance value between the mounting portion and the terminal, and ω is an angular frequency of an electrical signal output from the semiconductor element. | 2014-07-03 |
20140183548 | LIGHT DETECTION DEVICE - A light detection device includes a substrate, a buffer layer disposed on the substrate, a first band gap change layer disposed on a portion of the buffer layer, a light absorption layer disposed on the first band gap change layer, a Schottky layer disposed on a portion of the light absorption layer, and a first electrode layer disposed on a portion of the Schottky layer. | 2014-07-03 |
20140183549 | PHOTO DETECTION DEVICE, PHOTO DETECTION PACKAGE INCLUDING THE PHOTO DETECTION DEVICE, AND PORTABLE DEVICE INCLUDING THE PHOTO DETECTION PACKAGE - Exemplary embodiments of the present invention relate to a photo detection device including a substrate, a first light absorption layer disposed on the substrate, a second light absorption layer disposed in a first region on the first light absorption layer, a third light absorption layer disposed in a second region on the second light absorption layer, and a first electrode layer disposed on each of the first, the second, and the third light absorption layers. | 2014-07-03 |
20140183550 | PARASITIC INDUCTANCE REDUCTION FOR MULTILAYERED BOARD LAYOUT DESIGNS WITH SEMICONDUCTOR DEVICES - A highly efficient, single sided circuit board layout design providing magnetic field self-cancellation and reduced parasitic inductance independent of board thickness. The low profile power loop extends through active and passive devices on the top layer of the circuit board, with vias connecting the power loop to a return path in an inner layer of the board. The magnetic effect of the portion of the power loop on the top layer is reduced by locating the inner layer return path directly underneath the power loop path on the top layer. | 2014-07-03 |
20140183551 | BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS - A method of forming SSRW FETs with controlled step height between a field oxide and epitaxially grown silicon and the resulting devices are provided. Embodiments include providing a SiN layer on a substrate, forming first, second, and third spaced STI regions of field oxide through the SiN layer and into the substrate, removing a top portion of the field oxide for each STI region by a controlled deglaze, removing the SiN layer, forming an n-type region in the substrate between the first and second STI regions and a p-type region in the substrate between the second and third STI regions, and epitaxially growing a Si based layer on the substrate over the n-type and p-type regions. | 2014-07-03 |
20140183552 | TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME - A transistor device having a deep recessed P+ junction is disclosed. The transistor device may comprise a gate and a source on an upper surface of the transistor device, and may include at least one doped well region, wherein the at least one doped well region has a first conductivity type that is different from a conductivity type of a source region within the transistor device and the at least one doped well region is recessed from the upper surface of the transistor device by a depth. The deep recessed P+ junction may be a deep recessed P+ implanted junction within a source contact area. The deep recessed P+ junction may be deeper than a termination structure in the transistor device. The transistor device may be a Silicon Carbide (SIC) MOSFET device. | 2014-07-03 |
20140183553 | TRANSISTOR STRUCTURES HAVING REDUCED ELECTRICAL FIELD AT THE GATE OXIDE AND METHODS FOR MAKING SAME - A transistor device having reduced electrical field at the gate oxide interface is disclosed. In one embodiment, the transistor device comprises a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide. The transistor device has a P+ region within a JFET region of the transistor device in order to reduce an electrical field on the gate oxide. | 2014-07-03 |
20140183554 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A Schottky barrier diode includes: an n+ type silicon carbide substrate; an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate and includes an electrode area and a terminal area positioned outside of the electrode area; a first trench and a second trench disposed on the n− type epitaxial layer in the terminal area; a p area disposed under the first trench and the second trench; a Schottky electrode disposed on the n− type epitaxial layer in the electrode area; and an ohmic electrode disposed on a second surface of the n+ type silicon carbide substrate, wherein the first trench and the second trench are adjacently positioned to form a step. | 2014-07-03 |
20140183555 | ELECTRONIC COMPONENT - According to one embodiment, an electronic component includes a device having a plurality of electrodes; a lead electrically connected to each of the plurality of electrodes; a first resin body sealing the device and a portion of the lead; and a first conductive body connected to the leads and contactable with a second conductive body. | 2014-07-03 |
20140183556 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate. | 2014-07-03 |
20140183557 | SEMICONDUCTOR DEVICE STRUCTURE FOR OHMIC CONTACT AND METHOD FOR FABRICATING THE SAME - A semiconductor device structure for an ohmic contact is provided, including a silicon carbide substrate and an ohmic contact layer disposed on the silicon carbide substrate. A carbon layer is disposed on the ohmic contact layer. An anti-diffusion layer is disposed on the carbon layer, and a pad layer is disposed on the anti-diffusion layer. The anti-diffusion layer is made of any one of tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN). | 2014-07-03 |
20140183558 | SCHOTTKY BARRIER DIODE AND METHOD OF MANUFACTURING THE SAME - A schottky barrier diode includes: an n− type epitaxial layer that is disposed at a first surface of an n+ type silicon carbide substrate; a plurality of n type pillar areas that are disposed at the inside of the n− type epitaxial layer and that are disposed at a first portion of the first surface of the n+ type silicon carbide substrate; a p type area that is disposed at the inside of the n− type epitaxial layer and that is extended in a direction perpendicular to the n type pillar areas; a plurality of p+ areas in which the n− type epitaxial layer is disposed at a surface thereof and that are separated from the n type pillar areas and the p type area; a schottky electrode that is disposed on the n− type epitaxial layer and the p+ areas; and an ohmic electrode that is disposed at a second surface of the n+ type silicon carbide substrate. | 2014-07-03 |
20140183559 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present inventive concept has been made in an effort to improve the breakdown voltage of a silicon carbide MOSFET using a trench gate. | 2014-07-03 |
20140183560 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes an n+ type silicon carbide substrate; a plurality of n type pillar regions, a plurality of p type pillar regions, and an n− type epitaxial layer disposed on a first surface of the n+ type silicon carbide substrate; a p type epitaxial layer and an n+ region sequentially disposed on the n− type epitaxial layer; a trench penetrating the n+ region and the p type epitaxial layer and disposed on the n− type epitaxial layer; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate. | 2014-07-03 |
20140183561 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to one embodiment, a semiconductor device includes a first semiconductor part and a conductive electrode. The first semiconductor part is made of SiC. The SiC contains a first element as an n-type or p-type impurity. The first semiconductor part has a first interface part. The first interface part is configured to have maximum area density of the first element. The c conductive electrode is electrically connected to the first interface part. | 2014-07-03 |
20140183562 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor layer | 2014-07-03 |
20140183563 | NITRIDE SEMICONDUCTOR DEVICE WITH LIMITED INSTANTANEOUS CURRENT REDUCTION - A GaN device suppressing the instantaneous current reduction after the shut-off of a high frequency signal is disclosed. The GaN device provides, on a SiC substrate, an AlN layer, a GaN layer, and an AlGaN layer. The SiC substrate has an energy difference greater than 0.67 eV but less than 1.43 eV; the AlN layer has a thickness less than 50 nm; and the GaN layer has a thickness less than 1.5 μm, | 2014-07-03 |
20140183564 | LIGHT EMITTING ELEMENT - A light emitting element includes a first conductivity-type semiconductor layer, a first electrode, a second conductivity-type semiconductor layer and a second electrode. The second conductivity-type semiconductor layer has a square peripheral shape. The first electrode includes a first connecting portion on a first diagonal line and a first extending portion extending from the first connecting portion onto the first diagonal line. The second electrode includes a second connecting portion on the first diagonal line facing the first connecting portion via the first extending portion. Two second extending portions extend from the second connecting portion and having a first portion and a second portion respectively. The first connecting portion includes an end portion closer to the second connecting portion than a straight line intersecting the tip ends of the two second extending portions, and a center portion at a side father from the second connecting portion than the second diagonal line. | 2014-07-03 |
20140183565 | Light-Emitting Module Board and Manufacturing Method of the Light-Emitting Module Board - A light-emitting module board includes a metal board provided with an insulating layer, a light-emitting part and a white insulating film. The light-emitting part includes plural LED chips mounted on the metal board, and a white reflecting film of a ceramic coating formed in a light-emitting area on the metal board on which the plural LED chips are mounted. The white insulating film is an insulating film made of a same material as the white reflecting film and formed in a non-light-emitting area which is other than the light-emitting part and is provided on the metal board outside the light-emitting part. | 2014-07-03 |
20140183566 | MULTI-CHIP LED DIODE APPARATUS - In one aspect, there is an apparatus that comprises a plurality of light emitting chips that each have active areas that have elongated aspect ratios. This chips are mounted in a generally rectangular package. The chips are each arranged around a periphery of the package so that each narrow side of each chip abuts either a sidewall forming the periphery of the package or a long side another of the chips. Some of the chips receive a biasing voltage through one or more other of the chips. | 2014-07-03 |
20140183567 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME - A display device includes a data IC including a plurality of dummy output pads, and a plurality of signal output pads that are positioned at both sides of the plurality of dummy output pads; a plurality of dummy data pads and a plurality of signal input data pads in a non-display region of an array substrate of a display panel, the plurality of dummy data pads corresponding to the plurality of dummy output pads, and the plurality of signal input data pads corresponding to the plurality of the signal output pads; and a plurality of data link lines in the non-display region, and connected between the plurality of signal input data pads and the plurality of data lines in a display region of the display panel | 2014-07-03 |
20140183568 | LED PACKAGE WITH FLEXIBLE POLYIMIDE CIRCUIT AND METHOD OF MANUFACTURING LED PACKAGE - A light emitting diode (LED) package may include a base, at least one light emitting die on the base, and a flextape on the base. The flextape includes at least one metal trace connected to the light emitting die. In a method of manufacturing the LED package, the base may be formed so as to include a basin and at least one light emitting die may be placed within the basin. The flextape may be provided to include at least one metal trace that is electrically connected to the light emitting die. | 2014-07-03 |
20140183569 | LED CHIP UNIT AND MANUFACTURING METHOD THEREOF, AND LED MODULE - An LED chip unit and manufacturing method thereof, a LED module, an illuminating device and a display device. The LED chip unit includes a plurality of LED cores which are electrically isolated from each other. The LED chip unit is used for a cutting unit of an epitaxial wafer, so that scraping channels between the LED chip units are only reserved. The area which the space between the adjacent cores occupies is less than the scraping channel, so that utilization ratio of the epitaxial wafer is increased. The cores are integrated and the LED chip unit is packaged on the base plate as a basic unit, so that the cores are packaged on the base plate at a time thereby simplifying packaging. | 2014-07-03 |
20140183570 | Illumination Apparatuses - The present invention provides an illumination apparatus. The illumination apparatus comprises a body having a lower portion coupled to a standard metallic lamp adaptor and an upper portion; a light source module comprising an LED array of LED chips connected in series, a phosphor powder layer encapsulating the LED chips, and a pair of conductive wires electrically connected to the LED chips for transmitting electric power to the LED chips; and a transparent housing coupled to the upper portion of the body, so that the LED chips are enveloped within the transparent housing. | 2014-07-03 |
20140183571 | DISPLAY DEVICE - A display device includes a micro-lens film which has a high fill-factor and a high luminance ratio and prevents generation of moiré. The display device includes a display panel configured to display an image, a plurality of Light Emitting Diodes (LEDs) configured to generate light to supply light to the display panel, a light guide panel configured to guide light to the display panel, and a micro-lens film including a base film that concentrates and diffuses light emitted from the light guide panel, a lens unit at an upper surface of the base film, and a back-coating film at a lower surface of the base film. The lens unit includes unit block groups randomly arranged at the upper surface of the base film, each unit block group containing randomly arranged fixed-shape lenses having different sizes, and micro-beads randomly formed on surfaces of the fixed-shape lenses. | 2014-07-03 |
20140183572 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a plurality of light emitting cells disposed on the substrate to be spaced apart from each other, and a connection wire electrically connecting adjacent ones of the light emitting cells. One of the adjacent light emitting cells includes a plurality of first segments, and the other of the adjacent light emitting cells includes a plurality of second segments respectively facing the first segments. A separation distance is provided between first and second segments facing each other, where each of which has an end contacting the connection wire is greater than a separation distance between first and second segments facing each other, and each of which has an end that does not contact the connection wire. | 2014-07-03 |
20140183573 | LIGHT EMITTING DEVICE - A light emitting device includes a substrate, a plurality of light emitting cells disposed on the substrate to be spaced apart from each other, and a connection wire electrically connecting adjacent ones of the light emitting cells. A first separation distance between first adjacent light emitting cells that are not connected by the connection wire among the light emitting cells is smaller than a second separation distance between second adjacent light emitting cells connected by the connection wire among the light emitting cells. | 2014-07-03 |
20140183574 | LIGHT EMITTING DEVICE PACKAGE, LIGHT EMITTING DEVICE USING THAT PACKAGE, AND ILLUMINATION DEVICE USING THE LIGHT EMITTING DEVICES - The light emitting device package of the present invention has a longitudinal direction (as viewed from above) and a transverse direction perpendicular to the longitudinal direction, and is provided with a first and second lead-frame lined-up in the longitudinal direction and molded resin holds the first and second lead-frames integrally. The package is characterized in that the first lead-frame has a main body and an extension that extends from the main body with a narrowed width towards the second lead-frame. Further, a recess is established in the bottom surface of the first lead-frame, and at least part of the exposed region of the bottom surface of the extension is separated from the exposed region of the bottom surface of the main body by the molded resin that fills the recess. | 2014-07-03 |
20140183575 | LIGHT EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - The light-emitting device has a plurality of light-emitting elements that is mounted on one or more wiring patterns on a substrate. A new light-emitting element that replaces a defective element is mounted on the same wiring pattern on which the defective element is mounted. The defective element or a trace that remains after removal of the defective element is sealed by a same sealing member by which the new light-emitting element is sealed. | 2014-07-03 |
20140183576 | Display Device and Method of Fabricating the Display Device - In an EL element having an anode, an insulating film (bump) formed on the anode, and an EL film and a cathode formed on the insulating film, each of a bottom end portion and a top end portion of the insulating film is formed so as to have a curved surface. The taper angle of a central portion of the insulating film is set within the range from 35° to 70°, thereby preventing the gradient of the film forming surface on which the EL film and the cathode are to be formed from being abruptly changed. On the thus-formed film forming surface, the EL film and the cathode can be formed so as to be uniform in thickness, so that occurrence of discontinuity in each of EL film and the cathode is prevented. | 2014-07-03 |
20140183577 | LIGHT EMITTING DEVICES FOR LIGHT EMITTING DIODES (LEDS) - Light emitting devices for light emitting diodes (LEDs) are disclosed. In one embodiment a light emitting device can include a substrate and a plurality of light emitting diodes (LEDs) disposed over the substrate in patterned arrays. The arrays can include one or more patterns of LEDs. A light emitting device can further include a retention material disposed about the array of LEDs. In one aspect, the retention material can be dispensed. | 2014-07-03 |
20140183578 | ILLUMINATION METHOD AND LIGHT-EMITTING DEVICE - To provide an illumination method and a light-emitting device which are capable of achieving, under an indoor illumination environment where illuminance is around 5000 lx or lower when performing detailed work and generally around 1500 lx or lower, a color appearance or an object appearance as perceived by a person, will be as natural, vivid, highly visible, and comfortable as though perceived outdoors in a high-illuminance environment, regardless of scores of various color rendition metric. Light emitted from the light-emitting device illuminates an object such that light measured at a position of the object satisfies specific requirements. A feature of the light-emitting device is that light emitted by the light-emitting device in a main radiant direction satisfies specific requirements. | 2014-07-03 |
20140183579 | MISCUT SEMIPOLAR OPTOELECTRONIC DEVICE - A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In | 2014-07-03 |
20140183580 | GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND METHOD FOR PRODUCING SAME - A group III nitride semiconductor light-emitting element having a pn junction hetero structure composed of: an n-type aluminum gallium indium nitride layer; a light-emitting layer disposed contacting the n-type aluminum gallium indium nitride layer and including a gallium indium nitride layer containing crystals having a larger lattice constant than the n-type aluminum gallium indium nitride layer; and a p-type aluminum gallium indium nitride layer provided on the light-emitting layer. Further, the relative atomic concentrations of donor impurities at either interface of the light-emitting layer and within respective layers of the light-emitting element are specified herein. | 2014-07-03 |
20140183581 | LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD THEREOF - A light-emitting device comprises a substrate; a first semiconductor layer formed on the substrate; a light-emitting layer on the first semiconductor layer; and a second semiconductor layer having a rough surface formed on the light-emitting layer, wherein the rough surface comprises a plurality of cavities randomly distributed on the rough surface, and one of the plurality of cavities has a substantially hexagonal shape viewed from top and a curved sidewall viewed from cross-section. | 2014-07-03 |
20140183582 | LIGHT EMITTING DIODE PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME - A light emitting diode package includes a light emitting diode, an insulating layer, a plurality of light emitting particles, and a plurality of metal particles. The light emitting diode is configured to emit first light of a first wavelength in a visible light range. The insulating layer is disposed on the light emitting diode. The plurality of light emitting particles is dispersed in the insulating layer and is configured to receive the first light to generate a second light of a second wavelength different from the first wavelength. The plurality of metal particles is dispersed in the insulating layer, and is configured to receive at least one light component of the first light and the second light to cause, at least in part, surface plasmon resonance, the surface plasmon resonance being configured to yield a resonance wave comprising a peak wavelength in the range of the second wavelength. | 2014-07-03 |
20140183583 | WAVELENGTH CONVERTING MATERIAL AND APPLICATION THEREOF - This disclosure discloses a wavelength converting material. The wavelength converting material comprises a plurality of wavelength converting particles, the wavelength converting particles having an average particle size greater than 5 μm, and wherein each of the wavelength converting particles has a particle size. 90% of the wavelength converting particles have the particle size smaller than a μm; 50% of the wavelength converting particles have the particle size smaller than b μm; and 10% of the wavelength converting particles have the particle size smaller than c μm; wherein (a−c)/b≦0.5. | 2014-07-03 |
20140183584 | LED LAMP INCORPORATING REMOTE PHOSPHOR AND DIFFUSER WITH HEAT DISSIPATION FEATURES - LED lamps or bulbs are disclosed that comprise a light source, a heat sink structure and a remote phosphor carrier having at least one conversion material. The phosphor carrier can be remote to the light sources and mounted to the heat sink. The phosphor carrier can have a three-dimensional shape and comprise a thermally conductive transparent material and a phosphor layer, with an LED based light source mounted to the heat sink such that light passes through the phosphor carrier. The phosphor carrier converts at least some of the LED light, with some embodiments emitting a white light combination of LED and phosphor light. The phosphors in the phosphor carriers can operate at a lower temperature to have greater phosphor conversion efficiency and reduced heat related damage. The lamps or bulbs can also comprise a diffuser over the phosphor carrier to distribute light and conceal the phosphor carrier. | 2014-07-03 |
20140183585 | FABRICATION OF OPTICAL ELEMENTS AND MODULES INCORPORATING THE SAME - Fabricating a wafer-scale spacer/optics structure includes replicating optical replication elements and spacer replication sections directly onto an optics wafer (or other wafer) using a single replication tool. The replicated optical elements and spacer elements can be composed of the same or different materials. | 2014-07-03 |
20140183586 | LIGHT EMITTING ELEMENT - A light emitting element includes a semiconductor laminate structure including a first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of a second conductivity type different from the first conductivity type, a part of the second semiconductor layer and the light emitting layer being removed to expose a part of the first semiconductor layer, a first reflecting layer located on the semiconductor laminate structure and including an opening, the opening being formed in the exposed part of the first semiconductor layer, a transparent wiring electrode for carrier injection into the first semiconductor layer or the second semiconductor layer through the opening, and a second reflecting layer formed on the transparent wiring electrode and covering a part of the opening so as to reflect light emitted from the light emitting layer and passing through the opening back to the first semiconductor layer. | 2014-07-03 |
20140183587 | LIGHT EMITTING DIODE PACKAGE - An LED package includes a substrate, an LED chip arranged on the substrate, and a light transmission layer arranged on a light output path of the LED chip. The substrate includes a first electrode and a second electrode separated and electrically insulated from the first electrode. The LED chip is electrically connected to the first electrode and the second electrode of the substrate. The light transmission layer comprises two parallel transparent plates and a fluorescent layer sandwiched between the two transparent plates. The LED package further includes an encapsulation layer sealing the LED chip therein. The light transmission layer is directly located on a top surface of each LED chip, and the encapsulation layer seals the light transmission layer therein. | 2014-07-03 |
20140183588 | LIGHT-EMITTING DIODE AND METHOD OF MANUFACTURING SAME - Provided are a light-emitting diode which prevents degradation of reflectance and which enables high-luminosity light emission, and its manufacturing method. Such a light-emitting diode includes a substrate ( | 2014-07-03 |
20140183589 | METHOD FOR MANUFACTURING A SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT MANUFACTURED THEREBY - There are provided a method of manufacturing a semiconductor light emitting device and a semiconductor light emitting device manufactured thereby. According to an exemplary embodiment, a method of manufacturing a semiconductor light emitting device includes: forming a light emitting structure by sequentially growing a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer on a first main surface of a substrate, the substrate having first and second main surfaces opposing one another; forming a reflective film on the second main surface of the substrate, the reflective film including at least one laser absorption region; and performing a scribing process separating the light emitting structure and the substrate into device units by irradiating a laser from a portion of a top of the light emitting structure corresponding to the laser absorption region to the light emitting structure and the substrate. | 2014-07-03 |
20140183590 | NITRIDE SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME - A nitride semiconductor light emitting device and a method of manufacturing the same are disclosed. The nitride semiconductor light emitting device includes an n-type nitride layer; an active layer formed on the n-type nitride layer; a p-type nitride layer formed on the active layer; a current blocking pattern formed on the p-type nitride layer; a transparent conductive pattern formed to cover upper sides of the p-type nitride layer and the current blocking pattern, and having a contact hole through which a portion of the current blocking pattern is exposed; and a p-electrode pad formed on the current blocking pattern and the transparent conductive pattern, and directly connected to the current blocking pattern. The nitride semiconductor light emitting device can improve long term durability by securing excellent light scattering properties while enhancing adhesion of a p-electrode pad. | 2014-07-03 |
20140183591 | OPTOELECTRONIC PACKAGE AND METHOD OF MANUFACTURING THE SAME - An optoelectronic package includes an optoelectronic chip, a transparent protection layer and a plurality of pads. The optoelectronic chip has an upper surface and an active area defined on the upper surface. The transparent protection layer is connected to the optoelectronic chip and covers the upper surface. The transparent protection layer touches and is entirely attached to the active area. The pads are electrically connected to the optoelectronic chip. | 2014-07-03 |
20140183592 | Optical Device Package and Method of Manufacturing the Same - Provided are an optical device package and a method of manufacturing the same. The method of manufacturing the optical device package according to an exemplary embodiment of the present invention comprises: forming a metal layer on an insulating layer on which via holes are formed; forming a circuit pattern layer by etching the metal layer; forming a boundary part in a predetermined part of the metal layer; mounting an optical device on the circuit pattern layer; and forming a molding part by applying a transparent material to the optical device, wherein the predetermined part is a part corresponding to a boundary of the molding part. | 2014-07-03 |
20140183593 | ENCAPSULATING LAYER-COVERED OPTICAL SEMICONDUCTOR ELEMENT, PRODUCING METHOD THEREOF, AND OPTICAL SEMICONDUCTOR DEVICE - A method for producing an encapsulating layer-covered optical semiconductor element includes a disposing step of disposing an encapsulating layer at one side in a thickness direction of a support and a covering step of, after the disposing step, covering an optical semiconductor element with the encapsulating layer so as to expose one surface thereof to obtain an encapsulating layer-covered optical semiconductor element. | 2014-07-03 |
20140183594 | RADIATION-EMITTING SEMICONDUCTOR CHIP HAVING INTEGRATED ESD PROTECTION - A radiation-emitting semiconductor chip having a semiconductor layer sequence based on a nitride compound semiconductor material and having a pn junction includes a first protective layer having deliberately introduced crystal defects, a second protective layer having a higher doping than the first protective layer, wherein the first protective layer protects the semiconductor chip against electrostatic discharge pulses, an active zone that generates radiation disposed downstream of the first protective layer in a growth direction, wherein during operation of the semiconductor chip, a breakdown behavior of the semiconductor layer sequence in a reverse direction in regions having crystal defects differs from regions without crystal defects, and wherein in the event of electrostatic discharge pulses, electrical charge is dissipated in a homogeneously distributed manner via the regions having crystal defects. | 2014-07-03 |
20140183595 | LIGHT EMITTING DEVICE WITH BONDED INTERFACE - In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device. | 2014-07-03 |
20140183596 | ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE - An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers. | 2014-07-03 |
20140183597 | METAL ALLOY WITH AN ABRUPT INTERFACE TO III-V SEMICONDUCTOR - Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed. | 2014-07-03 |
20140183598 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD OF FORMING THE SAME - A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode. | 2014-07-03 |
20140183599 | Field Effect Transistor - Field effect transistors are provided. An active region protrudes from a substrate and a gate electrode is provided on the active region. Source/drain regions are provided at both sides of the active region under the gate electrode, respectively. A width of a lower portion of the gate electrode is greater than a width of an upper portion of the gate electrode. | 2014-07-03 |
20140183600 | NOVEL FIN STRUCTURE OF FINFET - A fin structure disposed over a substrate and a method of forming a fin structure are disclosed. The fin structure includes a mesa, a channel disposed over the mesa, and a convex-shaped feature disposed between the channel and the mesa. The mesa has a first semiconductor material, and the channel has a second semiconductor material different from the first semiconductor material. The convex-shaped feature is stepped-shaped, stair-shaped, or ladder-shaped. The convex-shaped feature includes a first isolation feature disposed between the channel and the mesa, and a second isolation feature disposed between the channel and the first isolation feature. The first isolation feature is U-shaped, and the second isolation feature is rectangular-shaped. A portion of the second isolation feature is surrounded by the channel and another portion of the second isolation feature is surrounded by the first isolation feature. | 2014-07-03 |
20140183601 | METHOD FOR TRANSFERRING A LAYER OF A SEMICONDUCTOR AND SUBSTRATE COMPRISING A CONFINEMENT STRUCTURE - A method for transferring a layer of semiconductor by providing a donor substrate that includes a useful layer of a semiconductor material, a confinement structure that includes a confinement layer of a semiconductor material having a chemical composition that is different than that of the useful layer, and two protective layers of semiconductor material that is distinct from the confinement layer with the protective layers being arranged on both sides of the confinement layer; introducing ions into the donor substrate, bonding the donor substrate to a receiver substrate, subjecting the donor and receiver substrates to a heat treatment that provides an increase in temperature during which the confinement layer attracts the ions in order to concentrate them in the confinement layer, and detaching the donor substrate from the receiver substrate by breaking the confinement layer. | 2014-07-03 |
20140183602 | ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AREA REDUCTION - An integrated circuit includes a plurality of N wells disposed on a P substrate. A plurality of tap columns is located across the plurality of N wells and a plurality of standard cells is located between the tap columns. A plurality of tap cells is disposed consecutively in the plurality of tap columns. Each tap cell further includes a first tap active and a second tap active. The first tap active of a first tap cell extends to the first tap active of a second tap cell which further extends to a well boundary of either the first tap cell or the second tap cell. The first tap active of the first tap cell and the first tap active of the second tap cell are adjacent to each other in the tap column. | 2014-07-03 |
20140183603 | SIGNAL PATH AND METHOD OF MANUFACTURING A MULTIPLE-PATTERNED SEMICONDUCTOR DEVICE - A multiple-patterned semiconductor device and a method of manufacture are provided. The semiconductor device includes one or more layers with signal tracks. The signal tracks have a quality characteristic. The semiconductor device also includes repeater banks to repower signals. The method of manufacture includes defining portions of layers with photomasks having signal track patterns, determining a quality characteristic of the signal track patterns, and selecting a photomask for etching vias. | 2014-07-03 |
20140183604 | SOLID-STATE IMAGING DEVICE, DRIVING METHOD THEREOF, AND ELECTRONIC DEVICE - A solid-state imaging device including a pixel region in which a plurality of pixels are arranged. The pixels each includes a photoelectric conversion section, a transfer transistor, a plurality of floating diffusion sections receiving a charge from the photoelectric conversion section through the transfer transistor, a reset transistor resetting the floating diffusion sections, a separating transistor performing on-off control of a connection between the plurality of floating diffusion sections, and an amplifying transistor outputting a signal corresponding to a potential of the floating diffusion sections. | 2014-07-03 |
20140183605 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper surface of the epitaxial layer over plurality of fin structures is substantially equal to the height of the upper surface of the epitaxial layer between the plurality of fin structures, and planarizing the upper surface of the epitaxial layer by one of etch back and reflow annealing. | 2014-07-03 |
20140183606 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - According to an embodiment of the invention, there is provided a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming a trench downward from an upper face of a semiconductor layer at a position where an element isolation area is formed in the semiconductor layer, and melting the upper face of the trench-formed semiconductor layer to close an open end of the trench. | 2014-07-03 |
20140183607 | Complementary Metal-Oxide-Semiconductor (CMOS) X-Ray Detector With A Repaired CMOS Pixel Array - A digital X-ray detector includes a scintillator that is configured to absorb radiation emitted from an X-ray radiation source and to emit light photons in response to the absorbed radiation. The detector also includes a complementary metal-oxide-semiconductor (CMOS) light imager that is configured to absorb the light photons emitted by the scintillator. The CMOS light imager includes a first surface and a second surface. The first surface is disposed opposite the second surface. The scintillator contacts the first surface of the CMOS light imager. The CMOS light imager further includes a repaired CMOS pixel array with at least one defective CMOS pixel isolated from a common column data line, a row select scan line, or a rest line within the CMOS pixel array. | 2014-07-03 |
20140183608 | MAGNETIC RANDOM ACCESS MEMORY HAVING PERPENDICULAR ENHANCEMENT LAYER AND INTERFACIAL ANISOTROPIC FREE LAYER - The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto. | 2014-07-03 |
20140183609 | COMPOUND SEMICONDUCTOR ESD PROTECTION DEVICES - The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resister, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor. | 2014-07-03 |
20140183610 | Decoupling Capacitor for FinFET Compatible Process - A decoupling capacitor formed from a fin field-effect transistor (FinFET) and method of using the same are provided. An embodiment decoupling capacitor includes a fin field-effect transistor (FinFET) having a semiconductor substrate supporting a gate stack, a source, and a drain, a first terminal coupled to the semiconductor substrate and to the gate stack, the first terminal configured to couple with a first power rail, and a second terminal coupled to the source and to the drain, the second terminal configured to couple with a second power rail having a higher potential than the first power rail. | 2014-07-03 |
20140183611 | METHOD TO INTEGRATE DIFFERENT FUNCTION DEVICES FABRICATED BY DIFFERENT PROCESS TECHNOLOGIES - The present disclosure is directed to an apparatus and method for manufacture thereof. The apparatus includes a first passive substrate bonded to a second active substrate by a conductive metal interface. The conductive metal interface allows for integration of different function devices at a wafer level. | 2014-07-03 |
20140183612 | NONVOLATILE MEMORY STRUCTURE AND FABRICATION METHOD THEREOF - A nonvolatile memory structure includes a semiconductor substrate having thereon a first oxide define (OD) region, a second OD region and a third OD region arranged in a row. The first, second, and third OD regions are separated from one another by an isolation region. The isolation region includes a first intervening isolation region between the first OD region and the second OD region, and a second intervening isolation region between the second OD region and the third OD region. A select gate transistor is formed on the first OD region. A floating gate transistor is formed on the second OD region. The floating gate transistor is serially coupled to the select gate transistor. The floating gate transistor includes a floating gate that is completely overlapped with the underlying second OD region and is partially overlapped with the first and second intervening isolation regions. | 2014-07-03 |
20140183613 | ELECTRON BLOCKING LAYERS FOR ELECTRONIC DEVICES - Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide, hafnium oxide, and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multi state (e.g., two, three or four bit) operation. | 2014-07-03 |
20140183614 | SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, at least a first gate, a shallow trench isolation (STI) and a third gate. The first gate is disposed on the semiconductor substrate, and the first gate partially overlaps the third gate and the shallow trench isolation. Furthermore, the third gate is disposed in a shallow trench isolation, and the third gate includes at least a protrusion. | 2014-07-03 |
20140183615 | NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS - A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed. | 2014-07-03 |
20140183616 | SEMICONDUCTOR DEVICE INCLUDING A FLOATING GATE - A semiconductor device includes a semiconductor layer with a trench dug downward from its surface, a source region formed on a surface layer portion adjacent to a first side of the trench in a prescribed direction, a drain region formed on the surface layer portion, adjacent to a second side of the trench opposite to the first side in the prescribed direction, a first insulating film on the bottom surface and the side surface of the trench, a floating gate stacked on the first insulating film and opposed to the bottom surface and the side surface of the trench through the first insulating film, a second insulating film formed on the floating gate, and a control gate at least partially embedded in the trench so that the portion embedded in the trench is opposed to the floating gate through the second insulating film. | 2014-07-03 |
20140183617 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND ITS MANUFACTURING METHOD - In a non-volatile semiconductor memory device and a method for manufacturing the device, each memory cell and its select Tr have the same gate insulating film as a Vcc Tr. Further, the gate electrodes of a Vpp Tr and Vcc Tr are realized by the use of a first polysilicon layer. A material such as salicide or a metal, which differs from second polysilicon (which forms a control gate layer), may be provided on the first polysilicon layer. With the above features, a non-volatile semiconductor memory device can be manufactured by reduced steps and be operated at high speed in a reliable manner. | 2014-07-03 |
20140183618 | SEMICONDUCTOR DEVICE - A semiconductor device comprising: at least one strained semiconductor layer to change the probability of an electron tunnelling from a first area to a second area. | 2014-07-03 |
20140183619 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THIN HARD MASK AND STRUCTURE MANUFACTURED BY THE SAME - A method for manufacturing semiconductor device is disclosed. A substrate with a plurality of protruding strips formed vertically thereon is provided. A charging trapping layer is formed conformally on the protruding strips. A conductive layer is formed conformally on the charging trapping layer. A thin hard mask is conformally deposited on the conductive layer, wherein a plurality of trenches are formed between the thin hard mask on the protruding strips. A patterned photo resist is formed on the thin hard mask, wherein the patterned photo resist fills into the trenches. The thin hard mask is patterned according to the patterned photo resist to form a patterned hard mask layer and expose a portion of the conductive layer. The conductive layer is patterned for removing the exposed portion of the conductive layer to form a patterned conductive layer and expose a portion of the charging trapping layer. | 2014-07-03 |
20140183620 | SEMICONDUCTOR DEVICE - A semiconductor substrate of a semiconductor device includes a first conductive body region that is formed in the element region; a second conductive drift region that is formed in the element region; a gate electrode that is formed in the element region, that is arranged in a gate trench, and that faces the body region; an insulating body that is formed in the element region and is arranged between the gate electrode and an inside wall of the gate trench; a first conductive floating region that is formed in the element region and that is surrounded by the drift region; a first voltage-resistance retaining structure that is formed in the peripheral region and that surrounds the element region; and a gate pad that is formed in the peripheral region, and is electrically connected to the gate electrode in a position on the element region-side of the first voltage-resistance retaining structure. | 2014-07-03 |
20140183621 | Charge Compensation Semiconductor Device - A semiconductor device has a source metallization, drain metallization, and semiconductor body. The semiconductor body includes a drift layer of a first conductivity contacted with the drain metallization, a buffer (and field-stop) layer of the first conductivity higher in maximum doping concentration than the drift layer, and a plurality of compensation regions of a second conductivity, each forming a pn-junction with the drift and buffer layers and in contact with the source metallization. Each compensation region includes a first portion between a second portion and the source metallization. The first portions and the drift layer form a first area having a vanishing net doping. The second portions and the buffer layer form a second area of the first conductivity. A space charge region forms in the second area when a reverse voltage of more than 30% of the device breakdown voltage is applied between the drain and source metallizations. | 2014-07-03 |
20140183622 | SCHOTTKY POWER MOSFET - A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode. | 2014-07-03 |
20140183623 | TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN - A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength. | 2014-07-03 |
20140183624 | Adaptive Charge Balanced MOSFET Techniques - An adaptive charge balanced MOSFET device includes a field plate stacks, a gate structure, a source region, a drift region and a body region. The gate structure includes a gate region surrounded by a gate insulator region. The field plate stack includes a plurality of field plate insulator regions, a plurality of field plate regions, and a field ring region. The plurality of field plates are separated from each other by respective field plate insulators. The body region is disposed between the gate structure, the source region, the drift region and the field ring region. Each of two or more field plates are coupled to the field ring. | 2014-07-03 |
20140183625 | Semiconductor Device - A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches. | 2014-07-03 |
20140183626 | DEVICES WITH CAVITY-DEFINED GATES AND METHODS OF MAKING THE SAME - Disclosed are methods, systems and devices, including a method that includes the acts of forming a semiconductor fin, forming a sacrificial material adjacent the semiconductor fin, covering the sacrificial material with a dielectric material, forming a cavity by removing the sacrificial material from under the dielectric material, and forming a gate in the cavity. | 2014-07-03 |
20140183627 | SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD FOR MANUFACTURING - A semiconductor device having an ESD protection structure and a method for forming the semiconductor device. The ESD protection structure is formed atop a termination area of the substrate and is electrically coupled between a source metal and a gate metal of the semiconductor device. The ESD protection structure has a first portion adjacent to the source metal, a second portion adjacent to the gate metal and a middle portion between and connecting the first portion and the second portion, wherein the middle portion has a first thickness greater than a second thickness of the first portion and the second portion. Such an ESD protection structure is beneficial to the formation of interlayer vias which are formed to couple the ESD protection structure to the source metal and the gate metal. | 2014-07-03 |
20140183628 | METAL OXIDE SEMICONDUCTOR DEVICES AND FABRICATION METHODS - A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a raised drain structure above and in contact with the second well and separate from the gate structure. The raised drain structure includes a drain connection point above the surface of the second well. | 2014-07-03 |
20140183629 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a channel region, doped with dopants of a first conductivity type, a source region, a drain region, the source and the drain region being doped with dopants of a second conductivity type different from the first conductivity type, a drain extension region, and a gate electrode adjacent to the channel region. The channel region is disposed in a first portion of a ridge. The drain extension region is disposed in a second portion of the ridge, and includes a core portion doped with the first conductivity type. The drain extension region further includes a cover portion doped with the second conductivity type, the cover portion being adjacent to at least one or two sidewalls of the second portion of the ridge. | 2014-07-03 |
20140183630 | DECMOS FORMED WITH A THROUGH GATE IMPLANT - An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor. | 2014-07-03 |
20140183631 | LOW COST TRANSISTORS - An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate. | 2014-07-03 |
20140183632 | Contact Structure Of Semiconductor Device - The invention relates to a contact structure of a semiconductor device. An exemplary structure for a semiconductor device comprises an insulation region over a substrate; a gate electrode layer over the insulation region comprising a gate middle line; a first contact structure over the insulation region adjacent to the gate electrode layer comprising a first middle line, wherein the first middle line and the gate middle line has a first distance; and a second contact structure over the insulation region on a side of the gate electrode layer opposite to the first contact structure comprising a second middle line, wherein the second middle line and the gate middle line has a second distance greater than the first distance. | 2014-07-03 |
20140183633 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes partially manufacturing a fin field effect transistor (FinFET) including a semiconductor fin comprising a first semiconductive material and a second semiconductive material disposed over the first semiconductive material. A top portion of the second semiconductive material of the semiconductor fin is removed, and a top portion of the first semiconductive material is exposed. A top portion first semiconductive material is removed from beneath the second semiconductive material. The first semiconductive material and the second semiconductive material are oxidized, forming a first oxide comprising a first thickness on the first semiconductive material and a second oxide comprising a second thickness on the second semiconductive material, the first thickness being greater than the second thickness. The second oxide is removed from the second semiconductive material, and manufacturing of the FinFET is completed. | 2014-07-03 |
20140183634 | Thin Film Transistor Short Channel Patterning by Substrate Surface Energy Manipulation - A method is provided for forming a printed top gate thin film transistor (TFT) with a short channel length. The method provides a substrate with a low surface energy top surface. A metal ink line is continuously printed across a region of the substrate top surface, and in response to the surface tension of the printed metal ink, discrete spherical ink caps are formed in the region. Then, the surface energy of the substrate top surface in the region is increased. A source metal ink line is printed overlying a source spherical ink cap contact, and a drain metal ink line, parallel to the source metal ink line, is printed overlying a drain spherical ink cap contact. After depositing a semiconductor film, a channel is formed in the semiconductor film between the source and drain spherical ink cap contacts having a channel length equal to the first distance. | 2014-07-03 |
20140183635 | THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME - A thin film transistor including a first insulating layer disposed on a substrate and having a first hole; a second insulating layer disposed on the substrate and having a second hole; a gate insulating layer disposed between the first and second insulating layers; a gate electrode formed in the first hole; a source electrode and second drain electrode formed at both sides of an inner portion of the second hole; and an activated layer formed between the source electrode and the second drain electrode of the inner portion of the second hole, and having a planarization layer. | 2014-07-03 |
20140183636 | METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SUBSTRATE FOR FORMING SEMICONDUCTOR SUBSTRATE, STACKED SUBSTRATE, SEMICONDUCTOR SUBSTRATE, AND ELECTRONIC DEVICE - Film thickness variations are prevented in a plurality of single crystal semiconductor films separated at a fragile layer reliably and transferred to a base substrate. A method for manufacturing a SOI substrate ( | 2014-07-03 |
20140183637 | STRUCTURE FOR SELF-ALIGNED SILICIDE CONTACTS TO AN UPSIDE-DOWN FET BY EPITAXIAL SOURCE AND DRAIN - An upside-down p-FET is provided on a donor substrate. The upside-down p-FET includes: self-terminating e-SiGe source and drain regions; a cap of self-aligning silicide/germanide over the e-SiGe source and drain regions; a silicon channel region connecting the e-SiGe source and drain regions; buried oxide above the silicon channel region; and a gate controlling current flow from the e-SiGe source region to the e-SiGe drain region. | 2014-07-03 |
20140183638 | METHODS OF USING A TRENCH SALICIDE ROUTING LAYER - Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure. | 2014-07-03 |
20140183639 | ESD PROTECTION STRUCTURE AND SEMICONDUCTOR DEVICE COMPRISING THE SAME - An ESD protection structure and a semiconductor device having an ESD protection structure with the ESD protection structure including a patterned conductive ESD protection layer. The ESD protection layer is patterned to have a first portion of a substantially closed ring shape having an outer contour line and an inner contour line parallel with each other. The outer and the inner contour lines are waved lines. The first portion further has a midline between and parallel with the outer and the inner contour lines. The midline is a waved line having a substantially constant curvature at each point of the midline. Therefore the ESD protection layer has a substantially uniform curvature and an increased perimeter which advantageously improve the breakdown voltage and the current handling capacity of the ESD protection structure. | 2014-07-03 |