27th week of 2015 patent applcation highlights part 58 |
Patent application number | Title | Published |
20150187510 | Electronic Component, Method for Producing Same, and Sealing Material Paste Used in Same - An electronic component has an organic member between two transparent substrates, in which outer peripheral portions of the two transparent substrates are bonded by a sealing material containing to melting glass. The low melting glass contains vanadium oxide, tellurium oxide, iron oxide and phosphoric acid, and satisfies the following relations (1) and (2) in terms of oxides. The sealing material is formed of a sealing material paste which contains the low melting glass, a resin binder and a solvent, the low melting glass containing vanadium oxide, tellurium oxide, iron oxide and phosphoric acid, and satisfies the following relations (1) and (2) in terms of the oxides. Thereby, thermal damages to an organic element or an organic material contained in the electronic component can be reduced and an electronic component having a glass bonding layer of high reliability can be produced efficiently. | 2015-07-02 |
20150187511 | DYE-SENSITIZED SOLAR CELL - Provided is a dye-sensitized solar cell which exhibits excellent heat resistance and high photoelectric conversion efficiency. This dye-sensitized solar cell is provided with: a negative electrode having a semiconductor layer with a pigment as a photosensitizer, an electrolyte layer located on the semiconductor layer of the negative electrode having a paired oxidized species and reduced species, and a positive electrode located on the electrolyte layer having a conductive polymer layer that acts as a catalyst to convert the oxidized species into the reduced species. The conductive polymer layer in the positive electrode contains a polymer derived from at least one monomer selected from the group consisting of 3,4-disubstituted thiophenes; and an anion as a dopant to the polymer generated from at least one organic non-sulfonate compound having an anion with the molecular weight of 200 or more. The thickness of the conductive polymer layer is within the range of 100 to 10000 nm. | 2015-07-02 |
20150187512 | COUNTER ELECTRODE FOR DYE SENSITIZED SOLAR CELL AND DYE SENSITIZED SOLAR CELL - A counter electrode for a dye sensitized solar cell ( | 2015-07-02 |
20150187513 | PHOTOSENSITIZERS, METHOD OF MAKING THEM AND THEIR USE IN PHOTOELECTRIC CONVERSION DEVICES - Disclosed are novel photosensitizers, method of making them, and their use in photoelectric conversion devices such as the Dye Sensitized Solar Cell (DSSC). The photosensitizers have the Formula M(L1) | 2015-07-02 |
20150187514 | COMPOSITION COMPRISING A SPECIFIC IONIC LIQUID - The invention relates to a composition comprising an ionic liquid consisting in the combination of a pyrrolidinium cation and a nitrate anion and comprising a solvent selected from lactone solvents, carbonate solvents, nitrile solvents and mixtures thereof. The composition may be used as an electrolyte, for example, for such applications as energy storage devices. | 2015-07-02 |
20150187515 | CHARGE STORAGE DEVICE, METHOD OF MAKING SAME, METHOD OF MAKING AN ELECTRICALLY CONDUCTIVE STRUCTURE FOR SAME, MOBILE ELECTRONIC DEVICE USING SAME, AND MICROELECTRONIC DEVICE CONTAINING SAME - In one embodiment a charge storage device includes first ( | 2015-07-02 |
20150187516 | BINDER COMPOSITION FOR ELECTRICAL STORAGE DEVICE ELECTRODES, SLURRY FOR ELECTRICAL STORAGE DEVICE ELECTRODES, ELECTRICAL STORAGE DEVICE ELECTRODE, AND ELECTRICAL STORAGE DEVICE - An electrical storage device electrode binder composition includes a polymer (A) and a liquid medium (B), the polymer (A) including a repeating unit (A4) derived from an unsaturated carboxylic acid in an amount of 5 to 40 parts by mass based on 100 parts by mass of the total repeating units included in the polymer (A), the polymer (A) being polymer particles, and the polymer particles having a surface acid content of more than 1 mmol/g and 6 mmol/g or less. | 2015-07-02 |
20150187517 | STRUCTURAL COMPOSITE BATTERY WITH FLUIDIC PORT FOR ELECTROLYTE - According to the invention there is provided a fluidic port ( | 2015-07-02 |
20150187518 | SECTIONALIZED CONTACT CONTACTOR - Described herein are contactors comprising one or more split or otherwise sectionalized contacts. By comprising split contacts, contactors incorporating features of the present invention increase the number of electrical contact sites between the split contactor and another contactor, allowing current to flow through multiple sites and preventing or mitigating the formation of magnetic fields, harmonic resonance and resulting vibration and noise production. In some embodiments, the contactors comprise at least one bifurcated (split in two) moveable contact and at least one fixed contact. The bifurcated contact can be configured such that it can be easily manipulated as if it were a singular contact, while simultaneously providing the advantages of a bifurcated one. | 2015-07-02 |
20150187519 | SWITCH CONTACT WETTING WITH LOW PEAK INSTANTANEOUS CURRENT DRAW - A contact wetting circuit | 2015-07-02 |
20150187520 | CLUTCH DEVICE OF GEAR TRANSMISSION SYSTEM OF CIRCUIT BREAKER SPRING OPERATING MECHANISM - A clutch device of a gear transmission system of a circuit-breaker spring operating mechanism includes an energy storage shaft, a large gear, and a small gear. At an energy storage holding position of the large gear, a toothless and special teeth area is arranged corresponding to the small gear. A clutch cam is provided in a cavity in the large gear at the area and a backward extended part and may be reset by a resetting spring. In the area, the large gear includes a first special tooth, a second special tooth, and a space between the first and second special teeth. When energy storage is completed, the small gear pushes the first special tooth to push the large gear and energy storage shaft to the energy storage holding position that is away from a friction dead zone, and the small gear is automatically disengaged from the large gear. | 2015-07-02 |
20150187521 | ROTARY ENCODER SWITCH - A rotary encoder switch includes a cover cap, a fixing sleeve, a first base board, an actuating device, and a second base board disposed under the actuating device. The actuating device includes a base seat and a rotary element rotatably connected to the base seat and mounted to the cover cap. The first base board is disposed on the actuating device and has multiple first lighting elements. The rotary element is rotatable in conjunction with rotation of the cover cap so as to generate encoding signals according to each rotary position of the cover cap for controlling functions of an applied product. The first lighting elements are capable of emitting light in sequence subject to the rotation of the cover cap, while the light being emitted is permeable to the cover cap for users to easily recognize the exact rotary position of the cover cap. | 2015-07-02 |
20150187522 | ELECTROMAGNETIC SWITCHING DEVICE - Disclosed is an electromagnetic switching device, including: a junction box having an accommodating space formed to be one side open by side plates and a bottom plate; and a relay having fixed contacts and movable contacts within an casing and detachable to and/or from the accommodating space, wherein the junction box includes a pair of protrusions which are protruded from the side plates to an opposite side to the accommodating space; wherein the relay includes a lever which is hinge-coupled to the casing and caught by the pair of protrusions; and wherein the lever is configured to press the relay toward the bottom plate when rotating in one direction, and to press the relay toward a direction to become distant from the bottom plate when rotating in opposite direction, thereby enabling the relay to be easily detachable from the junction box. | 2015-07-02 |
20150187523 | SYSTEM CABLING FOR A MULTIPLE RELAY ARRANGEMENT - A multiple relay arrangement having a plurality of relay sockets which are arranged next to each other and a plurality of relays. The relay sockets contain additional plug connections with which the relays are controlled by the system cabling. The system cabling contains a distribution section having cable sections and plug connectors and allows the plurality of relays to be controlled. | 2015-07-02 |
20150187524 | SAFETY RELAY CONFIGURATION SYSTEM WITH MULTIPLE TEST PULSE SCHEMES - A safety relay configuration system for configuring safety functions to be carried out by a safety relay is provided. The configuration system comprises a number of features that facilitate intuitive and simplified configuration of an industrial safety relay, including but not limited to features that guide the user through the configuration process using an intuitive sequential procedure that provides feedback and prompts based on user interaction, enforce design consistency throughout the configuration project by intelligently limiting user selections, and visually organize configuration and status information in a manner that efficiently utilizes display space and allows the user to quickly evaluate available configuration options. | 2015-07-02 |
20150187525 | ELECTRICAL SWITCHING APPARATUS AND RELAY INCLUDING A FERROMAGNETIC OR MAGNETIC ARMATURE HAVING A TAPERED PORTION - An electrical switching apparatus includes a ferromagnetic frame having first and opposite second portions, a ferromagnetic core disposed therebetween, a permanent magnet disposed on the first portion, a first tapered portion on the opposite second portion; a coil disposed about the core; and a ferromagnetic or magnetic armature including a first portion, an opposite second portion and a pivot portion pivotally disposed on the core between the portions of the armature. The armature opposite second portion has a complementary second tapered portion therein. In a first armature position, the armature first portion is magnetically attracted by the permanent magnet and the first and second tapered portions are moved apart with the coil de-energized. In a second armature position, the armature opposite second portion is magnetically attracted by the opposite second portion of the frame and the first tapered portion is moved into the second tapered portion with the coil energized. | 2015-07-02 |
20150187526 | ELECTROMAGNETIC RELAY - An electromagnetic relay including an electromagnet, a movable contact actuated by the electromagnet, and a fixed contact disposed opposite to the movable contact and capable of contacting and separating from the movable contact. The electromagnetic relay further includes a backstop for stopping movement of the movable contact in a direction separating from the fixed contact, and a backstop positioner for setting the backstop at a position for defining a predetermined contact gap between the fixed contact and the movable contact. In a state where movement of the movable contact is stopped by the backstop, different-sized contact gaps are defined between the fixed contact and the movable contact, depending on the position of the backstop set by the backstop positioner. | 2015-07-02 |
20150187527 | ELECTROMAGNETIC RELAY - An electromagnetic relay includes a fixed contact, a movable contact corresponding to the fixed contact, a movable element that retains the movable contact and moves in a contacting direction and a separating direction relative to the fixed contact, an axial core coupled to the movable element, a movable core coupled to the axial core to move in the contacting direction and the separating direction relative to a movement of the axial core, a driving part that drives the movable core in the contacting direction, an urging part that exerts force to the axial core in the separating direction, and a constraining part that constrains the relative movement of the axial core in the separating direction. | 2015-07-02 |
20150187528 | Mechanical Latching Relays and Hybrid Switches with Latching Relays for Use in Electrical Automation - Method and apparatus for a mechanical latching of at least one pole of a relay selected from SPST, SPDT, DPDT, reversing DPDT, multi pole MPST and MPDT including the integration of one of a single and plurality of hybrid SPDT or DPDT switches with one of SPDT and DPDT mechanically latching relay using springy element to maintain the contacts between the poles and one of the relay contact and a structured contactors to connect the poles of the relay and the switch including PCB assembly, for operating electrical loads via the switch manual key including the introduction of a key-plunger combination into the latching relay and remotely by powering the relay coil by a power pulse, including a CPU program for providing any of the manual keys of each SPDT or DPDT connected in a traveler lines to the integrated switch-relay to switch on-off group of loads and all the loads of home automation network or grid via optical cable, RF, IR in line of sight and bus line. | 2015-07-02 |
20150187529 | FUSE ELEMENT - A fuse element, in particular suited for use in electric and/or electronic circuits constructed by multilayer technology, including a printed circuit board substrate material, which is usable particularly in the multilayer technology and is coated with a metal or metal alloy from which the fuse is generated by means of photolithographic and/or printing image-producing techniques and ensuing etching or engraving processes, is proposed. The fuse is distinguished in that the printed circuit board substrate material, on which the fuse can be provided, includes at least a high-temperature-stable, electrically insulating material, with a coefficient of thermal expansion that varies essentially analogously to the coefficient of thermal expansion of the metal or metal alloy from which the fuse is made. | 2015-07-02 |
20150187530 | X-RAY TUBE HAVING PLANAR EMITTER WITH TUNABLE EMISSION CHARACTERISTICS - An electron emitter can include: a plurality of elongate rungs connected together end to end from a first emitter end to a second emitter end in a plane so as to form a planar pattern; a plurality of corners, wherein each elongate rung is connected to another elongate rung through a corner having a corner apex and an opposite corner nadir; a first gap between adjacent non-connected elongate rungs, wherein the first gap extends from the first emitter end to a middle rung; a second gap between adjacent non-connected elongate rungs, wherein the second gap extends from the second emitter end to the middle rung, wherein the first gap does not intersect the second gap; and one or more cutouts at one or more of the corners of the plurality of corners between the corner apex and corner nadir or at the corner nadir. | 2015-07-02 |
20150187531 | High Voltage High Current Vacuum Integrated Circuit - A high voltage, high current vacuum integrated circuit includes a common vacuum enclosure that includes at least two cold-cathode field emission electron tubes, and contains at least one internal vacuum pumping means, at least one exhaust tubulation, vacuum-sealed electrically-insulated feedthroughs, and internal electrical insulation. The cold-cathode field emission electron tubes are configured to operate at high voltage and high current and interconnected with each other to implement a circuit function. | 2015-07-02 |
20150187532 | FILM TARGET FOR LASER-INDUCED PARTICLE ACCELERATION AND METHOD OF MANUFACTURING THE SAME - A film target for laser-induced particle acceleration includes a first target layer on which a laser is incident; an intermediate layer located behind the first target layer along a propagating direction of the laser, and in which an intended ion beam is generated; and a second target layer located opposite to the first target layer with the intermediate layer interposed therebetween. | 2015-07-02 |
20150187533 | Cathode arrangement, electron gun, and lithography system comprising such electron gun - The invention relates to a cathode arrangement comprising:
| 2015-07-02 |
20150187534 | ELECTRON EMISSION SURFACE FOR X-RAY GENERATION - Embodiments of the disclosure relate to electron emitters for use in conjunction with X-ray emitting devices. In certain embodiments the emitter includes features that prevent, limit, or control deflection of the electron emitter at operating temperatures. In this manner, the electron emitter may be kept substantially flat or at a desired curvature during operation. | 2015-07-02 |
20150187535 | X-RAY GENERATING APPARATUS AND X-RAY FLUOROSCOPYIMAGING SYSTEM EQUIPPED WITH THE SAME - The present invention provides an X-ray generating apparatus and an X-ray fluoroscopy imaging system comprising the same. The X-ray generating apparatus comprises: an electron accelerator including an electron acceleration unit, an electron emission unit, and a target; a shielding and collimating device, including a shielding structure and a collimator arranged in the shielding structure, wherein the target is surrounded by the shielding structure, the collimator is arranged in a direction passing through the target point and forming an angle from 30 degrees to 150 degrees with the electron beam shooting the target. | 2015-07-02 |
20150187536 | X-RAY TUBE HAVING PLANAR EMITTER AND MAGNETIC FOCUSING AND STEERING COMPONENTS - An X-ray tube can include: a cathode planar emitter that emits an inhomogeneous electron beam; an anode to receive the electron beam; a first magnetic quadrupole having a first yoke with four evenly distributed first pole projections extending from the first yoke and oriented toward a central axis of the first yoke and each of the four first pole projections having a first quadrupole electromagnetic coil; a second magnetic quadrupole having a second yoke with four evenly distributed second pole projections extending from the second yoke and oriented toward a central axis of the second yoke and each of the four second pole projections having a second quadrupole electromagnetic coil; and at least one coil of a first pair of opposing coils with alternating current offset from the power supply. | 2015-07-02 |
20150187537 | X-RAY TUBE HAVING MAGNETIC QUADRUPOLES FOR FOCUSING AND STEERING - An X-ray tube comprising: a cathode including an emitter; an anode; a first magnetic quadrupole formed on a first yoke and having a magnetic quadrupole gradient for focusing an electron beam in a first direction and defocusing the beam in a second direction; a second magnetic quadrupole formed on a second yoke and having a magnetic quadrupole gradient for focusing the electron beam in the second direction and defocusing the electron beam in the first direction; wherein a combination of the first and second magnetic quadrupoles provides a net focusing effect in both first and second directions of a focal spot of the electron beam; and a pair of opposing quadrupole electromagnetic coils having alternating current offset being configured to deflect the electron beam in order to shift the focal spot of the electron beam on a target. | 2015-07-02 |
20150187538 | X-RAY TUBE HAVING MAGNETIC QUADRUPOLES FOR FOCUSING AND COLLOCATED STEERING COILS FOR STEERING - An X-ray tube can include: a cathode including an electron emitter that emits an electron beam; an anode configured to receive the electron beam; a first magnetic quadrupole between the cathode and the anode and having a first yoke with four first pole projections extending from the first yoke and oriented toward a central axis of the first yoke and each of the four first pole projections having a first quadrupole electromagnetic coil; a second magnetic quadrupole between the first magnetic quadrupole and the anode and having a second yoke with four second pole projections extending from the second yoke and oriented toward a central axis of the second yoke and each of the four second pole projections having a second quadrupole electromagnetic coil; and at least one steering coil collocated with a quadrupole on a pole projection. | 2015-07-02 |
20150187539 | SPARK GAP - A spark gap comprising a cathode and an anode is provided. The spark gap is divided into two partial spark gaps by means of a central piece, namely a high-pressure spark gap and an effective spark gap. The effective spark gap can for example, be used to generate monochromatic x-rays. In order to guarantee a defined switching time, the high pressure spark gap which is initially switched to defined, is used. The switching initiates a potential so high on the centre piece that, when the high pressure spark gap is switched, the effective spark gap can also be switched in a defined manner without significant delays, to a visibly higher voltage. | 2015-07-02 |
20150187540 | DRAWING APPARATUS AND METHOD OF MANUFACTURING ARTICLE - A drawing apparatus includes a plurality of optical systems, each of which irradiates with a beam a substrate, corresponding thereto, having a predetermined size, and a plurality of holders, each of which is movable and holds the substrate corresponding thereto. The drawing apparatus is configured to perform drawing on a plurality of the substrate respectively held by the plurality of holders with respective beams respectively by the plurality of optical systems with the plurality of holders being scanned relative to the plurality of optical systems in a scan direction, and in a direction orthogonal to the scan direction, an interval between two adjacent optical systems of the plurality of optical systems is smaller than a sum of a length of one of the plurality of holders and the size. | 2015-07-02 |
20150187541 | Cathode arrangement, electron gun, and lithography system comprising such electron gun - The invention relates to a cathode arrangement comprising:
| 2015-07-02 |
20150187542 | SUBSTRATE PROCESSING APPARATUS, SHUTTER DEVICE AND PLASMA PROCESSING APPARATUS - Abnormal discharge is suppressed from occurring within a chamber. A plasma processing apparatus | 2015-07-02 |
20150187543 | PLASMA EQUIPMENT FOR TREATING POWDER - A powder plasma processing apparatus is disclosed. The powder plasma processing apparatus includes: a chamber configured to perform plasma processing on a powder; a powder supply unit disposed in an upper portion of the chamber; and a plurality of plate-like surface discharge plasma modules disposed below the powder supply unit and positioned within the chamber, wherein surfaces of the surface discharge plasma modules are spaced apart from each other. According to the powder plasma processing apparatus, the powder can be uniformly processed, and the time that the powder spends in contact with the plasma can be controlled, thereby allowing efficient powder processing to be performed. | 2015-07-02 |
20150187544 | Plasma Block for Remote Plasma Source - Provided is plasma block for a remote plasma source, and more particularly, is a plasma block that induces plasma to be generated and to flow between a remote plasma source and a vacuum chamber during a cleaning process performed on the vacuum chamber by the remote plasma source. The plasma block includes an external connection path and an internal connection path, which are formed as two sub-blocks connected to each other are combined, wherein the internal connection path includes a linear extending portion that extends in a straight line along a length direction of the internal connection path, and a curve extending portion that extends in a curve to form a curved surface based on a location where the internal connection path and the external connection path contact each other, wherein the curve extending portion has a spherical surface of a complex spherical surface. | 2015-07-02 |
20150187545 | SUBSTRATE TREATING APPARATUS AND METHOD - Provided is a substrate processing apparatus. The substrate treating apparatus includes a processing chamber, a substrate supporting unit, a plasma generation unit, a gas supplying unit, an exhaust adjusting unit, or the like. Residual gas and reaction by-products are generated in a chamber after a substrate is treated by using a gas supplied from the gas supplying unit or plasma excited by the plasma generation unit. The gas exhaust adjusting unit adjusts discharge amounts of residual gas and reaction by-products to adjust residence time or pressure of gas, plasma, or the like in the apparatus, thereby controlling a uniformity of the substrate treating process. | 2015-07-02 |
20150187546 | Vacuum-Processing Apparatus, Vacuum-Processing Method, and Storage Medium - The present disclosure provides a vacuum-processing apparatus for forming a metal film on a substrate by sputtering targets with ions of plasma, and then oxidizing the metal film, the apparatus including: a first target composed of a material having a property of adsorbing oxygen; a second target composed of a metal; a power supply unit configured to apply a voltage to the targets; a shutter configured to prevent particles generated from one of the targets from adhering to the other of the targets; a shielding member; an oxygen supply unit configured to supply an oxygen-containing gas to the substrate mounted on the mounting unit; and a control unit configured to perform supplying a plasma-generating voltage to the targets and sputtering the targets and supplying the oxygen-containing gas from the oxygen supply unit to the substrate. | 2015-07-02 |
20150187547 | FILM DEPOSITION DEVICE - A film deposition device is disclosed. The device includes a driver, a sputtering target assembly, and at least one rotatable magnetoelectric device located at the back of the sputtering target assembly. The rotatable magnetoelectric device includes a transmission having a conveyor belt, and at least one pair of gears which cooperate with the conveyor belt and are disposed at an inner side of the conveyor belt, where an axial direction of the gears is substantially parallel to a surface of the sputtering target assembly. The rotatable magnetoelectric device also includes a first set of magnets, where the first set of magnets are disposed outside of the conveyor belt. In addition, the driver is configured to cause the gears to rotate. | 2015-07-02 |
20150187548 | COMPOSITE OXIDE SINTERED BODY AND OXIDE TRANSPARENT CONDUCTIVE FILM - To provide a composite oxide sintered body from which an oxide transparent conductive film having lower light absorption properties in a wide wavelength region and having a low resistance can be obtained, and an oxide transparent conductive film. A composite oxide sintered body containing indium, zirconium, hafnium and oxygen, wherein the atomic ratio of the elements constituting the sintered body satisfies the following formulae, where In, Zr and Hf are respectively contents of indium, zirconium and hafnium: | 2015-07-02 |
20150187549 | MAGNETRON SPUTTERING APPARATUS - To provide technology that can increase the productivity of an apparatus when magnetron sputtering is carried out using a target formed from magnetic material. The present disclosure is an apparatus provided with: a cylindrical body that is a target formed from magnetic material, disposed above a substrate; a rotating mechanism that rotates this cylindrical body around the axis of the cylindrical body; a magnet array provided inside a hollow part of the cylindrical body; and a power supply that applies voltage to the cylindrical body. Furthermore, the magnet array has a cross sectional profile, orthogonal to the axis of the cylindrical body. Thus, even if a target with a comparatively large thickness is used, reductions in the intensity of the magnetic field that leaks from the target can be suppressed, and local progress in erosion can be suppressed. | 2015-07-02 |
20150187550 | ELECTRON MULTIPLIER FOR MASS SPECTROMETER - A secondary electron multiplier includes: a conversion dynode for emitting a secondary electron in response to an incident ion; a plurality of dynodes configured to have multi-stages from second to final stages for receiving the secondary electron; and a first voltage applying device for applying a first negative voltage to the conversion dynode and sequentially dividing the first negative voltage to apply to each of the second-stage and subsequent dynodes, wherein the secondary electron multiplier is configured to sequentially multiply the emitted secondary electron by the second-stage and subsequent dynodes. In the secondary electron multiplier, any of the second-stage and subsequent dynodes have a second voltage applying device for applying a second negative voltage. The secondary electron multiplier has an improved ion detection efficiency without a large reduction of a usable period thereof, thereby enhancing the sensitivity of a mass spectrometer. | 2015-07-02 |
20150187551 | PHOTOMULTIPLIER AND SENSOR MODULE - A photomultiplier according to an embodiment of the present invention has a sealed container the interior of which is maintained in a vacuum state, and an electron multiplier unit housed in the sealed container, and the sealed container is partly constructed of ceramic side tubes, on the assumption that the photomultiplier is used under high-temperature, high-pressure environments. The photomultiplier further has a structure for fixing an installation position of the electron multiplier unit relative to the sealed container, for improvement in anti-vibration performance. | 2015-07-02 |
20150187552 | HIGH VOLTAGE POWER SUPPLY FILTER - Systems, devices, circuits, and methods are provided for an improved mass spectrometry detection system that comprises at least one component that operates at a high voltage. A number of high voltage filters or circuits are provided for reducing noise from high voltage power supplies that produce positive and negative voltages. In some embodiments, the filters can comprise one or more diodes. In some embodiments, the filters can comprise one or more transistors. In some embodiments, the filters can comprise one or more transistor pairs. A variety of embodiments of systems, devices, circuits, and methods in conjunction with the disclosures are provided. | 2015-07-02 |
20150187553 | MASS SPECTROMETRY DATA DISPLAY DEVICE AND MASS SPECTROMETRY DATA DISPLAY PROGRAM - A mass spectrometry data display device in which the mass axis (m/z axis) is made into a ring shape and the intensity axis is the radial direction thereof, and peak information (in the drawing, the compound name and structural formula candidates) are arranged in a ring shape in correspondence with the peaks along the outer circumference of the mass spectrum and displayed together therewith on a screen. | 2015-07-02 |
20150187554 | MASS SPECTROMETER - Provided is a mass spectrometer capable of easy exchange of a measurement sample and suppressing a carryover. The mass spectrometer includes a mass spectrometry section, an ion source the internal pressure of which is reduced by a differential pumping from the mass spectrometry section and the ion source ionizes the sample gas, a sample container in which the sample gas is generated by vaporizing the measurement sample, a thin pipe that introduces the sample gas generated in the sample container into the ion source, an elastic tube of openable and closable that connects the sample container and the thin pipe, a pair of weirs that closes or opens the elastic tube so as to sandwich the elastic tube, and a cartridge that integrates the sample container, the thin pipe, and the elastic tube, and is detachable in a lump from a main body of the mass spectrometer. | 2015-07-02 |
20150187555 | ION OPTICAL SYSTEM FOR MASS SPECTROMETER - A mass spectrometer includes: a plasma generation device for generating plasma for ionizing an introduced sample; an interface device for drawing the plasma into vacuum; an ion lens device for extracting and inducing ions as an ion beam from the plasma; a collision/reaction cell for removing an interference ion from the ion beam; a mass analyzer or filter for allowing a predetermined ion in the ion beam from the collision/reaction cell to pass along a first axis based on a mass-to-charge ratio; an ion detector for detecting the ion; an ion deflection device before the mass analyzer, and also an ion deflection device between the mass analyzer and the ion detector. The mass spectrometer reduces background noises in a mass analyzer by removing neutral particles from the ion beam without reducing the measurement sensitivity on ions to be analyzed as much as possible. | 2015-07-02 |
20150187556 | METHOD TO GENERATE DATA ACQUISITION METHOD OF MASS SPECTROMETRY - A process for automatically creating a measurement method suitable for plasma ion source mass spectrometry, including: semi-quantitatively measuring all elements in the sample that affect the measurement; determining a plasma condition based on the total concentration of the semi-quantitatively measured elements; for each of the semi-quantitatively measured elements, estimating signal strengths of the element and an interference component in the sample to be measured and based on the resultant estimates, estimating the concentration of the element; and, based on the estimated signal strengths of the elements and the interference components and the estimated concentrations of the elements, creating at least one mass spectrometry method including at least one of: (1) a plasma condition; (2) an internal standard to be added to the sample; (3) a tuning condition for the collision/reaction cell; (4) a mass-to-charge ratio used in the mass spectrometer; and (5) an integration time used in the mass spectrometer. | 2015-07-02 |
20150187557 | ELECTRON SOURCE FOR AN RF-FREE ELECTRONMAGNETOSTATIC ELECTRON-INDUCED DISSOCIATION CELL AND USE IN A TANDEM MASS SPECTROMETER - An electron source for electron-induced dissociation in an RF-free electromagnetostatic cell for use installation in a tandem mass spectrometer is provided. An electromagnetostatic electron-induced dissociation cell may include at least one magnet having an opening disposed therein and having a longitudinal axis extending through the opening, the magnet having magnetic flux lines associated therewith, and an electron emitter having an electron emissive surface comprising a sheet, the emitter disposed about the axis at a location relative to the magnet where the electron emissive surface is substantially perpendicular to the magnetic flux lines at the electron emissive surface. | 2015-07-02 |
20150187558 | PULSE-BURST ASSISTED ELECTROSPRAY IONIZATION MASS SPECTROMETER - The present invention relates to a mass spectrometer system, which combines laser desorption with pulse bursts comprising a train of ultrashort pulses and electrospray ionization. The pulse separation between individual pulses within the pulse burst is selected such that transient phenomena on an irradiated sample do not fully relax between individual pulses. Pulses with pulse widths ranging from fs to sub ns are conveniently implemented. The pulse widths can be selected to allow for multi-photon excitation of a sample while at the same time minimizing heat accumulation in a sample. Low cost laser systems such as fiber lasers can be configured to generate appropriate pulse bursts. The technique is suitable for mass spectrometry imaging with high spatial resolution. The laser system can serve as an electronic clock to which the whole mass spectrometry system or mass spectrometry imaging system is synchronized. | 2015-07-02 |
20150187559 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM - A method of manufacturing a semiconductor device includes forming a laminated film on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first film which contains a predetermined element, boron, and nitrogen and which does not contain a borazine ring skeleton, and forming a second film which contains the predetermined element and a borazine ring skeleton. The first film and the second film are laminated to form the laminated film. | 2015-07-02 |
20150187560 | Cyclic Deposition Method for Thin Film Formation, Semiconductor Manufacturing Method, and Semiconductor Device - A cyclic deposition method for thin film formation includes forming a silicon thin film on an object by injecting a silicon precursor into a chamber in which the object is loaded, depositing silicon on the object, and performing a first purge, removing an unreacted portion of the silicon precursor and reaction by-products from the interior of the chamber, pre-processing a surface of the silicon thin film by forming a plasma atmosphere in the chamber and supplying a first reaction source having a hydrogen atom, and forming the silicon thin film as an insulating film including silicon, by forming the plasma atmosphere in the chamber and supplying a second reaction source having one or more oxygen atoms, one or more nitrogen atoms, or a mixture thereof. | 2015-07-02 |
20150187561 | METHOD AND APPARATUS FOR LIQUID TREATMENT OF WAFER SHAPED ARTICLES - In an apparatus and method for treating a wafer-shaped article, a spin chuck is provided for holding and rotating a wafer-shaped article. A first liquid dispenser communicates with a supply of an organic liquid and is positioned so as to dispense the organic liquid onto a surface of a wafer-shaped article. A degasifying unit is positioned upstream of the first liquid dispenser and downstream of the supply. The degasifying unit is configured to reduce a dissolved gas content of the organic liquid to less than 20% of a saturation concentration at a pressure of 1 bar. | 2015-07-02 |
20150187562 | ABATEMENT WATER FLOW CONTROL SYSTEM AND OPERATION METHOD THEREOF - A system including a water flow controller arranged to transmit electrical signals between a fluoride ion clean tool and a fluoride emission abatement system is provided. Fluoride gas is configured to be released from the fluoride ion clean tool and lead to the fluoride emission abatement system, and water is introduced to the fluoride emission abatement system so as to process the fluoride gas. The water flow controller further includes a receiver for accepting electrical signals from a detector. The detector is configured to measure a flow rate of fluoride gas introduced to the fluoride ion clean tool. In addition, a computing unit is configured to process electrical signals from the detector. A transmitter is configured to send commands to an actuator of the fluoride emission abatement system so as to adjust water introduced to the fluoride emission abatement system based on a processing result of the computing unit. | 2015-07-02 |
20150187563 | PHOTO-ASSISTED DEPOSITION OF FLOWABLE FILMS - A method and apparatus for forming a flowable film are described. The method includes providing an oxygen free precursor gas mixture to a processing chamber containing a substrate. The oxygen free precursor gas is activated by exposure to UV radiation in the processing chamber. Molecular fragments resulting from the UV activation are encouraged to deposit on the substrate to form a flowable film on the substrate. The substrate may be cooled to encourage deposition. The film may be hardened by heating and/or by further exposure to UV radiation. | 2015-07-02 |
20150187564 | METHOD OF USING A VAPORIZING SPRAY SYSTEM TO PERFORM A TRIMMING PROCESS - A method of semiconductor device fabrication including placing a substrate having a first and second features disposed thereon in a vaporizing spray deposition system. An atomizing spray head of the vaporizing spray deposition system is used to deposit a conformal polymer layer on the first and second features. The first feature having the layer of the polymer disposed thereon and having a first width. A spray trim process is performed on the first and second features having the polymer layer disposed thereon using the atomizing spray head. | 2015-07-02 |
20150187565 | Gap Filling Materials and Methods - In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure. | 2015-07-02 |
20150187566 | HARDMASK COMPOSITION, METHOD OF FORMING PATTERNS USING THE HARDMASK COMPOSITION AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE INCLUDING THE PATTERNS - A hardmask composition includes a polymer including a moiety represented by one of the following Chemical Formulae 1a to 1c, a monomer represented by the following Chemical Formula 2 and a solvent. | 2015-07-02 |
20150187567 | SUBSTRATE PROCESSING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM - A substrate processing apparatus processes a substrate by supplying a gas into a processing space. The apparatus includes a buffer space wherein the gas is dispersed, the buffer space disposed at an upstream side of the processing space; a transfer space where the substrate passes when transferred to the processing space; a first, a second and a third exhaust pipe connected to the transfer space, the buffer space and the processing space, respectively; a fourth exhaust pipe connected to downstream sides of the first exhaust pipe, the second exhaust pipe and the third exhaust pipe; a first vacuum pump disposed at the first exhaust pipe; a second vacuum pump disposed at the fourth exhaust pipe; a first valve disposed at the first exhaust pipe at a downstream side of the first vacuum pump; and a second and a third valve disposed at the second and the third exhaust pipe, respectively. | 2015-07-02 |
20150187568 | PROCESS FEED MANAGEMENT FOR SEMICONDUCTOR SUBSTRATE PROCESSING - Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided. The example gas channel plate includes a heat exchange surface including a plurality of heat exchange structures separated from one another by intervening gaps. The example gas channel plate also includes a heat exchange fluid director plate support surface for supporting a heat exchange fluid director plate above the plurality of heat exchange structures so that at least a portion of the plurality of heat exchange structures are spaced from the heat exchange fluid director plate. | 2015-07-02 |
20150187569 | METHOD FOR PRODUCING FERROELECTRIC THIN FILM - A method for producing a ferroelectric thin film comprising: coating a composition for forming a ferroelectric thin film on a base electrode of a substrate having a substrate body and the base electrode that has crystal faces oriented in the (111) direction, calcining the coated composition, and subsequently performing firing the coated composition to crystallize the coated composition, and thereby forming a ferroelectric thin film on the base electrode, wherein the method includes formation of a orientation controlling layer b coating the composition on the base electrode, calcining the coated composition, and firing the coated composition, where an amount of the composition coated on the base electrode is controlled such that a thickness of the orientation controlling layer after crystallization is in a range of 35 nm to 150 nm, and thereby controlling the preferential crystal orientation of the orientation controlling layer in the (100) plane. | 2015-07-02 |
20150187570 | PROCESS FOR FORMING PZT OR PLZT THINFILMS WITH LOW DEFECTIVITY - Use of a non-solvent for the edge bead removal of spin-coated PZT or PLZT thinfilms, eliminates swelling of the exposed edges of the PZT or PLZT thinfilms and eliminates delamination and formation of particle defects in subsequent bake and anneal steps. | 2015-07-02 |
20150187571 | Germanium-Containing FinFET and Methods for Forming the Same - A method includes forming isolation regions in a semiconductor substrate, forming a first semiconductor strip between opposite portions of isolation regions, forming a second semiconductor strip overlying and contacting the first semiconductor strip, and performing a first recessing to recess the isolation regions. A portion of the second semiconductor strip over top surfaces of remaining portions of the isolation regions forms a semiconductor fin. A second recessing is performed to recess the isolation regions to extend the semiconductor fin downwardly, with an inter-diffusion region of the first semiconductor strip and the second semiconductor strip being exposed after the second recessing. The inter-diffusion region is then etched. | 2015-07-02 |
20150187572 | INTERLAYER DESIGN FOR EPITAXIAL GROWTH OF SEMICONDUCTOR LAYERS - An interlayer structure that, in one implementation, includes a combination of an amorphous or nano-crystalline seed-layer, and one or more metallic layers, deposited on the seed layer, with the fcc, hcp or bcc crystal structure is used to epitaxially orient a semiconductor layer on top of non-single-crystal substrates. In some implementations, this interlayer structure is used to establish epitaxial growth of multiple semiconductor layers, combinations of semiconductor and oxide layers, combinations of semiconductor and metal layers and combination of semiconductor, oxide and metal layers. This interlayer structure can also be used for epitaxial growth of p-type and n-type semiconductors in photovoltaic cells. | 2015-07-02 |
20150187573 | P-TYPE METAL OXIDE SEMICONDUCTOR MATERIAL AND METHOD FOR FABRICATING THE SAME - A P-type metal oxide semiconductor material is provided. The P-type metal oxide semiconductor material has a formula of
| 2015-07-02 |
20150187574 | IGZO with Intra-Layer Variations and Methods for Forming the Same - Embodiments described herein provide method for forming crystalline indium-gallium-zinc oxide (IGZO) with intra-layer variations and methods for forming such IGZO. At least a portion of a substrate is positioned in a processing chamber. A first sub-layer of an IGZO layer is formed above the at least a portion of the substrate while the at least a portion of the substrate is in the processing chamber. The first sub-layer of the IGZO layer is formed using a first set of processing conditions. A second sub-layer of the IGZO layer is formed above the first sub-layer of the IGZO layer while the at least a portion of the substrate is in the processing chamber. The second sub-layer of the IGZO layer is formed using a second set of processing conditions. The second set of processing conditions is different than the first set of processing conditions. | 2015-07-02 |
20150187575 | MANUFACTURING METHOD OF OXIDE SEMICONDUCTOR - A method of forming an oxide semiconductor includes a step of depositing an oxide semiconductor layer over a substrate by using a sputtering apparatus in which in a target containing indium, an element M (aluminum, gallium, yttrium, or tin), zinc, and oxygen, the substrate which faces a surface of the target, and a magnet unit comprising a first magnet and a second magnet on a rear surface side of the target are provided. In the method, deposition is performed under a condition that a maximum intensity of a horizontal magnetic field is greater than or equal to 350 G and less than or equal to 2000 G in a plane where a vertical distance toward the substrate from a surface of the magnet unit is 10 mm. | 2015-07-02 |
20150187576 | METHOD OF DEFINING POLY-SILICON GROWTH DIRECTION - The present invention relates to a method of defining poly-silicon growth direction. The method of defining poly-silicon growth direction includes Step | 2015-07-02 |
20150187577 | METHOD AND STRUCTURE FOR MULTIGATE FINFET DEVICE EPI-EXTENSION JUNCTION CONTROL BY HYDROGEN TREATMENT - Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin. | 2015-07-02 |
20150187578 | METHOD OF FORMING SILICON LAYER, AND METHOD OF MANUFACTURING FLASH MEMORY - A method of manufacturing a flash memory is provided. In the method, a hydrogen treatment is performed on a substrate, on which a polysilicon gate and a plurality of spacers on sidewalls of the polysilicon gate are formed. A silicon thin film is deposited on the polysilicon gate to extend a top area thereof. The hydrogen treatment and the deposition of the silicon thin film are accomplished repeatedly, and then a cobalt layer is deposited on the silicon thin film. A portion of the cobalt layer is converted to a CoSi | 2015-07-02 |
20150187579 | STRESS-CONTROLLED FORMATION OF TiN HARD MASK - A method to form a titanium nitride (TiN) hard mask in the Damascene process of forming interconnects during the fabrication of a semiconductor device, while the type and magnitude of stress carried by the TiN hard mask is controlled. The TiN hard mask is formed in a multi-layered structure where each sub-layer is formed successively by repeating a cycle of processes comprising TiN and chlorine PECVD deposition, and N | 2015-07-02 |
20150187580 | METHOD FOR OVERCOMING BROKEN LINE AND PHOTORESIST SCUM ISSUES IN TRI-LAYER PHOTORESIST PATTERNING - A method of patterning a semiconductor device using a tri-layer photoresist is disclosed. A material layer is formed over a substrate. A tri-layer photoresist is formed over the material layer. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a photo-sensitive layer disposed over the middle layer. A lithography process is performed to pattern the photo-sensitive layer into a mask having one or more openings. Undesired portions of the mask are removed via a first etching process. Thereafter, the middle layer is patterned via a second etching process. The second etching process includes forming a coating layer around the mask while the middle layer is being etched. In some embodiments, the second etching process includes a continuous plasma etching process. The plasma etching process is performed using at least a C | 2015-07-02 |
20150187581 | BASE FILM-FORMING COMPOSITION, AND DIRECTED SELF-ASSEMBLY LITHOGRAPHY METHOD - A base film-forming composition includes a compound including a group capable of reacting with Si—OH or Si—H, and a solvent. The base film-forming composition is for forming a base film provided between a layer including a silicon atom and a directed self-assembling film in a directed self-assembly lithography process. The receding contact angle of the base film for pure water is no less than 70° and no greater than 90°. The compound is preferably represented by formula (1). In the formula (1), A represents a linking group having a valency of (m+n); D represents a monovalent organic group having at least 10 carbon atoms; E represents the group capable of reacting with Si—OH or Si—H; and m and n are each independently an integer of 1 to 200. | 2015-07-02 |
20150187582 | DOPING METHOD, DOPING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a plasma doping apparatus and a plasma doping method for performing a doping on a processing target substrate by implanting dopant ions into the processing target substrate. The plasma doping method includes a plasma doping processing performed on the processing target substrate held on a holding unit within a processing container by generating plasma using a microwave. The plasma doping method also includes an annealing processing which is performed on the processing target substrate which has been subjected to the plasma doping processing. | 2015-07-02 |
20150187583 | DILUTION DOPED INTEGRATED CIRCUIT RESISTORS - A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body. | 2015-07-02 |
20150187584 | Tunneling Field Effect Transistor (TFET) Formed By Asymmetric Ion Implantation and Method of Making Same - An embodiment integrated circuit device and a method of making the same. The embodiment method includes forming a first nitride layer over a gate stack supported by a substrate, implanting germanium ions in the first nitride layer in a direction forming an acute angle with a top surface of the substrate, etching away germanium-implanted portions of the first nitride layer to form a first asymmetric nitride spacer confined to a first side of the gate stack, the first asymmetric nitride spacer protecting a first source/drain region of the substrate from a first ion implantation, and implanting ions in a second source/drain region of the substrate on a second side of the gate stack unprotected by the first asymmetric nitride spacer to form a first source/drain. | 2015-07-02 |
20150187585 | DUMMY GATE PLACEMENT METHODOLOGY TO ENHANCE INTEGRATED CIRCUIT PERFORMANCE - A method for increasing the performance of an integrated circuit by reducing the number of dummy gate geometries next to transistors in the speed path of an integrated circuit. | 2015-07-02 |
20150187586 | METHOD FOR FABRICATING A METAL HIGH-K GATE STACK FOR A BURIED RECESSED ACCESS DEVICE - A method for fabricated a buried recessed access device comprising etching a plurality of gate trenches in a substrate, implanting and activating a source/drain region in the substrate, depositing a dummy gate in each of the plurality of gate trenches, filling the plurality of gate trenches with an oxide layer, removing each dummy gate and depositing a high-K dielectric in the plurality of gate trenches, depositing a metal gate on the high-K dielectric in each of the plurality of gate trenches, depositing a second oxide layer on the metal gate and forming a contact on the source/drain. | 2015-07-02 |
20150187587 | Memory Device Structure and Method - A system and method for manufacturing a memory device is provided. A preferred embodiment comprises manufacturing a flash memory device with a tunneling layer. The tunneling layer is formed by introducing a bonding agent into the dielectric material to bond with and reduce the number of dangling bonds that would otherwise be present. Further embodiments include initiating the formation of the tunneling layer without the bonding agent and then introducing a bonding agent containing precursor and also include a reduced concentration region formed in the tunneling layer adjacent to a substrate. | 2015-07-02 |
20150187588 | PLASMA ETCHING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A plasma etching method for etching a substrate includes an adjustment step adjusting a concentration distribution of active species contained in plasma. The adjustment step adjusts a supply rate of an etching gas according to whether a supply region on a substrate to which the etching gas is supplied corresponds to a region where an effect of diffusion of the supplied etching gas is greater than an effect of flow of the supplied etching gas or a region where the effect of flow of the supplied etching gas is greater than the effect of diffusion of the supplied etching gas. | 2015-07-02 |
20150187589 | HARDMASK COMPOSITION AND METHOD OF FORMING PATTERNS USING THE HARDMASK COMPOSITION - A hardmask composition includes a polymer including a moiety represented by the following Chemical Formula 1 and a solvent. | 2015-07-02 |
20150187590 | Methods for Uniform Imprint Pattern Transfer of Sub-20 nm Features - Methods of increasing etch selectivity in imprint lithography are described which employ material deposition techniques that impart a unique morphology to the multi-layer material stacks, thereby enhancing etch process window and improving etch selectivity. For example, etch selectivity of 50:1 or more between patterned resist layer and deposited metals, metalloids, or non-organic oxides can be achieved, which greatly preserves the pattern feature height prior to the etch process that transfers the pattern into the substrate, allowing for sub-20 nm pattern transfer at high fidelity. | 2015-07-02 |
20150187591 | METHOD OF FORMING PATTERN FOR SEMICONDUCTOR DEVICE - The present disclosure provides a method including providing a semiconductor substrate and forming a first layer and a second layer on the semiconductor substrate. The first layer is patterned to provide a first element, a second element, and a space interposing the first and second elements. Spacer elements are then formed on the sidewalls on the first and second elements of the first layer. Subsequently, the second layer is etched using the spacer elements and the first and second elements as a masking element. | 2015-07-02 |
20150187592 | METHODS FOR SINGLE EXPOSURE - SELF-ALIGNED DOUBLE, TRIPLE, AND QUADRUPLE PATTERNING - A method including forming a pattern on a surface of a substrate, the pattern including one of discrete structures including at least one sidewall defining an oblique angle relative to the surface and discrete structures complemented with a material layer therebetween, the material layer including a volume modified into distinct regions separated by at least one oblique angle relative to the surface; and defining circuit features on the substrate using the pattern, the features having a pitch less than a pitch of the pattern. | 2015-07-02 |
20150187593 | ETCHING METHOD, STORAGE MEDIUM AND ETCHING APPARATUS - There is a method of selectively etching a silicon oxide film among a silicon nitride film and the silicon oxide film formed on a surface of a substrate to be processed, the method including: under a vacuum atmosphere, intermittently supplying at least one of a first processing gas composed of a hydrogen fluoride gas and an ammonia gas and a second processing gas composed of a compound of nitrogen, hydrogen and fluorine, to the substrate to be processed multiple times. | 2015-07-02 |
20150187594 | Composite Structure for Gate Level Inter-Layer Dielectric - A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process. | 2015-07-02 |
20150187595 | A SEMICONDUCTOR DEVICE COMPRISING A SURFACE PORTION IMPLANTED WITH NITROGEN AND FLUORINE - A method of fabricating a semiconductor device is provided. A substrate is provided. Thereafter, a dielectric layer is formed on the substrate, wherein the dielectric layer includes a first portion adjacent to the substrate and a second portion adjacent to the first portion. Afterwards, the dielectric layer is treated with nitrogen trifluoride (NF | 2015-07-02 |
20150187596 | Wet Etching of Silicon Containing Antireflective Coatings - Provided are methods for processing semiconductor substrates or, more specifically, etching silicon containing antireflective coatings (SiARCs) from the substrates while preserving silicon oxides layers disposed on the same substrates. An etching solution including sulfuric acid and hydrofluoric acid may be used for these purposes. In some embodiments, the weight ratio of sulfuric acid to hydrofluoric acid in the etching solution is between about 15:1 and 100:1 (e.g., about 60:1). The temperature of the etching solution may be between about 30° C. and 50° C. (e.g., about 40° C., during etching). It has been found that such processing conditions provide a SiARC etching rate of at least about 50 nanometers per minute and selectivity of SiARC over silicon oxide of greater than about 10:1 or even greater than about 50:1. The same etching solution may be also used to remove photoresist, organic dielectric, and titanium nitride. | 2015-07-02 |
20150187597 | METHOD TO IMPROVE SLIP RESISTANCE OF SILICON WAFERS - By controlling the concentration and size of bulk micro defects (BMD) during the manufacture of an integrated circuit slip and associated yield loss due to slip may be eliminated. A process for eliminating slip that is customized to an integrated circuit (IC) manufacturing flow is disclosed. The process is adapted to the oxygen content of the starting material and to the thermal budget of an IC manufacturing flow and generates a sufficient concentration of BMDs of a size that is optimized to getter microcracks thereby eliminating slip. Slip is eliminated in unpatterned wafers and in wafers containing shallow trench isolation and deep trench isolation using a BMD nucleation anneal and a BMD growth anneal. | 2015-07-02 |
20150187598 | HIGH PRECISION CAPACITOR DIELECTRIC - A process of forming an integrated circuit forms a high precision capacitor bottom plate with a metallic surface and performs a plasma treatment of the metallic surface. A high precision capacitor dielectric is formed by depositing a first layer of the capacitor dielectric on the high precision capacitor bottom plate wherein the first layer is silicon nitride, depositing a second layer of the capacitor dielectric on the first layer wherein the second portion is silicon dioxide, and depositing a third layer of the capacitor dielectric on the second portion wherein the third layer is silicon nitride. Plasma treatments may also be performed on the layers of capacitor dielectric pre-and/or post-deposition. A metallic high precision capacitor top plate is formed on the high precision capacitor dielectric. | 2015-07-02 |
20150187599 | METHODS OF MANUFACTURING NITRIDE SEMICONDUCTOR DEVICES - Provided is a method of manufacturing a nitride semiconductor device. The method includes forming a plurality of electrodes on a growth substrate on which first and second nitride semiconductor layers are sequentially stacked, forming upper metal layers on the plurality of electrodes respectively, removing the growth substrate to expose a lower surface of the first nitride semiconductor layer, and forming a third nitride semiconductor layer and a lower metal layer sequentially on the exposed lower surface of the first nitride semiconductor layer. | 2015-07-02 |
20150187600 | SELECTIVE FORMATION OF METALLIC FILMS ON METALLIC SURFACES - Metallic layers can be selectively deposited on surfaces of a substrate relative to a second surface of the substrate. In preferred embodiments, the metallic layers are selectively deposited on copper instead of insulating or dielectric materials. In preferred embodiments, a first precursor forms a layer or adsorbed species on the first surface and is subsequently reacted or converted to form a metallic layer. Preferably the deposition temperature is selected such that a selectivity of above about 90% is achieved. | 2015-07-02 |
20150187601 | INTERCONNECT STRUCTURE AND METHOD FOR FORMING THE SAME - Various embodiments provide semiconductor devices and methods for forming the same. A base including a substrate and an interlayer dielectric layer is provided. The base has a first region and a second region that have an overlapped third region. A mask layer having a stacked structure is formed on the interlayer dielectric layer at the overlapped third region. Using the mask layer as an etching mask, the interlayer dielectric layer at the first region at both sides of the mask layer is etched, to expose the substrate and form a first contact via at the first region. Using the mask layer as an etching mask, the interlayer dielectric layer at the second region at both sides of the mask layer is etched, to form a second contact via at the second region. A conductive layer is formed to fill the first contact via and the second contact via. | 2015-07-02 |
20150187602 | NANOSCALE PATTERNING METHOD AND INTEGRATED DEVICE FOR ELECTRONIC APPARATUS MANUFACTURED THEREFROM - Provided is a nanoscale patterning method using self-assembly, wherein nanoscale patterns having desirable shapes such as a lamella shape, a cylinder shape, and the like, may be formed by using a self-assembly property of a block copolymer, and low segment interaction caused in a structure of 10 nm or less which is a disadvantage of the block copolymer may be prevented. In addition, even though single photolithography is used, pattern density may double as that of the existing nano patterns, and pitch and cycle of the patterns may be controlled to thereby be largely utilized for electronic apparatuses requiring high integration of circuits such as a semiconductor device, and the like. | 2015-07-02 |
20150187603 | FABRICATION METHOD OF PACKAGING SUBSTRATE - A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer. | 2015-07-02 |
20150187604 | METHOD OF JOINING SEMICONDUCTOR SUBSTRATE - A method of joining semiconductor substrates includes: forming an alignment key on a first semiconductor substrate; forming a first protrusion and a second protrusion, and an alignment recess positioned between the first protrusion and the second protrusion on a second semiconductor substrate; forming a first metal layer and a second metal layer on the first protrusion and the second protrusion, respectively; and joining the first semiconductor substrate and the second semiconductor substrate, in which the alignment key is positioned at the alignment recess when the first semiconductor substrate and the second semiconductor substrate are joined. | 2015-07-02 |
20150187605 | METHOD OF PACKAGING A SEMICONDUCTOR DEVICE - A method of packaging a semiconductor device includes forming an insulating layer over a semiconductor device, wherein the semiconductor device has a contact pad, and a thickness of the contact pad is greater than a thickness of the insulating layer. The method further includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and a neighboring semiconductor device, wherein both semiconductor devices are on a carrier wafer. The method further includes planarizing a surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pad. | 2015-07-02 |
20150187606 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF - There is provided a technology enabling the improvement of the reliability of a semiconductor device manufactured by physically fixing separately formed chip mounting portion and lead frame. A feature of an embodiment resides in that, a second junction portion formed in a suspension lead is fitted into a first junction portion formed in a chip mounting portion, thereby to physically fix the chip mounting portion and the suspension lead. Specifically, the first junction portion is formed of a concave part disposed in the surface of the chip mounting portion. The second junction portion forms a part of the suspension lead. | 2015-07-02 |
20150187607 | TWO STEP MOLDING GRINDING FOR PACKAGING APPLICATIONS - Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die. | 2015-07-02 |
20150187608 | DIE PACKAGE ARCHITECTURE WITH EMBEDDED DIE AND SIMPLIFIED REDISTRIBUTION LAYER - A die package architecture with an embedded die and simplified redistribution layer is described. In one example a method includes attaching a front side of a die to a temporary carrier panel applying a molding compound around the die and over the temporary carrier panel. Removing the temporary carrier, applying a metal routing layer over the front side of the die and the molding compound, and applying a connection array to the metal routing layer. | 2015-07-02 |
20150187609 | Semiconductor Wafer Cleaning System - A semiconductor wafer cleaning apparatus comprising a first supporting unit, a movable unit having a first chamber, a second supporting unit having a second chamber, and a third supporting unit is provided. A micro processing chamber in which the semiconductor wafer is being processed is formed when the first chamber is brought in contact with the second chamber. Each of the supporting units is supported by a corresponding supporting plate, and each supporting plate is positioned and strengthened by a plurality of supporting bars on its peripheral. Such design will prevent the deformation of the supporting plates, reduce the particles generated by the friction of parts resulted from the opening or closure of the micro processing chamber, and allow the easy alignment of these units. | 2015-07-02 |