26th week of 2010 patent applcation highlights part 16 |
Patent application number | Title | Published |
20100163960 | FLASH MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed is a flash memory device and a method of manufacturing the same. The flash memory device includes a floating gate formed on a semiconductor substrate, a select gate self-aligned on one sidewall of the floating gate, and an ONO pattern interposed between the floating gate and the select gate. A self-aligned split gate structure is formed for an EEPROM tunnel oxide cell flash memory device employing a split gate structure, so that a cell current is constant and the erasing characteristic between cells is uniform, thereby improving the reliability. | 2010-07-01 |
20100163961 | METHOD FOR MANUFACTURING SEMICONDUCTOR FLASH MEMORY AND FLASH MEMORY CELL - A semiconductor flash memory includes a tunnel oxide film formed over a semiconductor substrate, a first spacer composed of polysilicon formed over the semiconductor substrate including the tunnel oxide film, a second spacer composed of an insulating material formed at sidewalls of the first spacer, a dielectric film formed at the uppermost surface of the first spacer and the second spacer, a control gate formed at the uppermost surface of the dielectric film, and a third spacer composed of an insulating material formed at and contacting sidewalls of the second spacer, the dielectric film and the control gate. A first source/drain region formed may be formed in the semiconductor substrate and self-aligned with the first spacer and a second source/drain region may be formed in the semiconductor substrate and self-aligned with the second spacer. | 2010-07-01 |
20100163962 | Printed Non-Volatile Memory - A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology. | 2010-07-01 |
20100163963 | NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - There is provided a nonvolatile memory device having a tunnel dielectric layer formed over a substrate, the charge capturing layer formed over the tunnel dielectric layer and including a combination of at least one charge storage layer and at least one charge trap layer, a charge blocking layer formed over the charge capturing layer, and a gate electrode formed over the charge blocking layer. | 2010-07-01 |
20100163964 | METHOD FOR MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing a flash memory device and devices thereof, which may be capable of preventing damage to a gate. A method of manufacturing a flash memory device may include preparing a semiconductor substrate having an active region defined by a device separator. A method of manufacturing a flash memory device may include forming a floating gate, a oxide-nitride-oxide (ONO) layer and/or a control gate layer on and/or over a substrate. A method of manufacturing a flash memory device may include forming a low temperature oxide (LTO) film on and/or over a control gate, etching a LTO film to expose a desired part of a control gate, using a LTO film as a mask to etch a desired part of each of a floating gate layer, a ONO layer and/or a control gate to form a gate pattern, and/or substantially removing a LTO film by wet etching. | 2010-07-01 |
20100163965 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes a floating gate including adjacent first and second floating gates on a substrate; first and second select gates respectively on the first and second floating gates; an insulating layer between the first floating gate and the first select gate and between the second floating gate and the second select gate; a drain region at outer sides of the first and second select gates; a source region between the first and second select gates; and a metal contact on each of the drain region and the source region. The select gate can be defined as a self-align structure, and the length of the select gate can be controlled depending on the thickness of the material used to form the select gate. | 2010-07-01 |
20100163966 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME - Disclosed are a flash memory device and a method for manufacturing the same. The flash memory device includes first and second memory gates on a substrate; a floating poly between the first and second memory gates; first and second select gates at respective outer sides of the first and second memory gates; an oxide layer between the first memory gate and the first select gate and between the second memory gate and the second select gate; a drain region in the substrate at outer sides of the first and second select gates; a source region in the substrate between the first and second memory gates; and a metal contact on each of the drain region and the source region. | 2010-07-01 |
20100163967 | Flash Memory Device and Method of Fabricating the Same - A flash memory device and a method for fabricating the same are disclosed. The flash memory device includes an ONO layer on a substrate, polysilicon gates on the ONO layer, a gate oxide layer on the substrate, the ONO layer and the polysilicon gates, and a low temperature oxide layer and polysilicon sidewall spacers on outer side surfaces of the polysilicon gates, except in a region between nearest adjacent polysilicon gates. | 2010-07-01 |
20100163968 | SEMICONDUCTOR MEMORY DEVICE HAVING INSULATION PATTERNS AND CELL GATE PATTERNS - Semiconductor memory devices and methods of forming semiconductor memory devices are provided. The methods may include forming insulation layers and cell gate layers that are alternately stacked on a substrate, forming an opening by successively patterning through the cell gate layers and the insulation layers, and forming selectively conductive barriers on sidewalls of the cell gate layers in the opening. | 2010-07-01 |
20100163969 | FLASH MEMORY DEVICE AND MANUFACTURING METHOD THE SAME - A flash memory device and a method of manufacturing a flash memory device. A flash memory device may include an isolation layer and/or an active area over a semiconductor substrate, a memory gate formed over an active area, a control gate formed over a semiconductor substrate including a memory gate, and/or a common source line contact formed over a semiconductor substrate including a control gate. A flash memory device may include a source plate having substantially the same interval as an interval of an active area of a bit line. A source plate may include an active area in which a common source line contact may be formed. A common source line contact may include a long butting contact extending in a direction traversing an active area. | 2010-07-01 |
20100163970 | Trigate transistor having extended metal gate electrode - A trigate device having an extended metal gate electrode comprises a semiconductor body having a top surface and opposing sidewalls formed on a substrate, an isolation layer formed on the substrate and around the semiconductor body, wherein a portion of the semiconductor body remains exposed above the isolation layer, and a gate stack formed on the top surface and opposing sidewalls of the semiconductor body, wherein the gate stack extends a depth into the isolation layer, thereby causing a bottom surface of the gate stack to be below a top surface of the isolation layer. | 2010-07-01 |
20100163971 | Dielectric Punch-Through Stoppers for Forming FinFETs Having Dual Fin Heights - A semiconductor structure includes a semiconductor substrate having a first portion and a second portion. A first Fin field-effect transistor (FinFET) is formed over the first portion of the semiconductor substrate, wherein the first FinFET includes a first fin having a first fin height. A second FinFET is formed over the second portion of the semiconductor substrate, wherein the second FinFET includes a second fin having a second fin height different from the first fin height. A top surface of the first fin is substantially level with a top surface of the second fin. A punch-through stopper is underlying and adjoining the first FinFET, wherein the punch-through stopper isolates the first fin from the first portion of the semiconductor substrate. | 2010-07-01 |
20100163972 | MULTI-DRAIN SEMICONDUCTOR POWER DEVICE AND EDGE-TERMINATION STRUCTURE THEREOF - An embodiment of a semiconductor power device provided with: a structural body made of semiconductor material with a first conductivity, having an active area housing one or more elementary electronic components and an edge area delimiting externally the active area; and charge-balance structures, constituted by regions doped with a second conductivity opposite to the first conductivity, extending through the structural body both in the active area and in the edge area in order to create a substantial charge balance. The charge-balance structures are columnar walls extending in strips parallel to one another, without any mutual intersections, in the active area and in the edge area. | 2010-07-01 |
20100163973 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a P-type substrate | 2010-07-01 |
20100163974 | SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device including a vertical channel transistor includes providing a substrate including a semiconductor pillar, forming a gate electrode surrounding the semiconductor pillar, forming an impurity region for a bit line by doping impurities into the substrate and forming a device isolation trench by etching a portion of the substrate including the impurity region to a certain depth, thereby defining the bit line, wherein the impurity doping is performed with given concentration so as to form the impurity region under the semiconductor pillar. | 2010-07-01 |
20100163975 | Trench metal oxide semiconductor field effect transistor (MOSFET) with low gate to drain coupled charges (Qgd) structures - A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further comprises tilt-angle implanted body dopant regions surrounding a lower portion of trench sidewalls for reducing a gate-to-drain coupling charges Qgd between the trenched gates and a drain disposed at a bottom of the semiconductor substrate. The trenched semiconductor power device further includes a source dopant region disposed below a bottom surface of the trenched gates for functioning as a current path between the drain to the source for preventing a resistance increase caused by the body dopant regions surrounding the lower portions of the trench sidewalls. | 2010-07-01 |
20100163976 | Semiconductor Device Having Saddle Fin Transistor and Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming a pad nitride layer that exposes an isolation region over a cell region of a semiconductor substrate; forming a trench in the isolation region of the semiconductor substrate; forming an isolation layer within the trench; etching an active region of the semiconductor substrate by a certain depth to form a recessed isolation region; etching the isolation layer by a certain depth to form a recessed isolation region; depositing a gate metal layer in the recessed active region and the recessed isolation region to form a gate of a cell transistor; forming an insulation layer over an upper portion of the gate; removing the pad nitride layer to expose a region of the semiconductor substrate to be formed with a contact plug; and depositing a conductive layer in the region of the semiconductor substrate to form a contact plug. | 2010-07-01 |
20100163977 | Semiconductor Device and Method for Fabricating the Same - A method for fabricating a semiconductor device includes forming a trench in a substrate, forming a gate electrode buried over the trench to form a buried gate pattern, etching portions of the substrate on both sides of the buried gate pattern to a certain depth, performing an ion implantation process on the substrate to form source/drain junctions, and forming metal patterns over the source/drain junctions. | 2010-07-01 |
20100163978 | METHOD FOR MANUFACTURING AN INTEGRATED POWER DEVICE ON A SEMICONDUCTOR SUBSTRATE AND CORRESPONDING DEVICE - An embodiment of a method for manufacturing a power device being integrated on a semiconductor substrate comprising at least the steps of making, in the semiconductor substrate, at least a trench having sidewalls and a bottom, covering the sidewalls and the bottom of said at least one trench with a first insulating coating layer and making, inside said at least one trench, a conductive gate structure. An embodiment of the method provides the formation of the conductive gate structure comprising the steps of covering at least the sidewalls with a second conductive coating layer of a first conductive material; making a conductive central region of a second conductive material having a different resistivity than the first conductive material; and making a plurality of conductive bridges between said second conductive coating layer and said conductive central region. | 2010-07-01 |
20100163979 | TRUE CSP POWER MOSFET BASED ON BOTTOM-SOURCE LDMOS - A semiconductor package may comprise a semiconductor substrate, a MOSFET device having a plurality cells formed on the substrate, and a source region common to all cells disposed on a bottom of the substrate. Each cell comprises a drain region on a top of the semiconductor device, a gate to control a flow of electrical current between the source and drain regions, a source contact proximate the gate; and an electrical connection between the source contact and source region. At least one drain connection is electrically coupled to the drain region. Source, drain and gate pads are electrically connected to the source region, drain region and gates of the devices. The drain, source and gate pads are formed on one surface of the semiconductor package. The cells are distributed across the substrate, whereby the electrical connections between the source contact of each device and the source region are distributed across the substrate. | 2010-07-01 |
20100163980 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes an isolation layer formed on and/or over a semiconductor substrate to define an isolation layer, a drift area formed in an active area separated by the isolation layer, a pad nitride layer pattern formed in a form of a plate on the drift area, and a gate electrode having step difference between lateral sides thereof due to the pad nitride layer pattern. | 2010-07-01 |
20100163981 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes: an active region defined by a device isolation layer on and/or over a substrate; a second conductive well on and/or over the active region; an extended drain formed at one side of the second conductive well; a gate electrode on and/or over the second conductive well and the extended drain; and a source and a drain formed at both sides of the gate electrode, in which extended regions are formed at the corners of the second conductive well under the gate electrode. | 2010-07-01 |
20100163982 | SEMICONDUCTOR DEVICE FOR HIGH VOLTAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which may be for a high voltage and a method of manufacturing the same. A semiconductor device may include a first conductivity-type well formed on and/or over a substrate, a second conductivity-type drift region formed on and/or over a first conductivity-type well, an isolation layer formed on and/or over a first conductivity-type well, an isolation layer defining an isolation region and/or an active region, a gate pattern formed on and/or over a predetermined upper surface of a second conductivity-type drift region and/or a first conductivity-type well at an active region of a substrate, and/or second conductivity-type source and/or drain regions formed on and/or over second conductivity-type drift regions at two sides of a gate pattern. A gate pattern and/or a drift region of a semiconductor device may be formed substantially without gaps. | 2010-07-01 |
20100163983 | Semiconductor Device and Method for Fabricating the Same - Semiconductor devices and methods for fabricating the same are disclosed. The semiconductor device includes gate electrodes having sidewall spacers on a semiconductor substrate, double diffusion drain regions in the semiconductor substrate adjacent to the sidewall spacers, double diffusion junction regions aligned with the gate electrodes, and source/drain regions in the double diffusion junction regions. | 2010-07-01 |
20100163984 | Lateral Double Diffused Metal Oxide Semiconductor - Disclosed are lateral double diffused metal oxide semiconductor (LDMOS) transistors having a uniform threshold voltage and methods for manufacturing the same. The methods include forming a polysilicon layer over the semiconductor substrate including a shallow trench isolation region, etching a portion of the polysilicon layer over an active region, implanting first conductive-type impurity ions using the polysilicon layer as a mask to form a first conductive-type body region, implanting second conductive-type impurity ions using the polysilicon layer as a mask to form a second conductive-type channel region in the first conductive-type body region, removing the polysilicon layer, forming gate electrodes in the polysilicon-free region, and forming a source region and a drain region in the first conductive-type body region using the gate electrode and the shallow trench isolation as ion-implantation masks. | 2010-07-01 |
20100163985 | SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME - A semiconductor includes a high voltage region formed in a substrate, first and second drift regions formed in the high voltage region, an isolation layer in the high voltage region, a gate formed on and/or over the first and second drift regions, and a drain and a source formed in the first drift region and the second drift region. | 2010-07-01 |
20100163986 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method of manufacturing a semiconductor device. A method may include forming a first well by injecting first conduction type impurity ions on and/or over a semiconductor substrate, forming an extended drain region overlapped with a region of said first well by injecting second conduction type impurities on and/or over a semiconductor substrate, and/or forming a first conduction type second well on and/or over a semiconductor substrate under an extended drain region to overlap with another region of a first well by injecting second conduction type impurities on and/or over a semiconductor substrate. A method may include forming a gate over a first well overlapped with an extended drain region, and/or forming a drain region by injecting second conduction type impurities on and/or over an extended drain region at one side of a gate. | 2010-07-01 |
20100163987 | Semiconductor device - Semiconductor device including semiconductor layer, first impurity region on surface layer portion of semiconductor layer, body region at interval from first impurity region, second impurity region on surface layer portion of body region, field insulating film at interval from second impurity region, gate insulating film on surface of the semiconductor layer between second impurity region and field insulating film, gate electrode on gate insulating film, first floating plate as ring on field insulating film, and second floating plate as ring on same layer above first floating plate. First and second floating plates formed by at least three plates so that peripheral lengths at centers in width direction thereof are entirely different from one another, alternately arranged in plan view so that one having relatively smaller peripheral length is stored in inner region of one having relatively larger peripheral length, and formed to satisfy relational expression: L/d=constant. | 2010-07-01 |
20100163988 | HIGH VOLTAGE (>100V) LATERAL TRENCH POWER MOSFET WITH LOW SPECIFIC-ON-RESISTANCE - In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain electrode spaced from the gate electrode, and in electrical communication with a drift region having a boundary with a lower end of the channel region. The device includes a gate dielectric layer in contact with the gate electrode, and disposed between the gate electrode and the drain electrode. The channel region is adjacent to a substantially vertical wall of the gate trench. The device includes a field plate contacting the gate electrode and configured to increase a breakdown voltage of the device. | 2010-07-01 |
20100163989 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region. | 2010-07-01 |
20100163990 | Lateral Double Diffused Metal Oxide Semiconductor Device - Disclosed is a lateral double diffused metal oxide semiconductor (LDMOS) device and methods of making the same. The LDMOS device may include a semiconductor substrate comprising a buried region and a first well region, a gate on the semiconductor substrate, a body region in the first well region and a source region in the body region on one side of the gate, a drift region and a drain region in the drift region on an opposite side of the gate relative to the body region, a second well region, a first deep sink region and a third well region in the first well region, and a second deep sink region in the first well region. | 2010-07-01 |
20100163991 | LATERALLY DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR, AND METHOD FOR FABRICATING THE SAME - A laterally double-diffused metal oxide semiconductor (LDMOS) and a method for fabrication thereof includes a well region formed in a semiconductor substrate having an active region defined by device isolation layers, a body region formed over the well region, a drain region spaced from the body region at a constant interval and formed above the well region, a source region and a source contact region formed in the body region in structural communication with the source region, a drift region having a trench formed therein formed in the well region between the body region and the drain region, and a gate formed over the semiconductor substrate which partially overlaps the source region and the drift region. | 2010-07-01 |
20100163992 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a high voltage first conduction type well in a semiconductor substrate, a second conduction type body in the high voltage first conduction type well, a source region in the second conduction type body, a trench in the high voltage first conduction type well, a first isolation oxide, an impurity doped polysilicon film, and a second isolation oxide stacked in the trench in succession, a drain region in the high voltage first conduction type well on one side of the trench, and a polygate on and/or over the high voltage first conduction type well. | 2010-07-01 |
20100163993 | METHOD OF FABRICATING A SEMICONDUCTOR ON INSULATOR DEVICE HAVING A FRONTSIDE SUBSTRATE CONTACT - A method of forming a substrate contact in a semiconductor device, comprising the steps of providing a semiconductor base substrate ( | 2010-07-01 |
20100163994 | SOI DEVICE WITH A BURIED INSULATING MATERIAL HAVING INCREASED ETCH RESISTIVITY - In SOI devices, the PN junction of circuit elements, such as substrate diodes, is formed in the substrate material on the basis of the buried insulating material that provides increased etch resistivity during wet chemical cleaning and etch processes. Consequently, undue exposure of the PN junction formed in the vicinity of the sidewalls of the buried insulating material may be avoided, which may cause reliability concerns in conventional SOI devices comprising a silicon dioxide material as the buried insulating layer. | 2010-07-01 |
20100163995 | Semiconductor Device With Cooling Element - Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed | 2010-07-01 |
20100163996 | METHOD FOR MANUFACTURING CMOS CIRCUITS AND CMOS CIRCUITS MANUFACTURED THEREOF - A method of manufacturing transistors of a first and second type on a substrate includes producing doped semiconductor areas with a first conductivity type in eventual contact areas of a first type of transistors, depositing a first intrinsic semiconductor layer over an entire surface, activating dopants in the semiconductor areas such that a contact area with the first conductivity type is produced in the intrinsic semiconductor layer, depositing a gate dielectric, producing a gate electrode by depositing a first conductive layer and patterning the first conductive layer, performing ion doping with dopants to produce contact areas with a second conductivity type for a second type of transistor, depositing a passivation layer, opening contact openings, and depositing and patterning a second conductive layer. | 2010-07-01 |
20100163997 | EPITAXIAL DEPOSITION-BASED PROCESSES FOR REDUCING GATE DIELECTRIC THINNING AT TRENCH EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface. The epitaxial comprising silicon layer is oxidized to convert at least a portion into a thermally grown silicon oxide layer, wherein the thermally grown silicon oxide layer provides at least a portion of a gate dielectric layer for at least one of said plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges. Fabrication of the IC is then completed. | 2010-07-01 |
20100163998 | TRENCH ISOLATION COMPRISING PROCESS HAVING MULTIPLE GATE DIELECTRIC THICKNESSES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including a first plurality of MOS transistors having a first gate dielectric having a first thickness in first regions, and a second plurality of MOS transistors having a second gate dielectric having a second thickness in second regions, wherein the first thickness2010-07-01 | |
20100163999 | SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING THE SAME - A semiconductor element according to embodiments may include: a semiconductor substrate, a first oxide layer pattern formed over the semiconductor substrate, and a first polysilicon pattern formed over the first oxide layer pattern, wherein the substrate, the first oxide layer pattern and the first polysilicon pattern define a recess formed at both sides of the first oxide layer pattern and the first polysilicon pattern. A second polysilicon pattern may be formed over the first oxide layer pattern and the side wall of the first polysilicon pattern in the recess. A second oxide layer pattern, a second nitride layer pattern, and a third oxide layer pattern may be interposed between the first polysilicon pattern and the second polysilicon pattern, and between the second polysilicon pattern and the recess. Embodiments can be operated with lower electrical power in programming and erasing operations by forming a tip portion near a memory gate to increase an electric field at that portion. | 2010-07-01 |
20100164000 | STRAINED TRANSISTOR AND METHOD FOR FORMING THE SAME - According to one embodiment, a semiconductor substrate is provided having at least two transistor regions formed therein. Overlying the channel regions is a gate dielectric and transistor gate electrodes overly the gate dielectric and are positioned overlying the channel regions. Source and drain regions are formed on either side of the channel regions to create a transistor structure. In order to provide isolation between transistors in the semiconductor substrate, a trench is formed in the substrate. A strain-inducting layer is then deposited over the transistor structures and into the trench in the semiconductor substrate. A high-stress nitride layer is one type of material which is suitable for forming the strain-inducing layer. | 2010-07-01 |
20100164001 | Implant process for blocked salicide poly resistor and structures formed thereby - Methods and associated structures of forming a microelectronic device are described. Those methods may include implanting an exposed p type silicon portion of a substrate with a carbon species, wherein endcap regions of a blocked salicide resistor and a p type structure that are both disposed on the exposed p type silicon portion of the substrate are implanted with the carbon species. | 2010-07-01 |
20100164002 | DUAL SALICIDE INTEGRATION FOR SALICIDE THROUGH TRENCH CONTACTS AND STRUCTURES FORMED THEREBY - Methods and associated structures of forming a microelectronic device are described. Those methods may include forming an NMOS silicide on an NMOS source/drain contact area, forming a first contact metal on the NMOS silicide, polishing the first contact metal to expose a top surface of a PMOS source/drain region, and forming a PMOS silicide on the PMOS source/drain region. | 2010-07-01 |
20100164003 | MULTIPLE INDIUM IMPLANT METHODS AND DEVICES AND INTEGRATED CIRCUITS THEREFROM - An integrated circuit (IC) includes at least one NMOS transistor, wherein the NMOS transistor includes a substrate having a semiconductor surface, and a gate stack formed in or on the surface including a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region are on opposing sides of the gate stack. An In region having a retrograde profile is under at least a portion of the channel region. The retrograde profile includes (i) a surface In concentration at a semiconductor surface interface with the gate dielectric of less than 5×10 | 2010-07-01 |
20100164004 | METHODS FOR REDUCING GATE DIELECTRIC THINNING ON TRENCH ISOLATION EDGES AND INTEGRATED CIRCUITS THEREFROM - A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors. A patterned gate electrode layer is formed over the gate dielectric, wherein the patterned gate electrode layer extends over at least one of the trench isolation active area edges to the silicon including surface, and fabrication is then completed. | 2010-07-01 |
20100164005 | SELECTIVE WET ETCH PROCESS FOR CMOS ICS HAVING EMBEDDED STRAIN INDUCING REGIONS AND INTEGRATED CIRCUITS THEREFROM - A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes providing a substrate having a semiconductor surface including PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate stack including a gate electrode layer is formed on a gate dielectric layer in or on both the PMOS regions and the NMOS regions. An n-type doping is used to create n-type wet etch sensitized regions on opposing sides of the gate stack in both the PMOS and said NMOS regions. Wet etching removes the n-type wet etch sensitized regions in (i) at least a portion of said PMOS regions to form a plurality of PMOS source/drain recesses or (ii) in at least a portion of said NMOS regions to form a plurality of NMOS source/drain recesses, or (i) and (ii). At least one of a compressive strain inducing epitaxial layer is formed in the plurality of PMOS source/drain recesses and a tensile strain inducing epitaxial layer is formed in the plurality of NMOS source/drain recesses. The fabrication of the IC is then completed. | 2010-07-01 |
20100164006 | GATE DIELECTRIC FIRST REPLACEMENT GATE PROCESSES AND INTEGRATED CIRCUITS THEREFROM - A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed. | 2010-07-01 |
20100164007 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - To provide a semiconductor device and a method of manufacturing the same capable of suppressing, when a plurality of MIS transistors having different absolute values of threshold voltage is used, the reduction of the drive current of a MIS transistor having a greater absolute value of threshold voltage. | 2010-07-01 |
20100164008 | METHOD FOR INTEGRATION OF REPLACEMENT GATE IN CMOS FLOW - Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes. | 2010-07-01 |
20100164009 | Method of manufacturing dual gate semiconductor device - The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities. | 2010-07-01 |
20100164010 | SEMICONDUCTOR DEVICE FOR IMPROVING CHANNEL MOBILITY - A semiconductor device includes a substrate, a gate electrode formed on the substrate, a source region and a drain region formed in the substrate, the source region and the drain region formed located on the both side of the gate electrode, a first insulating film formed on the substrate, the first insulating film for generating a stress in a channel region under the gate electrode, a contact formed on the source region and the drain region, and the contact formed so that an amount of the first insulating film formed on the source region is larger than an amount of the first insulating film formed on the drain region. | 2010-07-01 |
20100164011 | Techniques for Enabling Multiple Vt Devices Using High-K Metal Gate Stacks - Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET. | 2010-07-01 |
20100164012 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate including a CMOS region and a bipolar region, a first N well and a first P well in the CMOS region, a PMOS device in the first N well and an NMOS device in the first P well, a deep P well in the bipolar region, a second N well in the deep P, a second isolation layer between the deep P well and the second N well, a third isolation in the second N well, a collector in the second N well between the second and third isolation layers, and a base formed in the second N well and having a bottom surface including first type impurities to contact the emitter. | 2010-07-01 |
20100164013 | RANDOM PERSONALIZATION OF CHIPS DURING FABRICATION - Disclosed are embodiments of a method for randomly personalizing chips during fabrication, a personalized chip structure and a design structure for such a personalized chip structure. The embodiments use electronic device design and manufacturing processes to randomly or pseudo-randomly create a specific variation in one or more instances of a particular electronic device formed on each chip. The device design and manufacturing processes are tuned so that the specific variation occurs with some predetermined probability, resulting in a desired hardware distribution and personalizing each chip. The resulting personalized chips can be used for modal distribution of chips. For example, chips can be personalized to allow sorting when a single chip design can be used to support multiple applications. The resulting personalized chips can also be used for random number generation for creating unique on-chip identifiers, private keys, etc. | 2010-07-01 |
20100164014 | REDUCTION OF THRESHOLD VOLTAGE VARIATION IN TRANSISTORS COMPRISING A CHANNEL SEMICONDUCTOR ALLOY BY REDUCING DEPOSITION NON-UNIFORMITIES - A threshold adjusting semiconductor material, such as a silicon/germanium alloy, may be provided selectively for one type of transistors on the basis of enhanced deposition uniformity. For this purpose, the semiconductor alloy may be deposited on the active regions of any transistors and may subsequently be patterned on the basis of a highly controllable patterning regime. Consequently, threshold variability may be reduced. | 2010-07-01 |
20100164015 | SEMICONDUCTOR DEVICE - When MOS transistors having a plurality of threshold voltages in which a source and a drain form a symmetrical structure are mounted on the same substrate, electrically-symmetrical characteristics is provided with respect to an exchange of the source and the drain in each MOS transistor. A MOS transistor having a large threshold voltage is provided with a halo diffusion region, and halo implantation is not performed on a MOS transistor having a small threshold voltage. | 2010-07-01 |
20100164016 | ADJUSTING OF STRAIN CAUSED IN A TRANSISTOR CHANNEL BY SEMICONDUCTOR MATERIAL PROVIDED FOR THRESHOLD ADJUSTMENT - The threshold voltage of a sophisticated transistor may be adjusted by providing a specifically designed semiconductor alloy in the channel region of the transistor, wherein a negative effect of this semiconductor material with respect to inducing a strain component in the channel region may be reduced or over-compensated for by additionally incorporating a strain-adjusting species. For example, a carbon species may be incorporated in the channel region, the threshold voltage of which may be adjusted on the basis of a silicon/germanium alloy of a P-channel transistor. Consequently, sophisticated metal gate electrodes may be formed in an early manufacturing stage. | 2010-07-01 |
20100164017 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity. | 2010-07-01 |
20100164018 | HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR DEVICE - A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region. | 2010-07-01 |
20100164019 | METHOD OF MANUFACTURING NONVOLATILE MEMORY DEVICE - A method of manufacturing a nonvolatile memory (NVM) device having a memory gate and a selection gate. A method of manufacturing a NVM device may include a spacer poly formed on and/or over a surface of a substrate including a memory gate. A method of manufacturing a NVM device may include a sacrificing film formed on and/or over a surface of a spacer poly. A method of manufacturing a NVM device may include an etch-back process performed to form a selection gate. The thickness of a memory gate may be minimized. A bridge between a selection gate and a source/drain may be minimized. | 2010-07-01 |
20100164020 | TRANSISTOR WITH AN EMBEDDED STRAIN-INDUCING MATERIAL HAVING A GRADUALLY SHAPED CONFIGURATION - In a transistor, a strain-inducing semiconductor alloy, such as silicon/germanium, silicon/carbon and the like, may be positioned very close to the channel region by providing gradually shaped cavities which may then be filled with the strain-inducing semiconductor alloy. For this purpose, two or more “disposable” spacer elements of different etch behavior may be used in order to define different lateral offsets at different depths of the corresponding cavities. Consequently, enhanced uniformity and, thus, reduced transistor variability may be accomplished, even for sophisticated semiconductor devices. | 2010-07-01 |
20100164021 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include implanting fluorine ions into a portion of a poly gate region on a semiconductor substrate; forming a gate oxide film over the semiconductor substrate such that the gate oxide film is thicker in the fluorine-implanted region; forming the poly gate over the gate oxide film in the poly gate region; and forming lightly doped drains in active regions of the semiconductor substrate on both sides of the poly gate. Further, the method of manufacturing the semiconductor device includes forming spacers over both sidewalls of the poly gate; and forming source and drain regions in the active regions. | 2010-07-01 |
20100164022 | PMOS TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A technique for manufacturing a PMOS transistor may be capable of lowering the electrostatic capacitance of a transistor so as to improve the operation characteristics of a PMOS device. A donor wafer may be bonded onto a wafer having a tunnel oxide film formed thereon, and patterning is performed so as to form PMOS transistors having very low resistance. It is difficult to control resistance only by control with salicide, so by using a method of manufacturing a PMOS transistor using an ion-implanted donor wafer, a PMOS transistor having very low resistance and being voltage-controllable can be formed. | 2010-07-01 |
20100164023 | MICROMECHANICAL COMPONENT AND CORRESPONDING PRODUCTION METHOD - A micromechanical component having a conductive substrate, a first conductive layer provided above the substrate and that forms, above a cavity provided in the substrate, an elastically deflectable diaphragm region of monocrystalline silicon and an adjacent peripheral region, a circuit trace level provided above the first conductive layer in a manner that is electrically insulated from the first conductive layer, the circuit trace level having above the diaphragm region a first electrode region and having above the peripheral region a first connection region electrically connected to the same, and a second conductive layer that is provided above the circuit trace level, the second conductive layer having above the diaphragm region a second electrode region that is electrically insulated from the first electrode region, and having above the peripheral region a second connection region electrically insulated from the second electrode region and electrically connected to the first connection region. Also provided is a suitable production method. | 2010-07-01 |
20100164024 | HIGH ASPECT RATIO ALL SIGE CAPACITIVELY COUPLED MEMS DEVICES - A method that includes forming an opening between at least one first electrode and a second electrode by forming a recess in a first electrode layer, the recess having sidewalls that correspond to a surface of the at least one first electrode, forming a first sacrificial layer on the sidewalls of the recess, the first sacrificial layer having a first width that corresponds to a second width of the opening, forming a second electrode layer in the recess that corresponds to the second electrode, and removing the first sacrificial layer to form the opening between the second electrode and the at least one first electrode. | 2010-07-01 |
20100164025 | METHOD AND STRUCTURE OF MONOLITHETICALLY INTEGRATED MICROMACHINED MICROPHONE USING IC FOUNDRY-COMPATIABLE PROCESSES - A monolithically integrated MEMS and CMOS substrates provided by an IC-foundry compatible process. The CMOS substrate is completed first using standard IC processes. A diaphragm with stress relief corrugated structure is then fabricated on top of the CMOS. Air vent holes are then etched in the CMOS substrate. Finally, the microphone device is encapsulated by a thick insulating layer at the wafer level. The monolithically integrated microphone that adopts IC foundry-compatible processes yields the highest performance, smallest form factor, and lowest cost. Using this architecture and fabrication flow, it is feasible and cost-effective to make an array of Silicon microphones for noise cancellation, beam forming, better directionality and fidelity. | 2010-07-01 |
20100164026 | PREMOLD HOUSING HAVING INTEGRATED VIBRATION ISOLATION - A premold housing for accommodating a chip structure in which a part of the housing that is connected to the chip structure is connected in a manner that permits elastic deflection to another part of the housing which is attached to the supporting structure bearing the entire housing, the two housing parts not contacting one another. | 2010-07-01 |
20100164027 | METHOD FOR PRODUCING A COMPONENT, AND SENSOR ELEMENT - A method for producing a component having at least one diaphragm formed in the upper surface of the component, which diaphragm spans a cavity, and having at least one access opening to the cavity from the back side of the component, at least one first diaphragm layer and the cavity being produced in a monolithic semiconductor substrate from the upper surface of the component, and the access opening being produced in a temporally limited etching step from the back side of the substrate. The access opening is placed in a region in which the substrate material comes up to the first diaphragm layer. The etching process for producing the access opening includes at least one anisotropic etching step and at least one isotropic etching step, in the anisotropic etching step, an etching channel from the back side of the substrate being produced, which terminates beneath the first diaphragm layer in the vicinity of the cavity, and at least the end region of this etching channel being expanded in the isotropic etching step until the etching channel is connected to the cavity. | 2010-07-01 |
20100164028 | SEMICONDUCTOR PRESSURE SENSOR - A semiconductor pressure sensor includes a cavity disposed in one silicon substrate of a SOI substrate having two silicon substrates bonded to each other with an oxide film therebetween and a diaphragm formed from the other silicon substrate and the oxide film, wherein the oxide film, bordering the cavity, of the diaphragm includes an arc-shaped section at the boundary portion to the one silicon substrate defining the inner wall side surface of the cavity, the arc-shaped section having the same diameter as the diameter of the cavity in the one silicon substrate and reducing the cavity diameter from the boundary portion toward the diaphragm center. | 2010-07-01 |
20100164029 | GRADED ORDER-SORTING FILTER FOR HYPERSPECTRAL IMAGERS AND METHODS OF MAKING THE SAME - A graded order-sorting filter for hyperspectral imagers and methods of making the same are provided. The graded order-sorting filter includes a substrate wafer having a first side and a second side and is formed of a material that is substantially transparent to light photons. The graded order-sorting filter also includes an absorption filter deposited outwardly from the first side of the substrate wafer. The absorption filter is tapered along a taper direction and formed of a graded composition semiconductor material with a bandgap graded to decrease outwardly from the substrate wafer and/or graded along the taper direction. The graded composition semiconductor material is substantially transparent to the light photons for photon energies substantially less than the bandgap. The above filter can also be aligned to a two-dimensional array of pixels to form a hyperspectral imager. | 2010-07-01 |
20100164030 | CHIP CARRIER BEARING LARGE SILICON FOR HIGH PERFORMANCE COMPUTING AND RELATED METHOD - Embodiments of the present invention provide a system and method for manufacturing integrated circuit (IC) chip packages. In one embodiment, the integrated circuit (IC) chip package can include an IC chip and a substrate coupled to the IC chip. The substrate can include a glass fiber re-enforced epoxy core, a plurality copper circuitry containing particle re-enforced epoxy layers symmetrically-oriented to each surface of the glass fiber re-enforced epoxy core, and an outermost amorphous glass layer on each surface of the plurality of layers. The IC chip can be coupled to copper circuitry bonded to one of the outermost amorphous glass layers. | 2010-07-01 |
20100164031 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - An image sensor and a manufacturing method thereof are provided. The image sensor according to an embodiment includes: a semiconductor substrate where a light receiving device is formed for each pixel; a dielectric layer formed on the semiconductor substrate; and a metal layer formed in the dielectric layer and including metal wires and light shielding patterns formed on an interface between pixels. In the image sensor according to the embodiment, since the light shielding pattern is formed by using a dummy pattern of the metal wire, the light shielding pattern may be formed close to the semiconductor substrate to minimize generation of optical leakage current, thereby improving reliability of the device. | 2010-07-01 |
20100164032 | SEMICONDUCTOR OPTICAL SENSOR ELEMENT AND METHOD OF PRODUCING THE SAME - A method of producing a semiconductor optical sensor element includes the steps of: forming an oxide film on a silicon carbide substrate; forming a gate electrode layer on the oxide film; patterning the gate electrode layer to form a gate electrode; and processing thermally the gate electrode layer or the gate electrode under an oxidation environment. Further, the gate electrode layer or the gate electrode is thermally processed under the oxidation environment at a temperature between 750° C. and 900° C. | 2010-07-01 |
20100164033 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a method of manufacturing an image sensor. An image sensor may include a semiconductor substrate which may include a readout circuitry. An image sensor may include an interlayer dielectric over a semiconductor substrate, and/or a first metal pattern over an interlayer dielectric. An interconnection may penetrate an interlayer dielectric and/or may be connected to a readout circuitry. A first metal pattern may be formed over an interlayer dielectric, and/or may be connected to an interconnection. A second metal pattern may be formed over a first metal pattern. A photodiode pattern may be formed over a second metal pattern. | 2010-07-01 |
20100164034 | IMAGE SENSOR AND FABRICATION METHOD THEREOF - An image sensor and a method of fabricating an image sensor. A method of fabricating an image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate, a filter array including color filters arranged corresponding to upper parts of photodiodes, a plurality of hydrophilic lenses arranged over a filter array spaced apart from one another, and/or a plurality of hydrophobic lenses arranged over a filter array between hydrophilic lenses. A curvature of a lens may be substantially equal in a horizontal, vertical and/or diagonal direction. | 2010-07-01 |
20100164035 | BACK SIDE ILLUMINATON IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A back side illumination image sensor according to an embodiment includes: a device isolation region and a pixel region that are on a front side of a first substrate; a light sensor and a readout circuit that are on the pixel region; an interlayer dielectric layer and a metal line that are on the front side of the first substrate; a second substrate that is bonded to the front side of the first substrate on which the metal line is formed; a pixel isolating dielectric layer that is on the device isolation region at a back side of the first substrate; and a microlens that is on the light sensor at the back side of the first substrate | 2010-07-01 |
20100164036 | BACK SIDE ILLUMINATION IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed are a back side illumination image sensor and a method for manufacturing the same. The back side illumination image sensor includes an isolation region and a pixel area on a front side of a first substrate; a photo detector and a readout circuitry on the pixel area; an interlayer dielectric layer and a metal line on the front side of the first substrate; a second substrate bonded to the front side of the first substrate formed with the metal line; a pixel division ion implantation layer on the isolation region at a back side of the first substrate; and a micro-lens on the photo detector at the back side of the first substrate. | 2010-07-01 |
20100164037 | METHOD FOR MANUFACTURING IMAGE SENSOR - A method of manufacturing an image sensor. A method of manufacturing an image sensor may include forming a circuit area including a circuitry on and/or over a semiconductor substrate having a pixel area and/or a peripheral area, provided with a photodiode. A method may include forming a metal interconnection layer, which may include a metal interconnection on and/or over a interlayer dielectric layer, on and/or over a circuit area, forming a trench over a metal interconnection layer of a pixel area, performing a cleaning process on and/or over a the metal interconnection layer including a trench, and/or forming a micro-lens on and/or over a bottom surface of a trench of a metal interconnection layer. | 2010-07-01 |
20100164038 | IMAGE SENSOR - Embodiments relate to an image sensor and a method of manufacturing the image sensor. An image sensor according to the embodiment includes: silicon patterns that are formed on a flexible substrate; a device isolation pattern that is formed between the silicon patterns; a circuit layer that is formed on the silicon patterns and has a first isolation pattern directly connected with the device isolation pattern; and a wiring layer that is formed on the circuit layer and includes a second isolation pattern corresponding to the first isolation pattern, and a wiring electrically connected with the circuit layer. The embodiments provide a flexible image sensor that can be applied to a variety of products and a method of manufacturing the flexible image sensor. | 2010-07-01 |
20100164039 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a photodiode arranged over a semiconductor substrate, a core layer for an optical waveguide, to allow incident light to move toward the photodiode, the core layer being arranged over the photodiode, a clad layer for the optical waveguide, having a lower refractive index than the core layer to reflect the incident light to the photodiode, the clad layer being arranged over the side core layer, and a dielectric layer arranged over a side of the clad layer. An optical waveguide having a uniform refractive index and a flat light-reflection surface can be formed using semiconductor materials such as InP, InGaAsP, SiO2, SiON and PMMA. Furthermore, the optical waveguide can control a refractive index and thus reduce light loss, and a buffer layer can be simply formed by using a polymer. | 2010-07-01 |
20100164040 | Microlens Structure for Image Sensors - A microlens structure and a method of fabrication thereof are provided. The method comprises forming a layer of microlens material over a substrate, which has photo-sensitive elements formed therein. The microlens material, which comprises a photo-resist material, is exposed in accordance with a desired pattern a plurality of times. The energy used with each exposure process is less than the energy required if a single exposure is used. Furthermore, the masks used for each exposure may differ. In an embodiment, the masks are varied so as to create a notch in the upper corner of the microlens. The microlens structure may have a height less than about 0.5 um and/or a gap between microlenses less than about 0.2 um. In an embodiment, one or more dielectric layers having a combined thickness greater than about 3.5 um are interposed between the photo-sensitive elements and the microlenses. | 2010-07-01 |
20100164041 | BACK SIDE ILLUMINATON IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - A back side illumination image sensor according to an embodiment includes: a photosensitive device and a readout circuit on the front side of a first substrate; an interlayer dielectric layer on the front side of the first substrate; a metal line on the interlayer dielectric layer; a pad having a step on the interlayer dielectric layer; and a second substrate bonded with the front side of the first substrate over the interlayer dielectric layer, metal line, and pad. | 2010-07-01 |
20100164042 | BACKSIDE-ILLUMINATED (BSI) IMAGE SENSOR WITH BACKSIDE DIFFUSION DOPING - Embodiments of a process comprising forming a pixel on a front side of a substrate, thinning the substrate, depositing a doped silicon layer on a backside of the thinned substrate, and diffusing a dopant from the doped silicon layer into the substrate. Embodiments of an apparatus comprising a pixel formed on a front side of a thinned substrate, a doped silicon layer formed on a backside of the thinned substrate, and a region in the thinned substrate, and near the backside, where a dopant has diffused from the doped silicon layer into the thinned substrate. Other embodiments are disclosed and claimed. | 2010-07-01 |
20100164043 | METHOD FOR FABRICATING CMOS IMAGE SENSOR - A method of forming a CMOS image sensor and a CMOS image sensor. A method of forming a CMOS image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate at regular intervals, forming an interlayer insulating film on and/or over an entire surface of a semiconductor substrate including photodiodes, coating an organic compound on and/or over an entire surface of an interlayer insulating film, coating photoresist on and/or over an organic compound, subjecting a photoresist to exposure and/or development to form a photoresist pattern which may expose an interlayer insulating film opposite to a photodiode region, selectively etching a portion of an exposed interlayer insulating film using a photoresist pattern as a mask, and/or removing a photoresist pattern. | 2010-07-01 |
20100164044 | IMAGE SENSOR AND MANUFACTURING METHOD THEREOF - An image sensor includes first to fourth image sensing sections symmetrically aligned in a form of a 2×2 matrix, first to fourth pixel arrays aligned in the first to fourth image sensing sections, respectively, in adjacent to each other, and first to fourth peripheral circuit parts aligned at peripheral portions of the first to fourth image sensing sections. A middle-size CMOS image sensor is provided that is suitable for the available field size of conventional photo equipment, so the manufacturing cost may be minimized and price competitiveness may be maximized while providing high-quality images with high pixel resolution. | 2010-07-01 |
20100164045 | IMAGER METHOD AND APPARATUS EMPLOYING PHOTONIC CRYSTALS - An image sensor and a method of forming an image sensor. The image sensor includes an array of pixel cells at a surface of a substrate. Each pixel cell has a photo-conversion device. At least one a micro-electro-mechanical system (MEMS) element including a photonic crystal structure is provided over at least one of the pixel cells. The MEMS-based photonic crystal element is supported by a support structure and configured to selectively permit electromagnetic wavelengths to reach the photo-conversion device upon application of a voltage. As such, the MEMS-based photonic crystal element of the invention can replace or compliment conventional filters, e.g., color filter arrays. | 2010-07-01 |
20100164046 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor and a method for manufacturing the same are provided. The image sensor can include a semiconductor substrate, an interlayer dielectric, a second doped layer, a first doped layer, an ohmic contact layer, and metal contacts. The semiconductor substrate can have a pixel region and a peripheral region defined therein. The second doped layer, the first doped layer, and the ohmic contact layer can be stacked on the interlayer dielectric of the semiconductor substrate to form an image sensing device in the pixel region. | 2010-07-01 |
20100164047 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - An image sensor includes a semiconductor substrate, an interconnection and an interlayer dielectric, an image sensing device, a trench, a buffer layer, a barrier pattern, a via hole, and a metal contact. The semiconductor substrate includes a readout circuitry. The interconnection and an interlayer dielectric layer are formed on and/or over the semiconductor substrate while the interconnection is connected to the readout circuitry. The image sensing device may be formed on and/or over the interlayer dielectric and a trench may be formed in the image sensing device, the trench corresponding to the interconnection. The buffer layer may be formed on a sidewall of the trench. The barrier pattern may be formed on the buffer layer with the via hole penetrating through the image sensing device and the interlayer dielectric under the barrier pattern and exposing the interconnection. The metal contact may be formed in the via hole. | 2010-07-01 |
20100164048 | METHOD FOR FABRICATING A SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR SUBSTRATE - The disclosure provides a method for fabricating a semiconductor substrate comprising the steps of: providing a semiconductor on insulator type substrate, providing a diffusion barrier layer and providing a second semiconductor layer. By providing the diffusion barrier layer, it becomes possible to suppress diffusion from the highly doped first semiconductor layer into the second semiconductor layer. The invention also relates to a corresponding semiconductor substrate and opto-electronic devices comprising such a substrate. | 2010-07-01 |
20100164049 | IMAGE SENSOR AND METHOD FOR MANUFACTURING THE SAME - Provided are an image sensor and a method for manufacturing the same. The image sensor comprises an active region including a photodiode region, a transistor region, and an active pattern; a photodiode; and a plurality of transistors. The active region is formed on a substrate. The active region is defined by a device isolation region. The photodiode region and the transistor region are formed in the active region. The photodiode is formed in the photodiode region. The plurality of transistors is formed on the transistor region. The active pattern connects the photodiode region to the transistor region at a second location. | 2010-07-01 |
20100164050 | ROBUST STRUCTURE FOR HVPW SCHOTTKY DIODE - A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring. | 2010-07-01 |
20100164051 | SEMICONDUCTOR DEVICE HAVING SADDLE FIN-SHAPED CHANNEL AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate with an isolation layer formed in the semiconductor substrate to delimit active regions. Recess patterns for gates are defined in the active regions and the isolation layer. Gate patterns are formed in and over the recess patterns for gates, and a gate spacer is formed to cover the gate patterns. The recess patterns for gates have a first depth in the active regions and a second depth, which is greater than the first depth, in the isolation layer. Gaps are created between the gate patterns and upper parts of the recess patterns for gates that are defined in the isolation layer. The gate spacer fills the gaps and protects the gate spacer so as to prevent bridging. | 2010-07-01 |
20100164052 | HIGH POWER INTEGRATED CIRCUIT DEVICE - An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers. | 2010-07-01 |
20100164053 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor wafer in which semiconductor chip forming regions and a scribe region located between the semiconductor chip forming regions are formed, a plurality of semiconductor chip circuit portions provided over the semiconductor wafer, a plurality of first conductive layers, provided in each of the semiconductor chip forming regions, which is electrically connected to each of the circuit portions, and a first connecting portion that electrically connects the first conductive layers to each other across a portion of the scribe region. An external power supply or grounding pad is connected to any one of the first conductive layer and the first connecting portion. The semiconductor device includes a communication portion, connected to the circuit portion, which performs communication with the outside by capacitive coupling or inductive coupling. | 2010-07-01 |
20100164054 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are provided. The semiconductor device can include a semiconductor substrate including a trench, a first oxide layer in the trench, a second oxide layer filled in the trench to form an insulating layer, and a silicon nitride layer interposed between the first and second oxide layers. The silicon nitride layer can be etched such that the silicon nitride layer is recessed from top surfaces of the semiconductor substrate and the second oxide layer, thereby forming a divot at a top corner of the trench. | 2010-07-01 |
20100164055 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE AND WAFER - A deep isolation trench extending from the main surface of a substrate to a desired depth is formed on the substrate with an insulating film in buried in it to form a through isolation portion. Subsequently, after a MOSFET is formed on the main surface of the substrate, an interlayer insulating film is deposited on the main surface of the substrate. Then, a deep conduction trench extending from the upper surface of the interlayer insulating film to a depth within the thickness of the substrate is formed in a region surrounded by the through isolation potion. Subsequently, a conductive film is buried in the deep conduction trench to form through interconnect portion. Then, after the undersurface of the substrate is ground and polished to an extent not to expose the through isolation portion and the through interconnect portion, wet etching is performed to an extent to expose parts of the lower portion of each of the through isolation portion and the through interconnect portion. | 2010-07-01 |
20100164056 | MICROELECTRONIC ASSEMBLIES WITH IMPROVED ISOLATION VOLTAGE PERFORMANCE - Embodiments of microelectronic assemblies are provided. First and second semiconductor devices are formed over a substrate having a first dopant type at a first concentration. First and second buried regions having a second dopant type are formed respectively below the first and second semiconductor devices with a gap therebetween. At least one well region is formed over the substrate and between the first and second semiconductor devices. A barrier region having the first dopant type at a second concentration is formed between and adjacent to the first and second buried regions such that at least a portion of the barrier region extends a depth from the first and second semiconductor devices that is greater or equal to the depth of the buried regions. | 2010-07-01 |
20100164057 | PRECURSORS FOR SILICON DIOXIDE GAP FILL - A full fill trench structure comprising a microelectronic device substrate having a high aspect ratio trench therein and a full filled mass of silicon dioxide in the trench, wherein the silicon dioxide is of a substantially void-free character and has a substantially uniform density throughout its bulk mass. A corresponding method of manufacturing a semiconductor product is described, involving use of specific silicon precursor compositions for use in full filling a trench of a microelectronic device substrate, in which the silicon dioxide precursor composition is processed to conduct hydrolysis and condensation reactions for forming the substantially void-free and substantially uniform density silicon dioxide material in the trench. The fill process may be carried out with a precursor fill composition including silicon and germanium, to produce a microelectronic device structure including a GeO | 2010-07-01 |
20100164058 | CHIP PACKAGE WITH STACKED INDUCTORS - A semiconductor chip package with inductors includes a substrate, a semiconductor chip, an inductor and an insulator cover. The substrate has an active surface with a patterned circuit thereon. The inductor disposes on the active surface of the substrate. The semiconductor chip stacks over the inductor and electrically interconnects with the patterned circuit of the substrate and the inductor. The insulator cover encapsulates the inductor and the chip. | 2010-07-01 |
20100164059 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate; an insulating film formed over the semiconductor substrate, there being formed in the insulating film a trench that in a sectional view has a stepped shape; and a wiring formed in the trench, wherein the wiring includes, a main portion with a first thickness; and an extended portion with a second thickness that is thinner than the first thickness and that extends outward from a side of the main portion. | 2010-07-01 |