25th week of 2011 patent applcation highlights part 26 |
Patent application number | Title | Published |
20110148469 | STACKED DEVICE DETECTION AND IDENTIFICATION - Various embodiments include apparatus and methods having circuitry to detect and/or assign identification information to dice arranged in a stack and coupled by conductive paths. | 2011-06-23 |
20110148470 | Communication device - According to an exemplary aspect of the present invention, it is possible to provide a communication device that can prevent misdetection of a disconnection and achieve a high output level on a receptacle side. In the communication device, a reference voltage generating circuit outputs a reference voltage that changes according to a first control signal. A differential amplifier circuit amplifies input signals and outputs differential output signals, the voltages of which change according to a second control signal, to a receptacle. A disconnection detector circuit outputs a disconnection detecting signal when a differential amplitude voltage between the differential output signals is equal to or higher than the reference voltage. The reference voltage generating circuit outputs the reference voltage that is larger than the differential amplitude voltage when the receptacle is terminated and that is smaller than the differential amplitude voltage when the receptacle is opened. | 2011-06-23 |
20110148471 | Temperature-Independent Undervoltage Detector and Related Method - Embodiments related to an undervoltage detector are described and depicted. An undervoltage detector is formed to detect a low input bias voltage with a voltage divider network including first and second series circuits of semiconductor devices coupled to terminals of the input bias voltage source, and a resistor voltage divider including first and second voltage divider resistors coupled in series with the first and second series circuits. A ratio representing the numbers of semiconductor devices in the series circuits is substantially equal to a ratio of resistances in the resistor voltage divider. The equality of the ratios may be corrected by the presence of other resistances in the undervoltage detector. The semiconductor devices are each coupled in a diode configuration. The first series circuit is coupled to a current mirror to provide a bias current for a comparator that produces an output signal for the undervoltage detector. | 2011-06-23 |
20110148472 | VOLTAGE CHANGE DETECTION DEVICE - A voltage change detection device is provided, which can reduce a deviation of a detection potential and can detect a voltage change within a predetermined detection potential even when the threshold voltage of a field effect transistor is deviated. The voltage change detection device includes a first field effect transistor, a second field effect transistor, and a detection signal generator. The first field effect transistor has a drain connected to a power supply potential, a source connected to a first constant current source or a first resistor at a first node, and a gate connected to a fixed voltage. The second field effect transistor has a drain and a gate connected to the power supply potential and a source connected to a second constant current source or a second resistor at a second node. The detection signal generator generates a detection signal indicating that the power supply potential has crossed a predetermined detection potential according to a comparison between a voltage at the first node and a voltage at the second node. | 2011-06-23 |
20110148473 | SWITCH-BODY PMOS SWITCH WITH SWITCH-BODY DUMMIES - An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. | 2011-06-23 |
20110148474 | Circuitry and Methods for Improving Differential Signals That Cross Power Domains - Disclosed herein are circuitry and methods for improving differential signals that cross power domains. In an example embodiment, the power supply domain boundary along the output paths that generate the differential signal is staggered, such that the boundary occurs at an odd numbered stage in one differential output path and at an even numbered stage in the other differential output. Defining the power supply domain boundary in this manner can help ensure that the same logical state is present at the boundary in either of the differential output paths. This same logic signal should affect subsequent stages similarly from a speed perspective, and so should similarly affect the differential signals generated by each of the output paths. This means, among other things, that the differential signal as generated should tend to cross nearer to a midpoint voltage, which increases its compliance with certain integrated circuit specifications such as the Vox specification used for the differential data strobe in an SDRAM. | 2011-06-23 |
20110148475 | DRIVING CIRCUIT OF INPUT/OUTPUT INTERFACE - A driving circuit of an input/output (I/O) interface is provided. The driving circuit includes a main output stage and an enhancing unit. The main output stage receives at least one driving signal and outputs an output signal corresponding to an input signal accordingly. The enhancing unit is coupled to the main output stage. The enhancing unit receives and detects the level of the output signal so as to drive the output force of the main output stage in a first output level or a second output level, wherein the first output level is higher than the second output level. | 2011-06-23 |
20110148476 | Overload Protection for a Circuit Arrangement Having a Transistor - A drive circuit for a transistor and a method for driving a transistor are described. | 2011-06-23 |
20110148477 | SIGNAL TRANSMISSION DEVICE - A signal transmission device includes a transmitting circuit | 2011-06-23 |
20110148478 | FREQUENCY CONVERSION MIXER - Provided is a frequency conversion mixer. The frequency conversion mixer includes a transconductance stage, a switching stage, a load stage, a current bleeding circuit, and a bias stage. The transconductance stage receives an RF signal, and outputs a current corresponding to a voltage of the RF signal. The switching stage switches the current which is outputted from the transconductance stage in response to a local oscillation signal, for frequency conversion the RF signal into an intermediate frequency (IF) signal. The load stage is connected between the switching stage and a supply voltage terminal. The current bleeding circuit is connected parallel with the switching stage, especially, embodying inverter structure with transconductance stage to get not only current bleeding effect but also current reuse effect, and one resonant inductor for reducing noise which is generated in parasitic capacitance at node between transconductance stage and switching stage. The bias stage is connected between the transconductance stage and a ground terminal, and has the switched biasing technique for allowing not only the stable bias current but also lowering the flicker noise. | 2011-06-23 |
20110148479 | SIGNAL RECEIVING DEVICE AND SIGNAL RECEIVING METHOD USING SAME, AND SIGNAL SUPPLYING UNIT AND SIGNAL SUPPLYING METHOD USING SAME - A signal receiving device is provided which can prevent the imbalance occurring between in-phase and quadrature signals. A polarity of a local oscillator output signal to be outputted from a local oscillator | 2011-06-23 |
20110148480 | Divider with Enhanced Duty Cycle for Precision Oscillator Clocking Sources - A divider is disclosed that presents an enhanced duty cycle for use with precision oscillators in clock sources. In one example, the invention includes a first divider chain to receive an input clock and produce a first divided output, a second divider chain to receive the input clock and produce a second divided output, and a combiner to combine the first and second divided output to produce a third divided output with a duty cycle greater than the first and second divided output. | 2011-06-23 |
20110148481 | WAVEFORM GENERATION CIRCUIT - A waveform generation circuit includes: a waveform generation block configured to generate a waveform signal corresponding to a driving control signal; and a control signal generation block configured to generate a driving control signal for compensating the waveform signal for an environmental factor reflected into the waveform generation circuit. | 2011-06-23 |
20110148482 | METHOD OF CHOOSING A FUNCTIONING MODE OF AN INTEGRATED CIRCUIT DEVICE AND RELATIVE DEVICE - A method is for choosing a mode out of a set of functioning modes of an integrated circuit (IC) device powered from different supply voltages from respective supply nodes. The IC device may include a mode pin for determining a functioning mode of the device, an internal control circuit coupled to the supply nodes and to the mode pin for sensing an electrical value on the mode pin and to start the IC device in a respective functioning mode depending on the supply node that is powered first. The method may include identifying the different supply voltage that first exceeds a threshold voltage, when the internal control circuit is powered, sensing the electrical value on the mode pin, and powering circuits of the IC device from the different supply voltage that first exceeded the threshold voltage and starting the device in a functioning mode determined by a value of the electrical value sensed on the mode pin and by the different supply voltage that first exceeded the voltage threshold. | 2011-06-23 |
20110148483 | INTEGRATED ELECTRONIC DEVICE WITH REFERENCE VOLTAGE SIGNAL GENERATION MODULE AND UVLO LOGIC SIGNAL GENERATION MODULE - An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group. | 2011-06-23 |
20110148484 | PHASE-LOCKED LOOP FREQUENCY SYNTHESIZER - Described is a frequency synthesizer having a wide output frequency range and small frequency tuning steps. In-band spurious components are maintained at low levels and phase noise is significantly reduced. The frequency synthesizer can be fabricated as an integrated circuit device having a small area and low power dissipation. The frequency synthesizer can be used in wideband frequency systems to reduce cost and size by replacing multiple frequency synthesizers each devoted to a portion of the overall system frequency range. | 2011-06-23 |
20110148485 | PHASE-LOCKED LOOP CIRCUIT COMPRISING VOLTAGE-CONTROLLED OSCILLATOR HAVING VARIABLE GAIN - A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition. | 2011-06-23 |
20110148486 | CONTROLLED CLOCK GENERATION - Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL. | 2011-06-23 |
20110148487 | DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME - A DLL circuit includes a clock selection control unit configured to generate a clock selection signal on the basis of a phase difference between a reference clock and a feedback clock and, after the clock selection signal is generated, to generate an initialization signal. A delay control unit, when the initialization signal is enabled, transfers an initial voltage to be generated by dividing an external power supply voltage to a delay unit as a control voltage, and controls a delay operation of a delay reference clock to be selected on the basis of the clock selection signal. | 2011-06-23 |
20110148488 | DIGITAL PHASE LOCKED LOOP WITH CLOSED LOOP LINEARIZATION TECHNIQUE - Apparatuses, systems, and a method for providing a digital phase-locked loop (PLL) are described. In one embodiment, an apparatus includes an integration-mode phase frequency detector (PFD) that compares a phase and frequency of a reference clock signal to a phase and frequency of a generated feedback clock signal and generates a digitized output signal. A digital loop filter (DLF) receives the digitized output signal and applies a linearization technique to the digitized output signal. The DLF includes a derivative gain unit of a derivative path, a proportional gain unit of a proportional path, and an integral gain unit of an integral path. The derivative path provides a direct proportional feedback loop path to the integration-mode PFD by compensating the integration of an integrator that receives output signals from the paths. The integration-mode PFD can be implemented with a hybrid circuit or a substantially digital circuit. | 2011-06-23 |
20110148489 | Adaptive digital phase locked loop - In some embodiments, a digital PLL is disclosed with a dynamically controllable filter for changing the effective DPLL bandwidth in response to one or more real-time performance parameters such as phase error. | 2011-06-23 |
20110148490 | TIME-TO-DIGITAL CONVERTER AND ALL DIGITAL PHASE-LOCKED LOOP INCLUDING THE SAME - An all digital phase-locked loop (ADPLL) includes: a phase counter accumulating a frequency setting word value and the phase of a digitally controlled oscillator (DCO) clock and detecting a fine phase difference between a reference clock and a retimed clock; a phase detector detecting a digital phase error value compensating for a phase difference between the frequency setting word value and the DCO clock according to the fine phase difference to detect a digital phase error value; a digital loop filter filtering the digital phase error value and controlling PLL operational characteristics; a lock detector generating a lock indication signal according an output of the digital loop filter; a digitally controlled oscillator varying the frequency of the DCO clock according to the output from the digital loop filter; and a retimed clock generator generating the retimed clock by retiming the DCO clock at a low frequency. | 2011-06-23 |
20110148491 | SEMICONDUCTOR APPARATUS AND LOCAL SKEW DETECTING CIRCUIT THEREFOR - A local skew detecting circuit for a semiconductor apparatus include a reference delay block located on the center of the semiconductor apparatus, the reference delay block being configured to receive a predetermined signal and generate a reference delay signal by delaying the predetermined signal by a delay time and a first timing detecting block located on one edge of the semiconductor apparatus, the first timing detecting block being configured to receive the predetermined signal, generate a first delay signal by delaying the predetermined signal by the delay time, and detect an enable timing order of the reference delay signal and the first delay signal to generate a first detection signal. | 2011-06-23 |
20110148492 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus comprising a synchronization module that operates according to a reference clock and outputs a synchronization signal with a prescribed period, and a test module that operates according to a high-frequency clock with a frequency that is n times a frequency of the reference clock. The test module includes a period emulator that emulates the synchronization signal, a phase shifter that shifts a phase of the high-frequency clock by an amount equal to a result of (i) the product of n and the emulated synchronization phase data by (ii) a period of the reference clock, and a test period generating section that generates a test period pulse signal that transitions at an edge timing of the shifted high-frequency clock and test period phase data indicating a phase difference between the test period signal and an edge timing of the test period pulse signal. | 2011-06-23 |
20110148493 | OUTPUT SLEW RATE CONTROL - This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry. | 2011-06-23 |
20110148494 | SIGNAL DRIVER WITH FIRST PULSE BOOST - A driver boost signaling circuit provides a pulse boost to the first cycle of an output pulse wave applied to an associated load. The circuit includes a signal generator circuit generating a signal including a series of pulses, a determining circuit determining a high impedance state of a signal load line and a first one or more cycles of the series of pulses applied to the load line following the high impedance condition, and a receiving circuit receiving a control signal. A logic circuit generates first and second logical signals responsive to the control signal and to the determining circuit determining the first one or more cycles and other cycles of the series of pulses. A switchable impedance circuit coupling the signal generator with the associated load line is responsive to the first logical signal to provide a low impedance level between the signal generator circuit and the associated signal load line, and to the second logical signal to provide a high impedance level between the signal generator circuit and the associated signal load line. | 2011-06-23 |
20110148495 | DATA HOLDING CIRCUIT - A data holding circuit including a first input terminal through which data is inputted; at least one delay element for delaying the data inputted through the first input terminal; and a first element for holding data, wherein, when the data inputted through the first input terminal and the data delayed by the delay element are equal to each other, the first element holds data corresponding to the data inputted through the first input terminal and wherein, when the data inputted through the first input terminal and the data delayed by the delay element are different from each other, the first element continues to hold the data presently held by the first element. | 2011-06-23 |
20110148496 | LEAKAGE CURRENT REDUCTION IN A SEQUENTIAL CIRCUIT - A system and device for reducing leakage current in a sequential circuit is disclosed. In one embodiment, a system for reducing leakage current in a sequential circuit includes a combinational logic circuit, one or more reset flip-flops coupled to the combinational logic circuit, and one or more set-reset flip-flops coupled to the combinational logic circuit. The system further includes a control module coupled to the reset flip-flops and to the set flip-flops and configured to reset the reset flip-flops and to set the set-reset flip-flops when a standby mode of the sequential circuit is triggered. | 2011-06-23 |
20110148497 | SEMICONDUCTOR DEVICE - An object is to provide a low-power semiconductor device which does not require a latch circuit to hold data at the output of inverter circuits. In the semiconductor device, an input of a first inverter circuit is connected to an input terminal through a source and a drain of a first transistor. An input of a second inverter circuit is connected to an output of the first inverter circuit through a source and a drain of a second transistor. An output of the second inverter is connected to an output terminal. An inverted clock signal and a clock signal are input to gates of the first transistor and the second transistor, respectively. The first and the second transistor have extremely low off-current, which allows the output potential of the device to remain unchanged even when the input varies. | 2011-06-23 |
20110148498 | DIGITAL QUADRATURE PHASE CORRECTION - Methods and systems to adjust a phase difference between signals, such as to perform quadrature phase correction. First and second signals are digitally compared, such as with exclusive OR circuitry, to provide a comparison signal having a duty cycle representative of a phase difference between the signals. A phase delay of one or both of the first and second signals is adjusted until the duty cycle of the comparison signal corresponds to a desired phase difference. In a clock and data recovery system, the signals may correspond to a zero degree phase of a first phase interpolator and a ninety degree phase of a second phase interpolator, and digital codes to the first and second phase interpolators may be adjusted to provide a fifty percent duty cycle in the comparison signal. | 2011-06-23 |
20110148499 | SIGNAL GENERATING APPARATUS AND TEST APPARATUS - Provided is a signal generating apparatus that outputs from an output end thereof an output voltage corresponding to input data supplied thereto, comprising: a DA converter that outputs a voltage corresponding to data supplied thereto; a capacitor section that is provided between the output end and a standard potential; a transmission switch that provides a connection or a disconnect between a voltage generating end of the DA converter and the output end; and a control section that causes the DA converter to charge the capacitor section with a voltage corresponding to the input data by repeatedly connecting and disconnecting the transmission switch, thereby causing the voltage of the capacitor section to gradually approach the output voltage corresponding to the input data. | 2011-06-23 |
20110148500 | SAMPLE HOLD CIRCUIT AND METHOD THEREOF FOR ELIMINATING OFFSET VOLTAGE OF ANALOG SIGNAL - A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage. | 2011-06-23 |
20110148501 | VARIABLE ATTENUATOR HAVING STACKED TRANSISTORS - In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator. | 2011-06-23 |
20110148502 | TEMPERATURE COMPENSATION ATTENUATOR - In one embodiment, a temperature compensating attenuator is disclosed having an attenuation circuit and a control circuit. The temperature compensating attenuator circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with an impedance attenuation level having a continuous impedance range. The control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the attenuation level of the attenuation circuit. The temperature compensating attenuator includes a temperature compensating circuit that compensates for variations in operation of the attenuation circuit due to a temperature change. | 2011-06-23 |
20110148503 | TEMPERATURE CONTROLLED ATTENUATOR - In one embodiment, a temperature controlled attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. Furthermore, the temperature controlled attenuator includes a temperature controlled circuit that adjusts the attenuation level of the attenuation circuit in accordance to an operating temperature. In this manner, the attenuation level of the temperature controlled attenuator is temperature dependent. | 2011-06-23 |
20110148504 | APPARATUS AND METHOD FOR HDMI TRANSMISSION - Apparatus and methods are disclosed, such as those involving a high frequency transmitter. One such apparatus includes a pre-amplifier configured to receive an input signal via an input node; and a capacitor block electrically coupled between the pre-amplifier and an output node from which an output signal is transmitted. The capacitor block is configured to provide charge to the output node or pull charge from the output node while the output signal transitions. The apparatus further includes a switch electrically coupled between the output node and a voltage reference, wherein the switch is turned on or off at least partly in response to a signal from the pre-amplifier. This configuration effectively reduces rise and fall time of the output signal for high-frequency transmission. | 2011-06-23 |
20110148505 | SOLID-STATE ALTERNATING CURRENT (AC) SWITCH - A solid-state alternating current (AC) switch provides for the sequential turn-on of the associated solid-state switches to reduce the generation of electromagnetic interference (EMI). The solid-state AC switch includes at least first and second solid-state switches connected in series between an AC input and an AC load. A zero-cross detector circuit monitors the AC input to determine zero-crossings associated with the monitored AC input. A controller turns on the first solid-state switch and the second solid-state switch according to a turn-on sequence in which the first transistor is turned ON during a detected zero-crossing window associated with the first transistor and the second transistor is subsequently turned ON during a detected zero-crossing associated with the second transistor. | 2011-06-23 |
20110148506 | INTEGRATION OF MOSFETS IN A SOURCE-DOWN CONFIGURATION - An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch. | 2011-06-23 |
20110148507 | SWITCH-BODY NMOS-PMOS SWITCH WITH COMPLEMENTARY CLOCKED SWITCH-BODY NMOS-PMOS DUMMIES - A sample-and-hold feed switch has parallel PMOS branches and parallel NMOS branches, each extending from an input node to an output node connected to a hold capacitor. Each PMOS branch has a PMOS switch FET connected to a matching PMOS dummy FET, and each NMOS branch has an NMOS switch FET connected to a matching NMOS dummy FET. A sample clock switches the PMOS switch FETs on and off, and a synchronous inverse sample clock effects complementary on-off switching of the PMOS dummy FETs. Concurrently, a synchronous inverse sample clock switches the NMOS switch FETs on and off, and the sample clock effects a complementary on-off switching of the NMOS dummy FETs. A bias sequencer circuit biases the bodies of the PMOS switch FETs and the bodies of the PMOS dummy FETs, in a complementary manner, and biases the NMOS switch FETs and the NMOS dummy FETs, also in a complementary manner. The on-off switching of the PMOS dummy FETs injects charge, cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs. The on-off switching of the NMOS dummy FETs injects charge that cancels a charge injection by the NMOS signal switch FETs, and injects glitches that cancels glitches injected by the NMOS signal switch FETs. | 2011-06-23 |
20110148508 | CONTROL CIRCUIT OF CYCLING SWITCH AND CONTROL METHOD THEREOF - A control circuit of a cycling switch for controlling an electronic equipment includes a switch loop, a first control loop and a second control loop. The switch loop generates a driving signal to drive the electronic equipment. The first control loop is electrically connected with the switch loop and the electronic equipment respectively, and generates a first control signal according to a variation of the driving signal. The second control loop is electrically connected with the first control loop and the electronic equipment respectively. The second control loop has a storage unit which charges and discharges according to the first control signal, so that the second control loop generates a second control signal. The second control signal is inputted to the first control loop and controls the electronic equipment. A control method applied to the control circuit of the cycling switch is also disclosed. | 2011-06-23 |
20110148509 | Techniques to Reduce Charge Pump Overshoot - A charge pump system for supplying an output voltage to a load is described. The charge pump system includes a charge pump connected to receive an input voltage generate from it the output voltage. The system also includes regulation circuitry connected to receive the output voltage and a reference voltage, where the regulation circuitry is connected to the charge pump to regulate the output voltage based upon the values of the reference voltage and the output voltage. During ramp up or a recovery operation the output voltage is initially regulated according to a first level and subsequently regulated to a second level higher than the first level, the second level corresponding to a desired regulated output voltage. | 2011-06-23 |
20110148510 | REDUCED CURRENT CHARGE PUMP - This document discusses, among other things, a charge pump having a plurality of switching devices, coupled in parallel, and configured to selectively provide a variable available drive current for a capacitor using a comparison of an output voltage to at least one reference voltage. | 2011-06-23 |
20110148511 | AUTARKES FELDGERAT - An automation technology, autarkic, field device, which is connected via two connecting terminals to an I/O module. The I/O module is embodied as a 4-20 mA/HART I/O module. The I/O module is associated with a controllable energy source via which the field device is supplied with energy. An electrical current measuring unit is provided which ascertains the electrical current supplied by the energy source. In the I/O module, internal resistors are provided, across which occurs in each case a voltage drop dependent on the flowing electrical current. A control unit is provided, which operates the energy source in such a way that a predetermined terminal voltage is supplied on the connecting terminals for powering the field device. | 2011-06-23 |
20110148512 | FILTER CIRCUIT - A filter circuit that removes high-frequency components from an input signal, comprises: an operational amplifier; a first resistor connected between a non-inverting input terminal of the operational amplifier and an input signal source; a first capacitor connected to the non-inverting input terminal of the operational amplifier; a second resistor connected to the non-inverting input terminal of the operational amplifier; a third resistor connected between an inverting input terminal of the operational amplifier and the input signal source; a second capacitor connected between the inverting input terminal of the operational amplifier and an output terminal of the operational amplifier; and a fourth resistor connected to the inverting input terminal of the operational amplifier. | 2011-06-23 |
20110148513 | DISCRETE-TIME FILTER APPARATUS AND DISCRETE-TIME RECEIVER SYSTEM HAVING THE SAME - The discrete-time receiver system includes: a voltage current conversion device low-noise-amplifying an input voltage signal, and converting the amplified signal into a current signal; a first filter performing IIR filtering on the current signal output from the voltage current conversion device; a discrete-time filter performing FIR filtering on a signal output from the first filter; and a second filter performing IIR filtering on a signal output from the discrete-time filter, wherein the discrete-time filter includes a plurality of current supply units generating a current having a size obtained by multiplying an input current by a determined gain, respectively, an adding unit adding currents supplied from the plurality of current supply units, and a plurality of controllers connecting the plurality of current supply units and the adding unit and controlling the flow of current supplied from the current supply units to the adding unit. | 2011-06-23 |
20110148514 | FREQUENCY VARIABLE COMPOSITE RESONANCE CIRCUIT - A composite resonance circuit is provided of which the resonance frequency range can be set with greater degrees of freedom with the peak frequency of the resonance characteristic curve of a resonance unit having good linearity and the resonance sharpness Q-factor being kept within a desired range. In the composite resonance circuit according to the present invention, first and second relay circuits are respectively connected between the resonance unit and first and second phase shift circuits that shift an input frequency signal by different phases. Hence, the resonance frequency range can be set by setting the gains and impedances of the first and second relay circuits according to its use, without changing resonance elements or the like of the resonance unit. | 2011-06-23 |
20110148515 | QUASI-RESONANT COMPOSITE RESONANCE CIRCUIT - A composite resonance circuit is provided of which the resonance frequency is variable over a wide frequency range without changing the circuit constant of a non-resonant element having no resonance frequency. The composite resonance circuit comprises an input terminal; a resonance unit having first and second ports and quasi-resonating in response to AC signals respectively supplied to these ports; and phase shift circuits that perform different phase shifts on an AC signal supplied to the input terminal and supply first and second shifted signals subjected to the phase shift respectively to the first and second ports. The resonance unit is an impedance circuit that has at least four input terminals forming the first and second ports and that generates a quasi-resonant peak current under non-zero reactance in response to the first and second shifted signals coming in via the first and second ports. The quasi-resonant peak current is variable according to the frequency and phase shift quantities of the AC signals. Namely, the resonance frequency can be made to be variable. | 2011-06-23 |
20110148516 | MINUTE CAPACITANCE ELEMENT AND SEMICONDUCTOR DEVICE USING THE SAME - A minute capacitance element has a high accuracy capacitance and is resistant to external noises. The minute capacitance element includes: first and second metal electrodes having respective opposite facets facing each other formed on an insulator layer to define a first gap therebetween; and a shield electrode being connectable to an externally applied potential and formed on the insulator layer within the first gap to define a slit confining a synthetic capacitance. | 2011-06-23 |
20110148517 | Shift Register and Driving Method Thereof - A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion, of the inverter through a capacitor means. In this manner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided | 2011-06-23 |
20110148518 | DYNAMIC RANGE IMPROVEMENTS OF LOAD MODULATED AMPLIFIERS - The present invention relates to methods and devices to control and operate the functionality of a power amplifier system ( | 2011-06-23 |
20110148519 | POWER AMPLIFIER POWER CONTROLLER - A power amplifier power controller in the power amplifier system monitors various operating conditions of the power amplifier, and controls the output transmit power of the power amplifier by coordinated control of both the input drive level to the power amplifier and the gain of the power amplifier. The power amplifier power controller controls the input drive level to the power amplifier so that the input drive level does not change substantially while adjusting the gain of the power amplifier to maximize the transmit power. The power amplifier power controller may also adjust the input drive level by some portion of the overall change required to the power of the power amplifier, while adjusting the gain of the power amplifier by the remaining portion of such overall change. | 2011-06-23 |
20110148520 | SYSTEM AND A METHOD FOR SIGNAL PROCESSING - A system for processing an input signal, the system includes: a hardware memory module configured to store a lookup table; and a signal processing module, configured to process the input signal to provide a second signal, and to transmit the second signal to a power amplifier that is characterized by non-linearity and which is adapted to amplify the second signal to provide an amplified signal; wherein the signal processing module is configured to process the input signal in response to at least one filtering parameter to provide the second signal so as to at least partly compensate for the non-linearity of the amplifier; wherein the at least one filtering parameter is retrieved from the lookup table using a first, a second, and a third lookup table indexes, wherein the first index is responsive to a magnitude of the input signal at a first moment, the second index is responsive to a magnitude of the input signal at a second moment, and the third index is responsive to phases of the input signal at the first and the second moments; wherein the system includes a delay circuit for delaying the input signal before the input signal is provided to the signal processing module. | 2011-06-23 |
20110148521 | DYNAMIC CONSTANT POWER AMPLIFIER - A switching amplifier including a voltage sensor circuit connected to a high voltage supply rail for measuring the power supply voltage. A current sensor circuit is connected to the high voltage supply rail for measuring the power supply current. An error amplifier is connected to the switching amplifier and receives one or more values based on the measurements taken by the voltage sensor and current sensor, and the error amplifier produces an error signal when a predetermined power limit is exceeded. A signal limiting circuit is connected to the error amplifier and the switching amplifier and limits the output power to rated power at any rated load impedance when the error amplifier produces the error signal. This switching amplifier is capable of automatically limiting output power at rated power into all rated load impedances, and dynamically reacts to the frequency-dependant impedance of a typical audio system. | 2011-06-23 |
20110148522 | INTEGRATED CIRCUIT HAVING A DUMMY TRANSIMPEDANCE AMPLIFIER - Consistent with the present disclosure, a “dummy” transimpedance amplifier (dummy TIA) is provided on a substrate along with one or more other transimpedance amplifiers (TIAs) that are connected to photodiodes and output voltage signals for further processing. Typically, the dummy TIA is not connected to a photodiode and does not supply a useful output. The dummy TIA, however, is subject to the same processing and temperature variations as the other TIAs, and, as a result, the voltage on the dummy TIA inverting input will be the same or substantially the same as that of the other TIAs. Thus, by sensing the dummy TIA inverting input voltage, an appropriate photodiode bias can be obtained without direct measurement of the voltage on the inverting inputs of the other TIAs. | 2011-06-23 |
20110148523 | OP-AMP SHARING WITH INPUT AND OUTPUT RESET - An operational amplifier with two pairs of differential inputs for use with an input switch capacitor network. The operational amplifier has reset devices for resetting the second pair of differential inputs while amplifying the first pair of differential inputs, and for resetting the first pair of differential inputs while amplifying the second pair of differential inputs for reducing memory effect in electronic circuits. In an embodiment, the amplifier has an additional reset device for resetting the outputs during a prophase of amplifying the first pair of differential inputs and a prophase of amplifying the second pair of differential inputs. | 2011-06-23 |
20110148524 | RADIO FREQUENCY BUFFER - Systems, methods, and devices for receiving a differential input signal and generating a non-differential output signal are described herein. For example, an RF buffer is described that includes first and second transistor elements. The first transistor element receives a first polarity signal of a differential signal and drives a non-differential output of the RF buffer. A second transistor element receives a second polarity signal of the differential signal and drives the non-differential output of the RF buffer. The first and second transistor elements substantially simultaneously drive the non-differential output of the RF buffer. | 2011-06-23 |
20110148525 | CURRENT MIRROR WITH LOW HEADROOM AND LINEAR RESPONSE - A current mirror circuit provided in an emitter follower configuration achieves linearly output over a range of input currents by operating in response to a bias current that is a replica of the input current. The current mirror may include a pair of transistors and a pair of resistors, in which: a first resistor and a base of a first transistor are coupled to a first input terminal for a first input current, an emitter of the first transistor and a base of the second transistor are coupled to a second input terminal for a second input current, the first and second input currents being replicas of each other, an emitter of the second transistor being coupled to the second resistor, a collector of the second transistor being coupled to an output terminal of the current mirror, and a collector of the first transistor and the two resistors are coupled to a common node. | 2011-06-23 |
20110148526 | Low noise amplifier with variable frequency response - The present invention relates a low noise amplifier with adaptive frequency responses and method of altering frequency responses thereof. The low noise amplifier comprises an inductive degeneration circuit, N cascode circuits and N switches. The inductive degeneration circuit has an input impedance and a frequency response characteristic. Each of the cascode circuits is connected in parallel to the inductive degeneration circuit. Each of the switches is connected to a corresponding cascode circuit respectively. Each of the cascode circuit is turned ON or OFF by enabling or disabling the corresponding switches to alter the frequency response characteristic. | 2011-06-23 |
20110148527 | Dual-Loop Feedback Amplifying Circuit - An amplifying circuit arranged for converting an input signal into an amplified output signal comprising: an input node ( | 2011-06-23 |
20110148528 | AMPLIFICATION CELL EMPLOYING LINEARIZATION METHOD AND ACTIVE INDUCTOR USING THE SAME - An amplification cell employing a linearization scheme and an active inductor using the same are provided. The active inductor includes: first and second amplification cells each including a main amplifying unit amplifying an input signal, an auxiliary amplifying unit connected in parallel to the main amplifying unit and eliminating nonlinear characteristics of the main amplifying unit while amplifying the input signal, and a negative load unit connected to an output terminal of the main amplifying unit and that of the auxiliary amplifying unit; a plurality of load resistors for tuning frequency; and a plurality of capacitors for tuning frequency, wherein an output from the first amplification cell is negatively fed back to the second amplification cell, an output from the second amplification cell is negatively fed back to the first amplification cell, and the plurality of load resistors and the plurality of capacitors are disposed on negative feedback paths of the first and second amplification cells. | 2011-06-23 |
20110148529 | RADIO FREQUENCY AMPLIFIER WITH EFFECTIVE DECOUPLING - A variety of circuits, methods and devices are implemented for radiofrequency amplifiers. According to one such implementation, a radiofrequency amplifier circuit is implemented in a SMD package. The circuit amplifies a radiofrequency signal having a base-band portion and a plurality of carrier signals frequency-spaced larger than the base-band bandwidth. The circuit includes a radiofrequency transistor connected to a circuit output having a parasitic output capacitance. The source-drain terminal is electrically connected to the circuit output. An internal shunt inductor provides compensation for the parasitic output capacitance. A high-density capacitor is connected between the internal shunt inductor and a circuit ground. The high-density capacitor has a terminal with a surface area can be at least ten times that of a corresponding planar surface. | 2011-06-23 |
20110148530 | Oscillator with capacitance array - An oscillator is provided which comprises an array of capacitances. At least some capacitances in the array have different capacitance values. | 2011-06-23 |
20110148531 | OSCILLATORS HAVING ARBITRARY FREQUENCIES AND RELATED SYSTEMS AND METHODS - Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal. | 2011-06-23 |
20110148532 | DIFFERENTIAL RESONANT RING OSCILLATOR UTILIZING MAGNETICALLY TUNED YIG RESONATORS TO ACHIEVE ULTRA LOW PHASE NOISE AND MULTI-OCTAVE ELECTRONIC TUNING IN MICROWAVE FREQUENCIES - A differential resonant ring oscillator (“DRRO*) circuit using a ring oscillator topology to electronically tune the oscillator over multi-octave bandwidths. The oscillator tuning is substantially linear, because the oscillator frequency is related to the magnetic tuning of a YIG sphere, which has a resonant frequency equal to a fundamental constant multiplied by the DC magnetic field. The simple circuit topology uses half turn or multiple half turn loops magnetic coupling methods connecting a differential pair of amplifiers into a feedback loop configuration having a four port YIG tuned filter, thus creating a closed loop ring oscillator. The oscillator may use SiGe bipolar junction transistor technology and amplifiers employing heterojunction bipolar transistor technology SiGe is the preferred transitor material as it keeps the transistor's 1/f noise to an absolute minimum in order to achieve minimum RF phase noise. | 2011-06-23 |
20110148533 | CRYSTAL OSCILLATOR WITH FAST START-UP AND LOW CURRENT CONSUMPTION - An oscillator comprises an inverter, with a resonator connected between an input and an output of the inverter. A transistor external to the inverter is connected in a current mirror mode with a transistor of the inverter so that the inverter's transistor copies the current of the external transistor. The external transistor has its drain terminal connected to the gate terminals of the inverter's transistor and of the external transistor. A current source is connected to the gate terminal of the inverter's transistor, and a switch is connected between the drain and gate terminals of the external transistor. Circuitry controls the switch so as to open the connection between the drain and gate terminals of the external transistor at the beginning of a start-up phase of the oscillator. | 2011-06-23 |
20110148534 | LC VOLTAGE-CONTROLLED OSCILLATOR - An LC voltage-controlled oscillator (VCO) is provided. The LC VCO includes an LC resonant circuit including at least one inductor whose both terminals are connected to output nodes and at least one capacitor connected in parallel with the inductor, and an amplifier circuit including at least one pair of switching transistors. Here, drains of the pair of switching transistors are connected to the output nodes respectively, and gates of the switching transistors are connected with the drains through a variable capacitance block exhibiting different characteristics according to an input signal. | 2011-06-23 |
20110148535 | VOLTAGE CONTROLLED OSCILLATOR - A voltage controlled oscillator includes a resonant circuit including one or more transformers and a plurality of variable capacitor circuits connected in parallel to the one or more transformers and generating a plurality of oscillation frequencies having multiple phases, and a negative resistance circuit including a plurality of transistors cross-coupled via the one or more transformers and generating negative resistance for maintaining the oscillation of the resonant circuit. | 2011-06-23 |
20110148536 | CIRCUIT ARRANGEMENT OF A VOLTAGE CONTROLLED OSCILLATOR - A circuit for a voltage controlled oscillator has a bridge structure including two cross-coupled N-type transistors and two cross-coupled P-type transistors. A current mirror is coupled to the two N-type cross-coupled transistors and configured to generate a bias current. An LC resonator is coupled in parallel between the two cross-coupled N-type transistors and the two P-type cross-coupled transistors. The LC resonator includes two pairs of differential inductors mutually coupled by a mutual inductance coefficient, each pair comprising a first inductor arranged on a respective branch of an external loop, and a second inductor arranged on a respective branch of an internal loop. A first varactor is coupled to a common node and a first branch of the internal loop. A second varactor is coupled to the common node and the second branch of the internal loop. | 2011-06-23 |
20110148537 | MEMS OSCILLATOR AND METHOD OF MANUFACTURING THEREOF - An oscillator includes: a plurality of MEMS vibrators formed on a substrate; and an oscillator configuration circuit connected to the plurality of MEMS vibrators, wherein the plurality of MEMS vibrators each have a beam structure, and the respective beam structures are different, whereby their resonant frequencies are different. | 2011-06-23 |
20110148538 | Crystal device - An object is to provide a crystal device in which an influence due to an electroconductive adhesive is reduced, and vibration characteristics of a crystal piece are favourably maintained. A configuration is such that in a crystal device including: a container main body having a concavity, with a crystal retention terminal formed in a bottom face of the concavity, and with a mounting terminal that is electrically connected to the crystal retention terminal formed on an outer bottom face; a crystal piece accommodated in the concavity, with an excitation electrode formed on both main faces, and with a support electrode that is electrically connected to the excitation electrode using a connecting electrode, formed on both sides of one end portion, and with the support electrode bonded to the crystal retention terminal with an electroconductive adhesive; and a cover that is connected to an open end face of the container main body and hermetically seals the crystal piece, there is provided a jetty being a main face of the crystal piece, and that protrudes on a periphery of the support electrode, and the jetty is formed integral with the crystal piece. | 2011-06-23 |
20110148539 | PIEZOELECTRIC VIBRATOR, OSCILLATOR, ELECTRONIC EQUIPMENT AND RADIO-CONTROLLED TIMEPIECE, AND METHOD OF MANUFACTURING PIEZOELECTRIC VIBRATOR - A piezoelectric vibrator includes a base substrate and a lid substrate which are bonded to each other with a cavity formed therebetween; an external electrode that is formed on a lower surface of the base substrate; an internal electrode that is formed on an upper surface of the base substrate so as to be accommodated in the cavity; a through electrode which is formed so as to pass through the base substrate and electrically connect the external electrode with the internal electrode; a piezoelectric vibrating reed which is accommodated in the cavity in a state of being electrically connected to the internal electrode; and a getter material that is formed in the cavity, the getter material being formed of chromium or a metallic material consisting of chromium as a main ingredient. | 2011-06-23 |
20110148540 | DELAY CIRCUIT AND VOLTAGE CONTROLLED OSCILLATION CIRCUIT - A delay circuit includes a delay unit having a first and a second power supply terminals, a pair of differential signal input terminals and a pair of differential signal output terminals. The signals entered to the pair of differential signal input terminals are delayed and output at the pair of differential signal output terminals. The delay circuit also includes a current controller that exercises control to cause a current of a current source, controlled by a current control terminal, to flow through the first and second power supply terminals of the delay unit. The delay circuit also includes a voltage controller that exercises control to provide for a constant potential difference between the first and the second power supply terminals ( | 2011-06-23 |
20110148541 | TRANSMISSION MEDIUM - A transmission medium includes: first and second lines # | 2011-06-23 |
20110148542 | TRANSFORMER AND METHOD FOR USING SAME - Method for improving the symmetry of the differential output signals of an integrated transformer of the symmetric-asymmetric type comprising an inductive primary circuit and an inductive secondary circuit, characterized in that the capacitive coupling between the primary and secondary circuits is reduced. | 2011-06-23 |
20110148543 | Integrated Circuit With Inductive Bond Wires - An integrated circuit (IC) that includes a semiconductor die in an IC package. The semiconductor die includes an electrical endpoint. The IC also includes a pad affixed to the semiconductor die. The pad is characterized by a capacitance and is coupled to the electrical endpoint. The IC also includes a bond wire coupling the pad to an IC package pin. The bond wire is an inductor characterized by an inductance. The inductance is configured to decrease signal degradation caused by the capacitance of the pad on electrical signals transmitted between the pin and the electrical endpoint of the semiconductor die. | 2011-06-23 |
20110148544 | DIRECTIONAL COUPLER - A directional coupler includes a dielectric substrate having at least an input terminal and an output terminal on a surface thereof, a main line disposed in the dielectric substrate and extending between the input terminal and the output terminal, a first coupling line for monitoring a level of an input signal which is input through the input terminal, the first coupling line being disposed in the dielectric substrate and having an end electrically connected to a first terminating resistor, and a second coupling line for monitoring a level of a reflected signal which is input through the output terminal, the second coupling line being disposed in the dielectric substrate and having an end electrically connected to a second terminating resistor. | 2011-06-23 |
20110148545 | APPARATUS AND METHOD FOR EMBEDDING COMPONENTS IN SMALL-FORM-FACTOR, SYSTEM-ON-PACKAGES - According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a system-on-package architecture, the system-on-package architecture arranged as a stack of layers including a first layer having a first conformable material; a second layer having a second conformable material; one or more electronic components embedded within the stack of layers; and a heat dissipating element configured dissipating heat generating from the one or more electronic components, wherein the first conformable material, the second conformable material, or both are configured to allow high frequency signal routing. | 2011-06-23 |
20110148546 | Multilayer Component - A multilayer component includes at least one inductive region and at least one capacitive region. The inductive region includes a ferrite ceramic. Electrode structures are arranged on the outwardly facing top side of the inductive region. The electrode structures form at least one coil structure having an inductance. | 2011-06-23 |
20110148547 | PIEZOELECTRIC RESONATOR STRUCTURE - A piezoelectric resonator structure, comprising: (i) a substrate, (ii) an acoustic mirror, (iii) a first electrode, (iv) a piezoelectric layer, and (v) a second electrode, wherein each of the substrate, the acoustic mirror, the first electrode, the piezoelectric layer, and the second electrode has a top surface and a bottom surface, a first end portion and an opposite, second end portion, and a body portion defined therebetween, wherein the overlapped area of body portions of the substrate, the acoustic mirror, the first electrode, the piezoelectric layer and the second electrode is defined as an active area A. A plurality of air gaps and interference structures is formed at the first end portion of the piezoelectric layer and the second electrode, and the second end portion of the piezoelectric layer and the second electrode to enhance the performance of the piezoelectric resonator. | 2011-06-23 |
20110148548 | LINE FILTER FORMED ON DIELECTRIC LAYERS - Provided is a line filter. The line filter includes a plurality of dielectric layers stacked one another, a plurality of line resonator each comprising transmission lines on at least two of the dielectric layers, and a tuning unit adjusting a binding amount and resonance frequency of the line resonators. Since the line filter includes at least one line resonator on at least two stacked dielectric layers, the integration can be easily realized. Further, since the line filter can be adjusted even after the line filter is manufacture, the line filter has an excellent frequency property. Since the line filter is realized on the plurality of the dielectric layers, the frequency band can be widened. | 2011-06-23 |
20110148549 | Signal Transmission Arrangement - A signal transmission arrangement includes input terminals for receiving an input signal and output terminals for providing an output signal. A first transformer has a primary winding and a secondary winding, the primary winding being coupled to the input terminals. A second transformer has a primary winding and a secondary winding, the primary winding being coupled to the secondary winding of the first transformer, and the secondary winding being coupled to the output terminals. | 2011-06-23 |
20110148550 | METAMATERIAL TRANSMISSION LINE APPARATUS AND METHOD OF IMPLEMENTING THE SAME - A metamaterial transmission line for transmitting an electromagnetic wave. The metamaterial transmission line may include a substrate including a substrate configured to include a an upper portion and a lower portion on which a ground plane is formed, a signal line configured to be formed on the substrate, and a defected ground structure configured to include an etched region and two metal portions, wherein the etched region is generated by etching a part of the ground plane and the metal portions extend from the signal line and are disposed on the etched region. | 2011-06-23 |
20110148551 | Compact Thermoelastic Actuator for Waveguide, Waveguide with Phase Stability and Multiplexing Device Including Such an Actuator - A compact thermoelastic actuator includes at least two identical force pieces and a securing piece, the securing piece having a coefficient of thermal expansion less than the coefficient of thermal expansion of the force pieces. The force pieces are mounted head-to-tail one beside the other parallel to a longitudinal axis Y and are linearly offset relative to one another, along the longitudinal axis Y. The securing piece has two ends respectively linked to external ends of each force piece and internal ends of each force piece are positioned under a median region of the securing piece. The actuator and device is applicable to waveguides of multiplexers incorporated in space equipment for satellites. | 2011-06-23 |
20110148552 | SOLENOID ACTUATOR WITH AN INTEGRATED MECHANICAL LOCKING AND UNLOCKING FIXTURE - Electric Solenoid Actuators are used in a wide range of industries that require the combination of electrical, electromagnetic and mechanical apparatus and systems to activate or de-activate a device, automatically, or semi-automatically. Solenoid actuators are used in a variety of applications ranging from valve controls, electrical switch controls or contactors, or other electrical, electronic, hydraulic, pneumatic, mechanical systems and/or combinations thereof. Electric solenoid actuators are preferred from pneumatic and hydraulic actuators for many practical reasons. There are disadvantages with the use of electrical solenoids and this may include the limitation of motion as well as the limited force which is dictated by the strength of the electromagnet developed by the armature. The solenoid actuator of this disclosure operates on either AC or DC power supply depending on the coil and armature design which is dictated by the force required for specific applications and the type of power supply available. | 2011-06-23 |
20110148553 | ELECTROMAGNETIC ACTUATOR HAVING A MAGNETOSTRICTIVE ELEMENT AND METHOD FOR OPERATING THE ELECTROMAGNETIC ACTUATOR - An electromagnetic actuator ( | 2011-06-23 |
20110148554 | ELECTROMAGNETIC MULTI-AXIS ACTUATOR - An electromagnetic multi-axis actuator, which can realize small size, light weight and low power consumption while being capable of performing multi-axis motion by overcoming limitations in a driving range, compared to a typical electrostatic actuation scheme or a typical electric motor actuating scheme. The electromagnetic multi-axis actuator includes an actuating unit ( | 2011-06-23 |
20110148555 | LINEAR SOLENOID FOR VEHICLE - A guide of a coil device has a tongue portion, which is formed by resin integrally with the guide at a location radially outward of a slit of a yoke and axially extends toward an opening part of the yoke such that a distal end part of the tongue portion is resiliently bendable while exerting a resilient force. The tongue portion is resiliently engaged with a flange portion of a stator core upon filling of the coil device to the stator core. | 2011-06-23 |
20110148556 | POWER QUALITY IMPROVEMENT DEVICE AND POWER SUPPLY SYSTEM - The present invention relates to a power quality improvement device. The power quality improvement device is provided in the form of an autotransformer which comprises an iron core having first, second and third legs, and first, second and third coils which are wound in a zigzag fashion around said first, second and third legs. At least two coils selected from the group that includes said first, second and third coils, alternatively wound around each of said first, second and third legs, are over-lappingly wound around the core in a winding sequence. | 2011-06-23 |
20110148557 | Double Active Parts Structure of Reactor - A double active parts structure of a reactor comprises two separate active parts that are coupled together by its inner coils. The arrangement mode of the two active parts is parallel or in-line. | 2011-06-23 |
20110148558 | INDUCTOR - An inductor includes a conductive track forming at least three inductor turns. The conductive track has a plurality of track sections. The inductor also includes at least two groups of crossing points, each crossing point comprising a location at which the conductive track crosses over itself. The crossing points of each group collectively reverse the order of at least some of the track sections in the inductor, such that inner track sections of the conductive track cross over to become respective outer track sections, and such that outer track sections of the conductive track cross over to become respective inner track sections. | 2011-06-23 |
20110148559 | MULTI-TURN INDUCTORS - A multi-winding inductor includes a first foil winding and a second foil winding. One end of the first foil winding extends from a first side of the core and wraps under the core to form a solder tab under the core. One end of the second foil winding extends from a second side of the core and wraps under the core to form another solder tab under the core. Respective portions of each solder tab are laterally adjacent under the magnetic core. A coupled inductor includes a magnetic core including a first and a second end magnetic element and a plurality of connecting magnetic elements disposed between and connecting the first and second end magnetic elements. A respective first and second single turn foil winding is wound at least partially around each connecting magnetic element. Each foil winding has two ends forming respective solder tabs. | 2011-06-23 |
20110148560 | Two-Phase Coupled Inductors Which Promote Improved Printed Circuit Board Layout - Two-phase coupled inductors including a magnetic core, at least a first winding, and at least three solder tabs. Power supplies including a printed circuit board, a two-phase coupled inductor affixed to the printed circuit board, and first and second switching circuits affixed to the printed circuit board. Each of the first and second switching circuits are electrically coupled to a respective solder tab of the two-phase coupled inductor affixed to the printed circuit board. | 2011-06-23 |
20110148561 | CURRENT SENSING DEVICES AND METHODS - A low-cost and high-precision current sensing device and methods for use and manufacturing. In one embodiment, the current sensing apparatus comprises a Rogowski-type coil which is manufactured in segments so as to facilitate the manufacturing process. In an exemplary embodiment, the current sensing apparatus segments comprise a number of bobbin elements that are wound and subsequently formed into complex geometric shapes such as torus-like shapes. In an alternative embodiment, bonded windings are utilized which allow the segments to be formed without a bobbin or former. In yet another alternative embodiment, the aforementioned current sensing devices are stacked in groups of two or more. Methods of manufacturing and using the aforementioned current sensing apparatus are also disclosed. | 2011-06-23 |
20110148562 | FIELD COIL ASSEMBLY OF ELECTROMAGNETIC CLUTCH FOR POWER TRANSMISSION APPARATUS AND MANUFACTURING METHOD THEREOF - Disclosed is a field coil assembly of an electromagnetic clutch including a bobbin from which lead wires, which are both ends of a coil made of an aluminum-based material, protrude outward, a core that surrounds the bobbin such that the lead wires are exposed, a bobbin terminal installed at the bobbin while being adjacent to the lead wire of the coil, and a connector coupled to the core and including a lead wire terminal. The lead wires of the coil are connected to the bobbin terminal through heating and pressing. | 2011-06-23 |
20110148563 | PLANAR TRANSFORMER AND WINDING ARRANGEMENT SYSTEM BACKGROUND - A winding arrangement system of a planar transformer includes a primary winding arranges on a number of first circuit layers of a printed circuit board (PCB), and two secondary winding arranged on a number of second circuit layers. The turns of the primary winding are coupled in series. Each second circuit layer has a winding turn. A first half of the winding turn belongs to one of the two secondary winding. A second half of the winding turn belongs to the other of the two secondary winding. The first and second halves of winding turns on each of the second secondary circuit layers share a common grounded node. All of the first halves of winding turns are coupled in parallel. All of the second halves of winding turns are also coupled in parallel. | 2011-06-23 |
20110148564 | UNIVERSAL DUAL STUD MODULAR FUSE HOLDER ASSEMBLY FOR BUSSED AND NON-BUSSED POWER CONNECTIONS - Modular fuse holders include dual studs with stepped configuration allowing the fuse holders to be universally used with and without bus bars while ensuring proper connection of a fuse. | 2011-06-23 |
20110148565 | MONITORING SYSTEM AND INPUT AND OUTPUT DEVICE - A monitoring system includes a controller, a number of sensors, a number of alarms, and a number of input/output devices. Each input/output device is connected between the controller and a sensor or an alarm. Each input/output device includes an input circuit, an output circuit, and a connector to selectively connect to the sensor or the alarm. The input circuit and the output circuit are connected between the controller and the connector. The controller controls status of the input circuit and the output circuit. When the connector is connected to the alarm, the controller controls the alarm to work via the output circuit. When the connector is connected to the sensor, the sensor outputs a detection signal to the controller via the input circuit. | 2011-06-23 |
20110148566 | Remote Ignition System for a Vehicle and Method for Securing a Remote Ignition Function - The invention relates to a remote ignition system for a vehicle with a remote ignition control device for activating a remote ignition by providing a release signal, means for detecting a driver's intention to start driving, and an engine control device which comprises the following: a first evaluation unit for evaluating a signal which has been received from the remote ignition control device, a unit coupled to the first evaluation unit for starting of the engine in response to a release signal and for stopping the engine in response to a blocking signal, and a second evaluation unit for evaluating signals which have been received from the means for detecting the intention to start driving. The engine control device furthermore comprises a storage unit for storing the last signal evaluated by the first evaluation unit, and a test unit which is coupled to the second evaluation unit, to the storage unit, and to the unit for starting and stopping the engine and which is designed to read out the signal stored in the storage unit when the second evaluation unit has ascertained the intention to start driving and, if it is a release signal, to send a blocking signal to the unit for starting and stopping the engine and to modify the contents of the storage unit. The invention furthermore relates to a method for securing a remote ignition function. | 2011-06-23 |
20110148567 | Facilitating User Sensor Self-Installation - User self-installation of a sensor network for activity monitoring may be facilitated by providing a computer system that prompts the user through the installation process. Particularly, the computer system may prompt the user to identify an object to which a sensor has been attached and the activities with which identified objects are associated. The computer may prompt with potential activities based on the object identified by the user. The elicited information may be used to automatically generate a model, which may be automatically improved over time by examining the history of sensor readings. Thereafter, based on the data produced by the sensors, the system identifies what activities are actually being completed. | 2011-06-23 |
20110148568 | APPARATUS AND METHOD FOR CONTROLLING CONTENTS PLAYER - Provided is a technology for controlling a contents player based on a grasping power information of a hand by measuring a change of the bundle shape of a tendons in an inside muscle of wrist, in which the device and method for controlling the contents player comprises a sensing unit that generates a grasping power information; a control state managing unit that manages a control state of the contents player; and a control order generating unit that generates a control order controlling the contents player based on the control state and the grasping power information, and transmits the control order, in which the control state can be changed or can be generates in response to the grasping power information, and the sensing unit can be existed in both hands, respectively. | 2011-06-23 |