25th week of 2012 patent applcation highlights part 24 |
Patent application number | Title | Published |
20120153952 | METHOD AND SYSTEM FOR GRADIENT LINEAR CORRECTION - Methods, systems and computer program products are described for providing gradient linearity correction in a magnetic resonance image. The method in one example obtains, using a simulation, a time-dependent eddy current induced magnetic gradient field produced by a gradient system in response to a gradient switching pulse. Subsequently, the method determines time-dependent eddy current harmonic response coefficients for at least one higher harmonic frequency based upon the time-dependent eddy current induced magnetic gradient field. The method then corrects the magnetic resonance image based upon the time-dependent eddy current harmonic response coefficients. | 2012-06-21 |
20120153953 | MAGNETIC RESONANCE APPARATUS WITH A BASIC FIELD MAGNET FORMED BY AT LEAST TWO SEPARATED MAGNETIC COILS - A magnetic resonance apparatus for examination in THE teeth and/or jaw region of a patient has at least one basic magnet to generate a constant basic magnetic field. The basic magnet is formed at least in part from at least one magnetic coil pair with at least two magnetic coils, and the at least one magnetic coil pair generates the basic magnetic field with a homogeneous magnetic field region between the at least two magnetic coils thereof. | 2012-06-21 |
20120153954 | RF COIL DEVICE AND MAGNETIC RESONANCE IMAGING APPARATUS - In one embodiment, an RF coil device ( | 2012-06-21 |
20120153955 | MRI Short Coils - According to one aspect, a magnetic resonance imaging (MRI) scanner includes a short birdcage (e.g. millipede) distributed-capacitance radio-frequency (RF) coil formed from one or more patterned planar conductive foils. The transverse extent (e.g. diameter) of the coil is at least a factor of 3, for example about a factor of 10, larger than the longitudinal (z-axis) extent of the coil. Flux-return gaps may be provided between the sample measurement volume defined by the coil and RF shields adjacent to the sample measurement volume, to confine the RF magnetic field to the sample measurement volume. Exemplary coils described herein are particularly suited for very high-frequency MRI measurements. | 2012-06-21 |
20120153956 | MR COIL WITH MOVABLE ANTENNA ELEMENTS - The present embodiments relate to a local coil for a magnetic resonance tomography system. The local coil includes at least one coil element having an antenna. The at least one coil element is movable relative to a housing of the local coil. | 2012-06-21 |
20120153957 | RF COIL ASSEMBLY FOR MRI USING DIFFERENTLY SHAPED AND/OR SIZED COILS - A radio frequency coil assembly is provided that includes a first radio frequency coil for receiving a magnetic resonance signal from a tested body; a second radio frequency coil for receiving a magnetic resonance signal from the tested body; and a third radio frequency coil for receiving a magnetic resonance signal from the tested body and having a shape that is different from that of at least one of the first and second radio frequency coils so as to increase local sensitivity in an image-picked-up region. | 2012-06-21 |
20120153958 | METHODS FOR DETERMINING DIELECTRIC PERMITTIVITY SPECTRUM OF UNDERGROUND ROCK FORMATIONS - A method for determining the frequency-dependent dielectric permittivity spectrum of a rock sample, comprising:—defining a series of electromagnetic measurement data comprising at least a first measurement at a frequency from which a substantially frequency-independent value of dielectric permittivity ∈ | 2012-06-21 |
20120153959 | Electrode structure for marine electromagnetic geophysical survey transducers - A marine electromagnetic geophysical survey transducer cable includes a tow cable configured to couple to a tow vessel. A first electrode cable is coupled at a forward end to the tow cable. A second electrode cable is disposed aft of the first electrode cable and configured to indirectly couple to the tow vessel. At least one of the first and second electrode cables includes a cable core comprising a first core material having a first density selected to provide the transducer cable with a selected overall density, and at least one layer of electrically conductive strands disposed exterior to the cable core. | 2012-06-21 |
20120153960 | Negative Peak Voltage Detection for Enhanced FuelGauge Empty Voltage Prediction - Negative peak voltage detection for battery end of life estimations in fuel gauging is disclosed. Battery powered devices such cell phones and laptop computers create some noise in the form of negative excursions from the average output voltage of the battery which can cause the battery powered device to stop functioning. By negative peak detection relative to the average battery voltage, the end of life or discharged voltage condition can be altered in response to the negative peaks to obtain the maximum battery life without risk of the device inadvertently shutting down. Average output voltage of the battery may be taken as an estimated open circuit voltage or some other battery voltage. Various embodiments are disclosed. | 2012-06-21 |
20120153961 | APPARATUS FOR MONITORING OPERATION STATE OF BATTERY PACK COMPOSED OF PLURALITY OF CELLS MUTUALLY CONNECTED IN SERIES - An apparatus is provided, which monitors an operation state of a battery composed of a plurality of cells mutually connected in series. In this apparatus, a cell voltage of each of the plurality of cells is detected as information indicating an operation state of the battery. Based on the detected cell voltages, an operation state is monitored for a cell having a highest cell voltage and a cell having a lowest cell voltage among the plurality of cells. | 2012-06-21 |
20120153962 | STRESS TESTING OF SILICON-ON-INSULATOR SUBSTRATES USING APPLIED ELECTROSTATIC DISCHARGE - A method of implementing electrostatic discharge (ESD) testing of an integrated circuit includes applying an ESD event to an exposed backside of a substrate of the integrated circuit, wherein the backside of the substrate is electrically isolated from circuit structures formed at a front-end-of-line (FEOL) region of the integrated circuit. The operation of the circuit structures is tested to determine whether the ESD event has caused damage to one or more of the circuit structures as a result of a breakdown in the electrical isolation between the circuit structures and the backside of the substrate. | 2012-06-21 |
20120153963 | TESTING OF A TRANSIENT VOLTAGE PROTECTION DEVICE - A method of testing a voltage protection device in a circuit is provided. The circuit comprises a source and load and a detector is provided in parallel with the protection device. The method comprises opening a switching device provided in the circuit. The method further comprises detecting a property of a voltage spike caused by the rate of change of current in the circuit inductance produced by the opening of the switching device to determine the condition of the protection device. | 2012-06-21 |
20120153964 | SYSTEM AND METHOD FOR DETECTING ISOLATION BARRIER BREAKDOWN - A circuit system includes a first circuit for receiving an input signal, a second circuit for interfacing with a user, a signal path connecting the first circuit to the second circuit, the signal path including a first isolator and a second isolator serially connected to the first isolator, and a capacitance detector that detects a change in a combined capacitance of the first and second isolators as an indicator of a breakdown of one of the first and second isolators. | 2012-06-21 |
20120153965 | DC CAPACITOR DEGRADATION ALARM CIRCUIT - A DC capacitor degradation alarm circuit is a capacitor degradation detection device including two filter circuits and a degradation detection element. The two filter circuits, which receive a rectified voltage and perform filtering operation, are coupled in parallel and include a plurality of capacitor modules coupled in series. Each capacitor module can be a single capacitor or includes a plurality of capacitors coupled in series or parallel to allow users to arrange construction thereof to receive required capacitance. The degradation detection element electrically bridges the two filter circuits with connection nodes located between the capacitor modules to instantly detect a voltage difference value of the two filter circuits online and perform operation by incorporating with total output voltage to get voltage difference value percentage. In the event that the obtained percentage exceeds a preset range, the degradation detection element automatically generates a capacitor degradation alarm signal to alert users. | 2012-06-21 |
20120153966 | APPARATUS FOR DETECTING FAULT OF FLYING CAPACITOR OF INSULATED CONDITION DETECTING UNIT - An apparatus for detecting a fault of a flying capacitor of an insulated condition detecting unit measures (step S | 2012-06-21 |
20120153967 | LEAD ADAPTER FOR TESTING PACING THRESHOLDS ACROSS MULTIPLE VECTORS AT IMPLANT - An adapter is used in conjunction with a testing device to test pacing thresholds of an implanted lead. A main body of the adapter includes a plurality of adapter contacts that are configured to electrically couple to the plurality of connector contacts. A connector module includes a first port configured to couple to a first testing device connector and a second port configured to couple to a second testing device connector. A switch assembly includes a plurality of actuatable elements each associated with one of the adapter contacts. The actuatable elements are each selectably actuatable between a first state that electrically couples the associated adapter contact to the first port, a second state that electrically couples the associated adapter contact to the second port, and a third state that electrically decouples the associated adapter contact from the first and second ports. | 2012-06-21 |
20120153968 | Isolating and RFID-Based Sensor from Environmental Interference - An RFID-based sensor is provided with an RFID chip and an antenna electrically connected to the RFID chip. The antenna is adapted to receive energy from an RF field and produce a signal. The sensor also includes a sensing material electrically connected to the antenna and having an electrical property which varies in the presence of an environmental factor. The sensor is further provided with a dielectric spacer material and a ground element which is adapted to at least partially isolate the sensing material from the environmental factor. | 2012-06-21 |
20120153969 | Measuring device working with microwave - A measuring device working with high frequency microwaves, especially frequencies above 70 GHz, comprises a microwave module for the production of microwave transmission signals and/or for the reception and processing of received microwave signals, and an antenna unit for the transmission of the microwave transmission signals and/or for the receipt of the received microwave signals. The measuring device has a cost effective, flexibly usable connection between the microwave module and the antenna unit suitable for the transmission of high frequency microwave signals, especially frequencies of 70 GHz and more. The microwave module and the antenna unit are connected to one another via a dielectric waveguide, via which a transmission of the microwave transmission signals from the microwave module to the antenna unit and/or a transmission of the received microwave signals from the antenna unit to the microwave module occurs. | 2012-06-21 |
20120153970 | CAPACITIVE TOUCH SENSING DEVICES AND METHODS OF MANUFACTURING THEREOF - The present disclosure provides systems, methods, and apparatus for sensing the location(s) of conductive objects disposed near a sensor array. In one aspect, a sensor array includes a conductive row and a conductive column formed of non-transparent material(s). At least a portion of the conductive row overlaps at least a portion of the conductive column and each of the conductive rows and columns include sensing elements. The sensing elements at least partially define volumes including non-conductive and optically transparent material(s) to limit the loss of light that passes therethrough. | 2012-06-21 |
20120153971 | SYSTEM AND METHOD FOR TESTING AN ELECTROSTATIC CHUCK - The present invention provides a reliable, non-invasive, electrical test method for predicting satisfactory performance of electrostatic chucks (ESCs). In accordance with an aspect of the present invention, a parameter, e.g., impedance, of an ESC is measured over a frequency band to generate a parameter functions. This parameter function may be used to establish predetermined acceptable limits of the parameter within the frequency band. | 2012-06-21 |
20120153972 | VEHICLE OPENING DEVICE - A sensing arrangement for sensing a body part in a vehicle opening is described. The arrangement includes a flexible sealing member with two separate electrically conductive members. The two electrically conductive members are interconnected by an electrical oscillator which generates an electric field in the vehicle opening. The arrangement also includes detecting circuitry for detecting a change in the capacitance of the electric field when the body part is in the vicinity of the opening, and for detecting electrical continuity of the first and second electrically conductive members. | 2012-06-21 |
20120153973 | ON-CHIP MEASUREMENT OF CAPACITANCE FOR MICRO-ELECTRO-MECHANICAL SYSTEM (MEMS) ACTUATOR CIRCUIT - A micro-electro-mechanical system (MEMS) actuator circuit and method. The circuit includes a current mirror, a voltage divider having an interior contact and coupled between the mirror output and a potential, an operational amplifier having an input coupled to the interior contact and a switch having input/output contacts separately coupled to the amplifier output and the mirror input and having a switch control. The amplifier output can be coupled to a digital control circuit which can be coupled to the switch control contact and to a digital to analog circuit (DAC) which can be coupled to the digital control circuit and to another amplifier input. An enable signal at the switch control couples the switch input/output contacts together. The capacitance of a MEMS capacitor coupled to the mirror output is determined by measurement of time for the amplifier output to switch from one level to another following a change in DAC output potential. | 2012-06-21 |
20120153974 | TEST APPARATUS - Provided is a test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section provided in a path between the power supply section and the device under test; a plurality of semiconductor switches connected in series in a path between the inductive load section and the device under test; and a control section that turns OFF the semiconductor switches when a supply of voltage to the device under test is stopped. | 2012-06-21 |
20120153975 | DRIVER CIRCUIT - A branch circuit branches an input signal to be transmitted into multiple paths. Each timing adjustment circuit applies a delay to at least one from among a positive edge and a negative edge of a signal to be transmitted, which has been branched into a corresponding path. A combining output circuit combines the output signals of the multiple timing adjustment circuits, and outputs the signal thus combined to a transmission line. | 2012-06-21 |
20120153976 | DEVICE WITH OVERVOLTAGE PROTECTION AND METHOD FOR ITS TESTING - Exemplary embodiments are directed to a device with overvoltage protection that includes a varistor which can be connected by a first connection via a first line to high-voltage potential in a circuit arrangement, while a second connection is connected to ground via a second line. Furthermore, an additional impedance is provided, which can be connected between the second connection and ground or the first connection and the high voltage, or is mounted fixed in this position. The corresponding line can be interrupted by a switching arrangement. In order to test the withstand voltage of the circuit arrangement, at least one of the first and second line is interrupted and an additional impedance is inserted. A test voltage is applied to the circuit arrangement. After the overvoltage test, the interruption in at least one of the first and second lines is removed again. | 2012-06-21 |
20120153977 | TEST APPARATUS - To prevent an excessive current from flowing through a device under test. A test apparatus that tests a device under test, comprising a power supply section that generates a power supply voltage to be supplied to the device under test; an inductive load section that is provided in a path leading from the power supply section to the device under test; a first semiconductor switch that is provided in the path leading from the inductive load section to the device under test and is connected in parallel with the device under test; and a control section that turns the first semiconductor switch ON when supply of the power supply voltage to the device under test is stopped. | 2012-06-21 |
20120153978 | RIBBON TERMINAL CONNECTING APPARATUS - A ribbon terminal connecting apparatus for connecting a ribbon terminal of a photovoltaic device panel to an inspection apparatus terminal automatically when inspecting or measuring a photovoltaic device panel is provided. The ribbon-shaped terminal connecting apparatus includes a stand-up means, a base pressing means, a terminal connecting means and a moving means. The stand-up member of the stand-up means is lowered onto and contacted against the backing material of the photovoltaic device panel. The base portion of the ribbon terminal extended from the backing material is held down by the pressing means for pressing down on the base portion of the ribbon terminal. The moving means moves the stand-up member so that a leading edge of the ribbon terminal extending across the backing material is placed on the stand-up member. The terminal connecting means connects the terminal of the inspection apparatus to the ribbon terminal placed on the stand-up member. | 2012-06-21 |
20120153979 | E-Field Probe Integrated with Package Lid - A measurement apparatus is disclosed. The measurement apparatus includes a lid configured to be removably affixed to a microcircuit case. One or more penetrations through the lid allow insertion of a signal-conducting probe. The probe is removably affixed to the lid at the site of the penetration. The probe includes a central conductive pin. The central conductive pin transmits to a connection outside the case a radio-frequency signal inductively received from a source inside the case. The probe also includes a dielectric region radially surrounding a portion of the central conductive pin, and a grounded outer conductive housing radially surrounding the dielectric region and electrically isolated from the central conductive pin by the dielectric region. | 2012-06-21 |
20120153980 | PROBE ASSEMBLY - A probe assembly includes a transducer, a cable, and a probe. A cover of the cable is made of pliable metal material or a flexible metal conduit. Opposite ends of the cable are respectively coupled to the transducer and the probe. | 2012-06-21 |
20120153981 | System and Method for Manufacturing a Swallowable Sensor Device - Methods and systems for manufacturing a swallowable sensor device are disclosed. Such a method includes mechanically coupling a plurality of internal components, wherein the plurality of internal components includes a printed circuit board having a plurality of projections extending radially outward. A cavity is filled with a potting material, and the mechanically coupled components are inserted into the cavity. The cavity may be pre-filled with the potting material, or may be filled after the mechanically coupled components have been inserted therein. A distal end of each projection abuts against a wall of the cavity thereby preventing the potting material from covering each distal end. The cavity is sealed with a cap causing the potting material to harden within the sealed cavity to form a housing of the swallowable sensor device, wherein the distal end of each projection is exposed to an external environment of the swallowable sensor device. | 2012-06-21 |
20120153982 | TESTER AND TEST SYSTEM INCLUDING THE SAME - Provided are a tester configured to test a semiconductor device and a test system including the same. The tester may include at least one contact unit and at least one memory controller. The contact unit is in contact with the semiconductor device. The memory controller is connected to the contact unit. The memory controller controls data input/output (I/O) operations of the semiconductor device and tests the semiconductor device. | 2012-06-21 |
20120153983 | PROBE FIXING DEVICE - A fixing device for fixing probes of an oscillograph. The fixing device includes a base, a holding member for holding the probe, and an arm connected between the base and the holding member. The arm is made of pliable metal material. Therefore, the arm may be bent and deformed easily. | 2012-06-21 |
20120153984 | METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE - A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing. | 2012-06-21 |
20120153985 | TESTING APPARATUS FOR TESTING PORTS OF PRINTED CIRCUIT BOARD - A test assembly includes a printed circuit board, a first subsidiary test chipset, a second subsidiary test chipset, and a main test chipset. The printed circuit board includes a first CPU socket and a second CPU socket. The first CPU socket includes a first socket pin. The second CPU socket includes a second socket pin. The first subsidiary test chipset connects to the first CPU socket. The second subsidiary test chipset connects to the second CPU socket. The main test chipset connects to the first subsidiary test chipset and the second subsidiary test chipset. The first subsidiary test chipset outputs a first signal to the first socket pin. The second subsidiary test chipset receives a second signal from the second socket pin. The main test chipset compares the first signal and the second signal to test a connection of the first socket pin and the second socket pin. | 2012-06-21 |
20120153986 | SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor device includes a pump voltage detecting unit, an oscillation signal generating unit, and a pump voltage generating unit. The pump voltage detecting unit is configured to detect the level of a pump voltage based on a target level varying in response to a test signal. The oscillation signal generating unit is configured to generate an oscillation signal in response to an output signal of the pump voltage detecting unit, wherein the frequency of the oscillation signal varies in response to the test signal. The pump voltage generating unit is configured to generate the pump voltage by performing a charge pumping operation at a speed corresponding to the frequency of the oscillation signal. | 2012-06-21 |
20120153987 | DIGITAL NOISE PROTECTION CIRCUIT AND METHOD - A method of protection from noise of a digital signal generated by a comparator, including the steps of generating an output signal that switches from a first logic state to a second logic state at a first switching of logic state of the digital signal; detecting a change from the first logic state to the second logic state of the output signal; and inhibiting further switchings of the output signal for a first time interval after the change from the first logic state to the second logic state. | 2012-06-21 |
20120153988 | SEMICONDUCTOR DEVICE, CIRCUIT BOARD DEVICE, AND INFORMATION PROCESSING DEVICE - In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage. | 2012-06-21 |
20120153989 | Element Controller for a Resilient Integrated Circuit Architecture - The exemplary embodiments provide a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element controller, an element interface and a selected circuit element which may vary by element type, and which may be configurable. The state machine element assigns various functions based on element type, such as assigning a first configuration to a first element type, assigning a second configuration to a second element type, and providing a first data link for the corresponding assignments. The element controller controls the execution of data operations by the circuit element. Function assignment, routing, fault detection, and re-assignment and data re-routing can occur in real time for a wide variety of programs and algorithms, providing for the IC to continue the same functioning despite defects which may arise during operation. | 2012-06-21 |
20120153990 | EMBEDDED BLOCK CONFIGURATION VIA SHIFTING - A functional logic block for embedding into a reconfigurable array, the functional logic block comprises at least one multi-bit register including a plurality of single-bit registers, the single-bit registers being divided into at least two groups. The functional logic block also comprises a shift chain for connecting each group of single-bit registers, each shift chain being arranged to connect its respective group of single-bit registers into a configuration and test chain. | 2012-06-21 |
20120153991 | COMPARATOR WITH OFFSET COMPENSATION AND IMPROVED DYNAMIC RANGE - A comparator having first and second stages can provide component offset compensation and improved dynamic range. The first stage can receive first and second input signals and produce first and second output signals. The second stage can be coupled to the first stage to receive the first and second output signals at first and second input terminals of the second stage. The second stage can provide a voltage to the first and second terminals that differs from the supply voltage by less than a voltage of a diode drop. The comparator is operable to receive input voltages that reach the supply voltage. | 2012-06-21 |
20120153992 | Analog power sequencer and method - Supply voltage sequencing circuitry includes a first sequencer ( | 2012-06-21 |
20120153993 | USB PORT DETECTING CIRCUIT - A Universal Series Bus USB port detection and testing circuit, configured to detect the voltage output of a USB port of an electronic device, includes a voltage comparing circuit and an indicating circuit. The indicating circuit is connected to an output terminal of the voltage comparing circuit. The voltage comparing circuit compares the voltage output from the USB port against a reference voltage and output a signal whereby the indicating circuit indicates whether the voltage is within, or above, or below, the standard range. | 2012-06-21 |
20120153994 | Methods and Implementation of Low-Power Power-On Control Circuits - Methods and implementation of low-power power-on control circuits are disclosed. In a particular embodiment, an apparatus includes a power detector circuit powered by a first voltage supply. At least one voltage level-shifting device is coupled to a second voltage supply and a test input is provided to the power detector circuit. An optional leakage self-control device may reduce unwanted leakage currents associated with the first supply and the second supply. | 2012-06-21 |
20120153995 | RESONANT TANK DRIVE CIRCUITS FOR CURRENT-CONTROLLED SEMICONDUCTOR DEVICES - A resonant tank circuit has an output port configured to be coupled to a load comprising a current-controlled semiconductor device, such as a diode, thyristor, transistor or the like. A voltage generator circuit is configured to intermittently apply voltages to an input port of the resonant tank circuit in successive intervals having a duration equal to or greater than a resonant period of the resonant tank circuit. Such an arrangement may be used, for example, to drive a static switch. | 2012-06-21 |
20120153996 | GATE DRIVING CIRCUIT ON ARRAY APPLIED TO CHARGE SHARING PIXEL - The disclosure provides a gate driving circuit on array applied to a display panel with charge sharing pixel structure. In particular, the gate driving circuit is adapted to receive multi-phase clock signal and includes a plurality of shift registers. Each shift register includes a driving circuit including a first driving transistor and a second driving transistor, a pull-down unit and at least one pull-up unit, so that is capable of generating mutually non-overlapped main gate driving signal and sub gate driving signal. Furthermore, the advantage of the disclosure is to provide a gate driving circuit with simplified circuit structure and circuit layout. | 2012-06-21 |
20120153997 | Circuit for Generating a Reference Voltage Under a Low Power Supply Voltage - A circuit for generating a reference voltage including: a first current source in series with a first bipolar transistor, between a first and a second terminal of application of a power supply voltage; a second current source in series with a second bipolar transistor and a first resistive element, between said first and second terminals, the junction point of the first resistive element and of the second bipolar transistor defining a third terminal for providing the reference voltage; a follower assembly having an input terminal connected between the first current source and the first bipolar transistor, and having an output terminal connected to a base of the second bipolar transistor; and a resistive dividing bridge between the output terminal of the follower assembly and said second terminal, the midpoint of this dividing bridge being connected to a base of the first bipolar transistor. | 2012-06-21 |
20120153998 | GATE DRIVE CIRCUIT - A gate drive circuit capable of turning on a semiconductor switching element at high speed, which includes: a buffer circuit including a turn-on-drive switching element and a turn-off-drive switching element that are complementarily turned on and off, for driving the semiconductor switching element; a first DC voltage supply including a positive electrode connected to the source or emitter of the turn-on-drive switching element and a negative electrode connected to a reference potential; and a second DC voltage supply including a positive electrode connected to the source or emitter of the turn-off-drive switching element and a negative electrode connected to the reference potential. | 2012-06-21 |
20120153999 | CLOCK SIGNAL GENERATION CIRCUIT - A clock signal generation circuit includes a clock inversion unit inverting a reference clock signal and an internal clock signal to generate an inverted reference clock signal and an inverted internal clock signal, a first clock detection unit comparing the reference clock signal with the internal clock signal to output a first detection signal, a second clock detection unit comparing the inverted reference clock signal with the inverted internal clock signal to output a second detection signal, first and second charge pump units generating charge current or discharge current in response to the first second detection signals, respectively, a loop filter unit producing a control voltage signal having a voltage level corresponding to the charge currents or discharge currents, and an internal clock signal output unit producing the internal clock signal according to the control voltage signal. | 2012-06-21 |
20120154000 | PLL CIRCUIT - A PLL circuit, has a phase comparator for comparing phases of a reference clock and a feedback clock, and outputting a phase comparison signal indicating the phase difference; a charge pump circuit, which, during a time period corresponding to the phase difference, outputs a first charge pump current and a second charge pump current; a loop filter, having a capacitor storing electric charge based on the first and second charge pump currents, which generates a control voltage due to stored electric charge; an oscillator generating an output clock at a frequency according to the control voltage; a frequency divider frequency-dividing the output clock and outputs the feedback clock; and a charge pump adjustment circuit, which, when in a locked state, adjusts current quantity of the first or the second charge pump current such that the phase difference is suppressed, according to the phase difference indicated by the phase comparison signal. | 2012-06-21 |
20120154001 | SHIFT REGISTER AND SYNCHRONIZATION CIRCUIT USING THE SAME - A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal. | 2012-06-21 |
20120154002 | DELAY LOCKED LOOP - A delay locked loop includes a replica delay oscillator unit, a division unit, a pulse generation unit, a code value output unit, and a delay line. The replica delay oscillator unit generates a replica oscillation signal having a period corresponding to a replica delay. The division unit receives the replica oscillation signal and a clock signal and divides the replica oscillation signal and the clock signal at a first or second ratio in response to a delay locking detection signal. The pulse generation unit generates a delay pulse having a pulse width corresponding to a delay amount for causing a delay locking. The code value output unit adjusts a code value corresponding to the pulse width of the delay pulse in response to the delay locking detection signal. The delay line delays the clock signal in response to the code value. | 2012-06-21 |
20120154003 | SPUR REDUCTION TECHNIQUE FOR SAMPLING PLL'S - Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of a sampling control signal, in accordance with the PLL reference and output signals, spurious output signals from the sampling PLL being controlled can be reduced. | 2012-06-21 |
20120154004 | PULSE SIGNAL GENERATION CIRCUIT AND METHOD FOR OPERATING THE SAME - A pulse signal generation circuit includes a transfer path configured to receives and transfer a first pulse signal, a pulse adjustment unit configured to adjust a pulse width of the first pulse signal by applying charges to the transfer path in response to a control signal, and a pulse output unit configured to output a second pulse signal of the adjusted pulse width in response to an output of the transfer path. | 2012-06-21 |
20120154005 | PULSE WIDTH MODULATED SIGNAL GENERATION METHOD AND APPARATUS - Various embodiments associated with methods, apparatuses and systems, digital pulse width modulator (DPWM) comprising a counter logic, including a bitwise negator, and a delay-locked loop (DLL), are disclosed herein. The embodiments may potentially have a shorter processing delay, smaller footprint and/or less power consumption. Other embodiments be also be disclosed or claimed. | 2012-06-21 |
20120154006 | DUTY CYCLE CORRECTION CIRCUIT - A duty cycle correction circuit includes a duty cycle control unit configured to generate a corrected clock signal by correcting a duty cycle of an input clock signal in response to a control signal, a duty cycle detection unit configured to detect a duty cycle of the corrected clock signal and output a detection signal, and a control signal generation unit configured to generate the control signal in response to the detection signal. | 2012-06-21 |
20120154007 | SEMICONDUCTOR CIRCUIT AND SEMICONDUCTOR DEVICE - A semiconductor circuit of the present invention comprises a capacitor for charging ON driven electric charges in response to an ON driving signal, a capacitor for charging OFF driven electric charges in response to an OFF driving signal, a signal generating circuit for generating a first trigger signal in response to the ON driving signal, a signal generating circuit for generating a second trigger signal in response to the OFF driving signal, a discharging circuit for discharging the ON driven electric charges in response to the second trigger signal, and a discharging circuit for discharging the OFF driven electric charges in response to the first trigger signal. With this configuration, it is possible to provide a semiconductor circuit and a semiconductor device both of which have a general-purpose malfunction prevention function by which a malfunction due to dV/dt can be prevented without being affected by any external factor. | 2012-06-21 |
20120154008 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus may include a master chip, first to n | 2012-06-21 |
20120154009 | LATCH CIRCUITRY - A latch circuit comprises: a cross latch having a first node and a second node, a first transistor, a second transistor, a third transistor, a first current source, and a second current source. A third terminal of the first transistor and of the second transistor receives a first input signal and a second input signal, respectively. A first terminal of the first transistor and of the second transistor is coupled to the first node and the second node, respectively. A first terminal of the third transistor is coupled to the second terminal of the first transistor and of the second transistor. The first current source is coupled to the first node and affects a transition of a first output signal. The second current source is coupled to the second node and affects a transition of a second output signal. | 2012-06-21 |
20120154010 | SYSTEMS AND METHOD FOR SPUR SUPRESSION IN A MULTIPLE RADIO SoC - A digital system includes a spur calculator that computes harmonics of a frequency of a digital clock signal and that identities a harmonic that lies in a frequency band of operation of a radio frequency circuit. A duty cycle computation module receives the harmonic and computes a duty cycle for the harmonic. Further, a clock generator that is coupled to the duty cycle computation block generates a digital clock signal of the frequency and with the duty cycle such that amplitude of spur caused due to the harmonic is suppressed. | 2012-06-21 |
20120154011 | METHOD AND APPARATUS FOR PHASE SELECTION ACCELERATION - A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed. | 2012-06-21 |
20120154012 | Circuit and Method for Controlling Multi-Channel Power - A circuit and a method for controlling multi-channel power are disclosed. The method includes: according to a channel selection signal in the previous clock cycle, select one channel signal from the received at least one channel signal in the previous clock cycle; according to an amplification factor control signal in the previous clock cycle, amplify the selected one channel signal to acquire a first signal; perform A/D conversion on the first signal to acquire a second signal; and according to the second signal, generate an amplification factor control signal in the next clock cycle, so that according to the amplification multiple control signal in the next clock cycle, amplify the selected one channel signal in the next clock cycle when the next clock cycle comes. The scheme can be used to detect the multi-channel optical power and its circuit implementation is simple. | 2012-06-21 |
20120154013 | Power Converter for a Memory Module - An apparatus including a memory module and power converter and method of operating the same. In one embodiment, the apparatus includes a memory module, located on a circuit board, configured to operate from a first voltage and a second voltage being a multiple of the first voltage. The apparatus also includes a power converter employing a switched-capacitor power train, located on the circuit board, configured to provide the second voltage for the memory module from the first voltage. | 2012-06-21 |
20120154014 | LEVEL SHIFT CIRCUIT AND SWITCHING POWER SUPPLY DEVICE - A level shift circuit includes a level changing unit which includes first and second MOS transistors connected in series between a first power supply voltage terminal and a grounding point, and receives a signal having a first amplitude which varies between a lower second voltage and a ground potential to convert the signal to a signal having a second amplitude, and an output stage which includes first and second MOS transistors connected in series between the first power supply voltage terminal and a third voltage terminal to which a third voltage lower than the first power supply voltage and higher than the ground potential is supplied, and which stage is connected to an output node of the level changing unit. A first MOS transistor is connected in series between the first MOS transistor and the second MOS transistor of the level changing unit. | 2012-06-21 |
20120154015 | ANALOG MULTIPLIER - An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a first input voltage. The current passing through the voltage controlled resistance circuit is based upon a second input voltage. The first transistor and the second transistor form a current mirror to mirror the current passing through the voltage controlled resistance circuit to provide a power supply control current to a wideband code division multiple access radio frequency power amplifier. | 2012-06-21 |
20120154016 | SEMICONDUCTOR SWITCH AND METHOD FOR MEASURING SAME - According to one embodiment, a semiconductor switch includes a plurality of first switch elements, a second switch element, and a controller. The plurality of first switch elements are connected between a common terminal and each of a plurality of radio frequency terminals including a first terminal and a second terminal. The second switch element is connected between the first terminal and a ground terminal. The controller is configured to output a control signal to turn on or off the plurality of first switch elements and the second switch element and perform a normal operation mode to connect the common terminal to any one of the plurality of radio frequency terminals and a test mode to connect the common terminal to the first terminal, the second terminal, and the ground terminal according to a terminal switching signal. | 2012-06-21 |
20120154017 | HIGH FREQUENCY SWITCH - There is provided a high frequency switch capable of suppressing deterioration in distortion characteristics. The high frequency switch includes: a common port outputting a transmission signal to an antenna; a plurality of transmission ports each having the transmission signal input thereto; and a plurality of switching units each connected between the plurality of transmission ports and the common port to conduct or block the transmission signal from each of the transmission ports to the common port, wherein each of the switching units has one or more metal oxide semiconductor field effect transistors (MOSFETs) formed on a silicon substrate, and a capacitor connected between a body terminal of a MOSFET connected to the common port among the MOSFETs and a terminal of the MOSFET connected to the common port. | 2012-06-21 |
20120154018 | HIGH FREQUENCY SEMICONDUCTOR SWITCH - There is provided a high frequency semiconductor switch having an FET designed in consideration of characteristics required for a transmission terminal and a reception terminal. The high frequency semiconductor switch includes a plurality of field effect transistors that each include a source region and a drain region formed on a substrate to be spaced apart by a predetermined distance, a gate formed on the substrate to be disposed at the predetermined distance, a source contact formed on the substrate to be connected with the source region, and a drain contact formed on the substrate to be connected with the drain region. A distance between a source contact and a drain contact of a reception terminal side transistor is longer than a distance between a source contact and a drain contact of a transmission terminal side transistor. | 2012-06-21 |
20120154019 | FIELD-EFFECT MAGNETIC SENSOR - A field-effect magnetic sensor facilitates highly-sensitive magnetic field detection. In accordance with one or more example embodiments, current flow respectively between first and second source/drain terminals and a third source/drain terminal is controlled using inversion layers in separate channel regions for each of the first and second terminals. In response to a magnetic field, a greater amount of current is passed between the third source/drain terminal and one of the first and second source/drain terminals, relative to an amount of current passed between the third source/drain terminal and the other one of the first and second source/drain terminals. | 2012-06-21 |
20120154020 | STACK PACKAGE AND METHOD FOR SELECTING CHIP IN STACK PACKAGE - A stack package having stacked chips includes first voltage dropping units respectively formed in the chips; second voltage dropping units respectively formed in the chips; first signal generation units connected in parallel to a first line formed by connecting the first voltage dropping units in series, respectively formed in the chips, and configured to apply high level signals according to a voltage of the first line; second signal generation units connected in parallel to a second line formed by connecting in series the second voltage dropping units, respectively formed in the chips, and configured to apply high level signals according to a voltage of the second line; and chip selection signal generation units respectively formed in the chips, and configured to combine signals outputted from the first signal generation units and the second signal generation units and generate chip selection signals. | 2012-06-21 |
20120154021 | INTEGRATED CIRCUIT AND METHOD OF FABRICATING SAME - A method includes providing a wide bandgap semiconductor substrate that includes a first transistor and a second transistor defined thereon. The method also includes coupling the first transistor to the second transistor. The method further includes coupling a bias circuit to the first transistor and the second transistor and forming a junction therebetween. The method also includes coupling the first transistor to a first voltage source and coupling the second transistor to a second voltage source. The first voltage source and the second voltage source are configured to define a predetermined differential input voltage. | 2012-06-21 |
20120154022 | Charge Pump System that Dynamically Selects Number of Active Stages - A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly. | 2012-06-21 |
20120154023 | Charge Pump Systems with Reduction in Inefficiencies Due to Charge Sharing Between Capacitances - Improvements in the efficiency of two charge pump designs are presented. As a charge pump switches between modes, capacitances are charged. Due to charge sharing between capacitances, inefficiencies are introduced. Techniques for reducing these inefficiencies are presented for two different charge pump designs are presented. For a clock voltage doubler type of pump, a four phase clock scheme is introduced to pre-charge the output nodes of the pump's legs. For a pump design where a set of capacitances are connected in series to supply the output during the charging phase, one or more pre-charging phases are introduced after the reset phase, but before the charging phase. In this pre-charge phase, the bottom plate of a capacitor is set to the high voltage level prior to being connected to the top plate of the preceding capacitor in the series. | 2012-06-21 |
20120154024 | INTERNAL NEGATIVE VOLTAGE GENERATION DEVICE - An internal negative voltage generation device includes a first internal negative voltage generation block configured to generate a first internal negative voltage which is lower than a ground voltage; a second internal negative voltage generation block configured to generate a second internal negative voltage according to the first internal negative voltage, the second internal negative voltage being higher than the first internal negative voltage and lower than the ground voltage; and an initial driving block configured to additionally drive a second internal negative voltage terminal to the first internal negative voltage during an initial set time interval of an active operation time interval. | 2012-06-21 |
20120154025 | DUAL-GATE TRANSISTORS - A field effect transistor device comprising: a source electrode; a drain electrode; a semiconductive region comprising an organic semiconductor material and defining a channel of the device between the source electrode and the drain electrode; a first gate structure comprising a first gate electrode and a first dielectric region located between the first gate electrode and the semiconductive region; and a second gate structure comprising a second gate electrode and a second dielectric region located between the second gate electrode and the semiconductive region; whereby the conductance of the semiconductor region in the channel can be influenced by potentials applied separately or to both the first gate electrode and the second gate electrode. | 2012-06-21 |
20120154026 | INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE - An integrated circuit ( | 2012-06-21 |
20120154027 | APPARATUS - An impendence tuning apparatus is disclosed. The impendence tuning apparatus includes an operation amplifier, a reference resistor, a tuned resistor, a switching module, a current generator, a current detector and a controller. A first input terminal of the operation amplifier receives a basic voltage and the second terminal of the operation amplifier coupled to a first end. The switching module receives a control and coupled the first end to the tuned resistor or the reference resistor accordingly for generating a tuned current or a reference current separately. The current generator receives and mirrors the reference current or the tuned current to generate a first current and a second current. The current detector receives the first and the second currents and outputs current values the first and the second currents to the controller. The controller tunes an impendence of the tuned resistor according to the first and the second currents. | 2012-06-21 |
20120154028 | BIAS CIRCUIT AND ANALOG INTEGRATED CIRCUIT COMPRISING THE SAME - Disclosed is a bias circuit which includes a bias voltage generating part configured to generate a bias voltage using a reference current and a variable current; a reference current source part configured to provide the reference current to the bias voltage generating part; and a current adjusting part configured to provide the variable current to the bias voltage generating part and to adjust the amount of the variable current according to voltage levels of at least two input signals. The bias circuit prevents an increase in power consumption and improves a slew rate at the same time. | 2012-06-21 |
20120154029 | PMOS RESISTOR - Provided is a PMOS resistor. The PMOS resistor includes a PMOS transistor pair, a switching unit, and a negative feedback unit. The PMOS transistor pair is symmetrically connected between first and second nodes. The switching unit compares a voltage of the first node and a voltage of the second node to output one of the voltages of the first and second nodes. The negative feedback unit receives an output of the switching unit to control a current which flows in the PMOS transistor pair, for maintaining a constant resistance value. | 2012-06-21 |
20120154030 | FILTER CIRCUIT, INTEGRATED CIRCUIT INCLUDING THE SAME, AND SIGNAL FILTERING METHOD - A filter circuit includes a filtering unit configured to filter an input signal and generate an output signal, and a weight generation unit configured to monitor a variation of the output signal and generate weight information based on the monitored variation. | 2012-06-21 |
20120154031 | SIGNAL CANCELLATION TO REDUCE PHASE NOISE, PERIOD JITTER, AND OTHER CONTAMINATION IN LOCAL OSCILLATOR, FREQUENCY TIMING, OR OTHER TIMING GENERATORS OR SIGNAL SOURCES - A method includes obtaining an input signal and demodulating phase contamination in the input signal to generate a baseband signal. The method also includes modulating the input signal based on the baseband signal to generate an output signal, where the output signal has less phase contamination than the input signal. The phase contamination could be demodulated using a phase demodulator or a frequency modulation (FM) detector. A portion of the input signal could be down-converted to a lower frequency, and the phase contamination in the down-converted portion of the input signal could be demodulated. Additional phase contamination in the output signal can be demodulated and used to regulate a level of the baseband signal used during modulation of the input signal. The output signal could have less phase noise or period jitter than the input signal. | 2012-06-21 |
20120154032 | DC OFFSET COMPENSATION - An apparatus and method for DC offset compensation. An amplifier receives an input signal (A | 2012-06-21 |
20120154033 | AMPLIFYING APPARATUS AND DISTORTION COMPENSATION METHOD - An amplifying apparatus includes: a plurality of amplifiers; a linear combiner receiving a plurality of leakage signals resulting from cross leakage between outputs of the plurality of amplifiers and performing a linear combination of level values of the plurality of leakage signals to generate a plurality of linear combination signals; and an output calculator calculating real level values of a plurality of output amplified signals of the amplifiers from level values of the linear combination signals. | 2012-06-21 |
20120154034 | DOHERTY AMPLIFIER SYSTEM AND TRANSMITTER USING THE SAME - According to an embodiment, a Doherty amplifier system has a first Doherty amplifier and a second Doherty amplifier. The first Doherty amplifier operates in a SISO communication mode and in a MIMO communication mode. The first Doherty amplifier comprises a first carrier amplifier and a first peak amplifier. The second Doherty amplifier operates in the MIMO communication mode but not operates in the SISO communication mode. The second Doherty amplifier comprises a second carrier amplifier and a second peak amplifier. A distance between the first carrier amplifier and the second carrier amplifier is less than any of a distance between any of the first carrier amplifier and the second peak amplifier and any of the first peak amplifier and the second peak amplifier. In the SISO communication mode, heat generated by the first Doherty amplifier is conducted to the second Doherty amplifier to warm up the second Doherty amplifier. | 2012-06-21 |
20120154035 | AMPLIFYING DEVICE - An amplifying device which amplifies a signal, includes: an amplifier which amplifies an input signal by a power supplied from a power node; a first power source which supplies a fixed voltage to the power node; a second power source which supplies a variable voltage to the power node based on an envelope signal relating to the input signal and voltage of the power node; an active short device which reduces impedance of the power node when the first power source supplies the power to the power node and the second power source does not supply the power to the power node; a synthesizer which synthesizes the envelope signal and a cancel signal so that the second power source does not supply the power to the power node according to voltage variation of the power node by the active short device. | 2012-06-21 |
20120154036 | DIGITAL PRE-DISTORTION POWER AMPLIFYING APPARATUS AND METHOD FOR DIGITALLY CONTROLLING SYNCHRONIZATION THEREOF - A digital pre-distortion (DPD) power amplifying apparatus and a method for digitally controlling synchronization of the DPD power amplifying apparatus, which includes a power amplifier, a bias shifter and a DPD unit, are provided. The method includes acquiring a DPD path delay time at a path along which an input signal is fed back to the DPD unit; delaying an input signal incoming to the power amplifier by the DPD path delay time and acquiring synchronization by delaying a bias signal a predetermined number of times until the bias signal and the delayed input signal are synchronized with each other; and in response to synchronization between the bias signal and the delayed input signal being established, pre-distorting the input signal according to a feedback signal output from the power amplifier. | 2012-06-21 |
20120154037 | AMPLIFIER CURRENT CONSUMPTION CONTROL - The audio amplifier includes a variable gain amplifier receiving the input audio signal and providing the output signal, whereby the output signal corresponds to the input signal amplified by a limiter gain. The audio amplifier further includes a limiter gain calculation unit, thus the input signal is amplified by the limiter gain. A control unit receives a signal representative of the input signal and is configured to estimate, based on a mathematical model, the input current or the total output current of the audio amplifier thus providing an estimated current signal corresponding to (and resulting from) the output signal, whereby the limiter gain calculation unit is configured to calculate, dependent on the estimation, the limiter gain such that the actual input current or the total output current of the audio amplifier does not exceed a threshold current value. | 2012-06-21 |
20120154038 | Multi-band wideband power amplifier digital predistorition system and method - A high performance and cost effective method of RF-digital hybrid mode power amplifier systems with high linearity and high efficiency for multi-frequency band wideband communication system applications is disclosed. The present disclosure enables a power amplifier system to be field reconfigurable and support multiple operating frequency bands on the same PA system over a very wide bandwidth. In addition, the present invention supports multi-modulation schemes (modulation agnostic), multi-carriers and multi-channels. | 2012-06-21 |
20120154039 | Generation of pre-distortion coefficients - There is disclosed a method for generating pre-emphasis coefficients for a pre-emphasis stage of a non-linear distorting device, the method comprising the steps of: capturing, for a given time period, samples of an input signal and samples of an output signal; determining the direction of an error between the captured samples; adjusting the input signal in a direction to reduce the error to generate an estimate of the pre-distorted input signal; generating updated pre-distortion coefficients in dependence on the estimate of the pre-distorted input signal and generated pre-distortion coefficients for one or more previous time periods. | 2012-06-21 |
20120154040 | PREDISTORTER FOR COMPENSATING FOR NONLINEAR DISTORTION AND METHOD THEREOF - The predistorter may include: a predistortion filter predistorting an input signal to provide an output signal; a predistortion output estimation unit estimating the characteristics of a nonlinear device based on a signal processed by the nonlinear device and the output signal, and calculating a desired output signal of the predistortion filter by using the estimated characteristics of the nonlinear device; and an adaptive algorithm driving unit comparing the output signal with the desired output signal to output an error as a comparison result, calculating a filter coefficient according to which the calculated error is minimized, and providing the calculated filter coefficient to the predistortion filter in order to update a filter coefficient of the predistortion filter. | 2012-06-21 |
20120154041 | PREDISTORTION APPARATUSES AND METHODS - Provided is a predistortion apparatus which performs predistortion by reflecting a memory effect when linearizing an output of a nonlinear device using a wideband signal. The predistortion apparatus includes a predistortion unit and a coefficient extraction unit. The predistortion unit selects and outputs one of outputs of the sub-predistorters as an output signal according to intensity of an input signal. The coefficient extraction unit selects one of a plurality of coefficient extractors according to intensity of a nonlinear signal which is generated in response to the output signal, extracts a plurality of predistortion coefficients with the nonlinear signal and the output signal, and delivers the extracted predistortion coefficients to the predistortion unit. Accordingly, the memory effect is reflected even when the input signal is a wideband signal. | 2012-06-21 |
20120154042 | ANALOG MULTIPLIER - An exemplary embodiment of an analog multiplier may include a voltage controlled resistance circuit, a first transistor and a second transistor, where the resistance of the voltage controlled resistance circuit is based upon a difference between a supply voltage and a first input voltage and a constant current supply. The current passing through the voltage controlled resistance circuit is based upon a difference between the voltage supply and a second input voltage. The first transistor may be configured to mirror the current passing through the voltage controlled resistance circuit. | 2012-06-21 |
20120154043 | HIGH-FREQUENCY POWER AMPLIFIER DEVICE - Disclosed is a high-frequency power amplifier device capable of reducing a talk current. For example, the high-frequency power amplifier device has first and second power amplifier circuits, first and second transmission lines, and a region in which the first and second transmission lines are disposed close to each other. Either the first or second power amplifier circuit becomes activated in accordance with an output level. When the second power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the same direction so that magnetic coupling occurs to strengthen each transmission line's magnetic force. When, on the other hand, the first power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the opposite directions so that magnetic coupling occurs to weaken each transmission line's magnetic force. | 2012-06-21 |
20120154044 | Class-D Amplifier Circuit - A class-D amplifier circuit includes an amplifier that generates pulse-width modulated output signals according to input signals which have phases reverse to each other and are supplied to a first input end and a second input end, a first transistor interposed between a first input path extending from the first input end to the amplifier and a second input path extending from the second input end to the amplifier, and a voltage applying circuit that applies a control voltage corresponding to a predetermined value to a control terminal of the first transistor so that a current flowing between both ends of the first transistor increases in accordance with increase of levels of the input signals within a range in which the levels of the input signals are higher than the predetermined value. | 2012-06-21 |
20120154045 | PUSH-PULL LOW NOISE AMPLIFIER WITH VARIABLE GAIN, PUSH-PULL LOW NOISE AMPLIFIER WITH COMMON GATE BIAS CIRCUIT AND AMPLIFIER WITH AUXILIARY MATCHING - A push-pull low noise amplifier (LNA) includes at least one amplifier block. Each amplifier block includes a bypass stage and at least one gain cell. The bypass stage has a first node and a second node. The gain cell has an input terminal and an output terminal, comprising a loading stage and a driving stage. When the push-pull LNA is in a first gain mode, the loading stage is enabled and the bypassing stage is disabled; and when the push-pull LNA is in a second gain mode, the loading stage is disabled and the bypassing stage is enabled. | 2012-06-21 |
20120154046 | SENSE AMPLIFIER STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes a first signal line and a second signal line, and a sense amplifier that includes a plurality of PMOS transistors and a plurality of NMOS transistors. The sense amplifier is configured to sense amplify a potential difference between the first signal line and the second signal line. The junction regions of the NMOS and PMOS transistors having the same conductivity type, and to which the same signal is applied, are formed in one integrated active region. | 2012-06-21 |
20120154047 | LOW-NOISE AMPLIFIER - A low-noise amplifier comprises an input terminal to which a signal is input; a transistor configured to amplify the signal input to the input terminal; an output terminal through which the amplified signal from the transistor is output; a feedback amount regulator circuit configured to regulate an amplitude of the signal output from the transistor as a feedback amount and output a voltage; a bias circuit configured to generate a bias current fed to the transistor; a differential voltage comparator configured to compare the voltage output from the feedback amount regulator circuit to a reference voltage, determine whether or not a level of the signal input to the input terminal is a level at which a gain of the transistor is suppressed, and increase the bias current fed to the transistor when the differential voltage comparator determines that the level of the signal input to the input terminal is the level at which the gain of the transistor is suppressed; a first input bias circuit configured to generate the reference voltage and apply the reference voltage to one input end of the differential voltage comparator; and a second input bias circuit configured to add a bias voltage to the voltage output from the feedback amount regulator circuit and apply the voltage added with the bias voltage to the other input end of the differential voltage comparator. | 2012-06-21 |
20120154048 | Amplifier common-mode control methods - Systems and methods for providing a fully differential amplifier performing common-mode voltage control having reduced area and power requirements are disclosed. The amplifier disclosed comprises an additional input stage at the amplifier input which senses the common mode voltage of the amplifier's inputs and applies internal feedback control to adjust the output common-mode voltage until the input common-mode voltage matches a target voltage and thereby indirectly set the output common-mode voltage. Furthermore the internal common-mode control can be implemented in such a manner as to provide a feed-forward transconductance function in addition to common-mode control if desired. Moreover it is possible to use feedback from other amplifier stages in an amplifier chain to implement common-mode feedback. | 2012-06-21 |
20120154049 | Common-Mode Feedback Circuit - A differential amplifier circuit with common-mode feedback is disclosed. The amplifier may include a first stage comprising a first differential input configured to drive a first differential pair transistor in a first differential current path, a second differential input configured to drive a second differential pair transistor in a second differential current path, a first differential output, and a second differential output, a second stage comprising a first differential input, a second differential input, a first differential output, and a second differential output, a common-mode feedback circuit, a first conducting element in a first common-mode current path parallel to the first differential current path and comprising a first conducting terminal coupled to the first differential output of the first stage, and a second conducting element in a second common-mode current path parallel to the second differential current path and comprising a first conducting terminal coupled to the second differential output of the first stage. | 2012-06-21 |
20120154050 | CIRCUIT WITH REFERENCE SOURCE TO CONTROL THE SMALL SIGNAL TRANSCONDUCTANCE OF AN AMPLIFIER TRANSISTOR - A circuit has a reference source ( | 2012-06-21 |
20120154051 | VOLTAGE REGULATOR CIRCUIT - A voltage regulator circuit includes a differential amplifier circuit that includes a first input terminal and a second input terminal, the first input terminal supplied a reference voltage, an output circuit that receives an output voltage from the differential amplifier circuit to generate a first voltage based on the output voltage, and a control circuit that compares the first voltage with a second voltage, and outputs the first voltage or a third voltage to the second input terminal based on a result of comparing, the second and third voltage being different from the first voltage. | 2012-06-21 |