25th week of 2009 patent applcation highlights part 28 |
Patent application number | Title | Published |
20090154186 | VEHICLE LAMP ASSEMBLY - A vehicle lamp assembly includes a first lamp section and a second lamp section, which are disposed inside a lamp chamber defined by a lamp body and a front cover. The first lamp section includes a light source and a reflector which reflects light from the light source. The second lamp section includes a first light emitting device, a second light emitting device, a light guide member, and an optical component. The light guide member includes a base end face from which the light guide member extends in a strip shape along the front cover, a functional portion having a diffusing front surface which emits light from a first light emitting device, and a decorative portion having an internally reflecting rear surface which reflects light from a second light emitting device. A light emitting area of the decorative portion is larger than that of the functional portion. The optical component is disposed on a rear side of the functional portion to guide the light from the first light emitting device toward the diffusing front surface. The light emitted from the second light emitting device is incident on the base end face. | 2009-06-18 |
20090154187 | HEADLAMP FOR VEHICLE - A headlamp capable of preventing dazzling of an opposite driver is provided. The headlamp includes a projection lens, a reflector, a light source disposed at a first focal point of the reflector, and a light shade part positioned around a second focal point of the reflector. The light shade part includes a first shade comprising a plurality of shading plates for forming a desired light distribution pattern and a second shade formed as a continuous surface or discrete surfaces connected to the uppermost surfaces of the shading plates of the first shade. | 2009-06-18 |
20090154188 | VEHICLE LAMP - A vehicle lamp includes: N semiconductor light sources, wherein N is an integer of 1 or more; M fans configured to cool the N semiconductor light sources, wherein M is an integer of 1 or more; N current supply units configured to supply first current to the N semiconductor light sources, respectively; and a control unit configured to receive electric power supplied from an electric power source and supply second current to the N current supply units. The control unit includes: N switch elements that correspond to the N semiconductor light sources; M switch elements that correspond to the M fans; and a control circuit configured to control fan drive current supplied to the fans through the switch elements and the second current. The fans are coupled to the control unit. | 2009-06-18 |
20090154189 | HEAT-DISSIPATING APPARATUS FOR VEHICLE LAMP - A heat-dissipating apparatus for a vehicle lamp includes: a light source unit comprising at least one LED; a housing which houses the light source unit therein and is formed with an opening in a rear portion thereof; a dust cover coupled to the housing at or near the position of the opening; and a cooling fan coupled to the dust cover for dissipating heat generated by the light source unit. | 2009-06-18 |
20090154190 | APPARATUS FOR AIMING LED HEADLAMP - Disclosed herein is an LED (light emitting diode) headlamp aiming apparatus, which aims a mounting module that is provided with LEDs and is installed in a headlamp housing. The LED headlamp aiming apparatus includes a vertical aiming unit, which is provided on the rear side of the mounting module and is coupled to the headlamp housing, a horizontal aiming unit, which is provided on the rear side of the mounting module and is coupled to the headlamp housing, and a pivot unit which is coupled to the headlamp housing and is provided under the lower portion of the mounting module to support the mounting module and provide the center of the aiming operation. | 2009-06-18 |
20090154191 | ARRANGEMENT FOR GENERATING DUAL IMAGES - An arrangement and method for displaying at least a first and a second image. The arrangement comprises at least one light source ( | 2009-06-18 |
20090154192 | Illumination Device For Generating Light And Supplying The Light To An Observation Device Used In Endoscopy Or Microscopy - An illumination device for generating light and supplying the light to an observation device used in endoscopy or microscopy comprises a light source having at least one LED and at least one optical waveguide to guide the light emitted by the light source. The proximal end of the optical waveguide is arranged on a side of the light source which faces the optical waveguide. The illumination device furthermore comprises a cooling device to dissipate heat generated by the light source, which cooling device has at least one first cooling element for dissipating the heat generated by the light source, which cooling element is arranged on a side of the light source which faces away from the proximal end of the optical waveguide. The cooling device has a second cooling element for dissipating the heat generated by the light source, which second cooling element is arranged on the side of the light source which faces the proximal end of the optical waveguide. The at least one optical waveguide passes through the second cooling element. | 2009-06-18 |
20090154193 | SHEET-SHAPED LIGHTGUIDE MEMBER, OPERATION PANEL-LIGHTING DEVICE AND ELECTRONIC DEVICE - A sheet-shaped lightguide member has a first surface ( | 2009-06-18 |
20090154194 | LIGHT EMITTING DIODES, DISPLAY SYSTEMS, AND METHODS OF MANUFACTURING LIGHT EMITTING DIODES - Light emitting diodes, display systems, and manufacturing methods are provided. In an embodiment, by way of example only, a light emitting diode (“LED”) include a die and a lens. The die is configured to emit wavelengths of light within a first predetermined spectral range. The lens is disposed on at least a portion of the die and is configured to filter the light emitted from the die such that a second predetermined spectral range is emitted from the LED. | 2009-06-18 |
20090154195 | WHITE LIGHT-EMITTING DEVICE, METHOD FOR MANUFACTURING SAME, BACKLIGHT USING SAME, AND LIQUID CRYSTAL DISPLAY - A white light-emitting device | 2009-06-18 |
20090154196 | FLEXIBLE LIGHT EMITTING DEVICE - A flexible light emitting device including at least one light source and a flexible light guide is provided. The flexible light guide has at least one light emitting surface and at least one light incident surface. Moreover, micro-structures are located on at least one surface of the flexible light guide except the light incident surface. The light source is disposed beside the light incident surface of the flexible light guide. When the light of the light source is incident into the flexible light guide, the total reflection would be destroyed due to the micro-structures, and thus the light could emit out of the flexible light guide from the light emitting surface. | 2009-06-18 |
20090154197 | OPTICAL FILM AND BACKLIGHT SYSTEM USING THE SAME - An optical film with a plurality of micro structures which are capable of collecting incident light to the frontal and normalized view angle of the optical film for reducing the chance of incident light returning to light guild plate so as to enhance light collecting efficiency is provided in the present invention. In an embodiment, the optical film is combined with a flat light source so as to form a backlight system. By means of the merit of the optical film, the quantities of the optical film can be reduced so that the backlight system can have characteristics of thin thickness and low production cost. | 2009-06-18 |
20090154198 | REFLECTION TYPE DISPLAY APPARATUS - A reflection type display apparatus has a front light unit (FLU), and includes a display panel, a light guide disposed on the upper surface of the display panel, a light transparent adhesive layer attaching the lower surface of the light guide to the upper surface of the display panel, and a light source located at a side of the light guide for emitting light to the light guide. A protection window covers the light guide and the light source. By covering the display panel installed on the lower surface of the protection window and the light guide with a moisture-proof and light-shield film, moisture-proofing and light-shielding effects are obtained simultaneously. Further, by forming a light absorption layer at the edge of the light guide adjacent to the light source, generation of a hot spot at the edge of the light guide may be inhibited. | 2009-06-18 |
20090154199 | BURST FREQUENCY RESONANT INVERTER - A high frequency resonant apparatus is described that includes a closed loop resonant series circuit including a capacitor, an inductor, a load, and a switching device with an anti-parallel diode. An energy source is coupled to the closed loop series circuit. The high frequency resonant apparatus also includes a controller for turning on the switching device for a time longer than one cycle of the closed loop resonant series circuit. | 2009-06-18 |
20090154200 | CONTROLLER CIRCUIT AND SYSTEM HAVING SUCH A CONTROLLER CIRCUIT - A controller circuit is specified, having a step-up controller, a resonant converter connected downstream of the step-up controller on the output side, a transformer, a rectifier, which rectifier is connected to the secondary winding of the transformer on the input side, and a CLL resonant circuit connected to the resonant converter and to the primary winding of the transformer, which CLL resonant circuit has a resonance capacitance and a first and a second resonance inductance. In order to reduce the switching losses, the CLL resonant circuit is embodied as a “T” circuit. | 2009-06-18 |
20090154201 | ALTERNATING VOLTAGE GENERATOR EQUIPPED WITH A CURRENT LIMITING DEVICE - The invention relates to an alternating voltage generator ( | 2009-06-18 |
20090154202 | Backlight inverter and method of driving same - A backlight inverter is provided which includes at least one inverter transformer and to which a plurality of cold cathode fluorescent lamps are connected, wherein a plurality of primary windings of the inverter transformer are connected to each other either in series or in parallel, a resonance circuit including a leakage inductance and a capacitance component is formed at the secondary side of the inverter transformer, and wherein the inverter transformer is driven at an operating frequency which is included in a frequency range between a parallel resonance frequency and a series resonance frequency of the resonance circuit and which excludes a frequency range between a first inflection point and a second inflection point of a gain characteristic curve of the inverter transformer. | 2009-06-18 |
20090154203 | AC to DC power supply having zero low frequency harmonic contents in 3-phase power-factor-corrected output ripple - An AC-DC power supply circuit utilizing an output stage configuration designed to achieve no output ripple at the power line frequency. To eliminate the ripple formed, each separate processing output stage corresponding to a respective ac voltage source phase which provides a 120 Hz ripple, is stacked, in a series connection, and due to their respective ripple phase shifts of 120° degrees, achieves ripple cancellation at the output. | 2009-06-18 |
20090154204 | REVERSE BIASING ACTIVE SNUBBER - The present invention provides a transient suppression circuit for use with a rectifier coupled to a transformer. In one embodiment, the transient suppression circuit includes a triggering section configured to provide a timing signal corresponding to a dead time of the rectifier. Additionally, the transient suppression circuit also includes a biasing section coupled to the triggering section and configured to apply a reverse bias voltage to the rectifier based on the timing signal. | 2009-06-18 |
20090154205 | SNUBBER CAPACITOR RESETTING IN A DC-TO-DC CONVERTER - A DC-to-DC converter and associated methods are provided for controlling the discharge of snubber capacitances during a light/no load buck mode of operation. An operating method for a DC-to-DC converter detects conditions corresponding to a light/no load buck mode of operation, and, in response to the detection of that mode, controls the states of a first switch, a second switch, a first switched diode element, a second switched diode element, a third switched diode element, and a fourth switched diode element to facilitate discharging of a first capacitance element and a second capacitance element through a secondary winding of a transformer. | 2009-06-18 |
20090154206 | Circuit and associated method for reducing power consumption in an a power transformer - A method and circuit is provided for reducing power consumption in a power transformer, typically incorporated into an electrical or electronic device such as a consumer device. In an embodiment, a detection/isolation circuit is coupled to an input of a power transformer/rectifier via a switching device. The switching device can be, for example, a solid state relay. The detection/isolation circuit is configured to sense the occurrence of no-load conditions in the power transformer and responsively disengage the power transformer from a coupled source of power (e.g., wall outlet) via the coupled switching device. | 2009-06-18 |
20090154207 | NEGATIVE VOLTAGE GENERATING CIRCUIT - A negative voltage generating circuit includes a pulse generator U | 2009-06-18 |
20090154208 | POWER SUPPLY DEVICE - A power supply device with power conversion capabilities is disclosed. The power supply device comprises an input module, a power converter, and an output module. The input module is used for receiving an alternating current power. The power converter is coupled to the input module for converting the alternating current power to a direct current power. The output module is coupled to the power converter for outputting the direct current power. | 2009-06-18 |
20090154209 | SEMICONDUCTOR DEVICE AND POWER SUPPLY DEVICE USING THE SAME - A semiconductor device capable of reducing an inductance is provided. In the semiconductor device in which a rectification MOSFET, a commutation MOSFET, and a driving IC that drives these MOSFETs are mounted on one package, the rectification MOSFET, a metal plate, and the commutation MOSFET are laminated. A current of a main circuit flows from a back surface of the package to a front surface thereof. The metal plate is connected to an output terminal via a wiring in the package. Wire bondings are used for wirings for connecting the driving IC, the rectification MOSFET, and the commutation MOSFET, all terminals being placed on the same plane. For this reason, the inductance becomes small and also a power source loss and a spike voltage are reduced. | 2009-06-18 |
20090154210 | BIDIRECTIONAL FIELD-EFFECT TRANSISTOR AND MATRIX CONVERTER - The present invention provides a bi-directional field effect transistor and a matrix converter using the same, in which a current flowing bi-directionally can be controlled by means of a single device. | 2009-06-18 |
20090154211 | Placement and routing of ECC memory devices for improved signal timing - Various exemplary embodiments are a printed circuit board and related method of manufacturing, the printed circuit board including a memory controller, a plurality of synchronous data memory devices, each synchronous memory device including at least one data pin and at least one address/command pin, an ECC memory device including at least one ECC data pin and at least one ECC address/command pin, and at least one surface. In various exemplary embodiments, the plurality of synchronous data memory devices are arranged around a central location on the at least one surface and each synchronous data memory device is oriented such that the at least one data pin is further from the memory controller than the at least one address/command pin. | 2009-06-18 |
20090154212 | Memory module - A memory module, includes a memory module board and a plurality of memory devices on the memory module board. The memory module board includes one or more first input terminals configured to receive first signals to individually control the memory devices, and one or more second input terminals configured to receive second signals to commonly control the memory devices. Each of the memory devices includes a plurality of first signal input units configured to receive the first signals through one or more first input pins, a plurality of second signal input units configured to receive the second signals through one or more second input pins, and a plurality of dummy units, the dummy units being respectively connected to the first signal input units in parallel, and being configured to receive the first signals through one or more third input pins and to compensate for a signal line load. | 2009-06-18 |
20090154213 | SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE - A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size. | 2009-06-18 |
20090154214 | SEMICONDUCTOR MEMORY - Borderless contacts for word lines or via contacts for bit lines are formed using interconnect patterns, a part of which is removed. A semiconductor memory includes: a plurality of active regions AA | 2009-06-18 |
20090154215 | REDUCING NOISE AND DISTURBANCE BETWEEN MEMORY STORAGE ELEMENTS USING ANGLED WORDLINES - Devices and/or methods that facilitate reducing cross-talk noise and/or complementary bit disturb between adjacent storage elements in a memory device are presented. A memory device includes a memory array with wordlines formed in a zig-zag pattern such that each wordline can have segments that are parallel to the x-axis and other segments that are angled from a direction parallel to the x-axis based in part on a predetermined angle. Adjacent storage elements can be positioned at respective ends of an angled segment of a wordline to facilitate increasing the distance between such storage elements, as compared to the distance between storage elements associated with an orthogonal memory array, where the increase in distance can be based in part on the predetermined angle. The size of the memory array can be the same or substantially the same size, as compared to an orthogonal memory array. | 2009-06-18 |
20090154216 | Semiconductor memory device and semiconductor device group - A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region. | 2009-06-18 |
20090154217 | HIGH SPEED OTP SENSING SCHEME - A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline. | 2009-06-18 |
20090154218 | MEMORY ARRAYS USING NANOTUBE ARTICLES WITH REPROGRAMMABLE RESISTANCE - A memory array includes a plurality of memory cells, each of which receives a bit line, a first word line, and a second word line. Each memory cell includes a cell selection circuit, which allows the memory cell to be selected. Each memory cell also includes a two-terminal switching device, which includes first and second conductive terminals in electrical communication with a nanotube article. The memory array also includes a memory operation circuit, which is operably coupled to the bit line, the first word line, and the second word line of each cell. The circuit can select the cell by activating an appropriate line, and can apply appropriate electrical stimuli to an appropriate line to reprogrammably change the relative resistance of the nanotube article between the first and second terminals. The relative resistance corresponds to an informational state of the memory cell. | 2009-06-18 |
20090154219 | THREE-DIMENSIONAL MAGNETIC MEMORY WITH MULTI-LAYER DATA STORAGE LAYERS - Magnetic memories and methods are disclosed. A magnetic memory as described herein includes a plurality of stacked data storage layers to form a three-dimensional magnetic memory. The data storage layers are each formed from a multi-layer structure. At ambient temperatures, the multi-layer structures exhibit an antiparallel coupling state with a near zero net magnetic moment. At higher transition temperatures, the multi-layer structures transition from the antiparallel coupling state to a parallel coupling state with a net magnetic moment. At yet higher temperatures, the multi-layer structure transitions from the antiparallel coupling state to a receiving state where the coercivity of the multi-layer structures drops below a particular level so that magnetic fields from write elements or neighboring data storage layers may imprint data into the data storage layer. | 2009-06-18 |
20090154220 | PLATELINE DRIVER FOR A FERROELECTRIC MEMORY - One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed. | 2009-06-18 |
20090154221 | Non-Volatile memory device using variable resistance element with an improved write performance - A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator generating a first voltage, a voltage pad receiving an external voltage that has a level higher than the first voltage, a sense amplifier supplied with the first voltage and reading data from the non-volatile memory cells selected from the memory cell array, and a write driver supplied with the external voltage and writing data to the non-volatile memory cells selected from the memory cell array. | 2009-06-18 |
20090154222 | OPERATION METHOD FOR MULTI-LEVEL SWITCHING OF METAL-OXIDE BASED RRAM - Memory devices and methods for operating such devices are described herein. A method as described herein for operating a memory device includes applying a sequence of bias arrangements across a selected metal-oxide memory element to change the resistance state from a first resistance state in a plurality of resistance states to a second resistance state in the plurality of resistance states. The sequence of bias arrangements comprise a first set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the first resistance state to a third resistance state, and a second set of one or more pulses to change the resistance state of the selected metal-oxide memory element from the third resistance state to the second resistance state. | 2009-06-18 |
20090154223 | METHOD AND DEVICE FOR DEMULTIPLEXING A CROSSBAR NON-VOLATILE MEMORY - A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized. | 2009-06-18 |
20090154224 | MAGNETIC RANDOM ACCESS MEMORY AND WRITE METHOD OF THE SAME - A spin transfer type magnetic random access memory includes a magnetoresistive effect element including a fixed layer, a recording layer, and a nonmagnetic layer, a source line connected to one terminal of the magnetoresistive effect element, a transistor having a current path whose one end is connected to the other terminal of the magnetoresistive effect element, a bit line connected to the other end of the current path of the transistor, and running parallel to the source line, and a source/sinker which supplies a write current between the source line and the bit line via the magnetoresistive effect element and the transistor, a direction in which a magnetic field generated by the write current having passed through the bit line is applied to the magnetoresistive effect element being opposite to a direction of the write current passing through the magnetoresistive effect element. | 2009-06-18 |
20090154225 | THIN FILM MAGNETIC MEMORY DEVICE HAVING A HIGHLY INTEGRATED MEMORY ARRAY - Read word lines and write word lines are provided corresponding to the respective MTJ (Magnetic Tunnel Junction) memory cell rows, and bit lines and reference voltage lines are provided corresponding to the respective MTJ memory cell columns. Adjacent MTJ memory cells share at least one of these signal lines. As a result, the pitches of signal lines provided in the entire memory array can be widened. Thus, the MTJ memory cells can be efficiently arranged, achieving improved integration of the memory array. | 2009-06-18 |
20090154226 | INTEGRATED CIRCUIT INCLUDING QUENCH DEVICES - An integrated circuit includes a line, at least two quench devices coupled to the line, and a resistivity changing material memory cell coupled to the line. The at least two quench devices are configured to quench a write signal on the line during a write operation of the memory cell. | 2009-06-18 |
20090154227 | INTEGRATED CIRCUIT INCLUDING DIODE MEMORY CELLS - The integrated circuit includes a transistor and a contact coupled to the transistor. The integrated circuit includes a first diode resistivity changing material memory cell coupled to the contact and a second diode resistivity changing material memory cell coupled to the contact. The second diode resistivity changing material memory cell is positioned above the first diode resistivity changing material memory cell. | 2009-06-18 |
20090154228 | Random Access Memory Employing Read Before Write for Resistance Stabilization - An improved architecture and method for operating a PCRAM integrated circuit is disclosed which seeks to minimize degradation in the resistance of the phase change material in the cells. When an attempt is made during a write command to write a data state to a bit which already has that data state, such matching data states are identified and writing to those bits is precluded during the write command. In one embodiment, both the incoming data to be written to a bit and the data currently present at that bit address are latched. These latched data are then compared (e.g., with an XOR gate) to determine which bits have a matching data state. The results of this comparison are used as an enable signal to the write (column) driver in the PCRAM memory array, with the effect that only data bits having different data state are written, while data bits having a matching data state are not needlessly re-written. Because matching data states are ignored, reliability problems associated with such redundant writing are alleviated, and power is saved. | 2009-06-18 |
20090154229 | SENSING AND WRITING TO MAGNETIC RANDOM ACCESS MEMORY (MRAM) - A sensing circuit includes a sense amplifier circuit having a first and second nodes through which a magnetic memory element is sensed. A first current source is coupled to the first node a second current source is coupled to the second node. A reference magnetic memory element has a resistance associated therewith and is coupled to the first node, the reference magnetic memory element receives current from the first current source. At least one memory element, having a resistance associated therewith, is coupled to the second node and receives current from the second current source. Current from the first current source and current from the second current source are substantially the same. The logic state of the at least one memory element is sensed by a comparison of the resistance of the at least one memory element to the resistance of the reference magnetic memory element. | 2009-06-18 |
20090154230 | MAGNETIC MEMORY DEVICE AND METHOD - An exemplary embodiment of a magnetic random access memory (MRAM) device includes a magnetic tunnel junction having a free layer, a first electrode (first magnetic field generating means) having a first portion that covers a surface of the free layer, and an electric power source connected to the first electrode via a connection that covers less than half of the first portion of the first electrode. Another exemplary embodiment of an MRAM device includes a magnetic tunnel junction, first and second electrodes (first and second magnetic field generating means) directly connected to the magnetic tunnel junction on opposite sides of the magnetic tunnel junction, and an electric power source having one pole connected to the first electrode via a first connection and having a second pole connected to the second electrode via a second connection, wherein the first and second connections are laterally offset from the connections between the first and second electrodes and the magnetic tunnel junction. Methods of operating and manufacturing these magnetic random access memories are also disclosed. | 2009-06-18 |
20090154231 | Magnetic Random Access Memory and Operating Method of the Same - A magnetic random access memory of a spin transfer process, includes a plurality of magnetic memory cells | 2009-06-18 |
20090154232 | Disturb control circuits and methods to control memory disturbs among multiple layers of memory - Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for controlling memory disturbs to and among multiple layers of memory that include, for example, third dimensional memory technology. Each layer of memory can include a plurality of non-volatile memory cells that store data as a plurality of conductivity profiles that can be non-destructively read by applying a read voltage across a selected non-volatile memory cell. Data can be written to a selected non-volatile memory cell by applying a write voltage having a predetermined magnitude and polarity across the selected non-volatile memory cell. Stored data is retained in the plurality of non-volatile memory cells in the absence of power. | 2009-06-18 |
20090154233 | NAND TYPE MEMORY AND PROGRAMMING METHOD THEREOF - A memory includes many memory regions. The memory regions have multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The first bit line is coupled to a first column of the multi-level cells. The second bit line is coupled to a second column of the multi-level cells. The data buffer is coupled to the first bit line and the second bit line and for storing data to be programmed into the multi-level cells. The protecting unit is coupled to the first bit line, the second bit line and the data buffer and is for preventing a programming error from occurring. | 2009-06-18 |
20090154234 | READING ELECTRONIC MEMORY UTILIZING RELATIONSHIPS BETWEEN CELL STATE DISTRIBUTIONS - Providing distinction between overlapping state distributions of one or more multi cell memory devices is described herein. By way of example, a system can include a calculation component that can perform a mathematical operation on an identified, non-overlapped bit distribution and an overlapped bit distribution associated with the memory cell. Such mathematical operation can produce a resulting distribution that can facilitate identification by an analysis component of at least one overlapped bit distribution associated with cells of the one or more multi cell memory devices. Consequently, read errors associated with overlapped bits of a memory cell device can be mitigated. | 2009-06-18 |
20090154235 | REDUCED STATE QUADBIT - A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell. | 2009-06-18 |
20090154236 | Systems and methods for discrete channel decoding of LDPC codes for flash memory - Embodiments include systems and methods for soft encoding and decoding of data for flash memories using Log-Likelihood Ratios (LLRs). The LLRs are computed from statistics determined by observation of flash memory over time. In some embodiments, the write, retention and read transition probabilities are computed based on the observed statistics. These probabilities are used to compute the LLRs. During a read operation, a device reads the voltage of a cell of the flash memory. The level of the output is determined from the voltage. The level determines which LLRs to compute and transmit to a soft decoder. | 2009-06-18 |
20090154237 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE - A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a first register group configured to store control data used for controlling memory operations; an adjusting data storage area defined in the memory cell array so as to store adjusting data used for adjusting the control data; and a second register group configured to store the adjusting data read from the adjusting data storage area. | 2009-06-18 |
20090154238 | PROGRAMMING MULTILEVEL CELL MEMORY ARRAYS - Methods and apparatus, such as those for programming of multilevel cell NAND memory arrays to facilitate a reduction of program disturb, are disclosed. In one such method, memory cells are shifted from a first Vt distribution to a second Vt distribution higher than the first Vt distribution during a first portion of a programming operation if a second or a fourth data state is desired, while memory cells remain in the first Vt distribution if the first or a third data state is desired. During a second portion of the programming operating, if the third data state is desired, those memory cells are shifted from the first Vt distribution to a third Vt distribution higher than the second Vt distribution and, if the fourth data state is desired, those memory cells are shifted from the second Vt distribution to a fourth Vt distribution higher than the third Vt distribution. | 2009-06-18 |
20090154239 | NONVOLATILE SEMICONDUCTOR STORAGE APPARATUS - A nonvolatile semiconductor storage apparatus comprises a memory cell array having a plurality of memory cells which are connected to word lines and to bit lines and in each of which different information of x (x is an integer equal to or larger than 3) bits is stored in association with 2 | 2009-06-18 |
20090154240 | NAND FLASH MEMORY DEVICES HAVING WIRING WITH INTEGRALLY-FORMED CONTACT PADS AND DUMMY LINES AND METHODS OF MANUFACTURING THE SAME - A NAND flash memory device includes a plurality of continuous conductors disposed on a common level of a multilayer substrate, the plurality of continuous conductors including respective conductive lines extending in parallel along a first direction, respective contact pads disposed at ends of the respective conductive lines and respective conductive dummy lines extending in parallel from the contact pads along a second direction | 2009-06-18 |
20090154241 | NONVOLATILE SEMICONDUCTOR MEMORY, METHOD FOR READING OUT THEREOF, AND MEMORY CARD - A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory. | 2009-06-18 |
20090154242 | FLASH MEMORY WITH OPTIMIZED WRITE SECTOR SPARES - In certain exemplary embodiments, a memory device with optimized write sectors has a plurality P of memory write sectors and N memory spare sectors Cumulatively, the memory write sectors correspond to the specified storage capacity of the memory. The number N of spares is approximately equal to the number of write sectors expected to be decommissioned within an operational lifetime of the memory, which can be determined by empirical measurement. A method, by way of non-limiting example, of making memory includes specifying a plurality P of write sectors which define a specified storage capacity of a memory device, determining a number N of spare sectors, and making a memory device with about P write sectors and about N spare sectors. The number N can be determined, by way of example, by summing the infant mortality with the random failure of write sectors. One exemplary tool to determine infant mortality and random failure is to empirically create a cycle-based bathtub curve having infant mortality, random failure, and wear out regions. | 2009-06-18 |
20090154243 | NAND-TYPE FLASH MEMORY AND SEMICONDUCTOR MEMORY DEVICE - A NAND-type flash memory has a memory cell array having NAND cells, each having memory cells capable of being rewritten electrically, a drain of one memory cell and a source of the other memory cell neighboring in a first direction being connected to each other, each of the NAND cells being arranged in a second direction, a plurality of bit lines, each being provided for each of the NAND cells, a plurality of sense amplifiers, each being provided for each of the bit lines, a plurality of data latch circuits, each being provided for each of the sense amplifiers, each of the data latch circuits temporarily holding data sent to and received from the corresponding sense amplifier, at least one test latch circuit which temporarily holds test data supplied from outside, and a data switching circuit which performs control for supplying at least two among the data latch circuits with data held in the test latch circuit. | 2009-06-18 |
20090154244 | NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array including a plurality of word lines; a parameter storage part which stores a parameter related to a programming voltage which is applied to a word line for programming data; a word line selection circuit which selects a word line among the plurality of word lines which is connected to a memory cell to be programmed with data; a voltage application circuit which applies a programming voltage to the selected word line according to the parameter; a verify circuit which performs verification of programmed data; a control part which outputs a signal for selecting a word line and repeats the operations of the voltage application circuit until the verification is successful; a calculation circuit which calculates an average value of the number of times the control part repeats the operations of the voltage application circuit per each word line; and a parameter setting circuit which sets the parameter using the average value calculated. | 2009-06-18 |
20090154245 | NONVOLATILE SEMICONDUCTOR STORAGE DEVICE - A nonvolatile semiconductor storage device includes: a memory cell array in which electrically rewritable nonvolatile memory cells are arranged; and a register that holds good/bad information on a specific area that requires high reliability in a user accessible area of the memory cell array. An address conversion circuit internally accesses, when the specific area is bad and is accessed, a backup area in the user accessible area based on the good/bad information in the register. When the specific area is bad and the backup area is accessed, on the other hand, the address conversion circuit internally accesses the specific area based on the good/bad information in the register. | 2009-06-18 |
20090154246 | PROGRAMMING IN MEMORY DEVICES USING SOURCE BITLINE VOLTAGE BIAS - Systems and methods that facilitate improved programming memory cells in a nonvolatile memory (e.g., flash memory) are presented. An optimized voltage component can facilitate supplying respective voltages to a source, drain, and gate associated with a memory cell during operations, such as programming operations. The optimized voltage component can facilitate supplying a predetermined source bitline voltage to a memory cell during programming of the cell to facilitate reducing leakage currents associated with the bitlines, which can improve programming of the memory cell, and to facilitate reducing the programming current, which can result in power efficient programming and improved programming speed. | 2009-06-18 |
20090154247 | PROGRAMMING MEMORY DEVICES - A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device. | 2009-06-18 |
20090154248 | NONVOLATILE MEMORY DEVICE STORING DATA BASED ON CHANGE IN TRANSISTOR CHARACTERISTICS - A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors. | 2009-06-18 |
20090154249 | SENSE AMPLIFIER FOR LOW-SUPPLY-VOLTAGE NONVOLATILE MEMORY CELLS - A sense amplifier for nonvolatile memory cells includes a reference cell, a first load, connected to the reference cell, and a second load, connectable to a nonvolatile memory cell, both the first load and the second load having controllable resistance; a control circuit of the first load and of the second load supplies the first load and the second load with a control voltage irrespective of an operating voltage between a first conduction terminal and a second conduction terminal of the first load. | 2009-06-18 |
20090154250 | METHOD FOR READING NONVOLATILE MEMORY AT POWER-ON STAGE - A method for reading data in a nonvolatile memory at a power-on stage is provided and includes the following steps. Firstly, the data are read through a reference voltage. Next, a failure number is counted when reading the data has a fail result. Next, the reference voltage is adjusted when the failure number reaches a predetermined number. The effect effectively and exactly reading configuration information at a power-on stage is accomplished through the method. | 2009-06-18 |
20090154251 | ALGORITHM FOR CHARGE LOSS REDUCTION AND Vt DISTRIBUTION IMPROVEMENT - Methods and systems for accurately programming or erasing one or more memory cells on a selected wordline of a memory device are provided. In one embodiment, the memory device comprises a memory array, a threshold voltage measuring component configured to measure a threshold voltage of each memory cell on the selected wordline of the memory array, and an average threshold voltage determining component configured to determine an average threshold voltage result uniquely associated with the selected wordline, based on the measured threshold voltages. The memory device is configured to program one or more of the memory cells to a predefined program level relative to the determined average threshold voltage, or to erase memory cells of the selected wordline to the determined average threshold voltage. The method is particularly useful for multi-level flash memory cells to reduce charge loss while improving data reliability and Vt distributions of the programmed element states. | 2009-06-18 |
20090154252 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF SHORTENING ERASE TIME - In a memory cell array, a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines are arranged in a matrix. A control circuit controls the potentials of said plurality of word lines and said plurality of bit lines. In an erase operation, the control circuit erases an n number of memory cells (n is a natural number equal to or larger than 2) of said plurality of memory cells at the same time using a first erase voltage, carries out a verify operation using a first verify level, finds the number of cells k (k≦n) exceeding the first verify level, determines a second erase voltage according to the number k, and carries out an erase operation again using the second erase voltage. | 2009-06-18 |
20090154253 | SEMICONDUCTOR DEVICE - Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and −9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage. | 2009-06-18 |
20090154254 | CLUSTER BASED NON-VOLATILE MEMORY TRANSLATION LAYER - An improved non-volatile memory and logical block to physical block address translation method utilizing a cluster based addressing scheme is detailed. The translation of logical blocks/sectors to the physical blocks/sectors is necessary for a non-volatile memory to appear as a freely rewriteable device to a system or processor. Embodiments of the present invention utilize cluster based address translation to translate logical block addresses to physical block addresses, wherein each cluster contains a plurality of sequentially addressed logical blocks. This allows the use of a smaller RAM table for the address translation lookup and/or faster scanning of the memory device or memory subsystem for the matching cluster address. In one embodiment, a specially formatted cluster is utilized for frequently updated sectors/logical blocks, where the cluster stores a single logical block and a new sequential physical block of the cluster is written in turn with each update. | 2009-06-18 |
20090154255 | Symmetrically operating single-ended input buffer devices and methods - Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition of a signal applied to the second input terminal in the opposite direction. The aforementioned input buffer includes two amplifier circuits structured to be complementary with respect to each other. Each of the amplifier circuits includes a first transistor having a first input node that receives an input signal transitioning across a range of high and low voltage levels, and a second transistor having a second input node that receives a reference signal. The first input node is coupled to the second transistor through a capacitor that charges and discharges the drain of the second transistor responsive to the input signal transitioning to mimic the second input node transitioning in the direction opposite to the transition of the input signal, while the reference signal at the second input node is maintained at a constant voltage level. | 2009-06-18 |
20090154256 | Integrated Circuit Memory Devices Including Delayed Clock Inputs for Input/Output Buffers and Related Systems and Methods - A memory system may include an integrated circuit memory device and a memory controller coupled to the integrated circuit memory device. The integrated circuit memory device may include a memory cell array having a plurality of memory cells, a clock generator configured to generate a clock signal, a plurality of data input/output buffers, and a delay circuit. The plurality of data input/output buffers may be coupled between respective data input/output pads and the memory cell array, and each of the data input/output buffers may be configured to communicate data with the memory cell array responsive to the clock signal with the clock signal being applied to a clock input of each of the input/output buffers. The delay circuit may be coupled between the clock generator and a first one of the data input/output buffers so that the clock signal is delayed by different amounts at clock inputs of the first data input/output buffer and a second one of the data input/output buffers. Moreover, the memory controller may be configured to perform data training. Related methods and memory devices are also discussed. | 2009-06-18 |
20090154257 | MEMORY SYSTEM AND CONTROL METHOD FOR MEMORY - The memory system comprises: a semiconductor memory that includes an internal circuit, which operates according to a first power supply voltage, and a memory input/output circuit, which is coupled to the internal circuit and operates according to a second power supply voltage; a first control unit that includes a control input/output circuit, which is coupled to the memory input/output circuit and operates according to the second power supply voltage; a voltage generating unit that generates the second power supply voltage and changes the second power supply voltage according to a voltage adjustment signal; a clock generating unit that generates the clock signal and changes the frequency of the clock signal according to a clock adjustment signal; and a second control unit that generates the voltage adjustment signal and the clock adjustment signal according to an access state of the semiconductor memory by the first control unit. | 2009-06-18 |
20090154258 | FLOATING BODY CONTROL IN SOI DRAM - A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss, and a design structure including the DRAM memory device embodied in a machine readable medium is provided. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line. The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue. | 2009-06-18 |
20090154259 | Swapped-Body RAM Architecture - A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage. | 2009-06-18 |
20090154260 | SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS - Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli | 2009-06-18 |
20090154261 | REFERENCE-FREE SAMPLED SENSING - Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the applied plurality of different stimuli. An analysis component determines a logic state of each memory cell of the plurality of memory cells as a function of the sensed characteristic of each memory cell of the plurality of memory cells. | 2009-06-18 |
20090154262 | SEMICONDUCTOR DEVICE AND METHOD FOR WRITING DATA INTO MEMORY - It is an object to provide memory and a semiconductor device in which falsification of data written thereinto is prevented. The memory includes a memory circuit, a writing circuit, and a reading circuit. The memory circuit has a memory cell array in which a plurality of memory cells where “0” and “1” of binary data can be written are arranged. The writing circuit includes a first writing circuit which writes one of “0” and “1” of binary data into one of the memory cells included in the memory circuit, and a second writing circuit which writes the other of “0” and “1” of binary data into one of the memory cells included in the memory circuit. | 2009-06-18 |
20090154263 | DESIGN STRUCTURE FOR IMPROVING PERFORMANCE OF SRAM CELLS, SRAM CELL, SRAM ARRAY, AND WRITE CIRCUIT - A design structure embodied in a machine readable medium to improve performance of an SRAM cell or an SRAM array comprising a plurality of SRAM cells is described. The design structure includes a write circuit for an SRAM cell or an SRAM array. The write circuit includes a gate to switch the write circuit on and off. The cell is supplied by a first, higher voltage. The cell is accessible for read and write operations via at least one bit line connected to a write circuit. The cell is further addressable by at least one word line in order to access it by the bit line. To access the cell for read or write operations, the word line is supplied by the first, higher voltage and the bit line is supplied by a second, lower voltage. During write operations, the write circuit is driven by the first, higher voltage while the bit lines are still at the lower voltage. | 2009-06-18 |
20090154264 | Integrated circuits, memory controller, and memory modules - In accordance with embodiments of the invention, there are provided integrated circuits, memory controller, a method for determining a level for programming or erasing a memory segment, and a method for determining a wear level score for a memory segment. In an embodiment of the invention, a method for determining a level for programming or erasing a memory segment is provided, wherein a first level for programming or erasing a memory segment is determined as a function of an initial program/erase level. Furthermore, a first updated level is determined for a subsequent program/erase operation of the memory segment and a second level for programming or erasing the memory segment subsequent to programming or erasing the memory segment is determined using the first level, wherein the second level is determined as a function of the first updated level. | 2009-06-18 |
20090154265 | SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE - A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size. | 2009-06-18 |
20090154266 | SEMICONDUCTOR INTEGRATED CIRCUIT, MEMORY SYSTEM AND ELECTRONIC IMAGING DEVICE - A semiconductor integrated circuit ( | 2009-06-18 |
20090154267 | Clock signal generating circuit and data output apparatus using the same - A semiconductor memory device having a clock signal generating circuit which is capable of controlling a data output in compliance with PVT fluctuation by controlling a output timing of rising and falling clock signal based on a fuse cutting is described. The clock signal generating circuit includes a fuse unit for generating first and second fuse signals based on fuse cutting of fuses, a control signal generating unit for generating first and second fuse signals in response to the fuse signals, a clock signal delaying unit for generating a delayed clock signal by delaying the external clock signal by a delay section specified by the control signals, and a clock generating unit for generating a first internal clock signal in synchronization with a rising edge of the delayed clock signal and for generating a second internal clock signal in synchronization with a falling edge of the delayed clock signal. | 2009-06-18 |
20090154268 | DLL CIRCUIT, IMAGING DEVICE, AND MEMORY DEVICE - A variable delay circuit successively delays an input clock to generate a plurality of delayed clocks having different phases. A phase comparison circuit receives a first reference clock, which is either one of the delayed clocks or the input clock, and a second reference clock, which is one of the delayed clocks and whose phase lags behind that of the first reference clock, specifies a validated interval for the second reference clock, and compares the phases of the first and second reference clocks according to voltage levels of the first and second reference clocks only during the validated interval. A delay control circuit controls a delay time in the variable delay circuit according to a result of the comparison obtained by the phase comparison circuit. | 2009-06-18 |
20090154269 | MANAGING REDUNDANT MEMORY IN A VOLTAGE ISLAND - An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data. The redundancy initialization component is configured to initialize a memory using redundancy and associated repair register with repair data independent of, or in conjunction with, the initialization of other memories using redundancy and associated repair registers. | 2009-06-18 |
20090154270 | FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS - An integrated circuit having an integrated circuit and method for moving a failing address into a next available FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. A method of is disclosed that includes: providing a set of FARs and an associated set of redundant elements, wherein each FAR maps to a corresponding redundant element; testing a set of elements and placing an address of each failing element into a FAR; testing each redundant element and marking a FAR as bad when a redundant element corresponding to the FAR fails; and readdressing the set of elements and placing an address of an element being readdressed in a new FAR when the address of the element being readdressed matches an address in a FAR that has been marked as bad. | 2009-06-18 |
20090154271 | Semiconductor memory device and method for testing the same - Semiconductor memory device and method for testing the same includes a unit for characterized in that a burst length is increased in a test of a read operation and a write operation and a unit for connecting a plurality of banks to one data pad by sequentially and outputting the data. | 2009-06-18 |
20090154272 | FUSE APPARATUS FOR CONTROLLING BUILT-IN SELF STRESS AND CONTROL METHOD THEREOF - A fuse apparatus for controlling a built-in self stress unit including a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended, and a fuse configured to record a operation state of the built-in self stress according to the one-cycle end signal. | 2009-06-18 |
20090154273 | MEMORY INCLUDING A PERFORMANCE TEST CIRCUIT - A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells. | 2009-06-18 |
20090154274 | Memory Read Stability Using Selective Precharge - A memory device utilizes selective precharge and charge sharing to reduce a bit line voltage before accessing a bit cell. A reduction in bit line voltage is achieved by precharging different sections of the bit line to different voltages (e.g., a supply voltage and ground) and using charge sharing between these sections. Read stability improves as a result of the reduction of bit line voltage. The relative capacitance difference between bit line sections determines the bit line voltage after charge sharing. Thus, the memory device is tolerant to process or temperature variations. The bit line voltage may be controlled in design by selecting the sections that are precharged to supply voltage or ground. | 2009-06-18 |
20090154275 | SEMICONDUCTOR DEVICE AND TESTING METHOD THEREOF - A semiconductor device includes a sense amplifier, a drive circuit that operatively supplies a predetermined potential to the sense amplifier, and disconnection transistors that are provided between the sense amplifier and the drive circuit. According to the present invention, the disconnection transistors can disconnect the sense amplifier from the drive circuit. Therefore, when the sense amplifier is disconnected from the drive circuit during at least a part of a period from when the word line is activated till when the sense amplifier is activated, outflow and inflow of charge from and into the bit line can be stopped immediately. | 2009-06-18 |
20090154276 | Auto-refresh controlling apparatus - An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal generating unit for generating internal auto-refresh command signals in response to the counter signals when a test mode signal is activated. | 2009-06-18 |
20090154277 | METHOD OF REDUCING CURRENT OF MEMORY IN SELF-REFRESHING MODE AND RELATED MEMORY - The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a first terminal coupled to a word line, and a second terminal. The method includes: after the memory enters the self-refreshing mode: controlling a voltage difference between the control terminal and the second terminal to correspond to a first value during a self-refreshing operation period; and controlling a voltage difference between the control terminal and the second terminal to correspond to a second value smaller than the first value during a non self-refreshing operation period. | 2009-06-18 |
20090154278 | MEMORY DEVICE WITH SELF-REFRESH OPERATIONS - An apparatus and method for reducing power consumption within dynamic memory devices having internal self-refresh circuitry. The circuits for generating isolator control (ISO), pre-decoded row address (PXID) and/or word enable (WE) signals are configured in response to receipt of self-refresh and refresh counter signals to output different timing and sequencing when in self-refresh mode than when in normal mode of the memory device. Conventionally, ISO signals are controlled from a block selection circuit which also controls bit line equalization (BLEQ) and sense amplifier enable (SAPN). While in conventional circuits the PXID and WE signals are generated in response to the output of the address decoder and thus have a fixed timing in relation to the output of the address decoder. The use of different timing and sequencing can lower power consumption, such as by outputting fewer signal transitions per block during self-refresh. | 2009-06-18 |
20090154279 | REFRESH PERIOD SIGNAL GENERATOR WITH DIGITAL TEMPERATURE INFORMATION GENERATION FUNCTION - A refresh period signal generator with a digital temperature information generation function includes a temperature information generating part configured to generate temperature information by using a first period signal and a second period signal, a refresh period signal generating part configured to output a refresh period signal by selecting one signal having a shorter period between the first period signal and the second period signal, and an operation timing control part operating the temperature information generating part and the refresh period signal generating part at a predetermined timing. | 2009-06-18 |
20090154280 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously. | 2009-06-18 |
20090154281 | SEMICONDUCTOR DEVICE WITH REDUCED STANDBY FAILURES - A semiconductor memory device includes a cell core storing data, a plurality of peripheral circuit components, collectively driving data to/from the cell core and providing a default state at an output signal state during an initialization process upon power-up, and an initialization circuit detecting a standby mode of operation for the semiconductor memory device, and upon detecting the standby mode controlling operation of the plurality of peripheral circuit components to provide the default state as the signal state during standby mode. | 2009-06-18 |
20090154282 | SEMICONDUCTOR DEVICE - A semiconductor device comprises multiple memory cell blocks including multiple memory cells for storing a predetermined amount of data. Each of the memory cell blocks having three or more inputs and three or more outputs includes two readout address decoders as to the memory cells internally, stores truth table data for outputting a desired logical value as to predetermined address input, and is configured so as to operate as a logic circuit. Also, the memory cells include two readout word lines corresponding to the two readout address decoders, and in the case of the voltage of both of the two readout word lines being applied, the data held at this time is read out from readout data lines. Further, between the memory cell blocks is connected such that the three or more outputs from one memory cell block are input to three or more other memory cell blocks. | 2009-06-18 |
20090154283 | System for Blocking Multiple Memory Read Port Activation - A system for blocking multiple memory read port activation including a first memory read port word line driver that includes a first polarity hold latch with an output connected to an input of a first buffer, and a second memory read port word line driver that includes a second polarity hold latch with an output connected to an input of a blocking switch and a second buffer with an input connected to an output of the blocking switch, wherein a second input of the blocking switch is also connected to the output of the first polarity hold latch and the blocking switch is configured to allow or block a signal transmission between the input and the output of the blocking switch dependent on a signal assertion of the second input to the blocking switch. | 2009-06-18 |
20090154284 | SEMICONDUCTOR MEMORY DEVICE SUITABLE FOR INTERCONNECTION IN A RING TOPOLOGY - A semiconductor memory device, which comprises: memory; a plurality of inputs for receiving a command latch enable signal, an address latch enable signal, an information signal and a select signal indicative of whether the memory device has been selected by a controller; a plurality of outputs for releasing a set of output signals towards a next device; control circuitry; and bypass circuitry. When the select signal is indicative of the memory device having been selected by the controller, the control circuitry is configured to interpret the information signal based on the command latch enable signal and the address latch enable signal. When the select signal is indicative of the memory device not having been selected by the controller, the bypass circuitry is configured to transfer the command latch enable signal, the address latch enable signal and the information signal to the outputs of the memory device. | 2009-06-18 |
20090154285 | MEMORY CONTROLLER WITH FLEXIBLE DATA ALIGNMENT TO CLOCK - A system includes a memory controller and a plurality of memory devices that are connected in-series to the memory controller. The system operation is synchronous with clock that is provided in a fashion of source synchronous clock structure. The source synchronous clock structure includes a PLL (Phase-Locked Loop) that reshapes an incoming clock and a reshaped clock is provided. The PLL provides a shifted clock in phase of 90°. The phase-shifted clock and data are transmitted from the first device to the second device. Clock phase shift provides a center-edge clock with data to be transmitted. The devices are assigned with unique IDs. The least significant bit of the ID number of the last device is used for determination of clock alignment: edge- or center-aligned clock with data produced by the memory controller. | 2009-06-18 |