23rd week of 2015 patent applcation highlights part 52 |
Patent application number | Title | Published |
20150155294 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND A METHOD OF MANUFACTURING THE SAME - Semiconductor device including a memory cell featuring a first gate insulating film over a semiconductor substrate, a control gate electrode over the first gate insulating film, a second gate insulating film over the substrate and a side wall of the control gate electrode, a memory gate electrode over the second gate insulating film arranged adjacent with the control gate electrode through the second gate insulating film, first and second semiconductor regions in the substrate positioned on a control gate electrode side and a memory gate side, respectively, the second gate insulating film featuring a first film over the substrate, a charge storage film over the first film and a third film over the second film, the first film having a first portion between the substrate and memory gate electrode and a thickness greater than that of a second portion between the control gate electrode and the memory gate electrode. | 2015-06-04 |
20150155295 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes first semiconductor patterns with protrusions formed on the sidewalls thereof, and second semiconductor patterns respectively coupled to the first semiconductor patterns and increasing in width away from joining surfaces where the first semiconductor patterns and the second semiconductor patterns are coupled. | 2015-06-04 |
20150155296 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided is a semiconductor device including a first stacked structure in which first conductive patterns and first interlayer insulating layers are alternately stacked, a second stacked structure formed on the first stacked structure and including second conductive patterns and second interlayer insulating layers, which are alternately stacked, an interfacial pattern formed between the first stacked structure and the second stacked structure, first through-areas passing through the first stacked structure and the interfacial pattern, and including first protrusions protruding toward a sidewall of the interfacial pattern, second through-areas passing through the second stacked structure and connected to the first through-areas, and through-structures formed along sidewalls of the first through-areas and the second through-areas. | 2015-06-04 |
20150155297 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING DOUBLE-LAYERED BLOCKING INSULATING LAYERS - Provided is a method of fabricating a semiconductor memory device. The method includes alternately stacking interlayer insulating layers and sacrificial layers on a substrate, forming a channel hole exposing the substrate through the interlayer insulating layers and the sacrificial layers, sequentially forming a blocking insulating layer, an electric charge storage layer and a channel layer on a substrate exposed on a sidewall of the channel hole and in the channel hole wherein the blocking insulating layer includes a first blocking insulating layer and a second blocking insulating layer, selectively removing the sacrificial layers to expose the first blocking insulating layer and then forming a gap, removing the first blocking insulating layer exposed in the gap, forming first blocking insulating patterns between the interlayer insulating layers and the second blocking insulating layer, and forming a gate electrode in the gap. | 2015-06-04 |
20150155298 | THREE-DIMENSIONAL DEVICES HAVING REDUCED CONTACT LENGTH - Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed starting adjacent to a surface of a substrate. Peripheral circuitry is formed on an elevated portion that is adjacent to the memory array and has an uppermost portion substantially coplanar with an uppermost surface of the memory array. Additional apparatuses and methods are described. | 2015-06-04 |
20150155299 | COMPOSITE SUBSTRATE - Provided is a composite substrate having a semiconductor layer wherein diffusion of a metal is suppressed. This composite substrate has: a single crystal supporting substrate composed of an insulating oxide; a semiconductor layer, which has one main surface overlapping the supporting substrate, and which is composed of a single crystal; and a polycrystalline or amorphous intermediate layer, which is positioned between the supporting substrate and the semiconductor layer, and which has, as a main component, an element constituting the supporting substrate or an element constituting the semiconductor layer, and in which the ratio of accessory components other than the main component is less than 1 mass %. | 2015-06-04 |
20150155300 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE - A semiconductor device has a first element region, a second element region, and a first isolation region in a thin film region and a third element region, a fourth element region, and a second isolation region in a thick film region. It is manufactured with step (a) of providing a substrate having a silicon layer formed via an insulating layer, step (b) of forming element isolation insulating films in the silicon layer in the first isolation region and the second isolation region of the substrate step (c) of forming a hard mask in the thin film region, step (d) of forming silicon films over the silicon layer exposed from the hard mask in the third element region and the fourth element region, and step (e) of forming element isolation insulating films between the silicon films in the third element region and the fourth element region. | 2015-06-04 |
20150155301 | SEMICONDUCTOR SUBSTRATE WITH MULTIPLE SiGe REGIONS HAVING DIFFERENT GERMANIUM CONCENTRATIONS BY A SINGLE EPITAXY PROCESS - A substrate with two SiGe regions having different Germanium concentrations and a method for making the same. The structure includes an extremely-thin-silicon-germanium-on-insulator (ETSGOI) substrate with at least two active regions, wherein each of the at least two active regions has a SiGe layer with uniform Germanium concentration, and the Germanium concentration of the SiGe layer of one of the at least two active regions is different than the Germanium concentration of the SiGe layer of the other of at least two active regions. | 2015-06-04 |
20150155302 | DISPLAY DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE - A display device includes a lower wiring layer, an interlayer insulating layer, and an upper wiring layer. The lower wiring layer includes first partial electrode portions, first cuttable portions, and first openings; the upper wiring layer includes second partial electrode portions, second cuttable portions, and second openings. The first partial electrode portions and the second partial electrode portions are disposed in overlapping positions in the stacking direction; all the first cuttable portions and the second openings are disposed in overlapping positions in the stacking direction; all the second cuttable portions and the first openings are disposed in overlapping positions in the stacking direction. | 2015-06-04 |
20150155303 | ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME - An array substrate according to an embodiment includes a gate line and a data line in a display region and crossing each other to define a pixel region; first and second auxiliary patterns in a non-display region; a gate insulating layer between the gate and data lines and the first and second auxiliary patterns; a passivation layer on the data line and the second auxiliary pattern and including first and second contact holes respectively exposing the first and second auxiliary patterns; a planarization layer on the passivation layer and including first and second pack holes, which respectively correspond to the first and second contact holes; a bridge pattern between the first and second pack holes and overlapping the second auxiliary pattern; a pixel electrode on the planarization layer and in the pixel region; and a connection pattern on the bridge pattern and contacting the first and second auxiliary patterns. | 2015-06-04 |
20150155304 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to reduce the manufacturing cost of a semiconductor device. An object is to improve the aperture ratio of a semiconductor device. An object is to make a display portion of a semiconductor device display a higher-definition image. An object is to provide a semiconductor device which can be operated at high speed. The semiconductor device includes a driver circuit portion and a display portion over one substrate. The driver circuit portion includes: a driver circuit TFT in which source and drain electrodes are formed using a metal and a channel layer is formed using an oxide semiconductor; and a driver circuit wiring formed using a metal. The display portion includes: a pixel TFT in which source and drain electrodes are formed using an oxide conductor and a semiconductor layer is formed using an oxide semiconductor; and a display wiring formed using an oxide conductor. | 2015-06-04 |
20150155305 | TN-TYPE ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE - A TN-type array substrate and a fabrication method thereof, and a display device, the fabrication method of the TN-type array substrate includes: a step of forming a first metal layer, a gate insulating layer, an active layer, a second metal layer and a transparent conductive layer on a substrate, wherein the first metal layer includes a gate electrode, the second metal layer includes a data line, the transparent conductive layer includes a pixel electrode; and wherein the forming the second metal layer and the transparent conductive layer includes: sequentially forming a transparent conductive thin film and a metal thin film on the substrate; performing one-off patterning process on the transparent conductive thin film and the metal thin film to form a thin film transistor (TFT) channel region, the transparent conductive layer and the second metal layer. | 2015-06-04 |
20150155306 | STRUCTURE AND METHOD TO REDUCE CRYSTAL DEFECTS IN EPITAXIAL FIN MERGE USING NITRIDE DEPOSITION - FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over the buried insulator, and a nitride material filing spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride. | 2015-06-04 |
20150155307 | STRUCTURE AND METHOD TO REDUCE CRYSTAL DEFECTS IN EPITAXIAL FIN MERGE USING NITRIDE DEPOSITION - FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator, and a nitride material filing recessed spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride, and wherein the nitride material does not contact the bottom of the plurality of fins. | 2015-06-04 |
20150155308 | SEMICONDUCTOR DEVICE - Semiconductor elements deteriorate or are destroyed due to electrostatic discharge damage. The present invention provides a semiconductor device in which a protecting means is formed in each pixel. The protecting means is provided with one or a plurality of elements selected from the group consisting of resistor elements, capacitor elements, and rectifying elements. Sudden changes in the electric potential of a source electrode or a drain electrode of a transistor due to electric charge that builds up in a pixel electrode is relieved by disposing the protecting means between the pixel electrode of the light-emitting element and the source electrode or the drain electrode of the transistor. Deterioration or destruction of the semiconductor element due to electrostatic discharge damage is thus prevented. | 2015-06-04 |
20150155309 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a gate metal pattern including a gate line disposed on a base substrate and a gate electrode electrically connected with the gate line, an active pattern entirely overlapped with the gate metal pattern and comprising an oxide semiconductor and a data metal pattern disposed on the active pattern and including a data line, a source electrode electrically connected with the gate line and a drain electrode spaced apart from the source electrode. The active pattern has an overlapped region in which the active pattern is overlapped with the source electrode and the drain electrode and an exposed region in which the active pattern is not overlapped with the source electrode and the drain electrode. The thickness of the overlapping region and a thickness of the exposing region are same. | 2015-06-04 |
20150155310 | THIN FILM TRANSISTOR SUBSTRATE HAVING METAL OXIDE SEMICONDUCTOR AND MANUFACTURING THE SAME - The present disclosure relates to a thin film transistor substrate having a metal oxide semiconductor for flat panel displays and a method for manufacturing the same. The present disclosure suggests a thin film transistor substrate including: a gate electrode on a substrate; a gate insulating layer covering the gate electrode; a source electrode overlapping with one side of the gate electrode on the gate insulating layer; a drain electrode being apart from the source electrode and overlapping with other side of the gate electrode on the gate insulating layer; an oxide semiconductor layer contacting an upper surface of the source electrode and the drain electrode, and extending from the source electrode to the drain electrode; and an etch stopper having the same shape with the oxide semiconductor layer, and contacting an upper surface of the oxide semiconductor layer. | 2015-06-04 |
20150155311 | LIQUID CRYSTAL DISPLAY AND METHOD OF MANUFACTURING THE SAME - A liquid crystal display and a method of manufacturing the same are provided. The liquid crystal display includes an insulating substrate, a gate electrode formed on the insulating substrate, an oxide semiconductor layer formed on the gate electrode, an etch stopper formed on the oxide semiconductor layer in a channel area, a common electrode formed on the insulating substrate, source and drain electrodes separated from each other on the etch stopper and extending to an upper portion of the oxide semiconductor layer, a passivation layer formed on the etch stopper, the common electrode, the source and drain electrodes, and a pixel electrode formed on the passivation layer and connected to the drain electrode. | 2015-06-04 |
20150155312 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To improve productivity of a transistor that includes an oxide semiconductor and has good electrical characteristics. In a top-gate transistor including a gate insulating film and a gate electrode over an oxide semiconductor film, a metal film is formed over the oxide semiconductor film, oxygen is added to the metal film to form a metal oxide film, and the metal oxide film is used as a gate insulating film. After an oxide insulating film is formed over the oxide semiconductor film, a metal film may be formed over the oxide insulating film. Oxygen is added to the metal film to form a metal oxide film and added also to the oxide semiconductor film or the oxide insulating film. | 2015-06-04 |
20150155313 | SEMICONDUCTOR DEVICE - A novel semiconductor device in which a metal film containing copper (Cu) is used for a wiring, a signal line, or the like in a transistor including an oxide semiconductor film is provided. The semiconductor device includes an oxide semiconductor film having conductivity on an insulating surface and a conductive film in contact with the oxide semiconductor film having conductivity. The conductive film includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). | 2015-06-04 |
20150155314 | SOLID-STATE IMAGE CAPTURE DEVICE - A semiconductor substrate is provided with a plurality of photosensitive regions on a first principal surface side. An insulating film has a third principal surface and a fourth principal surface opposed to each other, and is arranged on the semiconductor substrate so that the third principal surface is opposed to the first principal surface. A cross section parallel to a thickness direction of the semiconductor substrate, of a region corresponding to each photosensitive region in the first principal surface is a corrugated shape in which concave curves and convex curves are alternately continuous. A cross section parallel to a thickness direction of the insulating film, of a region corresponding to each photosensitive region in the third principal surface is a corrugated shape in which concave curves and convex curves are alternately continuous corresponding to the first principal surface. The fourth principal surface is flat. | 2015-06-04 |
20150155315 | METHOD FOR DRIVING PHOTOELECTRIC CONVERSION APPARATUS - In a photoelectric conversion apparatus including a plurality of pixels arranged in a matrix, each pixel including a photoelectric conversion unit, first and second holding units that hold electric charge, a first transfer unit that connects the photoelectric conversion unit and the first holding unit, a second transfer unit that connects the first and second holding units, and a third transfer unit that connects the photoelectric conversion unit and a power supply, each pixel is controlled so that the potential of the third transfer unit for electric charge held in the photoelectric conversion unit is higher than that of the first transfer unit at least during a charge accumulation period of the pixel, and thereafter, the potential of the third transfer unit is higher than that of the photoelectric conversion unit while the potentials of the first and second transfer units are lower than that of the photoelectric conversion unit. | 2015-06-04 |
20150155316 | PHOTOELECTRIC CONVERSION DEVICE AND IMAGE-PICKUP APPARATUS - In a photoelectric conversion device, groups of unit pixels are arranged in a well, where each of the unit pixels includes photoelectric conversion elements, an amplifier transistor, and transfer transistors. The photoelectric conversion device includes a line used to supply a voltage to the well, a well-contact part used to connect the well-voltage-supply line to the well, and transfer-control lines used to control the transfer transistors. The transfer-control lines are symmetrically arranged with respect to the well-voltage-supply line in respective regions of the unit-pixel groups. | 2015-06-04 |
20150155317 | SOLID-STATE IMAGING DEVICE AND DRIVING METHOD THEREFOR - A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate potential between a first power-supply potential and a second power-supply potential. | 2015-06-04 |
20150155318 | SOLID-STATE IMAGING APPARATUS AND METHOD FOR MANUFACTURING THE SOLID-STATE IMAGING APPARATUS - A solid-state imaging apparatus includes a first substrate that includes a plurality of photoelectric conversion units, a second substrate that includes at least a part of a readout circuit configured to read signals based on electric charges of the plurality of photoelectric conversion units and a peripheral circuit including a control circuit, and a wiring structure that is disposed between the first substrate and the second substrate and includes a pad portion electrically connected to the peripheral circuit via a draw-out wiring and an insulating layer. The wiring structure has, at least at a part thereof, a seal ring disposed in such a way as to surround the photoelectric conversion units and the peripheral circuit. | 2015-06-04 |
20150155319 | METHOD FOR PRODUCING AN INTEGRATED IMAGING DEVICE WITH FRONT FACE ILLUMINATION COMPRISING AT LEAST ONE METAL OPTICAL FILTER, AND CORRESPONDING DEVICE - An integrated imaging device supports front face illumination with one or more photosensitive regions formed in a substrate. A lower dielectric region is provided over the substrate, the lower dielectric region having an upper face. A metal optical filter having a metal pattern is provided on the upper face (or extending into the lower dielectric region from the upper face). An upper dielectric region is provided on top of the lower dielectric region and metal optical filter. The lower dielectric region is at least part of a pre-metal dielectric layer, and the upper dielectric region is at least part of a metallization layer. | 2015-06-04 |
20150155320 | MECHANISMS FOR FORMING IMAGE SENSOR DEVICE - Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and a photodetector in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate, and the dielectric layer has a recess aligned with the photodetector. The image sensor device further includes a filter in the recess of the dielectric layer. In addition, the image sensor device includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the filter. | 2015-06-04 |
20150155321 | SEMICONDUCTOR SENSOR DEVICE - A semiconductor sensor device is disclosed. The semiconductor sensor device includes a plurality of pixels and a phase grating structure. The phase grating structure has periodically arranged patterns and is disposed on the pixels. | 2015-06-04 |
20150155322 | IMAGE SENSOR WITH REDUCED OPTICAL PATH - Among other things, one or more image sensors and techniques for forming image sensors are provided. An image sensor comprises a photodiode array configured to detect light. The image sensor comprises an oxide grid comprising a first oxide grid portion and a second oxide grid portion. A metal grid is formed between the first oxide grid portion and the second oxide grid portion. The oxide grid and the metal grid define a filler grid. The filler grid comprises a filler grid portion, such as a color filter, that allows light to propagate through the filler gird portion to an underlying photodiode. The oxide grid and the metal grid confine or channel the light within the filler gird portion. The oxide grid and the metal grid are formed such that the filler grid provides a relatively shorter propagation path for the light, which improves light detection performance of the image sensor. | 2015-06-04 |
20150155323 | CHIP-STACKED IMAGE SENSOR HAVING HETEROGENEOUS JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING SAME - The present invention relates to a chip-stacked image sensor and to a method for manufacturing the same. More particularly, the present invention relates to a chip-stacked image sensor having a heterogeneous junction structure and to a method for manufacturing the same, in which a first semiconductor chip and a second semiconductor chip are manufactured using substrate materials suitable for the characteristics of sensors formed on each semiconductor substrate, and the semiconductor chips are stacked to form an image sensor. According to the chip-stacked image sensor having a heterogeneous junction structure and the method for manufacturing the same, the material for a first semiconductor substrate used in a first semiconductor chip and the material for a second semiconductor substrate used in a second semiconductor chip are different from each other, thus enabling characteristics of sensors formed on each semiconductor chip to be properly exhibited. | 2015-06-04 |
20150155324 | ELECTRONIC DEVICE COMPRISING A CHIP OF INTEGRATED CIRCUITS STACKED WITH AN OPTICAL PLATE - An electronic device is formed by a stack of an integrated circuit chip and an optical plate. The integrated circuit chip includes integrated circuits (such as optical circuits) formed on or in a semiconductor substrate plate. The optical integrated circuits may form an optical sensor. An electrical connection network is provided on the top side of the semiconductor substrate plate. Electrical connection lugs, which are connected to the electrical connection network through electrical connection vias, are mounted on the back side of the semiconductor substrate plate. The vias are through silicon vias situated at a distance from the periphery of the semiconductor substrate plate. The optical plate is configured to allow light radiation to pass to the optical integrated circuits. | 2015-06-04 |
20150155325 | SEMICONDUCTOR MODULE, MOS TYPE SOLID-STATE IMAGE PICKUP DEVICE, CAMERA AND MANUFACTURING METHOD OF CAMERA - A back-illuminated type MOS (metal-oxide semiconductor) solid-state image pickup device | 2015-06-04 |
20150155326 | SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF - A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes an active area on a substrate, where the active area is at least one of a p-type region or an n-type region. The substrate includes a well, where the well is a p-well when the active area is a p-type region, and the well is an n-well when the active area is an n-type region. The well includes a photodiode. The active area is connected to a voltage supply having a voltage level, such as ground. The active area on the substrate increases a distance between the photodiode and the active area, which reduces junction leakage as compared to a semiconductor arrangement where the active area is formed at least partially within the substrate. | 2015-06-04 |
20150155327 | SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE - A solid-state imaging element includes a semiconductor substrate where a plurality of photodiodes are arranged in a plane, and a separation section which separates the photodiodes, in which the separation section has a photoelectric conversion section formed by filling a material which has a high light absorption coefficient and a high quantum efficiency in trenches which are formed in the semiconductor substrate. | 2015-06-04 |
20150155328 | IMAGE SENSOR - In an image sensor, a photoelectric convertor is arranged in an active region of substrate and a floating diffusion area is arranged over the photoelectric convertor. A transfer transistor transfers the photo charges to the floating diffusion area from the photoelectric convertor and the transfer gate electrode has a narrow upper structure that extends downwards vertically from the top surface of the substrate and a broad lower structure that is connected to the upper structure and has a width greater than a width of the upper structure. A reading device is on the top surface of the substrate and detects the photo charges from the floating diffusion area. Accordingly, the effective gate length of the transfer gate electrode is increased, and thus, high resolution image data can be obtained in spite of the size reduction of the image sensor. | 2015-06-04 |
20150155329 | METHOD OF MANUFACTURING IMAGING DEVICE - One portion of a first insulator film, which is positioned on a second semiconductor region, and another portion of the first insulator film, which is positioned on a third semiconductor region, are removed, while a first portion of the first insulator film, which is positioned on a first semiconductor region is remained, one portion of a second insulator film, which is positioned on the first semiconductor region, and another portion of the second insulator film, which is positioned on the second semiconductor region, are removed, while a second portion of the second insulator film, which is positioned on the third semiconductor region is remained, and a metal film that covers the first portion, the second semiconductor region, and the second portion, and the second semiconductor region are caused to react with each other and a metal compound layer is formed. | 2015-06-04 |
20150155330 | LIGHT EMITTING DIODE PACKAGE - One embodiment comprises first and second light-emitting chips, each comprising: a package body having a cavity; first to fourth lead frames disposed inside the package body; a first semiconductor layer; an active layer; and a second semiconductor layer and emitting light of a different wavelength from each other, wherein each of the first to fourth lead frames comprises: an upper surface part exposed to the cavity; and a side surface part bent from one side portion of the upper surface part and exposed by one surface of the package body. In addition, the first light-emitting chip is disposed on the upper surface part of the first lead frame, and the second light-emitting chip is disposed on the upper surface part of the third lead frame. | 2015-06-04 |
20150155331 | METHOD OF COLLECTIVE MANUFACTURE OF LEDS AND STRUCTURE FOR COLLECTIVE MANUFACTURE OF LEDS - The disclosure relates to a method of collective manufacturing of light-emitting diode (LED) devices comprising formation of elemental structures, each comprising an n-type layer, an active layer and a p-type layer, the method comprising: —reduction of the lateral dimensions of part of each elemental LED structure; —formation of a portion of insulating material on the sides of the elemental structures; —formation of n-type electrical contact pads and p-type electrical contact pads; —deposition of a conductive material layer; on the elemental structures and polishing of the conductive material layer; and—bonding by molecular adhesion of a second substrate on the polished surface of the structure. | 2015-06-04 |
20150155332 | MAGNETIC MEMORY AND MANUFACTURING METHOD THEREOF - According to one embodiment, a magnetic memory including an isolation region with an insulator in a trench is disclosed. The isolation region defines active areas extending in a 1st direction and having 1st and 2nd active areas, an isolation region extending in a 2nd direction perpendicular to the 1st direction exists between the 1st and 2nd active areas. 1st and 2nd word lines extending in the 2nd direction are buried in a surface of semiconductor substrate. 1st and 2nd select transistors connected to the word lines are on the 1st active area. 1st and 2nd variable resistance elements connected to drain regions of the 1st and 2nd select transistors are on the 1st active area. | 2015-06-04 |
20150155333 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film. | 2015-06-04 |
20150155334 | ZnO-Based System on Glass (SOG) for Advanced Displays - A ZnO based display pixel structure that includes system-on-glass (SOG) substrates with embedded non-volatile resistive random access memory iNV-RRAM) is provided. Such pixels feature high frame rates and low power consumption. The entire SOG is based on ZnO devices. Different devices including TFT, TCO, RRAM, inverters, and shift registers are obtained through doping of different elements into selected ZnO active regions. This reduces the cost to package control circuitry onto a backplane of a display system, resulting in a low cost, light weight and uUra-thin display. | 2015-06-04 |
20150155335 | VARIABLE RESISTANCE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A variable resistance memory device includes a semiconductor substrate having a vertical transistor with a shunt gate that increases an area of a gate of the vertical transistor. | 2015-06-04 |
20150155336 | SOLID STATE DEVICES HAVING FINE PITCH STRUCTURES - In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded. | 2015-06-04 |
20150155337 | ORGANIC LIGHT-EMITTING DEVICE - The present invention provides an organic light emitting device including: a substrate; and two or more stacked light emitting elements, which comprise a first electrode, at least one intermediate electrode, a second electrode, and an organic material layer disposed between the electrodes, the stacked organic light emitting elements including a first group of electrodes electrically connected to each other such that among the electrodes, at least two electrodes, which are not adjacent to each other, become a common electric potential, and a second group of electrodes which include one electrode among electrodes which are not electrically connected to the first group of electrodes, or at least two electrodes which are not electrically connected to the first group of electrodes and are electrically connected to each other so as to be a common electric potential without being adjacent to each other, in which the stacked organic light emitting elements are disposed at an interval apart from each other on the substrate and driven by an alternating current power source such that a form, in which a first group of electrodes of one stacked organic light emitting element among the stacked organic light emitting elements are directly connected to a second group of electrodes of another stacked organic light element, is continuously repeated. | 2015-06-04 |
20150155338 | ORGANIC LIGHT EMITTING DIODE DISPLAY AND METHOD FOR MANUFACTURING THE SAME - An organic light emitting diode display includes a p-doped layer that can obtain high efficiency at low-voltage driving and low current and prevent leakage current by differentially forming the p-doped layer for each pixel. | 2015-06-04 |
20150155339 | METHOD OF MAKING ORGANIC LIGHT EMITTING DIODE ARRAY - A method of making organic light emitting diode array includes following steps. A base having a number of first electrodes on a surface of the base is provided. A first organic layer is located on the surface of the base to cover the number of first electrodes. A first organic light emitting layer is applied on the first organic layer. A template with a first patterned surface with a number of grooves with different depths is provided. The template is attached on the first organic light emitting layer and separated from each other, wherein a number of protruding structures with different heights is formed. A second organic light emitting layer is deposited on a part of the plurality of protruding structures. A second organic layer is located on the organic light emitting layer. A second electrode is applied to electrically connect to the second organic layer. | 2015-06-04 |
20150155340 | DUAL-MODE PIXELS INCLUDING EMISSIVE AND REFLECTIVE DEVICES, AND DUAL-MODE DISPLAY USING THE PIXELS - Provided is a dual-mode display including a substrate and a plurality of sub-pixels on the substrate, in which each sub-pixel includes an emissive device, a color selection reflector disposed on one side of the emissive device, and an optical shutter disposed on another side of the emissive device, wherein the emissive device includes a cathode and an anode, and the cathode and the anode include a carbon-based material including graphene sheets, graphene flakes, and graphene platelets, and a binary or ternary transparent conductive oxide including indium oxide, tin oxide, and zinc oxide. | 2015-06-04 |
20150155341 | ORGANIC ELECTRO-LUMINESCENCE DISPLAY DEVICE AND METHOD OF FABRICATING THE SAME - A first substrate provided with a plurality of pixel electrodes is prepared. A bank layer is formed so as to be placed on the periphery of each pixel electrode to define a plurality of pixel regions and contain a metal ion adsorbent. An organic electro-luminescence film is formed so as to be placed on the bank layer and the plurality of pixel electrodes and contain a metal complex which is a compound having a ligand coordinated to a metal ion. A common electrode is formed on the organic electro-luminescence film. The organic electro-luminescence film is formed such that the concentration of the metal ions is decreased above the bank layer by the metal ion adsorbent. | 2015-06-04 |
20150155342 | ORGANIC LIGHT EMITTING DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF - An organic light emitting display device and a method for manufacturing the organic light emitting display device, which includes a light emitting region and a non-light emitting region, and having an organic light emitting element including first and second electrodes disposed in the light emitting region and an organic emission layer formed between the two electrodes, a driving voltage supply line disposed in the non-light emitting region and providing a driving voltage to the first and second electrodes, and a contact part disposed in the non-light emitting region and disposed to be in contact with the first electrode to supply the driving voltage provided from the driving voltage supply line to the first electrode, wherein the contact part is formed as multiple layers patterned such that a second conductive layer covers a first conductive layer. | 2015-06-04 |
20150155343 | DISPLAY MODULE - An organic display device includes a pixel driving circuit having a thin film transistor connected to a current supply line and a capacitor. A first insulation layer, with a first electrode thereon, covers a source electrode of the transistor. The first electrode is connected to the transistor through a contact hole in the insulation layer. A second insulation layer including an aperture is formed on the first insulation layer and electrode layers. An organic light emitting layer, with a second electrode thereon is formed in the aperture and connected to the first electrode. The second insulation layer includes an inner wall at the aperture, said inner wall having a surface of a convex plane on an edge of the recessed part of the first electrode. The convex plane is located between the organic light emitting layer and the edge of the first electrode, and the second electrode is formed over plurality of pixels. | 2015-06-04 |
20150155344 | ORGANIC LIGHT EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF - Provided are an organic light emitting display (OLED) apparatus and a manufacturing method thereof. The OLED apparatus includes: a thin film transistor (TFT) array substrate including: a support substrate, including a soft material and a plurality of TFTs on the support substrate corresponding to a plurality of pixel areas, a light emitting array (LEA) including a plurality of organic light emitting devices on the TFT array substrate corresponding to the plurality of pixel areas, a sealing structure facing the TFT array substrate, the LEA interposed between the TFT array substrate and the sealing structure, and an adhesive layer between the LEA and the sealing structure to adhere the LEA to the sealing structure, wherein the sealing structure includes: a protective layer on the LEA, a sealing layer over the TFT array substrate, and a barrier layer adhering the protective layer to the sealing layer. | 2015-06-04 |
20150155345 | LIGHT-EMITTING DEVICE - In a light-emitting device, supply of current is controlled using a transistor having a normal gate electrode (a first gate electrode) and a second gate electrode for controlling threshold voltage. The light-emitting device comprises one or more switches for selecting conduction or non-conduction between the first gate electrode and a drain terminal of the transistor. When the threshold voltage of the transistor is acquired, the first gate electrode and the drain terminal of the transistor are brought into conduction with the switch, and the threshold voltage of the transistor is shifted by controlling the potential of the second gate electrode. | 2015-06-04 |
20150155346 | DISPLAY UNIT AND ELECTRONIC APPARATUS - A display unit includes a light emitting layer including a light emitting device ( | 2015-06-04 |
20150155347 | Organic Light Emitting Display Device - An organic light emitting display device is provided having first and second pixel areas. The organic light emitting display device includes a first substrate; a second substrate facing the first substrate; a bank layer on the first substrate at a boundary region between the first and second pixel areas; a light emitting layer on the first substrate within the first pixel area; a light shielding layer on the second substrate at the boundary region between the first and second pixel areas; and a color filter on the second substrate within the first pixel area. A top of the bank layer is higher than a top of the light emitting layer with respect to the first substrate, and a top of the light shielding layer is higher a top of the color filter with respect to the second substrate. | 2015-06-04 |
20150155348 | LIGHT EMITTING DEVICE - A light emitting device is provided which can prevent a change in gate voltage due to leakage or other causes and at the same time can prevent the aperture ratio from lowering. A capacitor storage is formed from a connection wiring line, an insulating film, and a capacitance wiring line. The connection wiring line is formed over a gate electrode and an active layer of a TFT of a pixel, and is connected to the active layer. The insulating film is formed on the connection wiring line. The capacitance wiring line is formed on the insulating film. This structure enables the capacitor storage to overlap the TFT, thereby increasing the capacity of the capacitor storage while keeping the aperture ratio from lowering. Accordingly, a change in gate voltage due to leakage or other causes can be avoided to prevent a change in luminance of an OLED and flickering of screen in analog driving. | 2015-06-04 |
20150155349 | METAL-INSULATOR-METAL CAPACITOR FORMATION TECHNIQUES - Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using sacrificial, self-organizing materials that effectively create a pattern in response to treatment (heat or other suitable stimulus), which is transferred to a dielectric material in which the MIM capacitor is formed. The self-organizing material may be, for example, a layer of directed self-assembly material that segregates into two alternating phases in response to heat or other stimulus, wherein one of the phases then can be selectively etched with respect to the other phase to provide the desired pattern. In another example case, the self-organizing material is a layer of material that coalesces into isolated islands when heated. As will be appreciated in light of this disclosure, the disclosed techniques can be used, for example, to increase capacitance per unit area, which can be scaled by etching deeper capacitor trenches/holes. | 2015-06-04 |
20150155350 | Resurf High Voltage Diode - A trench-isolated RESURF diode structure ( | 2015-06-04 |
20150155351 | SEMICONDUCTOR DEVICE - A semiconductor device includes a lower interlayer insulating layer, a first stopper layer, and an upper interlayer insulating layer sequentially stacked on a substrate. First and second lower conductive layers, which are laterally separated from each other, are provided in the lower interlayer insulating layer. First and second upper via plugs are connected to the first and second lower conductive layers, respectively, through the upper interlayer insulating layer and the first stopper layer. Further, between the first and second upper via plugs, at least one line-shaped shield via plug extends into the lower interlayer insulating layer through the first stopper layer. The shield via plug is in an electrically-floating state. | 2015-06-04 |
20150155352 | METHOD OF FORMING A SHALLOW TRENCH ISOLATION STRUCTURE - Embodiments of the disclosure include a shallow trench isolation (STI) structure and a method of forming the same. A trench is formed in a substrate. A silicon oxide and a silicon liner layer are formed on sidewalls and a bottom surface of the trench. A flowable silicon oxide material fills in the trench, is cured, and then is partially removed. Another silicon oxide is deposited in the trench to fill the trench. The STI structure in a fabricated device includes a bottom portion having silicon oxide and a top portion having additionally a silicon oxide liner and a silicon liner on the sidewalls. | 2015-06-04 |
20150155353 | BORDERLESS CONTACT FOR ULTRA-THIN BODY DEVICES - After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer. | 2015-06-04 |
20150155354 | NANOTUBE SEMICONDUCTOR DEVICES - Semiconductor devices are formed using a thin epitaxial layer (nanotube) formed on sidewalls of dielectric-filled trenches. In one embodiment, a semiconductor device is formed in a semiconductor layer on a semiconductor substrate of opposite conductivity type and having trenches formed therein where the trenches extend from the top surface to the bottom surface of the semiconductor layer. The semiconductor device includes a first epitaxial layer formed on sidewalls of the trenches where the first epitaxial layer is substantially charge balanced with adjacent semiconductor regions. In another embodiment, a semiconductor device is formed in a first semiconductor layer having trenches and mesas formed thereon where the trenches extend from the top surface to the bottom surface of the first semiconductor layer. The semiconductor device includes semiconductor regions formed on the bottom surface of the mesas of the first semiconductor layer. | 2015-06-04 |
20150155355 | SYSTEMS AND METHODS FOR SEMICONDUCTOR DEVICES - The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.). A semiconductor device includes a well region extending a first depth into a surface of an epitaxial semiconductor layer positioned above a drift region. The device includes a junction field-effect transistor (JFET) region positioned adjacent to the well region in the epitaxial semiconductor layer. The device also includes a trench extending a second depth into the JFET region, wherein the trench comprises a bottom and a sidewall that extends down to the bottom at an angle relative to the surface of the epitaxial semiconductor layer. | 2015-06-04 |
20150155356 | SEMICONDUCTOR LAMINATE STRUCTURE AND SEMICONDUCTOR ELEMENT - Provided is a semiconductor laminate structure including a Ga | 2015-06-04 |
20150155357 | III-Nitride Semiconductor Structures with Strain Absorbing Interlayers - There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure. | 2015-06-04 |
20150155358 | Group III-V Transistor with Semiconductor Field Plate - There are disclosed herein various implementations of a group III-V transistor with a semiconductor field plate. Such a group III-V transistor includes a group III-V heterostructure situated over a substrate and configured to produce a two-dimensional electron gas (2DEG). In addition, the group III-V transistor includes a source electrode, a drain electrode, and a gate situated over the group heterostructure. The group III-V transistor also includes an insulator layer over the group III-V heterostructure and situated between the gate and the drain electrode, and a semiconductor field plate situated between the gate and the drain electrode, over the insulator layer. | 2015-06-04 |
20150155359 | Contact Structure of Semiconductor Device - The embodiments described above provide mechanisms of forming contact structures with low resistance. A strained material stack with multiple sub-layers is used to lower the Schottky barrier height (SBH) of the conductive layers underneath the contact structures. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer, and a SiGe top layer. The GeB layer moves the Schottky barrier to an interface between GeB and a metal germanide, which greatly reduces the Schottky barrier height (SBH). The lower SBH, the Ge in the SiGe top layer forms metal germanide and high B concentration in the GeB layer help to reduce the resistance of the conductive layers underneath the contact structures. | 2015-06-04 |
20150155360 | NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME - A non-volatile memory device may include a first well of a first conductive type formed over a substrate, a second well of a second conductive type formed over the substrate to contact the first well, a trench formed over the substrate on a border formed by the contact of the first well and the second well, and a memory gate having a memory layer formed over a surface of the trench, and a gate electrode formed to fill the trench over the memory layer. | 2015-06-04 |
20150155361 | SEMICONDUCTOR DEVICES INCLUDING TRESHOLD VOLTAGE CONTROL REGIONS - A semiconductor device includes a semiconductor substrate including isolation regions defining first and second active regions having a first and second conductivity type, respectively, first threshold voltage control regions in predetermined regions of the first active region, wherein the first threshold voltage control regions have the first conductivity type and a different impurity concentration from the first active region, a first gate trench extending across the first active region, wherein portions of side bottom portions of the first gate trench adjacent to the respective isolation region are disposed at a higher level than a central bottom portion of the first gate trench, and the first threshold voltage control regions remain in the first active region under the side bottom portions of the first gate trench adjacent to the respective isolation region, and a first gate pattern. Methods of manufacturing such semiconductor devices are also provided. | 2015-06-04 |
20150155362 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device includes an oxide semiconductor; a source electrode and a drain electrode in contact with the oxide semiconductor; a gate insulating film over the oxide semiconductor, the source electrode, and the drain electrode; and a gate electrode overlapping the oxide semiconductor, part of the source electrode, and part of the drain electrode with the gate insulating film positioned therebetween. The source electrode and the drain electrode each include a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti), and the thickness of a region of the oxide semiconductor over which neither the source electrode nor the drain electrode is provided is smaller than the thicknesses of regions of the oxide semiconductor over which the source electrode and the drain electrode are provided. | 2015-06-04 |
20150155363 | SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - A new semiconductor device in which a metal film containing Cu is used for a transistor including an oxide semiconductor film, and a method for manufacturing the semiconductor device are provided. The semiconductor device includes a transistor including a first gate electrode layer, a first gate insulating film over the first gate electrode layer, an oxide semiconductor film that is provided over the first gate insulating film to overlap the first gate electrode layer, a pair of electrode layers electrically connected to the oxide semiconductor film, a second gate insulating film over the oxide semiconductor film and the pair of electrode layers, and a second gate electrode layer that is over the second gate insulating film to overlap the oxide semiconductor film. The pair of electrode layers includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). | 2015-06-04 |
20150155364 | THRESHOLD VOLTAGE ADJUSTMENT IN METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR WITH SILICON OXYNITRIDE POLYSILICON GATE STACK ON FULLY DEPLETED SILICON-ON-INSULATOR - A fully depleted silicon-on-insulator MOSFET transistor with reduced variation in threshold voltage. The substrate of the transistor is doped to form a ground plane below a buried oxide layer. A lightly doped channel is formed over the buried oxide layer. A gate dielectric of Silicon Oxynitride is formed over the channel, and a polysilicon gate is formed over the gate dielectric. The polysilicon gate is doped to have a work function not greater 4.2 electron volts for a p-type doped channel (for an n-channel MOSFET), and not less than 5.0 electron volts for an n-type doped channel (for a p-channel MOSFET). The thickness of the buried oxide layer and the channel need not be greater than 20 nanometers and 10 nanometers, respectively. | 2015-06-04 |
20150155365 | SEMICONDUCTOR DEVICE WITH PROFILED WORK-FUNCTION METAL GATE ELECTRODE AND METHOD OF MAKING - The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function meta layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode. | 2015-06-04 |
20150155366 | Techniques to Form Uniform and Stable Silicide - In one aspect, a method of fabricating a metal silicide includes the following steps. A semiconductor material selected from the group consisting of silicon and silicon germanium is provided. A metal(s) is deposited on the semiconductor material. A first anneal is performed at a temperature and for a duration sufficient to react the metal(s) with the semiconductor material to form an amorphous layer including an alloy formed from the metal(s) and the semiconductor material, wherein the temperature at which the first anneal is performed is below a temperature at which a crystalline phase of the alloy is formed. An etch is used to selectively remove unreacted portions of the metal(s). A second anneal is performed at a temperature and for a duration sufficient to crystallize the alloy thus forming the metal silicide. A device contact and a method of fabricating a FET device are also provided. | 2015-06-04 |
20150155367 | METHOD FOR FABRICATING A RECESSED CHANNEL ACCESS TRANSISTOR DEVICE - A trench extends from a main surface of a semiconductor substrate to a predetermined depth. A gate oxide layer is formed in the trench. A buried gate electrode is formed at a lower portion of the trench. The buried gate electrode is capped with a dielectric layer. A pad layer and hard mask layer are formed on the semiconductor substrate. A recess through the pad layer and hard mask layer and into the semiconductor substrate is formed on one side of the trench. A portion of the dielectric layer is revealed within the recess. The hard mask layer is then removed. An ion implantation process is performed to implant dopants on both sides of the trench, thereby forming a source doping region and a drain doping region. The source doping region has a junction depth that is deeper than that of the drain doping region. | 2015-06-04 |
20150155368 | Amorphous Silicon Thin-Film Transistors with Reduced Electrode Contact Resistivity and Methods for Forming the Same - Embodiments described herein provide amorphous silicon thin-film transistors (a-Si TFTs) and methods for forming a-Si TFTs. A substrate is provided. A gate electrode is formed above the substrate. An a-Si channel layer is formed above the gate electrode. A contact layer is formed above the a-Si channel layer. The contact layer includes titanium, zinc, arsenic, or a combination thereof. A source electrode and a drain electrode are formed above the contact layer. | 2015-06-04 |
20150155369 | MANUFACTURING METHOD OF LOW TEMPERATURE POLYCRYSTALLINE SILICON THIN FILM AND MANUFACTURING METHOD OF THIN FILM TRANSISTOR - A manufacturing method of a low temperature polycrystalline silicon thin film and a manufacturing method of a thin film transistor are provided. The manufacturing method of the low temperature polycrystalline silicon thin film comprises: forming an amorphous silicon thin film on a substrate; and performing a rapid thermal annealing (RTA) process on the amorphous silicon thin film for several times at a predetermined temperature to form the low temperature polycrystalline silicon thin film, wherein the predetermined temperature is lower than a conventional RTA crystallization temperature. | 2015-06-04 |
20150155370 | METHODS FOR DOPING FIN FIELD-EFFECT TRANSISTORS - A method of doping a FinFET includes forming a semiconductor fin on a substrate, the substrate having a first device region and a second device region. The semiconductor fin is formed on a surface of the substrate in the second device region and has a top surface and sidewalls. The first device region is covered with a hard mask and the semiconductor fin and the hard mask are exposed to a deposition process to form a dopant-rich layer having an n-type or p-type dopant on the top surface and the sidewalls of the semiconductor fin. The dopant from the dopant-rich layer is diffused into the semiconductor fin by performing an annealing process in which the first device region is free of diffusion of the diffused dopant or another dopant from the hard mask. | 2015-06-04 |
20150155371 | 3-DIMENSIONAL NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A non-volatile memory device comprising a plurality of strings each including a drain select transistor, drain-side memory cells, a pipe transistor, source-side memory cells, and a source select transistor coupled in series, wherein the plurality of strings are arranged in a first direction and a second direction, and the strings arranged in the second direction form each of string columns; a plurality of bit lines extended in the second direction and coupled to the drain select transistors of the strings included in each string column; and a plurality of source lines extended in the first direction and in common coupled to the source select transistors of strings adjacent to each other in the second direction, wherein strings included in one of the string columns are staggered in the first direction and each of the string columns are coupled to at least two of the bit lines. | 2015-06-04 |
20150155372 | METHOD AND SYSTEM FOR DOPING CONTROL IN GALLIUM NITRIDE BASED DEVICES - A method of growing a III-nitride-based epitaxial structure is disclosed. The method includes forming a GaN-based drift layer coupled to the GaN-based substrate, where forming the GaN-based drift layer comprises doping the drift layer with indium to cause the indium concentration of the drift layer to be less than about 1×10 | 2015-06-04 |
20150155373 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film. | 2015-06-04 |
20150155374 | ELECTRONIC DEVICE - An electronic device includes a semiconductor layer, a tunneling layer formed of a material including a two-dimensional (2D) material so as to directly contact a certain region of the semiconductor layer, and a metal layer formed on the tunneling layer. | 2015-06-04 |
20150155375 | GATE-CONTROLLED P-I-N SWITCH WITH A CHARGE TRAPPING MATERIAL IN THE GATE DIELECTRIC AND A SELF-DEPLETED CHANNEL - The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with a low on-state voltage drop and a low turn-off energy. In an aspect, a power semiconductor device is provided that embodies a normally off trench gate-controlled p-i-n switch with a charge trapping material in the gate dielectric and a self-depleted channel. | 2015-06-04 |
20150155376 | SILICON-COMPATIBLE GERMANIUM-BASED TRANSISTOR WITH HIGH-HOLE-MOBILITY - The present invention provides a silicon-compatible germanium-based high-hole-mobility transistor with high-hole-mobility germanium channel comprising a semiconductor material having a valence band offset instead of the conventional gate insulating film, a germanium channel region, and a quantum well formed by heterojunctions of the upper and lower portions of the germanium channel on a silicon substrate. Thus, the present invention enables to gain maximum hole mobility of the germanium channel by using the two-dimensional hole gas gathered into the quantum well for high-speed and low-power operations and device reliability improvement. | 2015-06-04 |
20150155377 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device is a half bridged field effect transistor having a monolithic chip, and includes a semiconductor substrate with a 2-dimensional electron gas layer formed therein; a drain electrode formed on the semiconductor substrate; a first gate electrode, an output electrode, a second gate electrode, and a source electrode. The method of manufacturing the semiconductor device uses a method of monolithically forming a stack structure, which implements a half bridge function, on a substrate according to semiconductor processes. | 2015-06-04 |
20150155378 | SEMICONDUCTOR DEVICE - In a semiconductor power device such as a power MOSFET having a super-junction structure in each of an active cell region and a chip peripheral region, an outer end of a surface region of a second conductivity type coupled to a main junction of the second conductivity type in a surface of a drift region of a first conductivity type and having a concentration lower than that of the main junction is located in a middle region between an outer end of the main junction and an outer end of the super-junction structure in the chip peripheral region. | 2015-06-04 |
20150155379 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench. | 2015-06-04 |
20150155380 | Manufacturing a Semiconductor Device Using Electrochemical Etching, Semiconductor Device and Super Junction Semiconductor Device - A trench is formed in a semiconductor substrate between mesas of a first conductivity type. The trench extends from a process surface down to a bottom plane. A semiconductor layer of a second, complementary conductivity type is formed on sidewalls of the trench. At least in the mesas a vertical impurity concentration profile vertical to the process surface is non-constant between the process surface and the bottom plane. A portion of the semiconductor layer in the trench is removed by electrochemical etching. Thereafter, the thickness of the recessed semiconductor layer images the vertical impurity concentration profile in the mesa. | 2015-06-04 |
20150155381 | SEMICONDUCTOR DEVICES AND FABRICATION METHOD THEREOF - A method is provided for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a gate structure; and forming offset sidewall spacers around the gate structure. The method also includes forming trenches in the semiconductor substrate at outside of the gate structure; and forming isolation layers on side surfaces of the trenches to prevent diffusions between subsequently formed doping regions. Further, the method includes removing at least portions of the offset sidewall spacers to expose portions of the surface of the semiconductor substrate between the gate structure and the trenches; and forming filling layers with a top surface higher than the surface of the semiconductor substrate by filling the trenches and covering portions of the surface of the semiconductor substrate between the trenches and the gate structure. Further, the method also includes forming doping regions configured as raised source/drain regions in the filling layers. | 2015-06-04 |
20150155382 | Well Implant Through Dummy Gate Oxide In Gate-Last Process - The present disclosure relates to methods for fabricating a field-effect transistor. The method includes performing a pocket implantation to a semiconductor substrate; thereafter forming a polysilicon layer on the semiconductor substrate; and patterning the polysilicon layer to form a polysilicon gate. | 2015-06-04 |
20150155383 | Semiconductor Device with Strained Layer - A semiconductor device and method of fabricating thereof is described that includes a substrate including at least one fin, at least one gate stack formed on a top surface of the at least one fin, a first inter-layer dielectric (ILD) layer formed on the top surface of the at least one fin, and a strained layer formed at least on a top surface of the at least one gate stack, wherein the strained layer is configured to provide a strain force to the at least one gate stack. | 2015-06-04 |
20150155384 | ENHANCED DISLOCATION STRESS TRANSISTOR - A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. | 2015-06-04 |
20150155385 | SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS - The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure. | 2015-06-04 |
20150155386 | SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURE - A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface, and the isolation structure at two sides of the gate structure has a second top surface. The first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure. | 2015-06-04 |
20150155387 | Semiconductor Device - A highly reliable semiconductor device which uses an oxide semiconductor film for a backplane is provided. A semiconductor device includes a first conductive film, a first insulating film over the first conductive film, an oxide semiconductor film which is over the first insulating film and overlaps with the first conductive film, a second insulating film over the oxide semiconductor film, and a pair of second conductive films electrically connected to the oxide semiconductor film through an opening portion included in the second insulating film. The second insulating film overlaps with a region of the oxide insulating film in which a carrier flows between the pair of second conductive films and overlaps with end portions of the oxide semiconductor film. | 2015-06-04 |
20150155388 | SEMICONDUCTOR STRUCTURE - A semiconductor device comprises a plurality of stacking blocks and a plurality of conductive lines. Each stacking blocks comprises two opposite finger VG structures. Each finger VG structure includes a staircase structure and a plurality of bit line stacks. The staircase structure is perpendicular to the bit line stacks, and the bit line stacks of the two opposite finger VG structures are arranged alternately. The conductive lines is disposed over the stacking blocks at interval The direction of the conductive lines is parallel to a direction of the bit line stacks. The conductive lines include a plurality of bit lines and a plurality of ground lines, and each stacking block includes at least one ground line. | 2015-06-04 |
20150155389 | METAL OXIDE SEMICONDUCTOR THIN FILM TRANSISTOR - A metal oxide semiconductor thin film transistor includes a source, a drain, a metal oxide semiconductor layer, a gate, a first gate insulating layer and a second gate insulating layer. The metal oxide semiconductor layer is in contact with a portion of the source and a portion of the drain. The first gate insulating layer is interposed between the metal oxide semiconductor layer and the gate and in contact with the gate. The second gate insulating layer is interposed between the metal oxide semiconductor layer and the gate and in contact with the metal oxide semiconductor layer. | 2015-06-04 |
20150155390 | MANUFACTURING METHOD OF POLYSILICON LAYER, AND POLYSILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A manufacturing method of a polysilicon layer and a manufacturing method of a polysilicon thin film transistor. The manufacturing method of the polysilicon layer includes: providing a substrate; forming a barrier layer and a buffer layer on the substrate; disposing a plurality of grooves in the buffer layer by a patterning process, and forming crystal seeds on the buffer layer; forming an amorphous silicon layer on the buffer layer provided with the grooves and on the crystal seeds; transferring the amorphous silicon layer into a polysilicon layer using a thermal treatment process. | 2015-06-04 |
20150155391 | THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) includes a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor active layer includes a first doped region as a source region, a second doped region as a drain region, an undoped region between the first and second doped regions. A third doped region is disposed between the second doped region and the undoped region. The gate electrode is insulated from the semiconductor active layer and overlaps the third doped region and the undoped region. The source electrode and the drain electrode are connected to the first and second doped regions. | 2015-06-04 |
20150155392 | SEMICONDUCTOR DEVICE - Provided is a transistor including an oxide semiconductor in a channel formation region in which the threshold voltage is controlled, which is a so-called normally-off switching element. The switching element includes a first insulating film, an oxide semiconductor layer over the first insulating film and includes a channel formation region, a second insulating film covering the oxide semiconductor layer, a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The semiconductor device further includes a first gate electrode layer overlapping the channel formation region with the first insulating film therebetween, a second gate electrode layer overlapping the channel formation region with the second insulating film therebetween, and a third gate electrode layer overlapping a side surface of the oxide semiconductor layer in a channel width direction with the second insulating film therebetween. | 2015-06-04 |
20150155393 | DISPLAY PANEL AND DISPLAY DEVICE USING THE SAME - A display panel comprising a TFT substrate, a display medium and an opposite substrate is provided. The display medium is disposed between the TFT substrate and the opposite substrate. The TFT substrate comprises a substrate, a first electrode layer, a pixel electrode layer, a first insulating layer, a second electrode layer, a second insulating layer, a channel layer and an over coating layer. The first electrode layer and the pixel electrode layer are disposed on the substrate. The first insulating layer is disposed on the first electrode layer and the pixel electrode layer. The second electrode layer is disposed on the first insulating layer. The second insulating layer is disposed on the second electrode layer. The channel layer is interposed into a first contact hole and a second contact hole to electrically connect the first electrode layer. The over coating layer is disposed on the channel layer. | 2015-06-04 |