22nd week of 2013 patent applcation highlights part 15 |
Patent application number | Title | Published |
20130134520 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Provided are a semiconductor device including a high voltage transistor and a low voltage transistor and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate including a high voltage region and a low voltage region; a high voltage transistor formed in the high voltage region and including a first active region, a first source/drain region, a first gate insulating layer, and a first gate electrode; and a low voltage transistor formed in the low voltage region and including a second active region, a second source/drain region, a second gate insulating layer, and a second gate electrode. The second source/drain region has a smaller thickness than a thickness of the first source/drain region. | 2013-05-30 |
20130134521 | SEMICONDUCTOR DEVICE - A semiconductor device is equipped with an element region, an electrode, a thermal conduction portion, and a protective membrane. The element region is equipped with a plurality of gate electrodes. The electrode is formed on a surface of the element region. The thermal conduction portion is located on a surface side of a central portion of the electrode, and is higher in thermal conductivity than the element region. The protective membrane is formed on a peripheral portion that is located on the surface side of the electrode and surrounds a periphery of the central portion. In the element region, an emitter central region that is formed on a back side of the central portion of the electrode remains on for a longer time than an emitter peripheral region that is formed on a back side of the peripheral portion of the electrode. | 2013-05-30 |
20130134522 | Hybrid Fin Field-Effect Transistors - A hybrid Fin Field-Effect Transistor (FinFET) includes a first and a second FinFET. The first FinFET includes a first channel region formed of a first semiconductor fin, and a first source region and a first drain region of a first conductivity type. The second FinFET includes a second channel region formed of a second semiconductor fin, a second source region of a second conductivity type opposite the first conductivity type, and a second drain region of the first conductivity type. The second source region and the second drain region are connected to opposite ends of the second channel region. The first and the second gate electrodes are interconnected. The first and the second source regions are electrically interconnected. The first and the second drain regions are electrically interconnected. | 2013-05-30 |
20130134523 | CMOS TRANSISTORS HAVING DIFFERENTIALLY STRESSED SPACERS - CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels. | 2013-05-30 |
20130134524 | Multi-Transistor Exposed Conductive Clip for Semiconductor Packages - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 2013-05-30 |
20130134525 | METAL-OXIDE-SEMICONDUCTOR (MOS) DEVICE AND METHOD FOR FABRICATING THE SAME - A Metal-Oxide-Semiconductor (MOS) device is disclosed. The MOS device includes a substrate, a well region formed in the substrate, and a gate located on the substrate. The MOS device also includes a first lightly-doped region arranged in the well region at a first side of the gate and overlapping with the gate, and a second lightly-doped region arranged in the well region at a second side of the gate and overlapping with the gate. Further, the MOS device includes a first heavily-doped region formed in the first lightly-doped region, and a second heavily-doped region formed in the second lightly-doped region. The MOS device also includes a first high-low-voltage gate oxide boundary arranged between the first heavily-doped region and the gate, and a second high-low-voltage gate oxide boundary arranged between the second heavily-doped region and the gate. The gate covers the first high-low-voltage gate oxide boundary and the second high-low-voltage gate oxide boundary at the first side and the second side of the gate, respectively. | 2013-05-30 |
20130134526 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench. | 2013-05-30 |
20130134527 | STRUCTURE AND METHOD TO FABRICATE A BODY CONTACT - A structure and method to fabricate a body contact on a transistor is disclosed. The method comprises forming a semiconductor structure with a transistor on a handle wafer. The structure is then inverted, and the handle wafer is removed. A silicided body contact is then formed on the transistor in the inverted position. The body contact may be connected to neighboring vias to connect the body contact to other structures or levels to form an integrated circuit. | 2013-05-30 |
20130134528 | ETCHANT-FREE METHODS OF PRODUCING A GAP BETWEEN TWO LAYERS, AND DEVICES PRODUCED THEREBY - Etchant-free methods of producing a gap between two materials are provided. Aspects of the methods include providing a structure comprising a first material and a second material, and subjecting the structure to conditions sufficient to cause a decrease in the volume of at least a portion of at least one of the first material and the second material to produce a gap between the first material and the second material. Also provided are devices produced by the methods (e.g., MEMS and NEMS devices), structures used in the methods and methods of making such structures. | 2013-05-30 |
20130134529 | ELECTRIC DEVICE AND METHOD OF MANUFACTURING THE SAME - There is provided an electric device including a base member, a beam elastically deformable to bend upward and having an outline partially defined by a slit formed in the base member, a conductive pattern provided on a top surface of the beam, a contact electrode provided above the conductive pattern, the contact electrode coming into contact with the conductive pattern, and a bridge electrode elastically deformable, the bridge electrode connecting the conductive pattern and a portion of the base member outside the outline. | 2013-05-30 |
20130134530 | Method of fabricating isolated semiconductor structures - Embodiments related to semiconductor manufacturing and semiconductor devices with semiconductor structure are described and depicted. | 2013-05-30 |
20130134531 | FULLY EMBEDDED MICROMECHANICAL DEVICE, SYSTEM ON CHIP AND METHOD FOR MANUFACTURING THE SAME - A fully embedded micromechanical device and a system on chip is manufactured on an SOI-substrate. The micromechanical device comprises a moveable component having a laterally extending upper and lower surface and vertical side surfaces. The upper surface is adjacent to an upper gap which laterally extends over at least a part of the upper surface and results from the removal of a shallow trench insulation material. The lower surface is adjacent to a lower gap which laterally extends over at least a part of the lower surface and results from the removal of the buried silicon oxide layer. The side surfaces of the movable component are adjacent to side gaps which surround at least a part of the vertical side surfaces of the moveable component and result from the removal of a deep trench insulation material. | 2013-05-30 |
20130134532 | MEMORY ELEMENT AND MEMORY APPARATUS - A memory element includes a layered structure: a memory layer having a magnetization direction changed depending on information, the magnetization direction being changed by applying a current in a lamination direction of the layered structure to record the information in the memory layer, including a first ferromagnetic layer having a magnetization direction that is inclined from a direction perpendicular to a film face, a bonding layer laminated on the first ferromagnetic layer, and a second ferromagnetic layer laminated on the bonding layer and bonded to the first ferromagnetic layer via the bonding layer, having a magnetization direction that is inclined from the direction perpendicular to the film face, a magnetization-fixed layer having a fixed magnetization direction, an intermediate layer that is provided between the memory layer and the magnetization-fixed layer, and is contacted with the first ferromagnetic layer, and a cap layer that is contacted with the second ferromagnetic layer. | 2013-05-30 |
20130134533 | MAGNETIC TUNNEL JUNCTION (MTJ) AND METHODS, AND MAGNETIC RANDOM ACCESS MEMORY (MRAM) EMPLOYING SAME - Magnetic tunnel junctions (MTJs) and methods of forming same are disclosed. A pinned layer is disposed in the MTJ such that a free layer of the MTJ can couple to a drain of an access transistor when provided in a magnetic random access memory (MRAM) bitcell. This structure alters the write current flow direction to align the write current characteristics of the MTJ with write current supply capability of an MRAM bitcell employing the MTJ. As a result, more write current can be provided to switch the MTJ from a parallel (P) to anti-parallel (AP) state. An anti-ferromagnetic material (AFM) layer is provided on the pinned layer to fix pinned layer magnetization. To provide enough area for depositing the AFM layer to secure pinned layer magnetization, a pinned layer having a pinned layer surface area greater than a free layer surface area of the free layer is provided. | 2013-05-30 |
20130134534 | Magnetoresistive Device - According to embodiments of the present invention, a magnetoresistive device having a magnetic junction is provided. The magnetic junction includes at least one fixed magnetic layer structure having a fixed magnetization orientation; and at least two free magnetic layer structures, each of the at least two free magnetic layer structures having a variable magnetization orientation; wherein the at least one fixed magnetic layer structure overlaps with the at least two free magnetic layer structures such that a current flow is possible through the magnetic junction; and wherein the at least one fixed magnetic layer structure and the at least two free magnetic layer structures are respectively configured such that the fixed magnetization orientation and the variable magnetization orientation are oriented in a direction substantially perpendicular to a plane defined by an interface between the at least one fixed magnetic layer structure and either one of the at least two free magnetic layer structures. | 2013-05-30 |
20130134535 | BACKSIDE IMAGE SENSOR PIXEL WITH SILICON MICROLENSES AND METAL REFLECTOR - A backside illumination (BSI) image sensor pixel that includes microlenses with elevated refractive indices is provided. The image sensor pixel may include a photodiode formed in a silicon substrate, a first microlens formed in a back surface of the substrate, a second microlens formed over a front surface of the substrate, a dielectric stack formed on the front surface of the substrate, and a reflective structure formed in the dielectric stack above the second microlens. The first microlens may be fabricated by forming shallow trench isolation structures in the back surface. The second microlens may be fabricated by depositing polysilicon on the front substrate of the substrate. The first microlens may serve to concentrate light towards the photodiode, whereas the second microlens may serve to collimate light that traverses through the substrate so that light exiting the second microlens will reflect off the reflective structure and back into the photodiode. | 2013-05-30 |
20130134536 | SOLID-STATE IMAGING DEVICE AND METHOD OF MANUFACTURING THE SOLID-STATE IMAGING DEVICE - A solid-state imaging device in which a plurality of pixels are two-dimensionally arranged, the solid-state imaging device includes: a silicon layer; a plurality of photodiodes which are formed in the silicon layer to correspond to the pixels and generate signal charges by performing photoelectric conversion on incident light; and a plurality of color filters formed above the silicon layer to correspond to the plurality of the pixels, wherein a protrusion is formed in a region on a side of the silicon layer between adjacent ones of the color filters, the protrusion having a refractive index lower than refractive indices of the adjacent ones of the color filters and, each of the color filters is in contact with the adjacent ones of the color filters, above the protrusion. | 2013-05-30 |
20130134537 | SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREFOR, ELECTRONIC APPARATUS, AND COMPOSITION FOR SOLID-STATE IMAGING DEVICE - Disclosed herein is a solid-state imaging device including a plurality of pixels arranged two-dimensionally, wherein the pixels each have at least a planarizing film formed on the upper side of a photoelectric conversion element, a filter formed on the upper side of the planarizing film, and a microlens formed on the upper side of the filter. The filters of a part of the pixels are each a color filter permitting transmission therethrough of light of a predetermined color component, whereas the filters of another part of the pixels are each a white filter permitting transmission therethrough of light in the whole visible spectral range. The refractive indices of the white filter, the microlens and the planarizing film are in the following relationship: (Refractive index of white filter)≧(Refractive index of microlens)>(Refractive index of planarizing film). | 2013-05-30 |
20130134538 | SOLID-STATE IMAGING DEVICE - According to an embodiment, an image sensor is provided for photoelectrically converting blue light, green light and red light for each pixel. A photoelectric conversion layer for red light is provided having a light absorption coefficient that is different than the light absorption coefficient of the photoelectric conversion layers for blue light and green light. | 2013-05-30 |
20130134539 | Photodiode Comprising Polarizer - A photodiode includes a photosensitive area and a polarizing grating located in front of the photosensitive area. The polarizing grating is formed by a plurality of galvanically conducting filaments. | 2013-05-30 |
20130134540 | SOLID-STATE IMAGING DEVICE, METHOD FOR MANUFACTURING SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS - The present invention relates to a solid-state imaging device having good focusing properties, a method for manufacturing such a solid-state imaging device, and an electronic apparatus. The solid-state imaging device has a semiconductor substrate | 2013-05-30 |
20130134541 | Metal Shielding Layer in Backside Illumination Image Sensor Chips and Methods for Forming the Same - A device includes a semiconductor substrate having a front side and a backside. A photo-sensitive device is disposed at a surface of the semiconductor substrate, wherein the photo-sensitive device is configured to receive a light signal from the backside of the semiconductor substrate, and convert the light signal to an electrical signal. An amorphous-like adhesion layer is disposed on the backside of the semiconductor substrate. The amorphous-like adhesion layer includes a compound of nitrogen and a metal. A metal shielding layer is disposed on the backside of the semiconductor substrate and contacting the amorphous-like adhesion layer. | 2013-05-30 |
20130134542 | DARK CURRENT REDUCTION FOR BACK SIDE ILLUMINATED IMAGE SENSOR - Provided is a semiconductor image sensor device that includes a non-scribe-line region and a scribe-line region. The image sensor device includes a first substrate portion disposed in the non-scribe-line region. The first substrate portion contains a doped radiation-sensing region. The image sensor device includes a second substrate portion disposed in the scribe-line region. The second substrate portion has the same material composition as the first substrate portion. Also provided is a method of fabricating an image sensor device. The method includes forming a plurality of radiation-sensing regions in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. The method includes forming an opening in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The method includes filling the opening with an organic material. | 2013-05-30 |
20130134543 | CMOS Image Sensor Big Via Bonding Pad Application for AICu Process - An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension. | 2013-05-30 |
20130134544 | ENERGY HARVESTING IN INTEGRATED CIRCUIT PACKAGES - An energy harvesting integrated circuit (IC) includes electrical connectors, each having a portion of a first material and a portion of a second material. The first and the second materials have a thermoelectric potential. The IC includes a trace of the first material coupled to the first material of each electrical connector, and a trace of the second material coupled to the second material of each electrical connector and the first trace. A portion of the second trace extends away from a portion of the first trace. The IC has charge storing elements coupled to the first and/or second traces. The first material and the second material are heated to create an electron flow from a thermal gradient between a first zone of the heated first and second materials and a second zone of the first and the second materials away from the first zone. | 2013-05-30 |
20130134545 | SELF-LIMITING OXYGEN SEAL FOR HIGH-K DIELECTRIC, RELATED METHOD AND DESIGN STRUCTURE - A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region. | 2013-05-30 |
20130134546 | HIGH DENSITY MULTI-ELECTRODE ARRAY - A method includes forming one or more trenches in a substrate; lining the one or more trenches with a dielectric liner; filling the one or more trenches with a conductive electrode to form one or more trench electrodes; forming a transistor layer on the substrate; connecting each of the one or more trench electrodes to at least one access transistor in the transistor layer; and thinning the substrate to expose at least a portion of each of the trench electrodes. | 2013-05-30 |
20130134547 | METHOD FOR FABRICATING A LOCALLY PASSIVATED GERMANIUM-ON-INSULATOR SUBSTRATE - The invention relates to a method for fabricating a locally passivated germanium-on-insulator substrate wherein, in order to achieve good electron mobility, nitridized regions are provided at localised positions. Nitridizing is achieved using a plasma treatment. The resulting substrates also form part of the invention. | 2013-05-30 |
20130134548 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In a semiconductor device, the thickness of an insulating film formed in a through hole is reduced, while an annular groove having an insulating material embedded therein is provided so as to ensure a sufficient total thickness of the insulator, whereby a through silicon via is provided with an insulating ring which is improved in both processability and functionality. | 2013-05-30 |
20130134549 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device which eliminates the need for high fillability through a simple process and a method for manufacturing the same. A high breakdown voltage lateral MOS transistor including a source region and a drain region is completed on a surface of a semiconductor substrate. A trench which surrounds the transistor when seen in a plan view is made in the surface of the semiconductor substrate. An insulating film is formed over the transistor and in the trench so as to cover the transistor and form an air-gap space in the trench. Contact holes which reach the source region and drain region of the transistor respectively are made in an interlayer insulating film. | 2013-05-30 |
20130134550 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device according to the present invention includes a p-type semiconductor substrate, a first n-type collector diffusion layer formed in the p-type semiconductor substrate, a deep trench formed in the p-type semiconductor substrate so as to surround the first n-type collector diffusion layer, a p-type channel stopper layer formed beneath the deep trench, and an n-type diffusion layer formed between a sidewall of the deep trench and the first n-type collector diffusion layer. | 2013-05-30 |
20130134551 | INDUCTORS IN SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - An inductor in a semiconductor device may include a first interconnection line on a substrate; a second interconnection line on the first interconnection line; first and second common interconnection lines on the second interconnection line; a first via connecting a first end of the first interconnection line to a first end of the first common interconnection line; a second via connecting a second end of the first interconnection line to a second end of the second common interconnection line; a third via connecting a first end of the second interconnection line to the first end of the first common interconnection line; and a fourth via connecting a second end of the second interconnection line to the second end of the second common interconnection line. The first and second interconnection lines and the first and second common interconnection lines may extend in a direction parallel to a surface of the substrate. | 2013-05-30 |
20130134552 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series. | 2013-05-30 |
20130134553 | INTERPOSER AND SEMICONDUCTOR PACKAGE WITH NOISE SUPPRESSION FEATURES - Interposer and semiconductor package embodiments provide for the isolation and suppression of electronic noise such as EM emissions in the semiconductor package. The interposer includes shield structures in various embodiments, the shield structures blocking the electrical noise from the noise source, from other electrical signals or devices. The shields include solid structures and some embodiments and decoupling capacitors in other embodiments. The coupling structures includes multiple rows of solder balls included in strips that couple the components and surround and contain the source of electrical noise. | 2013-05-30 |
20130134554 | VERTICAL CAPACITORS AND METHODS OF FORMING THE SAME - Provided are vertical capacitors and methods of forming the same. The formation of the vertical capacitor may include forming input and output electrodes on a top surface of a substrate, etching a bottom surface of the substrate to form via electrodes, and then, forming a dielectric layer between the via electrodes. As a result, a vertical capacitor with high capacitance can be provided in a small region of the substrate. | 2013-05-30 |
20130134555 | CAPACITIVE ELEMENT - A capacitive element includes: an upper electrode; a lower electrode; and a dielectric layer that is disposed between the upper electrode and the lower electrode, and includes a first film, a second film and a third film which are made of any one of silicon nitride and aluminum oxide and laminated from a side of the lower electrode in order, a composition ratio of any one of silicon and aluminum in each of the first film and the third film being larger than a corresponding composition ratio in the second film. | 2013-05-30 |
20130134556 | SEMICONDUCTOR DEVICE - This semiconductor device according to the present invention includes a plurality of cylindrical lower electrodes aligned densely in a memory array region; a plate-like support which is contacted on the side surface of the cylindrical lower electrodes, and links to support the plurality of the cylindrical lower electrodes; a pore portion provided in the plate-like support; a dielectric film covering the entire surface of the cylindrical lower electrodes and the plate-like support in which the pore portion is formed; and an upper electrode formed on the surface of the dielectric film, wherein the boundary length of the part on the side surface of the cylindrical lower electrode which is exposed on the pore portion is shorter than the boundary length of the part on the side surface of the cylindrical lower electrode which is not exposed on the pore portion. | 2013-05-30 |
20130134557 | METAL-INSULATOR-METAL CAPACITORS WITH HIGH CAPACITANCE DENSITY - Metal-insulator-metal (MIM) capacitors and methods for fabricating MIM capacitors. The MIM capacitor includes an interlayer dielectric (ILD) layer with apertures each bounded by a plurality of sidewalls and each extending from the top surface of the ILD layer into the first interlayer dielectric layer. A layer stack, which is disposed on the sidewalls of the apertures and the top surface of the ILD layer, includes a bottom conductive electrode, a top conductive electrode, and a capacitor dielectric between the bottom and top conductive electrodes. | 2013-05-30 |
20130134558 | Self Aligned Silicide Device Fabrication - A method for fabricating a device includes forming a silicide layer on a substrate, forming a conductive layer over exposed portions of the substrate and the silicide layer, patterning and removing exposed portions of the conductive layer and the silicide layer with a first process, and patterning and removing exposed portions of the conductive layer with a second process. | 2013-05-30 |
20130134559 | Chip-on-Wafer Structures and Methods for Forming the Same - A package component includes a substrate, wherein the substrate has a front surface and a back surface over the front surface. A through-via penetrates through the substrate. A conductive feature is disposed over the back surface of the substrate and electrically coupled to the through-via. A first dielectric pattern forms a ring covering edge portions of the conductive feature. An Under-Bump-Metallurgy (UBM) is disposed over and in contact with a center portion of the conductive feature. A polymer contacts a sidewall of the substrate. A second dielectric pattern is disposed over and aligned to the polymer. The first and the second dielectric patterns are formed of a same dielectric material, and are disposed at substantially a same level. | 2013-05-30 |
20130134560 | SEMICONDUCTOR STRUCTURE COMPRISING MOISTURE BARRIER AND CONDUCTIVE REDISTRIBUTION LAYER - A semiconductor structure includes semiconductor devices on a substrate, a moisture barrier on the substrate surrounding the semiconductor devices, and a metal conductive redistribution layer formed over the moisture barrier. The metal conductive redistribution layer and the moisture barrier define a closed compartment containing the semiconductor devices. | 2013-05-30 |
20130134561 | BACKSIDE THERMAL PATTERNING OF BURIED OXIDE (BOX) - The dominant source of thermal resistance for silicon photonic devices patterned on SOI wafers is the buried oxide layer. To ensure efficient thermally driven silicon devices there is a need for a large thermal resistance. This is in contrast to temperature sensitive components need to have low thermal resistance in order to reduce their temperature to ensure good performance. Embodiments comprise etching the back of an SOI wafer to expose the buried oxide layer and depositing an additional layer of silicon oxide to increase the local thermal resistance. Thus, embodiments provide the ability to tailor the thermal resistance across the wafer or die depending on the device being fabricated. | 2013-05-30 |
20130134562 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR BURIED LAYER - The present disclosure provides a semiconductor device and a method for fabricating a semiconductor buried layer. The method includes: preparing a substrate which includes a first oxide layer; forming a first buried layer region in the surface of the substrate by using a photoresist layer with a first buried layer region pattern as a mask, in which a doping state of the first buried layer region is different from a doping state of other region of the substrate; forming a second oxide layer on the surface of the substrate and the first buried layer region; and forming a second buried layer region in the surface of the substrate through self alignment process by using the second oxide layer as a mask. The method disclosed by the present disclosure reduces the complexity of the buried layer procedures and the cost thereof, as well as the probability of crystal defects. | 2013-05-30 |
20130134563 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 2013-05-30 |
20130134564 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME - A semiconductor device implemented with structures to suppress leakage current generation during operation and a method of making the same is provided. The semiconductor device includes a semiconductor substrate of first conductivity type, a second insulation film, which has at least one aperture between first and second apertures, formed on top of a first insulation film. The semiconductor device layer structure accommodates tensile stress differences between device layers to suppress lattice dislocation defects during device manufacturing and thus improves device reliability and performance. | 2013-05-30 |
20130134565 | SYSTEM-IN-PACKAGE MODULE AND METHOD OF FABRICATING THE SAME - A method of fabricating a system-in-package (SiP) module is provided, which includes: providing a substrate having a plurality of scribe lines formed thereon, forming ground pads and ground vias along the scribe lines, disposing at least one electronic component on the substrate, forming on the substrate an encapsulant for encapsulating the electronic component, cutting the substrate along the scribe lines so as to expose the ground vias, and forming a shielding layer on the encapsulant and the ground vias to thereby obtain a plurality of SiP modules. Therefore, electromagnetic radiation interferences are avoided and the design complexity and fabrication cost are reduced. | 2013-05-30 |
20130134566 | STRUCTURE OF VERY HIGH INSERTION LOSS OF THE SUBSTRATE NOISE DECOUPLING - A structure includes a substrate comprising a region having a circuit or device which is sensitive to electrical noise. Additionally, the structure includes a first isolation structure extending through an entire thickness of the substrate and surrounding the region and a second isolation structure extending through the entire thickness of the substrate and surrounding the region. | 2013-05-30 |
20130134567 | LEAD FRAME AND SEMICONDUCTOR PACKAGE STRUCTURE THEREOF - The present invention relates to the field of semiconductor package structures, and more specifically to a lead frame and a semiconductor package structure thereof. In one embodiment, a lead frame can include a plurality of parallel-arrayed lead fingers with a plurality of grooves situated on surfaces of the lead fingers, where the depths of the grooves can be smaller than the thickness of the lead fingers. In one embodiment, a flip chip semiconductor package structure can include a chip, a group of bumps, and the above-described lead frame. The first surfaces of the bumps can be coupled to the front surface of the chip, and the second surfaces of the bumps can be coupled to the upper surface of the lead frame. | 2013-05-30 |
20130134568 | LEAD FRAME AND FLIP CHIP PACKAGE DEVICE THEREOF - The present invention relates to the field of semiconductor chip packages, and more specifically to a lead frame and flip chip package device thereof. In one embodiment, a lead frame for electrically connecting a chip to outside leads, can include a plurality of lead fingers, where each of the plurality of lead fingers comprises a plurality of outburst regions extending from an edge thereof. In one embodiment, a flip chip package device can include: a chip and a plurality of solder bumps, where one surface of the chip is connected to a first surface of each of the plurality of solder bumps; and the lead frame, where second surfaces of each of the plurality solder bumps are connected with corresponding outburst regions of the lead frame to connect the chip to the lead frame through the solder bumps. | 2013-05-30 |
20130134569 | SEMICONDUCTOR PACKAGE - Disclosed herein is a semiconductor package. | 2013-05-30 |
20130134570 | Sealed Body, Light-Emitting Module and Method of Manufacturing Sealed Body - A sealed body in which sealing is uniformly performed is provided. A light-emitting module in which sealing is uniformly performed is provided. A method of manufacturing the sealed body in which sealing is uniformly performed is provided. The sealed body comprises a first substrate alternately provided with a high-reflectivity region with respect to the energy ray and a low-reflectivity region with respect to the energy ray so as to overlap with a sealant surrounding a sealed object, and a second substrate capable of transmitting the energy ray. The sealed object is sealed between the first substrate and the second substrate by heating the sealant with irradiation with the energy ray through the second substrate. | 2013-05-30 |
20130134571 | POWER MODULE PACKAGE - Disclosed herein is a power module package including: a first heat dissipation plate including a first flow path, a second flow path, and a third flow path which are sequentially formed, the first flow path and the third flow path being formed to have a step therebetween; and a second heat dissipation plate formed under the first heat dissipation plate, having one face and the other face, having a semiconductor device mounting groove formed in the one face thereof, and including a fourth flow path having one end connected to the second flow path and the other end connected to the third flow path, wherein a cooling material introduced through the first flow path is distributed to the third flow path and the fourth flow path based on the second flow path. | 2013-05-30 |
20130134572 | SEMICONDUCTOR DEVICE INCLUDING CLADDED BASE PLATE - A semiconductor device includes a semiconductor chip joined with a substrate and a base plate joined with the substrate. The base plate includes a first metal layer clad to a second metal layer. The second metal layer is deformed to provide a pin-fin or fin cooling structure. The second metal layer has a sub-layer that has no pins and no pin-fins. The first metal layer has a first thickness and the sub-layer has a second thickness. The ratio between the first thickness and the second thickness is at least 4:1. | 2013-05-30 |
20130134573 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - This application relates to a semiconductor device comprising a semiconductor chip, a molded body covering the semiconductor chip, wherein the molded body comprises an array of molded structure elements, and first solder elements engaged with the molded structure elements. | 2013-05-30 |
20130134574 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a semiconductor element placed over a substrate, a heat conducting material placed over the semiconductor element, and a radiator placed over the heat conducting material. The radiator has a plurality of projections which are arranged outside a region opposite to the semiconductor element and which protrude toward the substrate. Even if the heat conducting material flows out from over the semiconductor element at fabrication time, the heat conducting material which flows out is made by the plurality of projections to adhere to and spread along the radiator. As a result, the outflow or scattering of the heat conducting material toward the substrate or an electric trouble caused by it is prevented. | 2013-05-30 |
20130134575 | PACKAGED DIE FOR HEAT DISSIPATION AND METHOD THEREFOR - A heat spreader die holder that covers at least 50% of both major sides of a semiconductor die. The heat spreader die holder includes at least one opening. The heat spreader die holder is attached to a substrate. Electrically conductive structures of the die are electrically coupled to electrically conductive structures of the substrate. | 2013-05-30 |
20130134576 | SEMICONDUCTOR APPARATUS, SEMICONDUCTOR-APPARATUS MANUFACTURING METHOD AND ELECTRONIC EQUIPMENT - A method for manufacturing the semiconductor apparatus includes an anchor process of forming a barrier metal film and carrying out physical etching making use of sputter gas. The anchor process is carried out at the same time on a wire connected to the lower portion of a first aperture serving as a penetration connection hole and a wire connected to the lower portion of a second aperture serving as a connection hole having an aspect ratio different from the aspect ratio of the penetration connection hole. The first and second apertures are apertures created on a semiconductor substrate obtained by bonding first and second semiconductor substrates to each other. The present technology can be applied to the semiconductor apparatus such as a solid-state imaging apparatus. | 2013-05-30 |
20130134577 | RIBBON BONDING IN AN ELECTRONIC PACKAGE - A flexible conductive ribbon is ultrasonically bonded to the surface of a die and terminals from a lead frame of a package. Multiple ribbons and/or multiple bonded areas provide various benefits, such as high current capability, reduced spreading resistance, reliable bonds due to large contact areas, lower cost and higher throughput due to less areas to bond and test. | 2013-05-30 |
20130134578 | DEVICE HAVING MULTIPLE WIRE BONDS FOR A BOND AREA AND METHODS THEREOF - Wire bonds are formed at an integrated circuit device so that multiple wires are bonded to a single bond pad. In a particular embodiment, the multiple wires are bonded by first applying a stud bump to the pad and successively bonding each of the wires to the stud bump. Another stud bump can be placed over the bonded wires to provide additional connection security. | 2013-05-30 |
20130134579 | Structure for High-Speed Signal Integrity in Semiconductor Package with Single-Metal-Layer Substrate - A semiconductor chip ( | 2013-05-30 |
20130134580 | Semiconductor Device and Method of Forming RDL Under Bump for Electrical Connection to Enclosed Bump - A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. A first conductive layer is formed over a surface of the wafer. A first insulating layer is formed over the surface of the wafer and first conductive layer. A second conductive layer has first and second segments formed over the first insulating layer. A second insulating layer is formed over the first insulating layer and second conductive layer. A UBM layer is formed over the second insulating layer and the first segment of the second conductive layer. A first bump is formed over the UBM layer. The first bump is electrically connected to the second segment and electrically isolated from the first segment of the second conductive layer. A second bump is formed over the surface of the wafer and electrically connected to the first segment of the second conductive layer. | 2013-05-30 |
20130134581 | PLANARIZED BUMPS FOR UNDERFILL CONTROL - The mechanisms for forming bump structures reduce variation of standoffs between chips and package substrates. By planarizing the solder layer on bump structures on chips and/or substrates after plating, the heights of bump structures are controlled to minimize variation due to within die and within wafer locations, pattern density, die size, and process variation. As a result, the standoffs between chips and substrates are controlled to be more uniform. Consequently, underfill quality is improved. | 2013-05-30 |
20130134582 | NOVEL BUMP STRUCTURES FOR MULTI-CHIP PACKAGING - The mechanisms for forming a multi-chip package described enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package. | 2013-05-30 |
20130134583 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - In one embodiment, a semiconductor device includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first and second semiconductor chips are electrically connected via first bump connection parts. Stopper projections and bonding projections are provided at least one of the first and second semiconductor chips. The stopper projections are in contact with the other of the first and second semiconductor chips in an unbonded state. The bonding projections are bonded to the first and second semiconductor chips. | 2013-05-30 |
20130134584 | SEMICONDUCTOR DEVICE HAVING WIRING PAD AND WIRING FORMED ON THE SAME WIRING LAYER - Disclosed herein is a device that includes a first wiring provided as a first-level wiring layer and elongated in a first direction; and a first wiring pad provided as the first-level wiring layer, the first wiring pad being rectangular and including a first side edge that is elongated in the first direction and a second side edge that is elongated in a second direction crossing to the first direction, the first side edge being greater in length than the second side edge, the first wiring pad being greater in length in the second direction than the first wiring. | 2013-05-30 |
20130134585 | INTEGRATED CIRCUIT ASSEMBLY AND METHOD OF MAKING - An integrated circuit assembly includes an insulating layer having a having a first surface and a second surface. A first active layer contacts the first surface of the insulating layer. A metal bond pad is electrically connected to the first active layer and formed on the second surface of the insulating layer. A substrate having a first surface and a second surface, with a second active layer formed in the first surface, is provided such that the first active layer is coupled to the second surface of the substrate. | 2013-05-30 |
20130134586 | Semiconductor Device Having Vertically Offset Bond on Trace Interconnects on Recessed and Raised Bond Fingers - A semiconductor device includes a substrate, a first recessed conductive layer embedded and recessed into a first surface of the substrate, and a first raised conductive layer disposed above the first surface. A first vertical offset exists between an upper surface of the first recessed conductive layer and an upper surface of the first raised conductive layer. The device includes a second recessed conductive layer embedded and recessed into a second surface of the substrate. The second surface of the substrate is opposite the first surface. The device includes a second raised conductive layer disposed beneath the second surface and an interconnect structure disposed on the first recessed and raised conductive layers and the second recessed and raised conductive layers. A second vertical offset exists between a lower surface of the second recessed conductive layer and a lower surface of the second recessed conductive layer. | 2013-05-30 |
20130134587 | MICROELECTRONIC PACKAGE WITH SELF-HEATING INTERCONNECT - A microelectronic package is provided. The microelectronic package includes a substrate having a plurality of solder bumps disposed on a top side of the substrate anda die disposed adjacent to the top side of the substrate. The die includes a plurality of glassy metal bumps disposed on a bottom side of the die wherein the plurality of glassy metal bumps are to melt the plurality of solder bumps to form a liquid solder layer. The liquid solder layer is to attach the die with the substrate. | 2013-05-30 |
20130134588 | Package-On-Package (PoP) Structure and Method - Package-On-Package (PoP) structures and methods of forming PoP structures are disclosed. According to an embodiment, a structure comprises a first substrate, stud bulbs, a die, a second substrate, and electrical connectors. The stud bulbs are coupled to a first surface of the first substrate. The die is attached to the first surface of the first substrate. The electrical connectors are coupled to the second substrate, and respective ones of the electrical connectors are coupled to respective ones of the stud bulbs. | 2013-05-30 |
20130134589 | CHIP-PACKAGE AND A METHOD FOR FORMING A CHIP-PACKAGE - A chip-package includes a chip-carrier configured to carry a chip, the chip arranged over a chip-carrier side, wherein the chip-carrier side is configured in electrical connection with a chip back side; an insulation material including: a first insulation portion formed over a first chip lateral side; a second insulation portion formed over a second chip lateral side, wherein the first chip lateral side and the second chip lateral side each abuts opposite edges of the chip back side; and a third insulation portion formed over at least part of a chip front side, the chip front side including one or more electrical contacts formed within the chip front side; wherein at least part of the first insulation portion is arranged over the chip-carrier side and wherein the first insulation portion is configured to extend in a direction perpendicular to the first chip lateral side further than the chip-carrier. | 2013-05-30 |
20130134590 | FORMATION OF AIR GAP WITH PROTECTION OF METAL LINES - A microelectronic substrate which includes a dielectric layer overlying a semiconductor region of a substrate, the dielectric layer having an exposed top surface; a plurality of metal lines of a first metal disposed within the dielectric layer, each metal line having edges and a surface exposed at the top surface of the dielectric layer; a dielectric cap layer having a first portion overlying the surfaces of the metal lines and a second portion overlying the dielectric layer between the metal lines, the first portion has a first height above the surface of the dielectric layer, and the second portion has a second height above the surface of the dielectric layer, the second height being greater than the first height; and an air gap disposed between the metal lines, the air gap underlying the second portion of the cap layer. | 2013-05-30 |
20130134591 | Bonding Material for Semiconductor Devices - A semiconductor device is provided which has internal bonds which do not melt at the time of mounting on a substrate. A bonding material is used for internal bonding of the semiconductor device. The bonding material is obtained by filling the pores of a porous metal body having a mesh-like structure and covering the surface thereof with Sn or an Sn-based solder alloy. | 2013-05-30 |
20130134592 | WIRE AND SEMICONDUCTOR DEVICE - A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other. | 2013-05-30 |
20130134593 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR ELEMENT - A method for manufacturing a semiconductor device includes preparing a semiconductor element including electrode pads laid out along the periphery of the semiconductor element in a tetragonal frame-shaped array to form a line of electrode pads along each side of the semiconductor element, preparing a wiring substrate including connection pads corresponding to the electrode pads, applying solder including a bulging central portion on an upper surface of each connection pad, forming pillar-shaped electrode terminals on the electrode pads so that each electrode terminal has an axis separated from a peak of the bulging central portion of the solder on the corresponding connection pad in a longitudinal direction of the corresponding connection pad, and electrically connecting the electrode terminals with the solder to the connection pad. | 2013-05-30 |
20130134594 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor element on which electrode pads are laid out. A wiring substrate includes connecting pads respectively arranged in correspondence with the electrode pads. Pillar-shaped electrode terminals are respectively formed on the electrode pads of the semiconductor element. A solder joint electrically connects a distal portion of each electrode terminal and the corresponding connecting pad on the wiring substrate. Each electrode terminal includes a basal portion, which is connected to the corresponding electrode pad, and a guide, which is formed in the distal portion. The guide has a smaller cross-sectional area than the basal portion as viewed from above. The guide has a circumference and the basal portion has a circumference that is partially flush with the circumference of the guide. The guide is formed to guide solder toward the circumference of the guide. | 2013-05-30 |
20130134595 | METHODS AND APPARATUS TO IMPROVE RELIABILITY OF ISOLATED VIAS - A method for increasing metal density around selected vias in a semiconductor device is provided. The semiconductor device includes a plurality of vias. The method includes: generating a layout database for the semiconductor device; identifying isolated vias of the plurality of vias; selecting the isolated vias; defining a zone around each of the selected isolated vias; and increasing area of a metal layer which is above the selected isolated via and which encloses the selected isolated via within each zone to achieve a target metal density within the zone. The method improves reliability of the semiconductor device by allowing moisture to vent from around the vias. | 2013-05-30 |
20130134596 | Wafer Level Semiconductor Package - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 2013-05-30 |
20130134597 | CHIP ON FILM, AND METHOD OF MANUFACTURE THEREOF - A chip on film includes a plastic film approximately rectangular in flat view, a designated wiring pattern having approximately rectangular electrodes arrayed longitudinally formed on a mounting surface of the plastic film, and an LSI chip mounted on the mounting surface of the plastic film and connected to the designated wiring pattern. At least one cutout part is formed on each short side of the approximate rectangle of the plastic film. | 2013-05-30 |
20130134598 | Semiconductor Device and Method of Forming a Power MOSFET With Interconnect Structure to Achieve Lower RDSON - A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure. | 2013-05-30 |
20130134599 | METHOD AND STRUCTURE OF INTEGRATED MICRO ELECTRO-MECHANICAL SYSTEMS AND ELECTRONIC DEVICES USING EDGE BOND PADS - A monolithic integrated electronic device includes a substrate having a surface region and one or more integrated micro electro-mechanical systems and electronic devices provided on a first region overlying the surface region. Each of the integrated micro electro-mechanical systems and electronic devices has one or more contact regions. The first region has a first surface region. One or more trench structures are disposed within one or more portions of the first region. A passivation material overlies the first region and the one or more trench structures. A conduction material overlies the passivation material, the one or more trench structures, and one or more of the contact regions. The device also has one or more edge bond pad structures within a vicinity of the one or more bond pad structures, which are formed by a singulation process within a vicinity of the one or more bond pad structures. | 2013-05-30 |
20130134600 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device and method for manufacturing the same. The semiconductor device includes a substrate, a dielectric layer, a metal layer, an interconnection metal and an insulation circular layer. The substrate has at least one through hole. The dielectric layer is disposed adjacent to the substrate. The metal layer is disposed adjacent to the dielectric layer. The interconnection metal is disposed in the at least one through hole. An insulation circular layer surrounds the interconnection metal, wherein the insulation layer has an upper surface and the upper surface contacts the dielectric layer. Whereby, the metal layer can be electrically connected to another surface of the substrate through the interconnection metal. | 2013-05-30 |
20130134601 | SEMICONDUCTOR DEVICE HAVING SHIELDED CONDUCTIVE VIAS AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a semiconductor device having a shielding layer and a method for making the same. The semiconductor device includes a substrate, an inner metal layer, a shielding layer, an insulation material, a metal layer, a passivation layer and a redistribution layer. The inner metal layer is disposed in a through hole of the substrate. The shielding layer surrounds the inner annular metal. The insulation material is disposed between the inner metal layer and the shielding layer. The metal layer is disposed on a surface of the substrate, contacts the shielding layer and does not contact the inner metal layer. The redistribution layer is disposed in an opening of the passivation layer so as to contact the inner metal layer. | 2013-05-30 |
20130134602 | FLIP CHIP PACKAGE FOR DRAM WITH TWO UNDERFILL MATERIALS - A microelectronic package can include a substrate having a first surface and a plurality of substrate contacts at the first surface and a microelectronic element having a front surface and contacts arranged within a contact-bearing region of the front surface. The contacts of the microelectronic element can face the substrate contacts and can be joined thereto. An underfill can be disposed between the substrate first surface and the contact-bearing region of the front surface of the microelectronic element. The underfill can reinforce the joints between the contacts and the substrate contacts. A joining material can bond the substrate first surface with the front surface of the microelectronic element. The joining material can have a Young's modulus less than 75% of a Young's modulus of the underfill. | 2013-05-30 |
20130134603 | Semiconductor Devices Including Protected Barrier Layers - Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern. | 2013-05-30 |
20130134604 | METHOD FOR CREATING AND PACKAGING THREE DIMENSIONAL STACKS OF BIOCHIPS CONTAINING MICROELECTRO-MECHANICAL SYSTEMS - Systems and methods of the present disclosure provide for three-dimensional stacks of microelectromechanical (MEMS) systems, such as sensors. The stacks may be encapsulated and sealed, and can be positioned within biological tissue, for example to monitor biological signals within the volume of the sensor, provide stimulating signals to a brain, and so forth. | 2013-05-30 |
20130134605 | SEMICONDUCTOR ASSEMBLIES, STACKED SEMICONDUCTOR DEVICES, AND METHODS OF MANUFACTURING SEMICONDUCTOR ASSEMBLIES AND STACKED SEMICONDUCTOR DEVICES - Stacked semiconductor devices, semiconductor assemblies, methods of manufacturing stacked semiconductor devices, and methods of manufacturing semiconductor assemblies. One embodiment of a semiconductor assembly comprises a thinned semiconductor wafer having an active side releaseably attached to a temporary carrier, a back side, and a plurality of first dies at the active side. The individual first dies have an integrated circuit, first through die interconnects electrically connected to the integrated circuit, and interconnect contacts exposed at the back side of the wafer. The assembly further includes a plurality of separate second dies attached to corresponding first dies on a front side, wherein the individual second dies have integrated circuits, through die interconnects electrically connected to the integrated circuits and contact points at a back side, and wherein the individual second dies have a thickness of approximately less than 100 microns. | 2013-05-30 |
20130134606 | SEMICONDUCTOR PACKAGES - A semiconductor package may include a substrate including a substrate pad on a top surface thereof; at least one semiconductor chip including a connection terminal electrically connected to the substrate on an active surface thereof, and mounted on the substrate; a heat release pattern formed between the substrate and the at least one semiconductor chip and configured to generate heat; and underfill resin underfilled between the substrate and the at least one semiconductor chip and comprising fillers. A semiconductor package may include a substrate including a substrate pad on a top surface thereof and a first heat release pattern configured to generate heat, and a semiconductor chip including a bonding pad formed on an active surface facing the substrate and a second heat release pattern configured to generate heat. | 2013-05-30 |
20130134607 | INTERPOSER FOR STACKED SEMICONDUCTOR DEVICES - A semiconductor device is disclosed, comprising a substrate having at least one substrate bonding pad. A plurality of semiconductor dies are stacked on the substrate. Each semiconductor die has at least one die bonding pad located on an active surface of the die. A plurality of interposers are each mounted on a corresponding one of the semiconductor dies. Each interposer has an aperture formed therethrough in alignment with the at least one die bonding pad. An electrical connection between the at least one die bonding pad and the at least one substrate bonding pad is formed at least in part by the interposer. The electrical connection includes at least one wire bond. | 2013-05-30 |
20130134608 | FUNCTIONAL PARTICLE, FUNCTIONAL PARTICLE GROUP, FILLER, RESIN COMPOSITION FOR ELECTRONIC COMPONENT, ELECTRONIC COMPONENT AND SEMICONDUCTOR DEVICE - A functional particle ( | 2013-05-30 |
20130134609 | Curable Organopolysiloxane Composition And Optical Semiconductor Device - A curable organopolysiloxane composition that can be used as a sealant or a bonding agent for optical semiconductor elements and comprises at least the following components: (A) an alkenyl-containing organopolysiloxane that comprises constituent (A-1) of an average compositional formula and constituent (A-2) of an average compositional formula; (B) an organopolysiloxane that contains silicon-bonded hydrogen atoms and comprises a constituent (B-1) containing at least 0.5 wt. % of silicon-bonded hydrogen atoms and represented by an average molecular formula, constituent (B-2) containing at least 0.5 wt. % of silicon-bonded hydrogen atoms and represented by an average compositional formula, and, if necessary, constituent (B-3) of an average molecular formula; and (C) a hydrosilylation-reaction catalyst. The composition can form a cured body that possesses long-lasting properties of light transmittance and bondability, and relatively high hardness. | 2013-05-30 |
20130134610 | EPOXY RESIN COMPOSITION AND SEMICONDUCTOR DEVICE - An epoxy resin composition for encapsulating a semiconductor chip according to this invention comprises (A) a crystalline epoxy resin, (B) a phenol resin represented by general formula (1): | 2013-05-30 |
20130134611 | FREE-FLOATING WEIGHTED SHIELD FOR PREVENTING SUNLIGHT EXPOSURE AND ALGAE GROWTH IN A COOLING TOWER BASIN - A non-chemical device and method prevents the growth of algae in a cooling tower basin. Cooling tower basins can experience algae growth when exposed to sunlight. This algae growth is typically controlled with chemicals (algaecides). Based on the chemical composition of the algaecides, adverse and/or counter-productive reactions may be experienced, resulting in adverse and/or counter-productive consequences. Further, algaecides are toxic and may be discharged into sanitary waste streams when treated cooling tower water is released. In addition, when algaecide treatment levels fall below effective levels, algae will return, requiring on-going dosing of algaecide into the cooling tower water to maintain control of algae. The device can create a block to prevent sunlight from reaching the cooling tower basin water. Since algae growth requires sunlight, by blocking the sunlight, algae growth can be prevented. | 2013-05-30 |
20130134612 | SYSTEM AND METHOD FOR FRAGMENTATION AND DISPERSAL OF A COMPRESSED GAS BODY - A method for fragmenting a bubble of compressed gas released from a compressed gas reservoir situated at a depth under a water surface. The method comprises maintaining a grid disposed between the reservoir and the water surface to fragment the bubble into a plurality of fragmented bubble portions, the grid allowing passage therethrough of the fragmented bubble portions of the body of compressed gas generally along a travel path. | 2013-05-30 |
20130134613 | SPHERICAL POWDER AND ITS PREPARATION - A spherical tungsten carbide powder is characterized by that the material has a microhardness higher than 3600 kgf/mm | 2013-05-30 |
20130134614 | Artificial Stone and Method of Making Same - A method of forming a lightweight artificial stone comprises sizing an existing rock to a first set of dimensions and compensating for shrinkage of moldable cement and expanded glass mixture, squaring the existing rock at least once, laying out at least one of the existing rock, forming a mold of the existing rock, removing the existing rock from the mold, filling the mold with the moldable cement and expanded glass mixture, forming at least one dimensionally accurate stone. | 2013-05-30 |
20130134615 | AUTOMATED GUSSET INFLATION SYSTEM AND METHOD - The invention is directed to a method and apparatus for maintaining the inflation level of a bubble formed by nips in a moving roll of tubular film, to form a gusset in a final product produced from the film. | 2013-05-30 |
20130134616 | IMPRINT APPARATUS, IMPRINT METHOD, AND ARTICLE MANUFACTURING METHOD - The present invention provides an imprint apparatus for performing an imprint process by which an imprint material on a substrate is molded by using a mold having a pattern region on which a pattern is formed, thereby transferring the pattern onto the substrate, including a detector configured to detect marks formed in each of a plurality of shot regions on the substrate, a deformation unit configured to deform the pattern region, and a controller configured to control the imprint process. | 2013-05-30 |
20130134617 | FLEXIBLE PIPE - Apparatus and methods are disclosed relating to flexible pipe and composite tape. Flexible pipe body for a flexible pipe comprises an internal pressure sheath and at least one armour layer over the sheath comprising a wound tape of composite material. A method for manufacturing a composite tape is disclosed making use of a pultrusion process. | 2013-05-30 |
20130134618 | PROCESS FOR PRODUCING A MOLDED PRODUCT - There is described a process for producing a molded product. The process comprises the steps of: (i) dispensing a molding material on a first molding belt comprising a first polymer layer; (ii) contacting the molding material with a second molding belt comprising a second polymer layer; and (iii) shaping the molding material between the first molding belt and the second molding belt to produce the molded product. A system for producing a molded product is also described. | 2013-05-30 |
20130134619 | BATCH MIXER WITH PLUNGER - A batch mixer is equipped with a plunger for pushing material from the batch mixer. The batch mixer includes a mixer tank structured to accommodate material. The mixer further includes a mixer head comprising at least one blade structured to blend the material within the mixer tank. The mixer further includes a plunger mechanism structured to push the blended material directly from the mixer tank. | 2013-05-30 |