22nd week of 2014 patent applcation highlights part 19 |
Patent application number | Title | Published |
20140145726 | INSULATION DETECTION CIRCUIT AND METHOD THEREOF - An insulation detection circuit suitable for detecting an insulation status between a high voltage power and a low voltage power of a vehicle is disclosed. The circuit includes a first energy storage unit, a second energy storage unit, a constant current unit, and a detection unit. The first energy storage unit is coupled to the high voltage power. The second energy storage unit is coupled between the first energy storage unit and the low voltage power. The constant current unit is coupled between the first energy storage unit and the second energy storage unit. The detection unit is coupled to the second energy storage unit for detecting a current change of the second energy storage unit. When the detection unit detects that current flowing through the second energy storage unit is smaller than a predetermined value, a detection signal representing that the insulation status is abnormal is outputted. | 2014-05-29 |
20140145727 | GROUND FAULT DETECTION CIRCUIT AND GROUND FAULT DETECTION APPARATUS - A ground fault detection circuit may include a switch circuit that connects or disconnects a path between a bus bar connected to a secondary battery and a ground potential section; an I/V conversion resistance element for detecting a ground fault of the bus bar based on an electric current flowing through the path; and a resistance element connected in series to the I/V conversion resistance element. | 2014-05-29 |
20140145728 | METHOD AND SYSTEM FOR DETECTING A SHORT CIRCUIT AFFECTING A SENSOR - A method of detecting a short circuit affecting a sensor, at least one terminal of the sensor being connected to a bias resistor, includes: applying to at least one bias resistor at least one test bias voltage having at least one predefined characteristic that is different from a corresponding characteristic of a nominal bias voltage of the resistor; measuring a resulting differential voltage across the terminals of the sensor; and as a function of at least one characteristic of the measured differential voltage corresponding to the predefined characteristic of the test bias voltages, determining whether the sensor presents a short circuit. | 2014-05-29 |
20140145729 | LOW FREQUENCY IMPEDANCE MEASUREMENT WITH SOURCE MEASURE UNITS - A method for measuring the impedance of a DUT having a capacitance of less than 1 pF includes applying a voltage or current signal to the DUT, the voltage or current signal including an AC component having a non-zero frequency of less than 1 kHz; monitoring a current or voltage signal, respectively, through the DUT in response to the voltage or current signal; digitizing the voltage signal and the current signal synchronously; and calculating the impedance from the digitized voltage and current signals. | 2014-05-29 |
20140145730 | DEVICE FOR THE CONTACTLESS DETERMINATION OF AN ELECTRICAL POTENTIAL OF AN OBJECT, CURRENT PROBE, AND METHOD - A device for the contactless determination of an electrical potential of an object, has an electrode and a potential controller which is electrically connected to the electrode. The potential controller changes a reference potential applied to the electrode to a final value in such a way that an electric field between the object and the electrode disappears at the final value if the electrode is located at a distance from the object. The electrical potential is determined from the final value. | 2014-05-29 |
20140145731 | Method For Producing A Capacitive Contact Sensor And Capacitive Contact Sensor - A method for producing a capacitive contact sensor and a capacitive contact sensor having a carrier plate made of plastic are described. The front surface of the sensor initiates a switching process when contacted, and the rear surface of the sensor has one or more capacitive sensor electrodes disposed thereon and connected via conductors to analysis electronics. The regions on the front surface of the carrier plate opposite the sensor electrodes thereby form contact zones. A plastic film supporting the sensor electrodes and conductors is placed on a first side wall of a cavity of an injection molding tool, wherein the sensor electrodes face the first side wall, and then a polycarbonate forming the carrier plate is injected into the cavity on the side of the plastic film facing away from the sensor electrodes. The cavity is then expanded, forming a gap on the side facing away from the plastic film and the gap is injected with a further plastic reacting with the polycarbonate in the contact region and forming a scratchproof coating. | 2014-05-29 |
20140145732 | DEVICE FOR GENERATING AN ALTERNATING VOLTAGE DIFFERENCE BETWEEN THE REFERENCE POTENTIALS OF ELECTRONIC SYSTEMS - The present invention relates to a device for generating an alternating voltage difference between a first and second reference potential. The device comprises: an oscillator electrically referenced to the first reference potential; and a voltage follower/amplifier device electrically referenced to the second reference potential and having an input connected to the oscillator and an output connected to the first reference potential such that it can impose an alternating voltage difference, which depends on the signal generated by the oscillator, between said first and second reference potentials. The invention also relates to a system that uses the device and to a method for generating an alternating voltage difference between a first and second reference potential. | 2014-05-29 |
20140145733 | PROXIMITY SWITCH ASSEMBLY AND ACTIVATION METHOD HAVING VIRTUAL BUTTON MODE - A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. The control circuitry controls the activation field of each proximity switch to sense activation, monitors signals indicative of the activation field, and determines a first stable signal amplitude and a subsequent second signal amplitude, and generates an activation output when the second stable signal amplitude exceeds the first stable amplitude by a known amount. | 2014-05-29 |
20140145734 | Capacitor Sensing Circuit - The present invention provides a capacitor sensing circuit, comprising a driving unit, a switching unit, a differential integrator circuit, and a post-processing circuit. The driving unit is for providing driving signals and timing required by the capacitor sensing circuit, the switching unit switches signals according to two inverting timings, φ | 2014-05-29 |
20140145735 | ULTRA-COMPACT, PASSIVE, VARACTOR-BASED WIRELESS SENSOR USING QUANTUM CAPACITANCE EFFECT IN GRAPHENE - An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer. | 2014-05-29 |
20140145736 | SELECTIVE NANOSCALE ASYMMETRIC GAS SENSORS - A selective nanoscale asymmetric gas sensor is disclosed, the sensor including a first electrode having a Schottky-type contact to a nanoengineered transducer with a barrier height between energy levels of the first electrode and the nanoengineered transducer; and a second electrode having an Ohmic contact to the nanoengineered transducer with a smaller or no barrier height than the first electrode. The first electrode can be palladium and the second electrode can be gold. | 2014-05-29 |
20140145737 | METHOD FOR CORRECTING THE VOLTAGE MEASURED ACROSS THE TERMINALS OF A SENSOR - A method for correcting measurement of a voltage across output terminals of a sensor, the sensor configured to be assimilated with an assembly including a generator and a series resistance, each of the output terminals being respectively connected to a pull up/down resistor. The method includes: evaluating the series resistance of the sensor, including measuring first and second voltages across the output terminals when first and second bias voltages are applied on each pull up/down resistor; evaluating the series resistance from the first and second voltages; and correcting, from the series resistance, a voltage measured across the output terminals of the sensor to infer therefrom a corresponding voltage generated by the generator. | 2014-05-29 |
20140145738 | DIGITALLY DISPLAYING INSPECTION SYSTEM FOR ESD PROTECTION CHIP - The present invention provides a digitally displaying inspection system for ESD protection chip, which includes an LVDS connector, a display system, first, second, and the third data lines, a power supply, and a resistor. The first, second, and third data lines each have an end electrically connected to the LVDS connector and an opposite end electrically connected to the display system. The display system includes a logic operation module and a digital display module electrically connected to the logic operation module. The logic operation module is electrically connected to the first, second, and third data lines. When an ESD protection chip is electrically connected to the LVDS connector, the logic operation module samples signals on the first, second, and third data lines and drive, after carrying out logic operations, the digital display module to display character signs, which can identify if the ESD protection chip is incorrectly connected. | 2014-05-29 |
20140145739 | DISPLAY PANEL AND METHOD FOR TESTING DISPLAY PANEL - A display panel including a display part including a plurality of sub-pixels configured to display a plurality of colors, and a plurality of data lines connected with the sub-pixels; a first test part configured to supply a test signal to (2K−1)th data lines (‘K’ is an integer above 0) by each color for the sub-pixels among the plurality of data lines; and a second test part configured to supply a test signal to 2Kth data lines by each color for the sub-pixels among the plurality of data lines when the first test part supplies the test signal. Further, a polarity of the test signal supplied by the second test part is opposite to a polarity of the test signal supplied by the first test part. | 2014-05-29 |
20140145740 | TESTING DEVICE - A testing device comprises a first probe member, a second probe member, and an insulation member. The first probe member comprises a tip portion for contacting a device being tested. The second probe member also comprises a tip portion for contacting the device being tested. The insulation member is located at or can be moved to a location between the tip portions of the first and second probe members. | 2014-05-29 |
20140145741 | PROBE CARD AND INSPECTION DEVICE - A probe card comes in touch with a test object to perform an inspection. The probe card contains: a probe substrate provided with a plurality of probes on the first surface and a plurality of anchor receiving portions on the second surface; and a supporting body disposed to support the periphery of the probe substrate, with at least a plurality of anchor receiving portions located within a probe existence region being arranged regularly and at an equal distance from each other on the second surface of the probe substrate. | 2014-05-29 |
20140145742 | PROBE APPARATUS AND TEST APPARATUS - A probe apparatus providing an electrical connection between a device under test and a test apparatus body, comprising a device-side terminal unit including a flexible sheet and device-side connection terminals passing through the sheet and connected to the device under test; an intermediate substrate provided on the test apparatus body side of the device-side terminal unit and including device-side intermediate electrodes electrically connected to the device-side connection terminals and tester-side intermediate electrodes electrically connected to the test apparatus body; a tester-side substrate that is provided on the test apparatus body side of the intermediate substrate and includes, on the intermediate substrate side thereof, tester-side electrodes electrically connected to the test apparatus body; and a contact section provided between the intermediate substrate and the tester-side substrate and including first pins connected to the tester-side intermediate electrodes and second pins connected to the tester-side electrodes. | 2014-05-29 |
20140145743 | MODULAR PROBER AND METHOD FOR OPERATING SAME - The invention relates to a prober for checking and testing electronic semiconductor components and methods of using the same. The prober comprises at least two checking units, each of which is equipped with a chuck, probes, and a positioning unit, and each of which is assigned to a machine control system and a process control system. The prober further comprises a loading unit for automatically loading both testing units and an additional loader for manually loading at least one of the testing units, a user interface, and a module control system for controlling the process control systems and/or the machine control systems and the loading unit. The user interface can optionally be connected to at least one of the process control systems or the module control system by means of a switching device of the prober. | 2014-05-29 |
20140145744 | DISPLAY PANEL AND TESTING METHOD THEREOF - A display panel and a testing method of the display panel are provided. The display panel has a display region and a non-display region and includes a first substrate, a second substrate, and a display medium. The display panel further includes scan lines, data lines, pixel units, at least one testing line, and at least one testing pad. The scan lines and the data lines are located on the first substrate within the display region. The pixel units are located on the first substrate within the display region. Each pixel unit electrically connects one of the scan lines and one of the data lines. The testing line is located on the first substrate within the non-display region, crosses over the scan lines, and is insulated from the scan lines. The testing pad is located on the first substrate within the non-display region and electrically connected to the testing line. | 2014-05-29 |
20140145745 | TEST SYSTEM FOR TESTING A CMOS IMAGE SENSOR AND A DRIVING METHOD THEREOF - A test system including a test device configured to transmit an input signal and a control signal to at least one complementary metal-oxide semiconductor (CMOS) image sensor via a probe card, and an interface board configured to map the probe card and the test device. The interface board includes an output receiver configured to receive an image signal from the at least one CMOS image sensor and transform the image signal into image data. | 2014-05-29 |
20140145746 | TESTING DEVICE - A testing device has plural pin electronics substrates and a control substrate. The control substrate includes a first instruction code memory storing an instruction code, a first program counter incrementing a count in synchronization with a clock, a code analysis circuit analyzing the instruction code read from the first instruction code memory in accordance with a counter value, and a control data output control circuit outputting control data for controlling the pin electronics substrates in accordance with the instruction code. Each pin electronics substrate includes a first pin memory storing pin data, a second program counter incrementing a count in synchronization with the clock, and a pin data output control circuit adjusting, based on control data, the count value of the second program counter and outputting pin data read from the first pin memory, the pin data being dependent on the count value of the second program counter. | 2014-05-29 |
20140145747 | LIGHT ACTIVATED TEST CONNECTIONS - A test circuit including a light activated test connection in a semiconductor device is provided. The light activated test connection is electrically conductive during a test of the semiconductor device and is electrically non-conductive after the test. | 2014-05-29 |
20140145748 | Method and Device for Controlling the Latency of Electronic Circuits - A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open. | 2014-05-29 |
20140145749 | METHOD AND APPARATUS OF RFID TAG CONTACTLESS TESTING - A semiconductor wafer includes a plurality of dies. Each of the plurality of dies includes a radio frequency identification (RFID) tag circuit and a coil. The RFID tag circuit includes a tag core, an RF front-end circuit, an ID decoder, a comparator and conductive line for a unique ID. The RF front-end circuit is configured to receive electromagnetic signals through the coil in each of the plurality of dies and to convert the received electromagnetic signals into commands. The ID decoder is configured to receive the commands and to generate an expect ID. The comparator is configured to compare the unique ID with the expect ID to generate a comparison result. The comparison result is arranged to decide if the tag core is configured to receive commands. | 2014-05-29 |
20140145750 | CIRCUITS FOR SELF-RECONFIGURATION OR INTRINSIC FUNCTIONAL CHANGES OF CHIPS BEFORE VS. AFTER STACKING - A method and system for testing one or more semiconductor structures, for example, chips or wafers, in a three-dimensional stack. The method and system includes controlling a logic signal of a first circuit in a first chip or wafer connected to a supply voltage to indicate a first state during pre-assembly testing of the first chip or wafer. The method and system further includes controlling the logic signal to indicate a second state when the first circuit is connected to a second circuit of a second chip or wafer resulting in a combined circuit. The combined circuit is in a three-dimensional chip or wafer stack during post-assembly testing of the three-dimensional chip or wafer stack. | 2014-05-29 |
20140145751 | ELECTRONIC DEVICE FOR IMPLEMENTING DIGITAL FUNCTIONS THROUGH MOLECULAR FUNCTIONAL ELEMENTS - An electronic device for implementing digital functions comprising a first and a second electrode regions, separated by an interposing region comprising a dielectric region, is described. The first and the second electrode regions comprise at least one first electrode and at least one second electrode, respectively, configured to generate in the interposing region an electric field depending on an electric potential difference applied thereto. In the interposing region, a molecular layer is comprised, which is composed of a plurality of molecules, each being capable of assuming one or more states, in a controllable manner, depending on a sensed electric field. The dielectric region has a spatially variable dielectric profile, to determine a respective spatially variable field profile of the sensed electric field at the molecular layer. | 2014-05-29 |
20140145752 | ANTI-DISASSEMBLING DEVICE FOR ELECTRONIC PRODUCTS - An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled. | 2014-05-29 |
20140145753 | THROUGH SILICON VIA REPAIR CIRCUIT OF SEMICONDUCTOR APPARATUS - A through silicon via (TSV) repair circuit of a semiconductor apparatus is provided. The TSV repair circuit includes a first chip, at least one second chip, at least two TSVs, at least two data path circuits, and an output logic circuit. Each data path circuit includes an input driving circuit, a short-circuit detection circuit, a bias circuit, and a leakage current cancellation circuit. The input driving circuit transforms an input signal into a pending signal and transmits the pending signal to a first terminal of the corresponding TSV. The short-circuit detection circuit detects a short circuit between the corresponding TSV and a silicon substrate according to the input signal and the first terminal of the TSV and generates a short-circuit detection output signal. The leakage current cancellation circuit prevents a leakage current produced by a first level voltage from entering the silicon substrate according to the short-circuit detection output signal. | 2014-05-29 |
20140145754 | INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF - An integrated circuit of a multiple die package structure having a plurality of semiconductor devices, each of the plurality of semiconductor devices may include an active termination circuit configured to perform an active termination operation to the semiconductor device, and to be turned off in a disable state of an active termination setting code, a multiple die package information transfer unit configured to transfer a multiple die package information signal, and a compulsory termination unit configured to selectively convert the active termination setting code into the disable state in response to the multiple die package information signal. | 2014-05-29 |
20140145755 | INTEGRATED CIRCUIT - An integrated circuit capable of improving all factors, which are area, cost, logic change function, operating frequency, flexibility, through-put and power consumption, and a reconfigurable processor capable of changing an instruction function are provided. Unit cells, each having four-input and two-output, are arranged in a brick manner to constitute a reconfigurable array. Based on selection information, A/L selection and B/R selection are performed. Based on configuration information, an output of logical operation on inputs being A/L, B, B/R and A, and a non-reversed/revered inputs are outputted to an adjacent unit cell unit cell. | 2014-05-29 |
20140145756 | MEMORY INTERFACE CIRCUITRY WITH IMPROVED TIMING MARGINS - Integrated circuits may include memory interface circuitry that communicates with memory. The memory interface circuitry may include latch circuitry that receives a data strobe enable signal from the memory controller and latches the data strobe enable signal using a data strobe signal received from the memory. The integrated circuit may include logic circuitry that gates the data strobe signal using the latched data strobe enable signal. The logic circuitry may pass the data strobe signal in response to activation of the latched data strobe enable signal. The integrated circuit may include counter circuitry that monitors the gated data strobe signal. The counter circuitry may monitor the gated data strobe signal by counting pulses in the gated data strobe signal to produce a counter value. When the counter value reaches a target value, the logic circuitry may block the data strobe signal from passing to the memory controller. | 2014-05-29 |
20140145757 | THREE DIMENSIONAL INTEGRATED CIRCUIT CONNECTION STRUCTURE AND METHOD - An integrated circuit die stack comprises a first die and a second die connected to each other. Each of the first and second dies comprise a functional circuitry, a plurality of first contacts on a first surface of the respective die, a plurality of second contacts on a second surface of the respective die, and a programmable array coupled to the functional circuitry and the plurality of first and second contacts. The programmable array includes a plurality of programmable connection elements in the first and second dies. The programmable connection elements are programmed to bypass one of the first and second dies. | 2014-05-29 |
20140145758 | APPARATUS FOR AUTOMATICALLY CONFIGURED INTERFACE AND ASSOCIATED METHODS - An integrated circuit (IC) includes a first circuit implemented using programmable circuitry of the IC, and a second circuit implemented using hardened circuitry of the IC. The IC further includes a configurable interface circuit to couple the first circuit to the second circuit using ready/valid signaling with a configurable ready-latency value. | 2014-05-29 |
20140145759 | SYSTEMS AND METHODS FOR PREVENTING SATURATION OF ANALOG INTEGRATOR OUTPUT - Systems and methods for preventing saturation of analog integrator outputs are provided. Applications of the systems and methods in hybrid analog-digital integrators are also provided. Exemplary systems include two switches, one operational amplifier, one capacitor C, four gain blocks, three comparators, one XOR gate, one OR gate, one T flip-flop, and one digital counter. | 2014-05-29 |
20140145760 | High-Speed Low Power Stacked Transceiver - A transceiver includes a transmitter and receiver that form a series current path between two power-supply nodes. Powering both the transmitter and receiver with the same supply current saves power. The transmitter functions as a resistive load for the receiver, and thus performs useful work with power that would otherwise be dissipated as waste heat. | 2014-05-29 |
20140145761 | LOW-POWER DUAL-EDGE-TRIGGERED STORAGE CELL WITH SCAN TEST SUPPORT AND CLOCK GATING CIRCUIT THEREFORE - A storage cell having a pulse generator and a storage element is proposed. The storage element input is connected to receive a data input signal. The storage element output is connected to provide a data output signal. The storage element is operable in one of a data retention state and a data transfer state in response to a storage control signal received from the pulse generator. The pulse generator is connected to receive a clock signal with rising and falling clock signal edges and is adapted to provide control pulses in the storage control signal. Each control pulse has a leading edge and a trailing edge. The control pulses have a polarity suited to invoke the data transfer state on their leading edges. The novel feature is that the pulse generator is adapted to initiate a rising-edge control pulse when receiving a rising clock signal edge and to initiate a falling-edge control pulse when receiving a falling clock signal edge. In this way, a dual-edge-triggered flip-flop may be made using only combinatorial logic circuitry and one level- or single-edge-triggered storage element. The storage cell has low power consumption, facilitates scan testing and can be used by existing design tools and test equipment. | 2014-05-29 |
20140145762 | POWER SUPPLY SENSING CIRCUITS IN INTEGRATED CIRCUITS - Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit. | 2014-05-29 |
20140145763 | GATE DRIVING CIRCUIT - A gate driving circuit for driving an insulated gate switching element, including a gate charging circuit configured to charge gate capacitance of the insulated gate switching element, and a gate discharging circuit that is connected in series with the gate charging circuit and configured to discharge a charge of the gate capacitance. The gate charging circuit includes a first p-channel metal oxide semiconductor field effect transistor (MOSFET), and a first hybrid normally-on enhancement MOSFET insertion (NOEMI) circuit connected in series with a drain of the first p-channel MOSFET. The gate discharging circuit includes a first n-channel MOSFET, and a second hybrid NOEMI circuit connected in series with a drain of the first n-channel MOSFET. | 2014-05-29 |
20140145764 | MULTI-PHASE CLOCK GENERATION CIRCUIT - A multi-phase clock generation circuit includes a first clock buffer unit configured to invert and buffer a first internal clock and a second internal clock in response to an external clock, and to generate a third internal clock and a fourth internal clock, and a second clock buffer unit configured to invert and buffer the third internal clock and the fourth internal clock in response to the external clock, and to generate the first internal clock and the second internal clock. | 2014-05-29 |
20140145765 | VOLTAGE RAMP-UP PROTECTION - Systems and methods for voltage ramp-up protection. In an illustrative, non-limiting embodiment, a method may include monitoring at least one of a first node or a second node, the first node configured to receive a first voltage greater than a second voltage present at a second node, and, in response to a slew rate of the first voltage creating a sneak condition between the first node and the second node, counteracting the sneak condition. For example, the sneak condition may favor an excess current to flow from the first node to the second node. In some cases, counteracting the sneak condition may include maintaining the second voltage below at or below a predetermined value. | 2014-05-29 |
20140145766 | INITIALIZATION CIRCUIT - An initialization circuit includes an initialization control unit configured to generate a start pulse, which is generated after a power supply voltage reaches a target voltage level, in response to the power supply voltage and an external command, and an initialization execution unit configured to extract a fuse signal from a programmed fuse in response to the start pulse, and to output stored data when an external address corresponding to the fuse signal is inputted. | 2014-05-29 |
20140145767 | PULSE GENERATION CIRCUITS IN INTEGRATED CIRCUITS - Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit. | 2014-05-29 |
20140145768 | CORRECTING FOR OFFSET-ERRORS IN A PLL/DLL - The main feedback loop of a PLL/DLL receives a reference clock and an output clock as inputs, and operates to achieve one or both of a phase and a frequency lock of the output clock with respect to the reference clock. The PLL/DLL includes an RS-latch connected to receive the output clock and the reference clock. The RS-Latch generates a digital output representing a phase difference between the reference clock and the output clock. A correction block in the PLL/DLL receives the digital output and adjusts an electrical characteristic of the main feedback loop by a value that is based on a polarity of the digital output. Effects of offset-errors in the PLL/DLL are thereby minimized or corrected for. | 2014-05-29 |
20140145769 | Phase Locked Loop with Self-Calibration - A method for self-calibrating a phase locked loop (PLL) includes setting a frequency range setting of a voltage controlled oscillator (VCO) to a first digital value for a first output frequency. A first difference is measured between a reference frequency and a feedback frequency resulting from the first output frequency. The frequency range setting is set to an inverted digital value of the first digital value for a second output frequency. A second difference is measured between the reference frequency and the feedback frequency resulting from the second output frequency. A value of the frequency range setting is selected based on the first difference and the second difference. | 2014-05-29 |
20140145770 | CLOCK GENERATION CIRCUIT - A clock generation circuit comprises an internal clock signal source providing an internal clock signal and a synchronization device for synchronization the internal clock signal with a reference clock signal provided externally from the clock generation circuit. The synchronization device comprises n delay locked loop circuits, n being an integer greater than 1, each delay locked loop circuit having a clock input for receiving the internal clock signal and a clock output for providing an output clock signal with an individual phase shift that is adjustable. The synchronization device further comprises a multiplexer having n inputs and an output wherein each of the n inputs is connected to an output of one of the n delay locked loops and a control circuit. The control circuit is adapted to adjust at least one of the delay locked loop circuits for providing an individual phase shift according to a current phase shift and to select that input of the multiplexer that receives an output clock signal of the adjusted delay locked loop circuit that is synchronized in frequency and phase with the reference clock signal, wherein the output of the multiplexer provides that output clock signal as synchronized clock signal, and wherein the control circuit is adapted to toggle between the n delay locked loop circuits, in a way that the phase of the internal clock signal is successively shifted according to the current phase shift between the internal clock signal and the reference clock signal. | 2014-05-29 |
20140145771 | DELAY LOCKED LOOP - A circuit includes a delay line and a delay locked loop. The circuit is configured to receive a delay parameter and a clock signal. The delay locked loop is configured to generate a pair of control codes based on a frequency of the clock signal and a frequency of an oscillator of the delay locked loop. The delay locked loop is configured to determine a difference between the frequency of the clock signal and the frequency of the oscillator based on a phase of an output of the oscillator and a phase of the clock signal after the output of the oscillator and the clock signal are aligned. The delay line is configured to receive an input signal and generate an output signal delayed from the input signal by a time delay that corresponds to a delay line control code calculated from the pair of control codes and the delay parameter. | 2014-05-29 |
20140145772 | STORAGE CIRCUIT - In accordance with an embodiment, a description is given of a storage circuit including an input stage configured to provide a value to be stored, a storage stage configured to store the value to be stored, an output stage configured to output a value stored by the storage circuit, and a control circuit, wherein the control circuit is configured to receive a signal from the output stage, which signal indicates the charge state of the output stage, and, if the charge state of the output stage is equal to a predefined precharge state, to output an activation signal to the storage stage, and wherein the storage stage is configured to store the value to be stored, provided by the input stage, in reaction to the activation signal. | 2014-05-29 |
20140145773 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING BACK-GATE-VOLTAGE CONTROL CIRCUIT - A semiconductor integrated circuit includes a latch circuit, a data applying circuit configured to apply data to an input node of the latch circuit at timing responsive to a synchronizing signal, and a back-gate-voltage control circuit configured to change a back-gate voltage of at least one transistor in an inverter included in the latch circuit at timing responsive to the synchronizing signal. | 2014-05-29 |
20140145774 | Microcontroller with Digital Clock Source - A microcontroller has a numerical controlled oscillator receiving a primary clock signal and is configured to provide an internal system clock of the microcontroller. A method for operating a microcontroller performs the following steps: Selecting a primary clock signal from a plurality of clock signals; feeding the primary clock signal to a numerical controlled oscillator; configuring the numerical controlled oscillator to generate a numerical controlled clock signal; and providing the numerical controlled clock signal as an internal system clock for the microcontroller. | 2014-05-29 |
20140145775 | OVERSHOOT SUPPRESSION FOR INPUT/OUTPUT BUFFERS - Disclosed is a diode clamping circuit that is used in an I/O buffer to suppress noise. Diode-connected CMOS transistors or PN junction transistors are utilized, which are native to the CMOS process. Switching circuitry is also disclosed to isolate the diodes and prevent current drain in the circuit. Switching circuitry is also used to switch between two different power supply voltages. | 2014-05-29 |
20140145776 | HIGH FREQUENCY SWITCH - There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices; a second signal transferring unit including a plurality of second switching devices; a first shunting unit including a plurality of third switching devices; and a second shunting unit including a plurality of fourth switching devices. | 2014-05-29 |
20140145777 | System and Method for a Level Shifter - In accordance with an embodiment, a level shifter circuit includes a reconfigurable level shifting core coupled to a first node and a second node. The reconfigurable level shifting core is configured as a current mirror in a first mode, and as a cross-coupled device in a second mode. In the first mode, the current mirror mirrors a current at the first node to the second node, and in the second mode, the cross-coupled device produces a current at the second node in response to a voltage at the first node, and a current at the first node in response to a voltage at the second node. | 2014-05-29 |
20140145778 | Subharmonic Mixer - A sub-harmonic electronic mixer has at least one field effect transistor (FET) having a gate, source, and drain; and a useful signal input at a useful frequency; and a local oscillator input. The input receives the oscillator signal at a frequency being an integral fraction of the useful frequency, plus or minus a mixing frequency to provide a signal output. A gate of the FET and/or the drain and/or the source receives the useful signal to generate a gate-source voltage and/or a drain-source voltage whereby the gate receives the local oscillator signal to generate a gate-source voltage, and the drain or a source receives the local oscillator signal to generate a drain-source voltage. A phase shift is introduced between the signal received at the gate and the signal received at the drain or source of the FET. | 2014-05-29 |
20140145779 | CIRCUIT ARRANGEMENT FOR SWITCHING A CURRENT, AND METHOD FOR OPERATING A SEMICONDUCTOR CIRCUIT BREAKER - A control voltage is generated at a control input of a semiconductor circuit breaker by an actuation circuit at switching flanks of a switching signal, said control voltage having a profile which is flattened in relation to the profile of the switching signal. With the disclosed method, the switching losses in a semiconductor circuit breaker are reduced. By defining a value for a switching parameter of a control device of the actuation circuit, the switching behavior of the actuation circuit can be influenced by the switching parameter. A specific parameter value of the switching parameter can be varied during operation of the actuation circuit. | 2014-05-29 |
20140145780 | SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor device has a transistor comprising a source electrode, a drain electrode, and a gate electrode, a diode and a switch element connected in series between the gate and source electrodes of the transistor, and a control circuit configured to supply a control signal for switching the switch element. The control circuit has a predetermined time constant and is configured to supply the control signal to the switch element if a pulse signal having a voltage that is equal to or higher than a predetermined voltage is supplied to the gate electrode of the transistor. | 2014-05-29 |
20140145781 | APPARATUS AND METHODS FOR ULTRASOUND TRANSMIT SWITCHING - Apparatus and methods for ultrasound transmit switching are provided. In certain implementations, a transmit switch includes a bias polarity control circuit, a bias circuit, a first high voltage field effect transistor (HVFET), and a second HVFET. The sources of the first and second HVFETs are connected to one another at a source node, the gates of the first and second HVFETs are connected to one another at a gate node, and the drains of the first and second HVFETs are connected to an input terminal and an output terminal, respectively. The bias circuit and the bias polarity control circuit are each electrically connected between the source node and the gate node. The bias polarity control circuit can turn on or off the HVFETs by controlling a polarity of a bias voltage across the bias circuit, such as by controlling a direction of current flow through the bias circuit. | 2014-05-29 |
20140145782 | HIGH FREQUENCY SWITCH - There is provided a high frequency switch including: a first signal transferring unit including a plurality of first switching devices and at least one first diode device individually connected to control terminals of the plurality of first switching devices to enable or block signal flow between a common port transmitting and receiving a first high frequency signal and a first port inputting and outputting the first high frequency signal; and a second signal transferring unit including a plurality of second switching devices and at least one second diode device individually connected to control terminals of the plurality of second switching devices to enable or block signal flow between the common port transmitting and receiving a second high frequency signal and a second port inputting and outputting the second high frequency signal. | 2014-05-29 |
20140145783 | SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit includes an output MOS transistor and a back gate control circuit. The output MOS transistor includes a first electrode connected to a power supply terminal and a second electrode connected to an output terminal. The output MOS transistor is configured to turn on and off to cause communications to be performed with another semiconductor integrated circuit connected to the output terminal. The back gate control circuit is configured to control an electric potential at a back gate of the output MOS transistor so that a current path between the power supply terminal and the output terminal at a time when a power supply connected to the power supply terminal is turned off is interrupted. | 2014-05-29 |
20140145784 | SIGNAL PROCESSING DEVICE WITHOUT MECHANICAL SWITCH FOR ON/OFF OPERATION - A signal processing device includes a detection unit configured to detect an intent to use the signal processing device based on whether the signal processing device is in contact with a subject; and a power supply unit configured to supply power to operate the signal processing device based on the detected intent to use the signal processing device without using a separate ON/OFF switch to supply the power to operate the signal processing device. | 2014-05-29 |
20140145785 | APPARATUS AND METHODS FOR EQUALIZATION - Apparatus and methods for equalization are provided. In certain implementations, an equalizer includes first and second feedback resistors, first and second equalization resistors, an equalization capacitor, and an amplification circuit that includes first to fourth input terminals and first and second output terminals. The amplification circuit can receive a differential input voltage signal between the first and third input terminals, and the first and second equalization resistors and the equalization capacitor are electrically connected in series between the second and fourth input terminals with the equalization capacitor between the first and second equalization resistors. Additionally, the first feedback resistor is electrically connected between the first output terminal and the second input terminal, and the second feedback resistor is electrically connected between the second output terminal and the fourth input terminal. | 2014-05-29 |
20140145786 | SYSTEM FOR AMPLIFYING A COMMON RF ENERGY SIGNAL AND SWITCHING THE AMPLIFIED SIGNAL BETWEEN ONE OF TWO OUTPUTS - A RF input signal system and method switches the RF input signal amplified by an amplifier PA | 2014-05-29 |
20140145787 | AMPLIFIER WITH FILTERING - Signals are processed to facilitate the mitigation and/or cancellation of undesirable components within the signal. As consistent with one or more embodiments, input/delay circuits offset the phase of an input signal, as presented to respective amplifiers. The phase offset is used, upon combination of the outputs of the respective amplifiers, to cancel the undesirable components of the signal. Such an approach may, for example, involve phase offset in a digital domain, with correction upon combination of the signals as presented in an analog domain. | 2014-05-29 |
20140145788 | DISTORTION COMPENSATION DEVICE AND DISTORTION COMPENSATION METHOD - A distortion compensation device includes a storage unit, an address generator, and a distortion compensation processor. The storage unit stores therein a distortion compensation coefficient for compensating distortion generated in an amplifier for amplifying an input signal. The address generator generates a first address based on a power value of the signal at a current time. Furthermore, the address generator delays, every time a new augend is input, the sum of the power value of the signal at the current time and the augend. The address generator generates a second address based on the sum obtained by calculating a new augend, from the delayed sum. The distortion compensation processor acquires a distortion compensation coefficient corresponding to a combination of the first address and the second address from the storage unit and performs distortion compensation processing on the signal by using the acquired distortion compensation coefficient. | 2014-05-29 |
20140145789 | AMPLIFIER - An amplifier includes a first input terminal, a second input terminal, a TIA, and a compensation circuit. The TIA includes a first transistor, a second transistor, a first current source connected to the first input terminal and an emitter of the first transistor, a second current source connected to the second input terminal and an emitter of the second transistor, a first load resistor connected to a collector of the first transistor, and a second load resistor connected to a collector of the second transistor. A bias voltage is supplied to bases of the first and second transistors, the compensation circuit adjusts a first load current and a second load current based on voltage signals, and the TIA outputs the voltage signals based on collector voltages of the first and second transistors. | 2014-05-29 |
20140145790 | METHOD AND APPARATUS FOR IMPLEMENTING A LOW NOISE AMPLIFIER WITH ASSOCIATED GAIN AND INPUT IMPEDANCE - An apparatus with associated gain and input impedance includes gain devices, a switching unit and a resistor. A first differential pair of gain devices and associated bias circuitry is configured to operate in a full gain mode. A second differential pair of gain devices is configured to operate in a reduced gain mode. The switching unit is configured to disable the first differential pair of gain devices and enable the second differential pair of gain devices in the reduced gain mode and to disable the second differential pair of gain devices and enable the first differential pair of gain devices in the full gain mode. The resistor is configured to maintain constant input impedance of the apparatus when in the reduced gain mode. | 2014-05-29 |
20140145791 | AMPLIFIER CIRCUIT - A integrated Doherty amplifier circuit comprising a main input terminal, a peak input terminal and an output terminal, a main input conductor and a peak input conductor that are offset from one another in a first direction, the main and peak input conductors extend in a second direction that is perpendicular to the first direction, and wherein an input end of the main input conductor is coupled to the main input terminal and an input end of the peak input conductor is coupled to the peak input terminal, an output conductor that extends in the second direction, an output end of the output conductor is coupled to the output terminal, a main amplifier stage extends in the second direction and has a main stage input and a main stage output, a peak amplifier stage extends in the second direction and has a peak stage input and a peak stage output. | 2014-05-29 |
20140145792 | Free Layer with Out-of-Plane Anisotropy for Magnetic Device Applications - Synthetic antiferromagnetic (SAF) and synthetic ferrimagnetic (SyF) free layer structures are disclosed that reduce Ho (for a SAF free layer), increase perpendicular magnetic anisotropy (PMA), and provide higher thermal stability up to at least 400° C. The SAF and SyF structures have a FL1/DL1/spacer/DL2/FL2 configuration wherein FL1 and FL2 are free layers with PMA, the coupling layer induces antiferromagnetic or ferrimagnetic coupling between FL1 and FL2 depending on thickness, and DL1 and DL2 are dusting layers that enhance the coupling between FL1 and FL2. The SAF free layer may be used with a SAF reference layer in STT-MRAM memory elements or in spintronic devices including a spin transfer oscillator. Furthermore, a dual SAF structure is described that may provide further advantages in terms of Ho, PMA, and thermal stability. | 2014-05-29 |
20140145793 | Module for the Mechanical Uncoupling of a Resonator Having a High Quality Factor - The device ( | 2014-05-29 |
20140145794 | POWER COMBINER - A power combining apparatus includes an output waveguide section having inner and outer coaxial conductors, wherein an outer surface of the inner conductor and an inner surface of the outer conductor each includes a substantially linear taper, a center waveguide section having an input, an output, and a plurality of antenna elements, the output of the center waveguide section being coupled to the output waveguide section, and an output waveguide section coupled to the output of the center waveguide section. A power combining apparatus includes an output waveguide section having a central longitudinal axis, and inner and outer coaxial conductors configured to maintain a substantially constant characteristic impedance along the central longitudinal axis, a center waveguide section having an input, an output, and a plurality of antenna elements, the output of the center waveguide section being coupled to the output waveguide section, and an input waveguide section coupled to the input of the center waveguide section. | 2014-05-29 |
20140145795 | POWER COMBINER USING TRI-PLANE ANTENNAS - A power combining apparatus includes a waveguide structure and a plurality of antenna elements arranged in the waveguide structure, wherein each of the antenna elements comprises a center planar antenna layer, two outer planar antenna layers arranged on opposite sides of the center planar antenna layer, a non-conductive layer between the center planar antenna layer and one of the outer planar antenna layers, and another non-conductive layer between the center planar antenna and the other one of the outer planar antenna layers. The power combining apparatus includes a waveguide structure having an input, an output, and a plurality of antenna elements arranged in the waveguide structure, wherein each antenna element is configured to transform an electric field direction of an electromagnetic field by substantially 90 degrees rotation about a longitudinal axis of the waveguide structure, wherein a bandwidth of the antenna is less than, equal to, or greater than a decade of frequency range. | 2014-05-29 |
20140145796 | COMMON MODE FILTER - A common mode filter | 2014-05-29 |
20140145797 | COMMON MODE NOISE CHIP FILTER AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a common mode noise chip filter and a method for manufacturing the same, the common mode noise chip filter including: a ferrite substrate; coil patterns formed on the ferrite substrate; and a ferrite-polymer complex layer formed on the result substrate having the coil patterns formed therein, wherein the ferrite-polymer complex layer has a multilayer structure, so that the ferrite-polymer complex layer filling an inner space of the substrate having inner coil patterns is formed to have the multilayer structure but not a single-layer structure, thereby lowering internal stress, and thus improving reliability of the common mode noise chip filter as a product. | 2014-05-29 |
20140145798 | ELECTRONIC COMPONENT - An electronic component includes a multilayer body including insulating layers that are stacked on each other. First and second LC parallel resonators each include via hole conductors extending in a z-axis direction and loop shaped conductive layers provided on the insulating layers. The first and second LC parallel resonators define a band pass filter. A first loop plane of the first LC parallel resonator and a second loop plane of the second LC parallel resonator are parallel or substantially parallel to the z-axis direction, are parallel or substantially parallel to each other, and are overlapped with each other at at least a portion of the first loop plane and the second loop plane in a plan view from the direction perpendicular or substantially perpendicular to the first loop plane. The first loop plane protrudes from the second loop plane at the positive direction in the z-axis direction. | 2014-05-29 |
20140145799 | ACOUSTIC WAVE BAND REJECT FILTER - A method and system for an acoustic wave band reject filter are disclosed. According to one aspect, an acoustic wave band reject filter includes a substrate and a plurality of acoustic wave band reject filter blocks. The substrate includes bonding pads formed on the substrate. Each one of the plurality of acoustic wave band reject filter blocks is fixed on a separate die. Each separate die has solder balls on a side of the die facing the substrate. The solder balls are positioned to electrically connect the bonding pads formed on the substrate to positions on each of the die. | 2014-05-29 |
20140145800 | ACOUSTIC WAVE BAND REJECT FILTER - A method and system for an acoustic wave band reject filter are disclosed. According to one aspect, an acoustic wave band reject filter includes a substrate and a plurality of acoustic wave band reject filter circuit blocks. The substrate includes bonding pads formed on the substrate. Each one of the plurality of acoustic wave band reject filter circuit blocks is fixed on a separate die. Each separate die has solder balls on a side of the die facing the substrate. The solder balls are positioned to electrically connect the bonding pads formed on the substrate to electrodes of the dies | 2014-05-29 |
20140145801 | MAGNETIC ACTUATOR WITH ROTATABLE ARMATURE - A magnetic actuator with a movable part and a non-movable part is disclosed. The movable part can include two rotatable ferromagnetic elements with a portion close to the non-movable part to reduce magnetic force acting on the movable part during a switching operation, while moving the movable part towards the non-movable part. As the distance between the movable part and the non-movable part is reduced, a current through a coil of the non-movable part for generating magnetic force for acting on the movable part during a switching operation. | 2014-05-29 |
20140145802 | ELECTROMAGNETIC RELAY - An electromagnetic relay includes: an iron core that has an end face and a groove which goes across the end face; and a shading coil that is fitted in the groove; wherein the shading coil is fixed to the iron core by applying caulking processing to a plurality of areas in the end face which sandwich the groove. | 2014-05-29 |
20140145803 | ELECTROMAGNETIC RELAY - An electromagnetic relay, in particular a motor vehicle relay, contains a magnet yoke, a relay coil, a hinged armature which is pivotable about an axis of rotation and on which a moving contact, as working or switchover contact, is retained relative to at least one fixed contact. A piezo actuator is provided, which keeps the working or switchover contact closed when the relay coil is de-energized as a result of the actuation of the piezo actuator. | 2014-05-29 |
20140145804 | MAGNETIC RELAY DEVICE MADE USING MEMS OR NEMS TECHNOLOGY - A magnetic relay device having a substrate of semiconductor material houses two through magnetic vias of electrically conductive ferromagnetic material. At least one coil is arranged underneath a first surface of the substrate in proximity of at least one between the first and second magnetic vias, and a contact structure, of ferromagnetic material, is arranged over a second surface of the substrate and is controlled by the magnetic field generated by the coil so as to switch between an open position, wherein the contact structure electrically disconnects the first and second magnetic vias, and a close position, wherein the contact structure electrically connects the first and second magnetic vias. | 2014-05-29 |
20140145805 | RELAY - A relay includes: a fixed terminal on which a fixed contact is provided; a movable terminal on which a movable contact is provided; a cam that has an elliptical circumference shape, and is rotatable while a portion of the circumference shape is contacting a surface of the movable terminal; and a driving unit that rotates the cam so that respective portions located at one ends of a major axis and a minor axis of the elliptical circumference shape alternately contact the surface of the movable terminal; wherein when the portion located at one end of the major axis of the elliptical circumference shape of the cam contacts the surface of the movable terminal, the movable terminal is deformed elastically so that the movable contact contacts the fixed contact. | 2014-05-29 |
20140145806 | ELECTROMAGNETIC COIL ASSEMBLIES HAVING BRAIDED LEAD WIRES AND/OR BRAIDED SLEEVES AND METHODS FOR THE FABRICATION THEREOF - Embodiments of an electromagnetic coil assembly are provided, as are methods for the manufacture of an electromagnetic coil assembly. In one embodiment, the method includes joining a first end portion of a braided lead wire to a coiled magnet wire. A dielectric-containing material is applied in a wet-state over the coiled magnet wire and over the first end portion of the braided lead wire. The dielectric-containing material is cured to produce an electrically-insulative body in which the coiled magnet wire and the first end portion of the braided lead wire are at least partially embedded. Prior to application of the dielectric-containing material, the braided lead wire is at least partially impregnated with a masking material deterring wicking of the dielectric-containing material into an intermediate portion of the braided lead wire. | 2014-05-29 |
20140145807 | MAGNETIC SHEET OF CONTACTLESS POWER TRANSMISSION DEVICE - There are provided a magnetic sheet and a contactless power transmission device including the same. The magnetic sheet includes a ferrite sheet, a metal sheet formed on the ferrite sheet and including a polymer resin and a metal powder, and an adhesive film inserted between the ferrite sheet and the metal sheet. | 2014-05-29 |
20140145808 | RARE-EARTH PERMANENT MAGNET AND METHOD FOR MANUFACTURING RARE-EARTH PERMANENT MAGNET - There are provided a rare-earth permanent magnet and a manufacturing method of a rare-earth permanent magnet capable of preventing deterioration of magnet properties. In the method, magnet material is milled into magnet powder. Next, a mixture | 2014-05-29 |
20140145809 | System and Method for Positioning a Multi-Pole Magnetic Structure - Systems and methods for arranging magnetic sources for producing field patterns having high gradients for precision positioning, position sensing, and pulse generation. Magnetic fields may be arranged in accordance with codes having a maximum positive cross correlation and a maximum negative cross correlation value in proximity in the correlation function, thereby producing a high gradient slope corresponding to a high gradient force or signal associated with the magnetic structure. Various codes for doublet, triplet, and quad peak patterns are disclosed. Applications include force and torque pattern generators. A variation including magnetic sensors is disclosed for precision position sensing. The forces or sensor outputs may have a precision zero crossing between two adjacent and opposite maximum correlation peaks. | 2014-05-29 |
20140145810 | COIL FOR ENHANCING THE DEGREE OF FREEDOM OF A MAGNETIC FIELD - A coil for forming an induced magnetic field may include a first coil bundle formed of a first conducting wire wound in a first direction, the first coil bundle having an inner space of a prescribed inner width, a second coil bundle formed of a second conducting wire wound in a second direction, the second coil bundle having a prescribed outer width that is smaller than the inner width of the first coil bundle, and a connector that electrically connects the first conducting wire and the second conducting wire to each other. The second coil bundle may be provided in the inner space of the first coil bundle. The conducting wires of the first and second coil bundles may be wound in opposite directions and gaps between coil bundles may be changed. Accordingly, the magnetic field can be more evenly distributed in a wider area while maintaining a constant inductance. | 2014-05-29 |
20140145811 | TRANSFORMER INCLUDING A CONTACTLESS SIGNAL CONNECTION - An improved transformer for use in a power tool, wherein the power tool includes a stationary body and a shaft which is movable relative to the body. The transformer includes a stator which is fixed relative to the body, and at least one stator winding. The transformer also includes a rotor which is movable with the shaft, and at least one rotor winding. A magnetic field is shared by the at least one stator and rotor windings, and is used for creating a contactless signal connection between the body and an at least one sensor of the shaft. The stator and the rotor are arranged in a mutual geometrical relationship such that the contactless signal connection is provided for different positions in both an axial direction and a rotational direction of the shaft. | 2014-05-29 |
20140145812 | MULTILAYER INDUCTOR AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein is a multilayer inductor, manufactured by stacking laminates each including: a substrate having internal electrode coil patterns formed thereon; and a magnetic substance filling the substrate on which the internal electrode coil patterns are formed, wherein the substrate is formed by using a composition including a magnetic material, so that, when the substrate is placed in the middle of the electrode circuit patterns at the time of manufacturing a power inductor, the substrate can be utilized as a gap material, and thus the thickness of an inductor chip can be minimized, and, in addition, the magnetic material is included in the substrate forming composition, thereby improving magnetic characteristics, and the liquid crystal oligomer and the nanoclay are added to the composition, to thereby increase insulating property between magnetic metals, thereby raising inductance, and thus dimensional stability and physical hardness of the structure can be secured. | 2014-05-29 |
20140145813 | PLANAR HIGH VOLTAGE TRANSFORMER - A planar high voltage transformer comprising a magnetic core, a primary winding, a secondary winding, and an insulating plate is provided, wherein the secondary winding comprises a plurality of secondary winding printed circuit boards each having a secondary coil distributed thereon. | 2014-05-29 |
20140145814 | THIN FILM TYPE CHIP DEVICE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a thin film type chip device including a coil pattern formed on the substrate; a cavity defining pattern defining a cavity through which a part of the coil pattern is exposed; a filling layer filled in the cavity; and a magnetic layer including a surface layer covering a surface of the filling layer. | 2014-05-29 |
20140145815 | LAMINATED INDUCTOR - A laminated inductor includes a component body that provides a mounting surface on one of its faces, and at least a pair of external electrodes are formed on the mounting surface, wherein the component body has a laminate constituted by multiple insulator layers, a spiral coil conductor formed in the laminate, and leader parts that electrically connect the coil conductor and external electrodes; the coil conductor comprises conductor patterns formed in the insulator layers and via hole conductors that penetrate through the insulator layers and electrically connect the multiple conductor patterns, and also has a coil axis running roughly in parallel with the mounting surface and a turn unit having one or more sides running roughly in parallel with the mounting surface; and the via hole conductors are formed only on the side farthest away from the mounting surface among the one or more sides. | 2014-05-29 |
20140145816 | LAMINATED COIL COMPONENT - A laminated coil component includes an element assembly formed by laminating a plurality of insulation layers and a coil unit formed inside the element assembly by a plurality of coil conductors. The element assembly includes a coil unit arrangement layer which has the coil unit arranged therein, and at least a pair of shape retention layers which is provided to have the coil unit arrangement layer interposed therebetween to retain a shape of the coil unit arrangement layer. The shape retention layer is made from glass-ceramic containing SrO, and a softening point of the coil unit arrangement layer is lower than a softening point or a melting point of the shape retention layer. | 2014-05-29 |
20140145817 | TOUCH PANEL - A resistance-type touch panel includes a first electrode plate and the second electrode plate spaced from and opposite to the first electrode plate. The first electrode plate includes a first substrate and a first transparent conductive layer. The second electrode plate includes a second substrate and a second transparent conductive layer. The first transparent conductive layer includes a carbon nanotube film. The carbon nanotube film includes a number of carbon nanotube wires substantially parallel with each other and a number of carbon nanotube clusters located between the number of carbon nanotube wires. The carbon nanotube wires extend along an X direction and are spaced from each other along a Y direction. The carbon nanotube clusters between each adjacent two of the carbon nanotube wires are spaced from each other along the X direction. The X direction is intercrossed with the Y direction. | 2014-05-29 |
20140145818 | THERMISTOR AND METHOD OF CONSTRUCTING A THERMISTOR - A method of constructing a thermistor includes forming a semiconductor ceramic substrate. The method also includes coating a surface of the substrate with contact material and applying a solder mask on the contact material. The applying includes applying the solder mask to one or more portions of the contact material to leave an exposed area without the solder mask and a masked area with the solder mask. The method includes trimming the contact material at the masked area to adjust a resistance of the thermistor. | 2014-05-29 |
20140145819 | PORTABLE LOW COST FIREARM SAFE - A rapid-access gun safe includes a portable enclosing structure and a communication module. The portable enclosing structure encloses a firearm. The portable enclosing structure includes a fixed portion and a collapsing wall. The collapsing wall provides rapid access to the firearm. The communication module is coupled to the fixed portion of the enclosing structure. The communication module facilitates incoming and outgoing electronic communication of at least one access signal from a device external to the rapid-access gun safe. | 2014-05-29 |
20140145820 | METHOD FOR GENERATING A CURRENTLY VALID ONE-TIME RELEASE CODE FOR AN ELECTRONIC LOCK - The invention relates to a method for generating a currently valid one-time release code ( | 2014-05-29 |
20140145821 | Screen Unlocking Method, Apparatus, and Device - The present invention discloses a screen unlocking method, apparatus, and device, and relates to the field of touch control technologies, which can shorten the unlocking time and improve user experience. The method includes: displaying a screen unlocking interface which includes a password unlocking area and a shortcut unlocking area on a screen; receiving an unlocking pattern which includes a password unlocking pattern input through the password unlocking area and a shortcut unlocking pattern input through the shortcut unlocking area; determining whether the password unlocking pattern input by the user is consistent with a preset password unlocking pattern; and if the password unlocking pattern input by the user is consistent with the preset password unlocking pattern, unlocking the screen to enter a function interface corresponding to the shortcut unlocking pattern. The present invention is applicable to unlocking technologies of touch devices. | 2014-05-29 |
20140145822 | Anesthesia Cart with RFID Keyless Entry - A controlled access anesthesia cart has at least one drawer or compartment for storing general-use anesthesia items, and at least one drawer or compartment for storing controlled substances, e.g., narcotics. An RFID reader in the cart senses for RFID signals, and if a portable RFID transceiver is in range of about 3 meters of the cart, the compartments in the cart are unlocked for access. The anesthesiologist needs to enter a pass code for access to the controlled substances compartment(s). The compartments then remain unlocked so long as the portable RFID transceiver is present. When the portable transceiver is out of range, the cart immediately relocks the compartments automatically. | 2014-05-29 |
20140145823 | ACCESS CONTROL SYSTEM - The present disclosure is generally directed toward access control systems and, more specifically, toward access control systems that utilize Near Field Communications (NFC)-enabled devices. The disclosed system enables an NFC device to be remotely checked-in to the access control system; however, the NFC device operates in a read/write mode rather than a card emulation mode when interacting with RFID readers of the access control system. | 2014-05-29 |
20140145824 | SYSTEM FOR CAUSING GARAGE DOOR OPENER TO OPEN GARAGE DOOR AND METHOD - A system and a method for causing a garage door to open using a garage door opener having a wireless receiver is provided. The system comprises an interface coupled to an environment sensor and configured to receive data from the environment sensor. The system can include processing electronics coupled to the interface and configured to receive the data from the interface and to use the received data to determine whether an environmental condition exists. The processing electronics provide a command to cause the garage door opener to open the garage door based on the determination of whether the environmental condition exists. | 2014-05-29 |
20140145825 | Localization Using Virtual Antenna Arrays in Modulated Backscatter Rfid Systems - A localization method for use in a tag communication system includes associating a supertag having a plurality of tags with an item, reading backscatter signals from the tags of the plurality of tags to provide a plurality of backscatter signals, estimating a signal parameter of the backscatter signals of the plurality of backscatter signals to provide a plurality of derived signal parameters, and localizing the item in accordance with the plurality of derived signal parameters. The backscatter signals are read by a tag reader having a single antenna and the item is localized in accordance with an antenna array technique performed upon the plurality of derived signal parameters. The backscatter signals are read with an antenna array to provide a further plurality of derived signal parameters for each tag of the plurality of tags, and the item is localized in accordance with the further pluralities of derived signal parameters. | 2014-05-29 |